JP2010118538A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus which has small color mixing and large pixel capacity (saturation signal amount), and less forms an after-image. <P>SOLUTION: The solid-state imaging apparatus includes a first-conductivity type semiconductor substrate 1, a second-conductivity type semiconductor layer 2 formed on the first-conductivity type semiconductor substrate 1, a first first-conductivity type semiconductor region 3 formed selectively on a lower side in the second-conductivity type semiconductor layer 2 in contact with the first-conductivity type semiconductor substrate 1, and a first-conductivity type pixel isolation region 6 defining a pixel region including the first first-conductivity type semiconductor region 3 and the second-conductivity type semiconductor layer 2 at its periphery, and penetrating the second-conductivity type semiconductor layer 2 without coming in contact with the first first-conductivity type semiconductor region 3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device using a photodiode as a photoelectric conversion element.

  Recently, development of products equipped with cameras such as digital cameras, video cameras, and mobile phones has been actively conducted. This type of camera is equipped with a solid-state imaging device. The solid-state imaging device has a configuration in which photodiodes (photoelectric conversion elements) are two-dimensionally arranged in an imaging region and charges accumulated in the photodiodes are read (Patent Document 1). In the device structure of the solid-state imaging device disclosed in Patent Document 1, two or more convex N-type impurity regions are added to the bottom surface of the N-type impurity region in order to increase the pixel capacitance. However, in the case of this device structure, the pixel center is separated into three or more by the addition of the convex N-type impurity region, and the accumulated electrons (especially those at the farthest pixel center) can be read efficiently. However, there is a problem that afterimages increase.

A solid-state imaging device is desired to have little color mixing, a large pixel capacity (saturation signal amount), and a small afterimage. However, it is difficult to realize a solid-state imaging device that satisfies all of these requirements.
JP 2002-31451 A

  An object of the present invention is to provide a solid-state imaging device with little color mixing, a large pixel capacity (saturation signal amount), and little afterimage.

  A solid-state imaging device according to an aspect of the present invention includes a first conductivity type semiconductor substrate, a second conductivity type semiconductor layer formed on the first conductivity type semiconductor substrate, and a lower side in the second conductivity type semiconductor layer. And a first first conductivity type semiconductor region that contacts the first conductivity type semiconductor substrate, the first first conductivity semiconductor region, and the second conductivity type semiconductor layer around it. And a first conductivity type pixel isolation region penetrating through the second conductivity type semiconductor layer without contacting the first first conductivity type semiconductor region. To do.

  According to the present invention, it is possible to realize a solid-state imaging device with little color mixing, a large pixel capacity (saturation signal amount), and little afterimage.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the first conductivity type is assumed to be P-type, and the second conductivity type is assumed to be N-type.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing a basic cell of a solid-state imaging device according to an embodiment of the present invention. FIG. 2 is a plan view corresponding to the AA ′ cross section of FIG. 1.

In the figure, reference numeral 1 denotes a P-type semiconductor substrate, and an N-type epitaxial semiconductor layer 2 is formed on the P-type semiconductor substrate 1. In the present embodiment, the P-type semiconductor substrate 1 is a P-type silicon substrate. The P-type impurity concentration of the P-type semiconductor substrate 1 is, for example, 1 × 10 ¹⁸ cm ⁻³ . The P-type impurity concentration of the N-type epitaxial semiconductor layer 2 is, for example, 1 × 10 ¹⁵ cm ⁻³ . In order to photoelectrically convert light having a long wavelength such as red light at a deep position on the substrate and efficiently store electrons (charges) generated by the photoelectric conversion in the red pixel, the thickness of the N-type epitaxial semiconductor layer 2 is 5 μm or more.

A first P-type semiconductor region 3 is selectively formed on the lower side in the N-type epitaxial semiconductor layer 2. The first P-type semiconductor region 3 is in contact with the P-type semiconductor substrate 1. The P-type impurity concentration of the first P-type semiconductor region 3 is, for example, 1 × 10 ¹⁵ cm ⁻³ .

  The N type epitaxial semiconductor layer 2 and the P type semiconductor region 3 are formed by, for example, multistage epitaxial and ion implantation. That is, a semiconductor layer corresponding to the thickness of the P-type semiconductor region 3 is formed by a series of steps including an epitaxial growth step of the semiconductor layer and a step of ion-implanting N-type and P-type impurities into the semiconductor layer. Then, a series of steps consisting of a step of epitaxially growing the semiconductor layer and a step of ion-implanting N-type impurities into the semiconductor layer are formed to form a semiconductor layer corresponding to the thickness of the N-type epitaxial semiconductor layer 2. Repeat until

An N-type semiconductor region 4 is selectively formed on the surface of the N-type epitaxial semiconductor layer 2. The N-type impurity concentration of the N-type semiconductor region 4 is, for example, 1 × 10 ¹⁷ cm ⁻³ . A second P-type semiconductor region 5 having a higher impurity concentration than that of the first P-type semiconductor region 3 is selectively formed on the surfaces of the N-type semiconductor region 4 and the N-type epitaxial semiconductor layer 2. The P-type impurity concentration of the second P-type semiconductor region 5 is, for example, 1 × 10 ¹⁸ cm ⁻³ . The N-type semiconductor region 4 and the P-type semiconductor region 5 are not in contact with the P-type semiconductor region 3, and an N-type epitaxial semiconductor is interposed between the N-type semiconductor region 4 and the P-type semiconductor region 5 and the P-type semiconductor region 3. Layer 2 is interposed.

A P-type isolation region 6 for pixel isolation is formed in the N-type epitaxial semiconductor layer 2. The P-type isolation region 6 penetrates the N-type epitaxial semiconductor layer 2 and contacts the surface of the P-type semiconductor substrate 1. The P-type isolation region 6 includes a pixel region (basic cell) including the first P-type semiconductor region 3 and the surrounding N-type epitaxial semiconductor layer 2, and the N-type semiconductor region 4 and the second P-type semiconductor region 5. ). The P-type isolation region 6 is not in contact with the first P-type semiconductor region 3, so that the periphery of the first P-type semiconductor region 3 is an N-type epitaxial semiconductor layer as shown in FIG. 2 is surrounded by a P-type isolation region 6. The P-type impurity concentration of the P-type isolation region 6 is, for example, 1 × 10 ¹⁵ cm ⁻³ .

  A gate insulating film 7 is formed on the P-type isolation region 6, and a gate electrode 8 is formed on the gate insulating film 7. A high impurity concentration N-type diffusion layer (drain) 9 is selectively formed on the surface of the N-type epitaxial semiconductor layer 2 in the adjacent pixel region so as to contact the P-type isolation region 6. The portion of the N-type semiconductor region (source) 4, the gate insulating film 7, the gate electrode 8, and the N-type diffusion layer 9 in contact with the P-type isolation region 6 constitutes a charge transfer MOS transistor.

  The solid-state imaging device of this embodiment includes a first PN junction PN-J1 on the surface of the pixel region. The first PN junction PN-J1 is composed of a PN junction between the N-type semiconductor region 4 and the second P-type semiconductor region 5.

  In addition, the solid-state imaging device according to the present embodiment includes the second PN junction PN-J2 at the center in the depth direction of the pixel region. The second PN junction PN-J2 is composed of a PN junction between the upper portion of the first P-type semiconductor region 3 and the N-type epitaxial semiconductor layer 2.

  Furthermore, the solid-state imaging device according to the present embodiment includes a third PN junction PN-J3 in a portion deeper than the second PN junction PN-J2. The third PN junction PN-J3 includes a PN junction between the first P-type semiconductor region 3 and the N-type epitaxial semiconductor layer 2 at a portion deeper than the central portion in the depth direction of the pixel region, A PN junction between the lower portion of the P-type semiconductor region 3 and the P-type semiconductor substrate 1 is formed. FIG. 1 also shows an electric field vector E in the PN junctions PN-J1 to PN-J3. In FIG. 1, the P-type semiconductor region is grounded.

  According to the present embodiment, since the first P-type semiconductor region 3 is formed in the N-type epitaxial semiconductor layer 2, compared to the case where the first P-type semiconductor region 3 is not present (FIGS. 3 and 4). In view of the equivalent circuit, the distance between the electrodes of the capacitor in the pixel region is reduced, and the pixel capacitance (saturation signal amount) is increased. FIG. 4 is a plan view corresponding to FIG.

As a structure for increasing the pixel capacitance, as shown in FIG. 5, it is conceivable that a deep position of the pixel region is made P-type by the P-type semiconductor layer 30. In the case of FIG. 5, the depth (position) of the pixel center 20 is, for example, about 1 μm. However, in this case, there is a problem that electrons e ⁻ that flow in the pixel region without being accumulated in the PN junction of the pixel region flow into the adjacent pixel region, and the color mixture increases.

  On the other hand, in the present embodiment, since almost no electrons flow into adjacent pixel regions, the color mixture is sufficiently small. This point will be further described below.

  Considering that incident light is photoelectrically converted at a depth (position) of, for example, 4 μm and electrons are generated, a strong electric field E toward the pixel center 20 is generated at each of the PN junctions PN-J1 to PN-J3. The electric field E at the PN junction PN-J2 is sufficiently stronger than the electric field E at the remaining PN junctions PN-J1 and J3. Therefore, most of the electrons generated by photoelectric conversion are pulled by the electric field E at the PN junction PN-J2 and drift to the pixel center 20. Some of the electrons generated by the photoelectric conversion are pulled by the electric field E at the PN junction PN-J3 and drift to the adjacent pixel region. However, since the amount is sufficiently small, the color mixture is sufficiently small.

  In FIG. 1, the electron drift is schematically shown by white arrows. A thick white arrow indicates a drift due to the electric field E at the PN junction PN-J2, and a thin white arrow indicates a drift due to the electric field E at the PN junction PN-J3 (side surface of the P-type semiconductor region 3).

  3 and 5 also show white arrows schematically showing electron drift. In the case of FIG. 5, the distance from the position where electrons are generated to the PN junction PN-J2 where a strong electric field is generated is longer than that in FIG. Therefore, in the case of FIG. 5, the amount of electrons that are pulled by the electric field E at the PN junction PN-J2 and drift to the pixel center 20 is reduced as compared with FIG. As the amount increases, the color mixture increases.

  Furthermore, according to the present embodiment, since the pixel center 20 is shifted to the surface side of the N-type epitaxial semiconductor layer 2 as compared with the case where the first P-type semiconductor region 3 is not provided (FIGS. 3 and 4), The distance between the pixel center 20 and the gate electrode 8 (transfer gate) is shortened, the afterimage becomes sufficiently small, and the afterimage characteristics are improved. In the case of FIG. 1, the depth (position) of the pixel center 20 is about 1 μm, for example. In the case of FIG. 3, the depth (position) of the pixel center 20 is about 2 μm, for example.

  As described above, according to the present embodiment, the first P-type semiconductor region 3 can increase the pixel capacitance, reduce the afterimage, and suppress the color mixture. And the afterimage can be improved at the same time.

  The present invention is not limited to the above embodiment.

  For example, in the above embodiment, the first conductivity type is P-type and the second conductivity type is N-type. However, the first conductivity type may be N-type and the second conductivity type may be P-type.

  In the above embodiment, a silicon substrate is used, but an SOI substrate, SiC substrate, or SiGe substrate may be used.

  The solid-state imaging device of the above embodiment includes three PN junctions PN-J1, J2, and J3. However, if at least the PN junction PN-J3 is included, it is advantageous over the conventional solid-state imaging device. Has an effect.

  Although a device to which the solid-state imaging device according to the present embodiment is applied is not particularly mentioned, it is specifically a product including a camera such as a digital camera, a video camera, and a mobile phone. Furthermore, the solid-state imaging device of this embodiment may be a solid-state imaging device as a discrete product.

  Furthermore, the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  In addition, various modifications can be made without departing from the scope of the present invention.

1 is a cross-sectional view schematically showing a basic cell of a solid-state imaging device according to an embodiment of the present invention. The top view corresponding to the A-A 'cross section of FIG. Sectional drawing which shows the basic cell of the solid-state imaging device of a comparative example typically. The top view of the comparative example of FIG. Sectional drawing which shows typically the basic cell of the solid-state imaging device of another comparative example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... P type semiconductor substrate (1st conductivity type semiconductor substrate), 2 ... N type epitaxial semiconductor layer (2nd conductivity type semiconductor layer), 3 ... 1st P type semiconductor region (1st 1st conductivity type semiconductor region) 4... N type semiconductor region (second conductivity type semiconductor region), 5... 2 P type semiconductor region (second first conductivity type semiconductor region), 6... P type isolation region (first conductivity type pixel) (Isolation region), 7... Gate insulating film, 8... Gate electrode, 9... N-type diffusion layer, 20... Pixel center, 30 ... P-type semiconductor layer, PN-J1, PN--J2, PN-J3.

Claims (5)

A first conductivity type semiconductor substrate;
A second conductive type semiconductor layer formed on the first conductive type semiconductor substrate;
A first first conductivity type semiconductor region selectively formed on a lower side in the second conductivity type semiconductor layer and in contact with the first conductivity type semiconductor substrate;
The second conductive semiconductor layer defining a pixel region including the first first conductive semiconductor region and the second conductive semiconductor layer surrounding the first conductive semiconductor region without contacting the first first conductive semiconductor region A solid-state imaging device, comprising: a first conductivity type pixel separation region penetrating through the first conductive type pixel separation region. A second conductivity type selectively formed on a surface of the second conductivity type semiconductor layer, not contacting the first first conductivity type semiconductor region, and having a higher impurity concentration than the second conductivity type semiconductor layer; A semiconductor region and a second conductivity type second semiconductor region selectively formed on the surface of the second conductivity type semiconductor region and having a higher impurity concentration than the first conductivity type semiconductor region. The solid-state imaging device according to claim 1, wherein: The solid-state imaging device according to claim 1, wherein a periphery of the first first conductivity type semiconductor region is surrounded by the second conductivity type semiconductor layer. 4. The solid-state imaging device according to claim 1, wherein the second conductive semiconductor layer is an epitaxial semiconductor layer. 5. 5. The solid-state imaging device according to claim 4, wherein the first first conductivity type semiconductor region is a region formed by ion implantation of a first conductivity type impurity in the epitaxial semiconductor layer.

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