JP2010114258A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device having a delay cell with an increased delay amount without increasing the area is provided.
A CMOS inverter includes a PMOS transistor (50b) formed in an N well (5) and an NMOS transistor (50a) formed in a P well (6). The N well (5) and the P well (6) have a predetermined vertical direction. A plurality of delay cells 9 and normal logic cells 17 arranged in a pattern and arranged in the horizontal direction;
A plurality of empty area cells each having an N well 5 and a P well 6 arranged adjacent to the delay cell 9 and the normal logic cell 17 in the horizontal direction and arranged in a predetermined pattern in the vertical direction 8 and
The well arrangement pattern in the delay cell 9 is an inversion of the pattern of the empty area cell 8 adjacent to the left and right, and the well arrangement pattern in the normal logic cell 17 is the same as the pattern in the empty area cell 8 adjacent to the left and right. It is.
[Selection] Figure 3A

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, for example, a semiconductor device having a delay element and a manufacturing method thereof.

  In the semiconductor integrated circuit, a delay element that delays a signal is arranged. One application of the delay element is to adjust a time difference (so-called clock skew) when a clock signal reaches each flip-flop when supplying a clock signal to a plurality of flip-flops. In general, a CMOS inverter is used as the delay element. The delay amount is controlled by changing the number of connection stages of the CMOS inverter. Therefore, in order to obtain a large delay, a multistage delay element is required. In addition, the delay cells in which the delay elements are arranged may be arranged in the order of tens of thousands in one chip, and the ratio of the delay cells to the entire chip area cannot be ignored.

  Furthermore, in recent years, with the spread of personal computers and mobile devices, there is a strong demand to reduce the chip area. For this reason, it is required to reduce the area occupied by the delay cells in the entire chip.

By the way, a well proximity effect is known in which the characteristics of a MOS transistor change according to the distance between the MOS transistor and the well boundary (for example, Patent Document 1). Here, the well boundary is a boundary between wells having different conductivity types (N-type and P-type). This well proximity effect is that when ion implantation is performed with a resist mask covering the other region in order to form a well in a certain region on the wafer, the implanted ions are scattered in the resist mask. caused by. For example, consider forming an N-well in a P-type semiconductor substrate in a process of manufacturing a PMOS transistor. Ion implantation of an N-type impurity such as phosphorus is performed in a state where a region other than a region to be an N well is covered with a resist mask. At this time, as a result of part of the N-type impurities being scattered in the resist mask, N-type impurity ions are implanted into the N well in excess of a desired amount. As a result, the threshold voltage (Vth) of the PMOS transistor formed on the N well increases from a desired value, and the delay characteristic of the MOS transistor increases. The well proximity effect increases as the distance between the well boundary and the MOS transistor is shorter.
JP 2007-335562 A

  The present invention provides a semiconductor device having a delay cell with an increased delay amount without increasing the area.

  According to one aspect of the present invention, a PMOS transistor formed in a logic cell N well and an NMOS transistor formed in a logic cell P well constituting a CMOS circuit, the logic cell N well and the logic cell are provided. The cell P wells are arranged adjacent to each other in a predetermined well arrangement pattern in a first direction, and a plurality of logic cells arranged along a second direction intersecting with the first direction, A plurality of non-logic cells arranged adjacent to the logic cells along a second direction and having non-logic cell N-wells and non-logic cells P-wells adjacent to each other in a predetermined well arrangement pattern in the first direction And the plurality of logic cells include a delay cell using the CMOS circuit as a delay element and a normal logic cell using the CMOS circuit for a purpose other than the delay element. The well arrangement pattern in the delay cell is obtained by inverting the well arrangement pattern in the non-logic cell adjacent to the delay cell along the second direction, and the well arrangement pattern in the normal logic cell is A semiconductor device is provided which is the same as the well arrangement pattern in the non-logic cell adjacent to the normal logic cell along the second direction.

  According to another aspect of the present invention, there is provided a first conductivity type silicon substrate in which first, second, and third cells are arranged adjacent to each other on the left and right sides, and the first and second silicon substrates in the silicon substrate are prepared. The lower region of the third cell and the upper region of the second cell are covered with a resist mask, and an impurity of the second conductivity type is ion-implanted into the silicon substrate, whereby the upper region of the first and third cells And forming the second conductivity type well in the lower region of the second cell, peeling the resist mask from the silicon substrate, and forming the second conductivity type in the upper region of the second cell. There is provided a method for manufacturing a semiconductor device, wherein a MOS transistor having a source / drain region of a first conductivity type is formed, and a MOS transistor having a source / drain region of the first conductivity type is formed in the lower region of the second cell. Is The

  According to the present invention, a semiconductor device having a delay cell with an increased delay amount without increasing the area can be obtained.

  Before describing the embodiments of the present invention, the background of how the present inventors have made the present invention will be described.

  In order to increase the delay amount without increasing the area of the delay cell, the present inventors first considered increasing the delay amount by increasing the gate width of the CMOS inverter. As the amount of delay per delay element increases, the number of required delay cells decreases, and as a result, the area occupied by the delay cells decreases.

  However, when a CMOS inverter serving as a delay element is formed on the same wafer as other MOS transistors by the same process, the gate width of the CMOS inverter is required to be uniform with that of the MOS transistors other than the delay elements. For this reason, it turned out that it is difficult to take said method. Here, the reason why a uniform gate width is required will be described. In recent years, miniaturization of MOS transistors constituting semiconductor integrated circuits has progressed, and the so-called deep submicron generation is about to enter. In the photolithography of the deep sub-micron generation, the nature of the exposure light wave comes to the surface. For this reason, in order to obtain a desired transfer pattern on the wafer, it is necessary to perform optical proximity correction (OPC: Optical Proximity Correction). In order to perform this optical proximity correction, it is required to make the gate width and the gate arrangement interval of the MOS transistors uniform.

  Next, the layout of a conventional MOS transistor will be described.

  FIG. 1 shows a plurality of CMOS inverters 50 fabricated in a cell (logic cell 7 described later) on the wafer.

  Here, the cell is a basic unit that divides a region on the wafer, and specifically refers to a region surrounded by cell boundary lines CB1 to CB10 in FIG. Hereinafter, a cell in which a semiconductor element that contributes to the operation of the semiconductor integrated circuit is formed is referred to as a logic cell. Among these logic cells, a cell in which a semiconductor element that functions as a delay element is formed is called a delay cell, and a cell in which a semiconductor element that functions as a device other than the delay element is formed is called a normal logic cell. A cell in which a dummy semiconductor element that does not contribute to the operation of the semiconductor integrated circuit is formed is called a dummy cell, and a cell in which no semiconductor element is formed is called an empty area cell. The dummy cells and the empty area cells are collectively referred to as non-logic cells. Note that a circuit including a plurality of semiconductor elements may be formed in one cell.

  As can be seen from FIG. 1, one CMOS inverter 50 is formed in one logic cell 7. Further, the logic cells 7 and the empty area cells 8 are alternately arranged in the horizontal direction.

  In FIG. 1, three CMOS inverters 50 are arranged in each of the upper, middle and lower stages. Each CMOS inverter 50 includes an NMOS transistor 50a and a PMOS transistor 50b. The NMOS transistor 50 a has N type diffusion layers 2 and 2 formed in the P well 6 and a gate 1 for forming an inversion layer between the N type diffusion layers 2 and 2. N-type diffusion layers 2 and 2 constitute source / drain regions of NMOS transistor 50a. The PMOS transistor 50 b has P-type diffusion layers 3 and 3 formed in the N well 5 and a gate 1 for forming an inversion layer between the P-type diffusion layers 3 and 3. The P-type diffusion layer 3 constitutes a source / drain region of the PMOS transistor 50b.

  The gate 1 also serves as the gates of the NMOS transistor 50 a and the PMOS transistor 50 b and functions as an input terminal of the CMOS inverter 50. The well terminal 4 is an electrode for fixing the potential of the well.

  As can be seen from FIG. 1, the upper three CMOS inverters 50 have a configuration in which the middle three CMOS inverters 50 are flipped (inverted) around the cell boundary line CB2, and the middle three CMOS inverters 50 and N well 5 are shared. Similarly, the lower three CMOS inverters 50 have a configuration in which the middle three CMOS inverters 50 are flipped around the cell boundary line CB3, and share the P well 6 with the middle three CMOS inverters 50. Yes.

  Since the well proximity effect that increases the delay is not preferable for the MOS transistor of the normal logic cell that requires high-speed operation, the cell is arranged so that the distance from the well boundary to the MOS transistor becomes large. This will be described with reference to FIG.

  FIG. 2 is an enlarged view of the logic cell 7 arranged in the center of the middle stage in FIG. As can be seen from FIG. 2, first, in the vertical direction, the distance from the P-type diffusion layer 3 of the CMOS inverter to the well boundary WB1 is relatively large, and the distance to the well boundary WB2 is relatively small. Next, in the horizontal direction, since the N well 5 and the P well 6 are formed in a horizontally long shape, there is basically no well boundary.

  Such a configuration is preferable for a normal logic cell that requires high-speed operation, but is not preferable for a delay cell. This is because, as a result of suppressing the well proximity effect, the delay amount per delay cell is reduced, and the number of delay cells required to obtain a desired delay amount is increased. This causes a problem that the area of the delay cell in the chip increases.

  In order to solve the above problem, the present invention actively utilizes the well proximity effect to control the delay characteristics of the delay element, thereby increasing the delay amount without increasing the area of the delay cell. is there.

  Hereinafter, five embodiments according to the present invention will be described with reference to the drawings. In the first and second embodiments, the well proximity effect is increased by reversing the arrangement pattern of the wells of the delay cells with the adjacent empty area cells. In the third embodiment, a delay element is also formed in an empty area cell adjacent to the delay cell. In the fourth and fifth embodiments, instead of changing the arrangement pattern of the delay cell well, the well configuration of the cell adjacent to the delay cell is changed.

  In addition, the same code | symbol is attached | subjected to the component which has an equivalent function, and the overlapping description is abbreviate | omitted suitably.

(First embodiment)
A first embodiment will be described. FIG. 3A is a diagram showing a layout of the delay cell according to the present embodiment. As can be seen by comparing FIG. 3A with FIG. 1 described above, the delay cells 9 are arranged adjacent to each other in the vertical direction in the center of FIG. 3A. The delay cell 9 is sandwiched between the left and right empty cells 8 and 8.

  The cell having the CMOS inverter 50 arranged on the left and right in FIG. 3A is the normal logic cell 17.

  Furthermore, it demonstrates in detail using FIG. 3B. FIG. 3B is an enlarged view of the delay cell 9 arranged in the center of the middle stage in FIG. 3A. As can be seen from this figure, empty area cells 8 and 8 are arranged on the left and right sides of the delay cell 9. A PMOS transistor is formed in the N well 5 of the delay cell 9, and an NMOS transistor is formed in the P well 6.

  As can be seen from FIG. 3B, the arrangement pattern of the wells of the delay cell 9 is opposite to that of the empty area cell 8 adjacent to the left and right. That is, the empty cell 8 has an N well 5 (non-logic cell N well) on the upper side and a P well 6 (non-logic cell P well) on the lower side, while the delay cell 9 has an upper side. P well 6 (logic cell P well) is arranged on the lower side, and N well 5 (logic cell N well) is arranged on the lower side.

  By adopting the above configuration, as shown by the arrow in FIG. 3B, the distance from the MOS transistor formed in the delay cell 9 to the well boundary in the lateral direction is remarkably shortened compared to the conventional case (see FIG. 2). . As a result, the well proximity effect is strengthened, so that the threshold voltage of the MOS transistor of the delay cell 9 increases and the delay amount of the delay cell 9 increases. Therefore, the number of delay cells required to obtain a desired delay amount can be reduced, and the area of the delay cells in the chip can be reduced.

  Next, two methods for manufacturing the delay cell of this embodiment shown in FIG. 3B will be described. First, a single well structure will be described with reference to FIGS. 4A to 4D, and a twin well structure will be described with reference to FIGS. 5A to 5F.

  First, a manufacturing method using a single well structure will be described.

(1) A p-type silicon substrate 101 is prepared. As shown in FIG. 4A, cells 61a, 61b, 61c are assigned to the surface region of the p-type silicon substrate 101. These cells (61a, 61b, 61c) are arranged adjacent to each other on the left and right and each have a p-type region 101A.

(2) Next, as shown in FIG. 4B, the lower half of the cells 61a and 61c and the upper half of the cell 61b are covered with a resist mask 60 by photolithography.

(3) Next, n-type impurities (for example, phosphorus) are ion-implanted into the p-type silicon substrate 101. Thereafter, the resist mask 60 is peeled off.

  As a result, as shown in FIG. 4C, the region covered with the resist mask 60 remains as the p-type region 101A, and the N well 5 is formed in the region not covered with the resist mask 60. Due to the above-described well proximity effect, a part of the n-type impurity ions is scattered in the resist mask 60, so that the impurity concentration of the N well 5 is increased accordingly.

(4) Next, as shown in FIG. 4D, an NMOS transistor 50a is formed in the p-type region 101A of the cell 61b and a PMOS transistor 50b is formed in the N well 5 of the cell 61b by using a conventional MOSFET manufacturing technique. . More specifically, the common gate 1 is formed for the NMOS transistor 50a and the PMOS transistor 50b. Thereafter, N-type diffusion layers 2 and 2 to be source / drain regions of the NMOS transistor 50a are formed in the p-type region 101A of the cell 61b. In addition, P-type diffusion layers 3 and 3 that become source / drain regions of the PMOS transistor 50b are formed in the N well 5 of the cell 61b. Then, as shown in FIG. 4D, well terminals 4 and 4 for fixing the potentials of the N well 5 and the p-type region 101A are formed.

  Through the above process, a CMOS inverter composed of the NMOS transistor 50a and the PMOS transistor 50b is formed in the cell 61b, and the cell 61b becomes the delay cell 9. Further, nothing is formed in the cells 61a and 61c, so that the empty area cells 8 and 8 are formed. Since the impurity concentration of the N well 5 of the delay cell 9 is high due to the well proximity effect, the threshold voltage of the PMOS transistor 50b increases and the delay amount of the delay cell 9 increases.

  Next, the manufacturing method by a twin well structure is demonstrated using FIG. 5A-FIG. 5F.

(1) A semi-insulating silicon substrate 102 is prepared. As shown in FIG. 5A, cells 62a, 62b, 62c are assigned to the surface region of the semi-insulating silicon substrate 102. These cells (62a, 62b, 62c) are arranged adjacent to each other on the left and right and each have a semi-insulating region 102A.

(2) Next, as shown in FIG. 5B, the lower half of the cell 62a and the cell 62c and the upper half of the cell 62b are covered with a resist mask 60 by photolithography.

(3) Next, n-type impurities (for example, phosphorus) are ion-implanted into the semi-insulating silicon substrate 102. Thereafter, the resist mask 60 is peeled off.

  As a result, as shown in FIG. 5C, the N well 5 is formed in a region not covered with the resist mask 60. Due to the above-described well proximity effect, a part of the n-type impurity ions is scattered in the resist mask 60, so that the impurity concentration of the N well 5 is increased accordingly.

(4) Next, as shown in FIG. 5D, the upper half of the cell 62a and the cell 62c and the lower half of the cell 62b are covered with a resist mask 60 by photolithography.

(5) Next, a p-type impurity (for example, boron) is ion-implanted into the semi-insulating silicon substrate 102. Thereafter, the resist mask 60 is peeled off.

  As a result, as shown in FIG. 5E, the P well 6 is formed in a region not covered with the resist mask 60. Due to the above-described well proximity effect, a part of the p-type impurity ions is scattered in the resist mask 60, so that the impurity concentration of the P well 6 is increased accordingly.

(6) Next, as shown in FIG. 5F, an NMOS transistor 50a is formed in the P-well 6 of the cell 62b and a PMOS transistor 50b is formed in the N-well 5 of the cell 62b by using a conventional MOSFET manufacturing technique. Further, as shown in FIG. 5F, well terminals 4 and 4 for fixing the potentials of the N well 5 and the P well 6 are formed.

  Through the above steps, similar to the above-described manufacturing method, a CMOS inverter including the NMOS transistor 50a and the PMOS transistor 50b is formed in the cell 62b, and the cell 62b becomes the delay cell 9. Further, nothing is formed in the cells 62a and 62c, so that the empty area cells 8 and 8 are formed.

  One of the differences from the above-described method is that not only the N well 5 of the delay cell 9 but also the impurity concentration of the P well 6 is increased due to the well proximity effect. For this reason, not only the PMOS transistor 50b but also the threshold voltage of the NMOS transistor 50a increases, and the delay amount of the delay cell 9 can be further increased.

  In addition to the above two manufacturing methods, a delay cell may be manufactured using a so-called triple well structure. In this case, a P well is formed in the N well, and an NMOS transistor is formed in the P well.

  Next, a modified example of the delay cell according to the present embodiment will be described. In this modification, as can be seen from FIG. 6, the N well 12 is formed in the vicinity of the left and right cell boundary lines on the upper side of the delay cell 9. Thereby, as shown in part B of FIG. 6, the wells of the same conductivity type do not make point contact as shown in part A of FIG. 3B, so that the MOS transistor can be operated more stably. A P well may be formed in the vicinity of the left and right cell boundary lines below the delay cell 9.

  Note that the delay cell according to this modification can also be manufactured by a method similar to the above-described manufacturing method by changing the range covered by the resist mask 60.

  In the description of the present embodiment, the adjacent cells on the left and right of the delay cell are vacant area cells, but the above-described dummy cells may be used.

  As described above, in the present embodiment, the arrangement pattern of the wells in the delay cell 9 is reversed from that of the empty area cells 8 and 8 adjacent to the left and right, so that the delay cell 9 and the empty area cell adjacent to the left and right thereof. A well boundary is provided in the vicinity of the boundary with 8,8. By doing so, the well proximity effect is strengthened and the characteristics of the MOS transistor formed in the delay cell are deteriorated. Thereby, the delay amount of the delay cell can be increased without increasing the area of the delay cell.

(Second Embodiment)
Next, a second embodiment will be described. One of the differences between the first embodiment and the second embodiment is that, in the second embodiment, the well proximity effect is provided not only in the left-right direction but also in the vertical direction in the vicinity of the cell boundary line. It is the point which made it strengthen further.

  FIG. 7 shows the delay cell 10 according to the present embodiment. As can be seen from this figure, as in the first embodiment, the delay cell 10 is sandwiched between the left and right empty area cells 8 and 8, and the arrangement pattern of the wells of the delay cell 10 and the empty area cell 8 is as follows. Therefore, there are well boundaries on the left and right of the delay cell 10.

  As can be seen from FIG. 7, an N well 22 having the same conductivity type as that of the empty area cell 8 adjacent to the left and right is arranged in the vicinity of the upper cell boundary line of the delay cell 10. Further, in the vicinity of the cell boundary line on the lower side of the delay cell 10, a P-type well 23 having the same conductivity type as that of the empty area cell 8 adjacent to the left and right is arranged.

  By configuring as described above, the distance from the MOS transistor of the delay cell 10 to the well boundary can be shortened not only in the horizontal direction but also in the vertical direction, as indicated by arrows in FIG. For this reason, the well proximity effect can be further enhanced compared to the first embodiment.

  Next, FIG. 8 shows a modification of the delay cell according to the present embodiment. In this modification, in order to avoid the point contact of wells of the same conductivity type, N wells 12 are formed in the vicinity of the left and right cell boundary lines on the upper side of the delay cell 10. Thereby, the MOS transistor can be operated more stably. A P well may be formed in the vicinity of the left and right cell boundary lines below the delay cell 10.

  In the description of this embodiment, the adjacent cells on the left and right of the delay cell are vacant area cells, but may be dummy cells. Alternatively, only one of the N well 22 and the P well 23 may be arranged.

  In addition, the delay cell according to the present embodiment can be manufactured by the method described in the first embodiment by changing the range covered with the resist mask.

  As described above, in this embodiment, by providing the N well 22 and the P well 23 in the vicinity of the upper and lower boundaries of the delay cell 10, the well proximity effect is further enhanced and the characteristics of the MOS transistor are deteriorated. Thereby, the delay amount of the delay cell can be further increased without increasing the area of the delay cell.

(Third embodiment)
Next, a third embodiment will be described. One of the differences between the present embodiment and the first embodiment is that, as described above, in this embodiment, the cells adjacent to the left and right of the delay cell are not the empty area cells but the delay cells. That is, in this embodiment, delay cells are continuously arranged.

  FIG. 9 shows three delay cells 9a, 9b and 9c arranged side by side in the horizontal direction according to the present embodiment. As can be seen from this figure, the delay cell 9b arranged in the center has a well arrangement pattern opposite to the well arrangement pattern of the normal logic cell, like the delay cell according to the first embodiment. . Further, the well arrangement pattern in the delay cells 9a and 9c adjacent to the left and right of the delay cell 9b is the same as that of the normal logic cell.

  With the above configuration, the distance from the MOS transistor to the well boundary can be shortened for each delay cell. Thereby, since the well proximity effect is strengthened, the delay amount of each of the delay cells 9a, 9b and 9c is increased. Also, unlike the first and second embodiments, this embodiment does not arrange empty area cells, so that delay cells having a large delay amount can be arranged at high density.

  Next, FIG. 10 shows a modification of the delay cell according to the present embodiment. In this modification, in order to avoid the point contact of wells of the same conductivity type, the P well 63 is formed in the vicinity of the left and right cell boundary lines on the lower side of the delay cell 9b. Thereby, the MOS transistor can be operated more stably. An N well may be formed in the vicinity of the left and right cell boundary lines above the delay cell 9b.

  In the above description, a configuration in which three delay cells are arranged has been described. However, the present embodiment is not limited to this. In FIG. 9 (FIG. 10), an arbitrary number of delay cells in which the well arrangement pattern is alternately reversed may be arranged along the horizontal direction.

  Next, wiring for connecting a plurality of CMOS inverters formed in each delay cell in series and wiring for supplying a power supply voltage (VDD) and a ground voltage (VSS) will be described with reference to FIGS. .

  11 is obtained by adding a contact 30, an input terminal 31, a wiring 32 between the CMOS inverters, a wiring 33 between the MOS transistor and the well terminal 4, and an output terminal 34 to FIG.

  The wiring 32 connects the CMOS inverters via the contacts 30. That is, as can be seen from FIG. 11, the wiring 32 is connected to the output of the CMOS inverter fabricated in the delay cell 9a (PMOS and NMOS transistor drain regions) and the input of the CMOS inverter fabricated in the delay cell 9b (gate electrode). Connect. Similarly, the output of the CMOS inverter arranged in the delay cell 9b and the input of the CMOS inverter arranged in the delay cell 9c are connected.

  The wiring 33 connects the P type diffusion layer 3 (source region) of the PMOS transistor and the well terminal 4 of the N well, and also connects the N type diffusion layer 2 (source region) of the NMOS transistor and the well terminal 4 of the P well. Connect.

  The input terminal 31 is connected to the gate 1 of the CMOS inverter formed in the delay cell 9a. The output terminal 34 is connected to the output of the CMOS inverter formed in the delay cell 9c (the drain regions of the PMOS and NMOS transistors).

  12 is a diagram in which power supply wirings 35 and 36 for supplying a power supply voltage, ground wirings 37 and 38 for supplying a ground voltage, and a via contact 39 are added to FIG. As can be seen from this figure, the power supply wiring 35 is connected to the wiring 33 of the delay cells 9a and 9c via the via contact 39, and supplies the power supply voltage to the PMOS transistors arranged in the delay cells 9a and 9c. Similarly, the power supply wiring 36 is connected to the wiring 33 of the delay cell 9b through the via contact 39, and supplies the power supply voltage to the PMOS transistor arranged in the delay cell 9b.

  The ground wiring 37 is connected to the wiring 33 of the delay cell 9b through the via contact 39, and supplies the ground voltage to the NMOS transistor arranged in the delay cell 9b. Similarly, the ground wiring 38 is connected to the wiring 33 of the delay cells 9a and 9c via the via contact 39, and supplies the ground voltage to the NMOS transistors arranged in the delay cells 9a and 9c.

  Thus, by providing two pairs of the power supply wirings 35 and 36 and the ground wirings 37 and 38 for the delay cells 9a and 9c and the delay cell 9b, the shapes of the power supply wiring and the ground wiring can be made simple and substantially straight. be able to.

  Note that the delay cell according to the present embodiment can be manufactured in the same manner as the method described in the first embodiment. That is, after a delay cell is manufactured by the method described in the first embodiment, a CMOS inverter including a PMOS transistor and an NMOS transistor may be manufactured in cells adjacent to the delay cell.

  As described above, in this embodiment, the delay cells 9a, 9b, and 9c are alternately arranged in the horizontal direction while inverting the well arrangement pattern, so that the well boundary is formed in the vicinity of the boundary between the left and right adjacent cells. Try to provide it. As a result, delay cells having an increased delay amount can be arranged with high density.

  Further, by providing two pairs of the power supply wiring and the ground wiring, the shape of the power supply wiring and the ground wiring can be made into a simple substantially linear shape.

(Fourth embodiment)
Next, a fourth embodiment will be described. One of the differences between this embodiment and the first embodiment is that, instead of reversing the arrangement pattern of the wells of the delay cells with those of the adjacent cells, at least some of the cells adjacent to the left and right of the delay cells By forming a well having a conductivity type opposite to that of the well of an adjacent cell, a well boundary is provided in the adjacent cell.

  FIG. 13 shows the delay cell 11 according to the present embodiment. As can be seen by comparing this figure with FIG. 3A, the arrangement pattern of the wells of the delay cell 11 is the same as that of the normal logic cell 17. As can be seen from FIG. 13, a P well 43 is formed in a part of the N well 5 (non-logic cell N well) of the empty area cells 8 and 8 sandwiching the delay cell 11, and the P well 6 (non-logic cell) is formed. An N well 42 is formed in a part of the (P well).

  With the above configuration, the distance from the MOS transistor of the delay cell 11 to the well boundary can be shortened in the lateral direction as indicated by the arrow in FIG. Thereby, the threshold voltage of the MOS transistor fabricated in the delay cell 11 due to the well proximity effect increases, and the delay amount of the delay cell 11 increases. As described above, this embodiment has an advantage that the arrangement pattern of the wells of the delay cells does not need to be changed from the normal logic cell pattern.

  As can be seen from FIG. 13, the N well 42 and the P well 43 are arranged so that the wells of the same conductivity type are not point-contacted. However, when point contact is allowed, the width of the empty area cell 8 is increased. The area of the empty area cell 8 may be made smaller by narrowing. Further, only one of the N well 42 and the P well 43 may be formed.

  Next, a method for manufacturing the delay cell according to the present embodiment will be described with reference to FIGS. 14A to 14D. Here, a manufacturing method using a single well structure will be described.

(1) A p-type silicon substrate 101 is prepared. As shown in FIG. 14A, cells 63a, 63b, and 63c are assigned to the surface region of the p-type silicon substrate 101. These cells (63a, 63b, 63c) are arranged adjacent to each other on the left and right and each have a p-type region 101A.

(2) Next, as shown in FIG. 14B, a part of the upper half of the cell 63a and the cell 63c and a part of the lower half are covered with a resist mask 60 by photolithography. Similarly, the lower half of the cell 63b is covered with a resist mask 60.

(3) Next, n-type impurities (for example, phosphorus) are ion-implanted into the p-type silicon substrate 101. Thereafter, the resist mask 60 is peeled off.

  As a result, as shown in FIG. 14C, the N well 5 is formed in a region not covered with the resist mask 60. As described above, due to the well proximity effect, a part of the n-type impurity ions is scattered in the resist mask 60, so that the impurity concentration of the N well 5 is increased accordingly.

(4) Next, a PMOS transistor 50b is formed in the N well 5 of the cell 63b and an NMOS transistor 50a is formed in the P well 6 of the cell 63b by using a conventionally used MOSFET manufacturing technique. Further, well terminals 4 and 4 for fixing the potentials of the N well 5 and the P well 6 are formed.

  Through the above process, a CMOS inverter including the NMOS transistor 50a and the PMOS transistor 50b is formed in the cell 63b, and the cell 63b becomes the delay cell 11. Since nothing is formed in the cells 63a and 63c, the empty cells 8 and 8 are formed. As can be seen from FIG. 13 and FIG. 14D, the upper p-type region 101 </ b> A in the empty region cell 8 corresponds to the P well 43, and the lower N well 5 corresponds to the N well 42.

  Note that the delay cell according to the present embodiment may be manufactured using a twin well structure or a triple well structure as described in the first embodiment, in addition to the above manufacturing method.

  As described above, in the present embodiment, at least part of the empty area cells 8 and 8 adjacent to the left and right of the delay cell 11 are provided with wells (N of the conductivity type opposite to the conductivity type of the wells of the adjacent cells). By forming the well 42 and the P well 43), a well boundary is provided in the empty area cells 8 and 8 adjacent to the left and right of the delay cell 11. Thereby, the well proximity effect can be strengthened, the characteristics of the MOS transistor formed in the delay cell can be deteriorated, and the delay amount of the delay cell can be increased.

  As described above, according to the present embodiment, it is possible to obtain a delay cell having an increased delay amount without increasing the area of the delay cell.

(Fifth embodiment)
Next, a fifth embodiment will be described. In this embodiment, the widths of the N well 42 and the P well 43 in the fourth embodiment are adjusted to obtain a delay cell having a desired delay amount.

  FIG. 15 shows the delay cell 11 according to the present embodiment. As in the fourth embodiment, the empty area cells 8 are arranged adjacent to the left and right of the delay cell 11. As can be seen from FIG. 15, an N well 42 and a P well 43 are formed in the empty area cell 8 adjacent to the right side of the delay cell 11, and the empty area cell 8 adjacent to the left side of the delay cell 11. An N well 52 and a P well 53 are formed. The width (lateral length) of the N well 52 is smaller than that of the N well 42, and the width of the P well 53 is also smaller than that of the P well 43. For this reason, as shown by the arrows in FIG. 15, in the horizontal direction, the distance from the MOS transistor of the delay cell 11 to the well boundary is longer on the left side than on the right side. Thus, by partially increasing the distance to the well boundary, the well proximity effect can be weakened and the delay amount of the delay cell 11 can be reduced.

  As described above, when the delay amount is larger than a desired value, the width of the N well and the P well formed in the empty region cell 8 is reduced to increase the distance between the MOS transistor and the well boundary, thereby delaying the delay. The amount of cell delay can be reduced.

  Next, a case where the delay amount of the delay cell shown in FIG. 15 is still larger than a desired value will be described. FIG. 16 shows a configuration in which the N well 52 and the P well 53 are formed also in the empty area cell 8 adjacent to the right side of the delay cell 11. As indicated by the arrows in FIG. 16, the distance from the MOS transistor of the delay cell 11 to the well boundary in the lateral direction is as long on the left side as that on the right side. For this reason, the delay amount of the delay cell 11 can be further reduced.

  In the above description, the delay amount of the delay cell is reduced by weakening the well proximity effect. On the contrary, if the widths of the N well 42 and the P well 43 are increased, the well proximity effect is enhanced. The delay amount of the delay cell can be increased. That is, a delay cell having a desired delay amount can be obtained by adjusting the widths of the N well 42 and the P well 43 formed in the empty area cells.

  In the present embodiment, the sizes of the N well 42 and the P well 43 of the empty area cell 8 are changed simultaneously, but only one of them may be changed.

  Further, only one of the N well 52 (42) and the P well 53 (43) may be provided.

  Further, the shape of the N well 52 (42) and the P well 53 (43) is not limited to a rectangle, and may be an arbitrary shape so as to satisfy a desired delay amount.

  As described above, according to the present embodiment, the delay amount of the delay cell 11 can be adjusted to a desired value by changing the width of the N well 52 and / or the P well 53 formed in the empty region cell 8. .

  The five embodiments have been described above. Regarding the conductivity type in the above embodiment, the p-type may be replaced with the n-type, and the n-type may be replaced with the p-type. Further, the delay element formed in the delay cell is not limited to the CMOS inverter, and may be composed of other CMOS circuits.

  Based on the above description, those skilled in the art may be able to conceive additional effects and various modifications of the present invention, but the aspects of the present invention are not limited to the individual embodiments described above. . Various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.

  For example, the N well 22 and the P well 23 (described in the second embodiment) provided in the vicinity of the upper and lower cell boundary lines of the delay cell may be applied to the third to fifth embodiments.

It is a figure which shows the layout of the conventional MOS transistor. It is the figure expanded centering on the logic cell arrange | positioned in the center center of FIG. It is a figure which shows the layout of the delay cell which concerns on 1st Embodiment. It is the figure expanded centering on the delay cell arrange | positioned in the middle stage center of FIG. 3A. It is a figure which shows the manufacturing process of the delay cell which concerns on 1st Embodiment. FIG. 4B is a diagram illustrating manufacturing steps of the delay cell according to the first embodiment following FIG. 4A. FIG. 4B is a diagram illustrating the manufacturing process of the delay cell according to the first embodiment, following FIG. 4B. FIG. 4D is a diagram illustrating the manufacturing process of the delay cell according to the first embodiment, following FIG. 4C. It is a figure which shows another manufacturing process of the delay cell which concerns on 1st Embodiment. It is a figure which shows another manufacturing process of the delay cell which concerns on 1st Embodiment following FIG. 5A. FIG. 5B is a diagram showing another manufacturing process for the delay cell according to the first embodiment, following FIG. 5B. FIG. 5D is a diagram illustrating another manufacturing process for the delay cell according to the first embodiment, following FIG. 5C; It is a figure which shows another manufacturing process of the delay cell which concerns on 1st Embodiment following FIG. 5D. It is a figure which shows another manufacturing process of the delay cell which concerns on 1st Embodiment following FIG. 5E. It is a figure which shows the modification of the delay cell which concerns on 1st Embodiment. It is a figure which shows the delay cell which concerns on 2nd Embodiment. It is a figure which shows the modification of the delay cell which concerns on 2nd Embodiment. It is a figure which shows the some delay cell arranged in the horizontal direction which concerns on 3rd Embodiment. It is a figure which shows the modification of the delay cell which concerns on 3rd Embodiment. It is the figure which added the wiring of the CMOS inverter to FIG. It is the figure which added the power supply wiring and grounding wiring of the CMOS inverter to FIG. It is a figure which shows the delay cell which concerns on 4th Embodiment. It is a figure which shows the manufacturing process of the delay cell which concerns on 4th Embodiment. FIG. 14B is a diagram illustrating manufacturing steps of the delay cell according to the fourth embodiment following FIG. 14A. FIG. 14B is a diagram illustrating manufacturing steps of the delay cell according to the fourth embodiment following FIG. 14B. FIG. 14D is a diagram illustrating manufacturing steps of the delay cell according to the fourth embodiment following FIG. 14C. It is a figure which shows the delay cell which concerns on 5th Embodiment. It is another figure which shows the delay cell which concerns on 5th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Gate 2 ... N type diffused layer 3 ... P type diffused layer 4 ... Well terminal 5, 12, 22, 42, 52 ... N well 6, 23, 63, 43, 53 ... P well 7 ... logic cell 8 ... vacant area cells 9, 9a, 9b, 9c, 10, 11 ... delay cell 17 ... normal logic cell 30 ... contact 31 ... Input terminals 32, 33 ... wiring 34 ... output terminals 35, 36 ... power supply wiring 37, 38 ... ground wiring 39 ... via contact 50 ... CMOS inverter 50a ... NMOS transistor 50b ... PMOS transistor 60 ... resist 61a, 61b, 61c ... cell 62a, 62b, 62c ... cell 101 ... p-type silicon substrate 101A ... p-type region 102 ... semi-insulating Silicon substrate 102A ... half Edge regions CB1～CB10 · · · cell-boundary WB1～WB3 · · · well boundary

Claims (5)

A PMOS transistor formed in a logic cell N well and an NMOS transistor formed in a logic cell P well, which constitute a CMOS circuit, and the logic cell N well and the logic cell P well are arranged in a first direction. A plurality of logic cells arranged adjacent to each other in a predetermined well arrangement pattern and arranged along a second direction intersecting the first direction;
Each has a non-logic cell N-well and a non-logic cell P-well arranged adjacent to the logic cell along the second direction and adjacent in a predetermined well arrangement pattern in the first direction. Multiple non-logic cells;
With
The plurality of logic cells include a delay cell using the CMOS circuit as a delay element, and a normal logic cell using the CMOS circuit for applications other than the delay element,
The well arrangement pattern in the delay cell is an inversion of the well arrangement pattern in the non-logic cell adjacent to the delay cell along the second direction,
The well arrangement pattern in the normal logic cell is the same as the well arrangement pattern in the non-logic cell adjacent to the normal logic cell along the second direction.
A semiconductor device. A PMOS transistor formed in a logic cell N well and an NMOS transistor formed in a logic cell P well constituting a CMOS circuit functioning as a delay element, and the logic cell N well and the logic cell P well are A plurality of delay cells arranged adjacent to each other in the first direction and adjacent along a second direction intersecting the first direction;
In the plurality of delay cells, the well arrangement pattern along the first direction of the logic cell N well and the logic cell P well is alternately inverted along the second direction.
A semiconductor device. A semiconductor device according to claim 1 or claim 2, wherein
An N well formed on at least a part of the peripheral edge of the logic cell P well of the delay cell and / or a P well formed on at least a part of the peripheral edge of the logic cell N well of the delay cell; A semiconductor device further comprising: A PMOS transistor formed in a logic cell N well and an NMOS transistor formed in a logic cell P well, which constitute a CMOS circuit, and the logic cell N well and the logic cell P well are arranged in a first direction. A plurality of logic cells arranged adjacent to each other in a predetermined well arrangement pattern and arranged in a second direction intersecting with the first direction;
A plurality of non-logic cells N-wells and non-logic cells P-wells are arranged adjacent to the logic cells along the second direction and are adjacent in the same arrangement pattern as the well arrangement pattern. A logic cell;
With
The plurality of logic cells include a delay cell using the CMOS circuit as a delay element, and a normal logic cell using the CMOS circuit for applications other than the delay element,
The non-logic cell adjacent to the delay cell along the second direction is a P-well formed in at least a part of the non-logic cell N-well and / or at least a part of the non-logic cell P-well Having an N-well formed in
The size and arrangement position of the P well and / or the N well are determined based on a desired delay amount of the delay cell.
A semiconductor device. Preparing a first conductivity type silicon substrate in which first, second and third cells are arranged adjacent to each other on the left and right;
Covering the lower region of the first and third cells and the upper region of the second cell with a resist mask in the silicon substrate,
By ion-implanting a second conductivity type impurity into the silicon substrate, the second conductivity type well is formed in the upper region of the first and third cells and the lower region of the second cell. ,
Peeling the resist mask from the silicon substrate;
Forming a MOS transistor having a source / drain region of the second conductivity type in the upper region of the second cell;
Forming a MOS transistor having the source / drain region of the first conductivity type in the lower region of the second cell;
A method for manufacturing a semiconductor device.

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