JP2010113282A - Method of driving electrophoretic display device, electrophoretic display device, and electronic device - Google Patents

Abstract

An electrophoretic display device driving method capable of erasing an image without generating an afterimage while suppressing power consumption.
A method for driving an electrophoretic display device in which an electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates and a display unit 5 including a plurality of pixels 40A, 40B, and 40C is provided, and an image is erased. In the image erasing step, the pixel 40A that displays the first gradation and forms the image component, and the second gradation that is arranged adjacent to the pixel that forms the contour of the image component are displayed. A method for driving an electrophoretic display device, wherein an image erasing region R including at least a pixel 40B is set, and pixels 40A and 40B constituting the image erasing region R are selectively shifted to a second gradation. It was.
[Selection] Figure 13

Description

  The present invention relates to a method for driving an electrophoretic display device, an electrophoretic display device, and an electronic apparatus.

In an electrophoretic display device, it is known that a thin afterimage along the contour of an image is generated when image erasure is executed by driving only pixels that form a displayed image component. This afterimage is generated when an image in which the contour region is expanded is generated by generating an oblique electric field that crosses between the pixel forming the contour and the pixel forming the background during image display.
Therefore, a driving method for erasing an image by executing erasure on all pixels including pixels whose gradation is not changed is disclosed so that an afterimage of the previous image does not remain when the image is updated (Patent Document). 1).
Special table 2007-512571 gazette

  However, in such a driving method, the electrophoretic particles are driven so that the final display gradation does not change even for a pixel having no change in display. Power consumption at the time increases.

  Therefore, an object of the present invention is to provide an electrophoretic display device driving method, an electrophoretic display device, and an electronic apparatus capable of erasing an image without generating an afterimage while suppressing power consumption.

  An electrophoretic display device driving method according to the present invention is an electrophoretic display device driving method in which an electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, and the display unit includes a plurality of pixels. In the image erasing step for erasing the image, the pixel displaying the first gradation and forming the image component and the second gradation arranged adjacent to the pixel forming the contour of the image component An image erasing area including at least the pixel displaying the image is set, and the pixels constituting the image erasing area are selectively shifted to the second gradation.

  According to this, in the image erasing step, only the pixels constituting the image erasing area set in a wider range than the image component are driven, so that the image can be generated without generating an afterimage while suppressing power consumption. The driving method of the electrophoretic display device that can erase the image can be obtained.

In the image erasing step, the pixel that forms the image component, and the pixel that is arranged adjacent to the pixel that forms the contour of the image component and displays the second gradation, It is preferable to set the image erasing area consisting of:
According to this, an image display area composed of the image component and a band-like area for one pixel that borders the outline of the image is set as the image erasure area. Since only a limited number of the pixels are driven, it is possible to provide an electrophoretic display device driving method capable of erasing the image without generating an afterimage while further reducing power consumption.

  An electrophoretic display device according to the present invention includes an electrophoretic element including electrophoretic particles sandwiched between a pair of substrates, and includes a display unit including a plurality of pixels and a control unit that controls the display unit. When the image of the display unit is erased, the control unit displays the first gradation and forms the image component and the contour of the image component An image erasing area including at least the pixel arranged adjacent to the pixel and displaying the second gradation is set, and the pixels constituting the image erasing area are selectively set to the second gradation. It is made to shift.

  According to this, when erasing the image, only the pixels constituting the image erasing area set in a wider range than the image component are driven, so that afterimage is not generated while suppressing power consumption. The electrophoretic display device can erase the image.

In addition, when erasing the image on the display unit, the control unit is arranged adjacent to the pixel forming the image component and the pixel forming the contour of the image component, and the second floor. It is preferable to set the image erasing area including the pixels displaying the tone.
According to this, by setting an image display area consisting of the image component and a band-like area for one pixel that borders the outline of the image as the image erasing area, the image erasing area is minimized when erasing the image. Since only a limited number of the pixels are driven, it is possible to provide an electrophoretic display device capable of erasing the image without generating an afterimage while further reducing power consumption.

An electronic apparatus of the present invention includes the electrophoretic display device of the present invention.
According to this, when erasing the image, only the pixels constituting the image erasing area set in a wider range than the image component are driven, so that afterimage is not generated while suppressing power consumption. The electronic device can erase the image.

The electrophoretic display device according to the present invention will be described below with reference to the drawings. In the present embodiment, an electrophoretic display device driven by an active matrix method will be described.
Note that this embodiment shows one aspect of the present invention, and does not limit the present invention, and can be arbitrarily changed within the scope of the technical idea of the present invention. Moreover, in the following drawings, in order to make each configuration easy to understand, the actual structure is different from the scale and number of each structure.

FIG. 1 is a schematic configuration diagram of an electrophoretic display device 100 of an active matrix driving system according to the present embodiment.
The electrophoretic display device 100 includes a display unit 5 in which a plurality of pixels 40 are arranged. Around the display unit 5, a scanning line driving circuit 61, a data line driving circuit 62, a controller (control unit) 63, and a common power supply modulation circuit 64 are arranged. The scanning line driving circuit 61, the data line driving circuit 62, and the common power supply modulation circuit 64 are each connected to the controller 63. The controller 63 comprehensively controls these based on image signals and synchronization signals supplied from the host device.

  A plurality of scanning lines 66 extending from the scanning line driving circuit 61 and a plurality of data lines 68 extending from the data line driving circuit 62 are formed in the display unit 5, and the pixels 40 are provided corresponding to the intersection positions thereof. It has been.

  The scanning line driving circuit 61 is connected to each pixel 40 via m scanning lines 66 (Y1, Y2,..., Ym). Under the control of the controller 63, the first to mth rows are connected. The scanning lines 66 are sequentially selected, and a selection signal defining the ON timing of the driving TFT 41 (see FIG. 2) provided in the pixel 40 is supplied via the selected scanning line 66.

The data line driving circuit 62 is connected to each pixel 40 via n data lines 68 (X1, X2,..., Xn), and corresponds to each pixel 40 under the control of the controller 63. An image signal defining 1-bit image data is supplied to the pixel 40.
In this embodiment, when image data (pixel data) “0” is defined, a low-level image signal is supplied to the pixel 40, and when image data (pixel data) “1” is defined, a high level is supplied. The image signal is supplied to the pixel 40.

  The display unit 5 is also provided with a low potential power line 49, a high potential power line 50, a common electrode wiring 55, a first control line 91, and a second control line 92 extending from the common power modulation circuit 64. Each wiring is connected to the pixel 40. Under the control of the controller 63, the common power supply modulation circuit 64 generates various signals to be supplied to each of the above wirings, and electrically connects and disconnects these wirings (high impedance).

FIG. 2 is a circuit configuration diagram of the pixel 40.
As shown in FIG. 2, the pixel 40 includes a driving TFT (Thin Film Transistor) 41 (pixel switching element), a latch circuit (memory circuit) 70, a switch circuit 80, an electrophoretic element 32, and a pixel electrode. 35 and a common electrode 37 are provided. A scanning line 66, a data line 68, a low potential power line 49, a high potential power line 50, a first control line 91, and a second control line 92 are arranged so as to surround these elements. The pixel 40 has an SRAM (Static Random Access Memory) type configuration in which the latch circuit 70 holds an image signal as a potential.

  The driving TFT 41 is a pixel switching element composed of an N-MOS (Negative Metal Oxide Semiconductor) transistor. The gate terminal of the driving TFT 41 is connected to the scanning line 66, the source terminal is connected to the data line 68, and the drain terminal is connected to the data input terminal N 1 of the latch circuit 70. The switch circuit 80 is connected to the data output terminal N 2 and the data input terminal N 1 of the latch circuit 70 and the pixel electrode 35. The electrophoretic element 32 is sandwiched between the pixel electrode 35 and the common electrode 37.

  The latch circuit 70 includes a transfer inverter 70t and a feedback inverter 70f. Both the transfer inverter 70t and the feedback inverter 70f are C-MOS inverters. The transfer inverter 70t and the feedback inverter 70f have a loop structure in which the other output terminal is connected to each other's input terminal, and each inverter has a high potential connected via a high potential power supply terminal PH. A power supply voltage is supplied from the power supply line 50 and the low potential power supply line 49 connected via the low potential power supply terminal PL.

  The transfer inverter 70t has a P-MOS transistor 71 and an N-MOS transistor 72 whose drain terminals are connected to the data output terminal N2. The source terminal of the P-MOS transistor 71 is connected to the high potential power supply terminal PH, and the source terminal of the N-MOS transistor 72 is connected to the low potential power supply terminal PL. The gate terminals of the P-MOS transistor 71 and the N-MOS transistor 72 (input terminal of the transfer inverter 70t) are connected to the data input terminal N1 (output terminal of the feedback inverter 70f).

  The feedback inverter 70f has a P-MOS transistor 73 and an N-MOS transistor 74 whose drain terminals are connected to the data input terminal N1. The gate terminals of the P-MOS transistor 73 and the N-MOS transistor 74 (input terminal of the feedback inverter 70f) are connected to the data output terminal N2 (output terminal of the transfer inverter 70t).

  When pixel data “1” (high level image signal) is stored in the latch circuit 70, a low level signal is output from the data output terminal N 2 of the latch circuit 70. On the other hand, when pixel data “0” (low level image signal) is stored in the latch circuit 70, a high level signal is output from the data output terminal N2.

The switch circuit 80 includes a first transmission gate TG1 and a second transmission gate TG2.
The first transmission gate TG1 includes an N-MOS transistor 81 and a P-MOS transistor 82. The source terminals of the N-MOS transistor 81 and the P-MOS transistor 82 are connected to the first control line 91, and the drain terminals of the N-MOS transistor 81 and the P-MOS transistor 82 are connected to the pixel electrode 35. The gate terminal of the N-MOS transistor 81 is connected to the data input terminal N1 of the latch circuit 70 (the drain terminal of the driving TFT 41), and the gate terminal of the P-MOS transistor 82 is connected to the data output terminal N2 of the latch circuit 70. It is connected to the.

  The second transmission gate TG 2 includes an N-MOS transistor 83 and a P-MOS transistor 84. The source terminals of the N-MOS transistor 83 and the P-MOS transistor 84 are connected to the second control line 92, and the drain terminals of the N-MOS transistor 83 and the P-MOS transistor 84 are connected to the pixel electrode 35. The gate terminal of the N-MOS transistor 83 is connected to the data output terminal N 2 of the latch circuit 70, and the gate terminal of the P-MOS transistor 84 is connected to the data input terminal N 1 of the latch circuit 70.

  Here, when pixel data “1” (high level image signal) is stored in the latch circuit 70 and a low level signal is output from the data output terminal N2, the first transmission gate TG1 is turned on, The potential S <b> 1 supplied through one control line 91 is input to the pixel electrode 35. On the other hand, when pixel data “0” (low level image signal) is stored in the latch circuit 70 and a high level signal is output from the data output terminal N2, the second transmission gate TG2 is turned on, and the second The potential S <b> 2 supplied via the control line 92 is input to the pixel electrode 35.

  FIG. 3 is a partial cross-sectional view of the electrophoretic display device 100 in the display unit 5. The electrophoretic display device 100 has a configuration in which an electrophoretic element 32 formed by arranging a plurality of microcapsules 20 is sandwiched between an element substrate 30 and a counter substrate 31. In the display unit 5, a plurality of pixel electrodes 35 are arranged on the electrophoretic element 32 side of the element substrate 30, and the electrophoretic elements 32 are bonded to the pixel electrodes 35 through an adhesive layer 33.

  The element substrate 30 is a substrate made of glass, plastic, or the like and is not required to be transparent because it is disposed on the side opposite to the image display surface. The pixel electrode 35 is an electrode in which nickel plating and gold plating are laminated in this order on a Cu foil, or an electrode formed of Al, ITO (indium tin oxide), or the like. Although not shown, the scanning line 66, the data line 68, the selection transistor 41, the latch circuit 70, and the like shown in FIGS. 1 and 2 are formed between the pixel electrode 35 and the element substrate 30. .

  On the other hand, the counter substrate 31 is a substrate made of glass, plastic, or the like, and is a transparent substrate because it is disposed on the image display side. A planar common electrode (opposite electrode) 37 facing the plurality of pixel electrodes 35 is formed on the counter substrate 31 on the side of the electrophoretic element 32, and the electrophoretic element 32 is provided on the common electrode 37. The common electrode 37 is a transparent electrode formed of MgAg, ITO, IZO (indium / zinc oxide), or the like.

  In general, the electrophoretic element 32 is formed in advance on the counter substrate 31 side, and is handled as an electrophoretic sheet including the adhesive layer 33. In the manufacturing process, the electrophoretic sheet is handled in a state where a protective release sheet is attached to the surface of the adhesive layer 33. And the display part 5 is formed by affixing the said electrophoretic sheet which peeled off the peeling sheet with respect to the element board | substrate 30 (The pixel electrode 35, various circuits, etc.) which were manufactured separately. For this reason, the adhesive layer 33 exists only on the pixel electrode 35 side.

  FIG. 4 is a schematic cross-sectional view of the microcapsule 20. The microcapsule 20 has a particle size of, for example, about 50 μm and encloses therein a dispersion medium 21, a plurality of white particles (electrophoretic particles) 27, and a plurality of black particles (electrophoretic particles) 26. It is a spherical body. As shown in FIG. 3, the microcapsule 20 is sandwiched between the common electrode 37 and the pixel electrode 35, and one or more microcapsules 20 are arranged in one pixel 40.

The outer shell (wall film) of the microcapsule 20 is formed using a transparent polymer resin such as acrylic resin such as polymethyl methacrylate and polyethyl methacrylate, urea resin, and gum arabic.
The dispersion medium 21 is a liquid that disperses the white particles 27 and the black particles 26 in the microcapsules 20. Examples of the dispersion medium 21 include water, alcohol solvents (methanol, ethanol, isopropanol, butanol, octanol, methyl cellosolve, etc.), esters (ethyl acetate, butyl acetate, etc.), ketones (acetone, methyl ethyl ketone, methyl isobutyl ketone, etc.). ), Aliphatic hydrocarbons (pentane, hexane, octane, etc.), alicyclic hydrocarbons (cyclohexane, methylcyclohexane, etc.), aromatic hydrocarbons (benzene, toluene, benzenes having a long-chain alkyl group ( Xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene)), halogenated hydrocarbons (methylene chloride, chloroform, tetrachloride) Element, and 1,2-dichloroethane), can be exemplified a carboxylate, it may be other oils. These substances can be used alone or as a mixture, and a surfactant or the like may be further blended.

The white particles 27 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white, and antimony trioxide, and are used, for example, by being negatively charged. The black particles 26 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are used by being charged positively, for example.
These pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, compound charge control agents, titanium-based coupling agents, aluminum-based coupling agents, silanes as necessary. A dispersant such as a system coupling agent, a lubricant, a stabilizer, and the like can be added.
Further, instead of the black particles 26 and the white particles 27, for example, pigments such as red, green, and blue may be used. According to such a configuration, red, green, blue, or the like can be displayed on the display unit 5.

FIG. 5 is an explanatory diagram of the operation of the electrophoretic element 20. FIG. 5A shows a case where the pixel 40 displays white (second gradation), and FIG. 5B shows a case where the pixel 40 displays black (first gradation).
5A, the common electrode 37 is held at a relatively high potential and the pixel electrode 35 is held at a relatively low potential. As a result, the negatively charged white particles 27 are attracted to the common electrode 37, while the positively charged black particles 26 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side which is the display surface side, white is recognized.
In the case of black display shown in FIG. 5B, the common electrode 37 is held at a relatively low potential, and the pixel electrode 35 is held at a relatively high potential. As a result, the positively charged black particles 26 are attracted to the common electrode 37, while the negatively charged white particles 27 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side, black is recognized.

  In the electrophoretic display device 100, an image signal is input to the data input terminal N1 of the latch circuit 70 via the driving TFT 41, whereby the latch circuit 70 stores the image signal as a potential. The first control line 91 or the second control line 92 and the pixel electrode 35 are connected by the switch circuit 80 that operates based on the potential output from the data output terminal N2 of the latch circuit 70. As a result, a potential corresponding to the image signal is input to the pixel electrode 35, and the pixel 40 is displayed in black or white based on the potential difference between the pixel electrode 35 and the common electrode 37 as shown in FIG.

[Control unit]
FIG. 6 is a block diagram showing details of the controller 63 provided in the electrophoretic display device 100.
The controller 63 includes a control circuit 161 as a CPU (Central Processing Unit), an EEPROM (Electrically-Erasable and Programmable Read-Only Memory; storage unit) 162, a voltage generation circuit 163, a data buffer 164, and a frame memory 165. A memory control circuit 166 and an image erasure area setting circuit 167.

The control circuit 161 generates control signals (timing pulses) such as a clock signal CLK, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync, and supplies these control signals to each circuit arranged around the control circuit 161.
The EEPROM 162 stores setting values and the like necessary for operation control of each circuit by the control circuit 161. The EEPROM 162 may store preset image information used for displaying the operating state of the electrophoretic display device.
The voltage generation circuit 163 is a circuit that supplies a driving voltage to the scanning line driving circuit 61, the data line driving circuit 62, and the common power supply modulation circuit 64.
The data buffer 164 is an interface unit with the host device in the controller 63, holds the image data D input from the host device, and transmits the image data D to the control circuit 161.
The frame memory 165 has a readable / writable memory space corresponding to the arrangement of the pixels 40 of the display unit 5. The memory control circuit 166 develops the image data D supplied from the control circuit 161 in correspondence with the pixel array of the display unit 5 according to the control signal, and writes it in the frame memory 165. The frame memory 165 sequentially transmits a data group including the stored image data D as an image signal to the data line driving circuit 62.
The data line driving circuit 62 latches the image signal transmitted from the frame memory 165 line by line based on the control signal supplied from the control circuit 161. Then, the latched image signal is supplied to the data line 68 in synchronization with the sequential selection operation of the scanning line 66 by the scanning line driving circuit 61.
The image erasure area setting circuit 167 sets an image erasure area composed of the pixels 40 to be driven when executing image erasure based on the image data D developed in the frame memory 165, and pixel information constituting the image erasure area Is output to the control circuit 161.

[Driving method]
Next, a driving method related to image update in the electrophoretic display device 100 will be described. In the present embodiment, as an example, a driving method in the case where a square image is displayed and then updated to a horizontally long rectangular image will be described.

  FIG. 7 is a flowchart relating to image update. Steps related to image updating include image display step S101, image erasing step S111, and updated image display step S121.

(Image display step)
First, the image display step S101 will be described. The image display step S101 is a step of displaying an image on the display unit 5. FIG. 8 is a timing chart relating to image update. FIG. 9 is a diagram illustrating a change in the display image when the image is updated. FIG. 10 is a diagram illustrating a potential relationship between the pixels 40A, 40B, and 40C in the image display step S101.
8 and 9 show timing charts corresponding to the image display step S101 to the update image display step S121 and the display image on the display unit 5. FIG. Further, in the following description, when a pixel 40 in a certain area is pointed to and any one of the pixels 40A, 40B, and 40C is included in the area, as in “pixel 40 (40A)”, Symbols are added in parentheses.

9 and 10, the pixel 40A is the pixel 40 that forms the contour of the image P1, and the pixel 40B is the pixel 40 that forms the background arranged adjacent to the pixel 40A. The pixel 40C is a pixel 40 that is arranged adjacent to the pixel 40B and forms a background, and is the pixel 40 opposite to the pixel 40A with respect to the pixel 40B. A combination of these pixels 40A, 40B, and 40C can be arbitrarily selected. For example, the pixels 40A, 40B, and 40C illustrated in FIG. 10 are the pixels 40 that belong to the same scanning line 66, but the pixels 40 that belong to the same data line 68 may be used as 40A, 40B, and 40C.
In FIGS. 8 and 10, the subscripts “a”, “b”, and “c” of the reference numerals clearly indicate the three pixels 40 (40A, 40B, and 40C) to be described and the components that belong to them. It is attached to distinguish between the two and has no other intention.

  FIG. 8 shows the potential S1 of the first control line 91, the potential S2 of the second control line 92, the potential Va of the pixel electrode 35a, the potential Vb of the pixel electrode 35b, and the potential Vcom of the common electrode 37. Yes. In FIG. 9, a part of the display unit 5 on which the image P1 is displayed is extracted and displayed by 8 pixels × 8 pixels.

In the driving method of the present embodiment, an image signal is input to the latch circuits 70 (70a, 70b, 70c) of all the pixels 40 (40A, 40B, 40C) prior to image display.
As shown in FIG. 10, in the pixel 40A that forms the image P1 and is displayed black, a high level (H) image signal is input from the data line 68a to the latch circuit 70a via the driving TFT 41a. On the other hand, in the pixels 40B and 40C that form a background and are displayed in white, low level (L) image signals are input from the data lines 68b and 68c to the latch circuits 70b and 70c via the driving TFTs 41b and 41c.

  When an image signal is input to the latch circuits 70a, 70b, and 70c, the potential Vdd of the high potential power supply line 50 is set to a high level (VH) for image display, and the potential Vss of the low potential power supply line 49 is set to a low level ( VL). Thereby, the potential of the data input terminal N1a in the pixel 40A becomes high level (VH; Vdd), and the potential of the data output terminal N2a becomes low level (VL; Vss). Further, the potentials of the data input terminals N1b and N1c in the pixels 40B and 40C are low level (VL; Vss), and the potentials of the data output terminals N2b and N2c are high level (VH; Vdd).

  As described above, when the image signal is input to the latch circuits 70a, 70b, and 70c of the pixels 40A, 40B, and 40C, the high-level potential VH is supplied to the first control line 91 as shown in FIG. The control line 92 is supplied with a low-level potential VL.

In the pixel 40A to which a high level (H) image signal is input, the potential of the data input terminal N1a is high level (VH; Vdd), and the potential of the data output terminal N2a is low level (VL; Vss). As a result, the transmission gate TG1a of the switch circuit 80a is turned on, and the high-level potential VH is supplied from the first control line 91 to the pixel electrode 35a.
In the pixels 40B and 40C to which low level (L) image data is input, the potentials of the data input terminals N1b and N1c are low level (L) and the potentials of the data output terminals N2b and N2c are high level (H). As a result, the transmission gate TG2b of the switch circuit 80b is turned on, and the low-level potential VL is supplied from the second control line 92 to the pixel electrodes 35b and 35c.
The common electrode 37 receives a pulse-like signal that periodically repeats a high level (VH) period and a low level (VL) period.

Then, during the period in which the common electrode 37 is at the low level (VL), a voltage corresponding to the potential difference between the pixel electrode 35a and the common electrode 37 is applied to the electrophoretic element 32, as shown in FIG. Further, the positively charged black particles 26 are attracted to the common electrode 37 side, the negatively charged white particles 27 are attracted to the pixel electrode 35a side, and the pixel 40A is displayed in black, and the square shown in FIG. The image P1 is displayed.
Further, during the period in which the common electrode 37 is at the high level (VH), a voltage corresponding to the potential difference between the pixel electrodes 35b and 35c and the common electrode 37 is applied to the electrophoretic element 32, as shown in FIG. As described above, the negatively charged white particles 27 are attracted toward the common electrode 37, and the positively charged black particles 26 are attracted toward the pixel electrodes 35b and 35c, so that the pixels 40B and 40C are displayed in white to form a background. Is done.

In the driving method according to the present embodiment, a pulse signal that periodically repeats a high level (VH) and a low level (VL) is input to the common electrode 37 for a plurality of periods. This driving method is referred to as “common swing driving” in the present application. The definition of common swing driving is a driving method in which a pulse that repeats a high level (VH) and a low level (VL) is applied to the common electrode 37 for at least one cycle when an image is displayed.
In addition, it is preferable that the frequency and the number of cycles of the common swing drive are appropriately determined according to the specifications and characteristics of the electrophoretic element 32.

  When the square image P1 is displayed, the first control line 91, the second control line 92, and the common electrode 37 are electrically disconnected by the common power supply modulation circuit 64 to be in a high impedance state. In addition, the pixel electrodes 35 (35a, 35b, 35c) to which the voltage is supplied from the first control line 91 and the second control line 92 are also in a high impedance state, and the image display step S101 is completed. At this time, the latch circuit 70 (70a, 70b, 70c) is driven, and the input image signal is stored.

(Image deletion step)
Next, the image erasing step S111 will be described. Prior to that, a case will be described in which only the image P1 is selectively deleted by driving only the pixels 40 (A) forming the image P1.
FIG. 11 is a diagram illustrating a change in the display unit 5 when the image P1 is selectively deleted. FIG. 11A shows a state before the erasing operation, and FIG. 11B shows a state after the erasing operation. When image erasure is executed by driving only the pixels 40 (40A) forming the image P1 in FIG. 11A, the display unit 5 follows the contour of the image P1 as shown in FIG. 11B. Afterimage P2 is generated. This afterimage P2 occurs in the vicinity of the boundary between the pixel 40 (40A) that forms the contour and the pixel 40 (40B) that is arranged adjacent to the pixel 40 (40A) and forms the background.

As shown in FIGS. 8 and 10, when the image P1 is displayed in the image display step S101, a high level (VH) potential is applied to the pixel electrode 35 (35a) of the pixel 40 (40A) forming the image P1. Then, a low level (VL) potential is supplied to the common electrode 37. At this time, an electric field in an oblique direction is generated from the pixel electrode 35 (35a) of the pixel 40 (40A) forming the image P1 toward the common electrode 37 on the background side. Due to this oblique electric field, the vicinity of the boundary between the image P1 and the background is also displayed in black, and the contour portion of the image P1 swells slightly.
Then, when only the image P1 is deleted, only the swelled contour portion remains and becomes an afterimage P2.

  Therefore, in the driving method of the present embodiment, the image P1 is erased by the following driving method described below.

  In the image erasing step S111, an image erasing area consisting of an area for forming the image P1 and an area bordering the outline of the image P1 is set, and only the pixels 40 (40A, 40B) constituting the image erasing area are driven. In this step, the image P1 is erased. FIG. 12 is a diagram illustrating a potential relationship between the pixels 40A, 40B, and 40C according to the image erasing step S111. FIG. 13 is a diagram showing the image erasing region R. FIG. 12 is a drawing corresponding to FIG. 10, and the same reference numerals are given to the components common to FIG. 10. FIG. 13 shows an image P1 and an image erasing region R.

  Here, a method for setting the image erasing region R will be described. The image erasure area setting circuit 167 extracts, from the image data D developed in the frame memory 165, the background side pixel 40 (40B) arranged adjacent to the pixel 40 (40A) that forms the contour of the image P1. . The pixels 40 (40B) extracted in this way constitute a band-like region having a width corresponding to one pixel bordering the outline of the image P1. These pixels 40 (40B) may be extracted by a general method adopted in image processing software, for example.

  Then, the image erasure area setting circuit 167 sets, as the image erasure area R, an area composed of the pixels 40 (40A) that form the image P1 and the pixels 40 (40B) that border the outline of the image P1. The set image erasing area R is an area obtained by expanding the image P1 by one pixel outward as shown in FIG.

  Pixel information constituting the image erasing region R is output from the image erasing region setting circuit 167 to the control circuit 161, and the control circuit 161 generates image data D for erasing the image. The image erasing image data D created by the control circuit 161 is developed in the frame memory 165 and then input to the latch circuit 70 (70a, 70b, 70c) of each pixel 40 (40A, 40B, 40C). The

  In the present embodiment, the pixels 40 (40B) bordering the image P1 are extracted from the image data D after being developed in the frame memory 165. However, the control circuit 161 analyzes the image data D before being developed. By doing so, you may make it extract the pixel 40 (40B) which borders the outline of the image P1. In this case, the control circuit 161 consistently executes from the setting of the image erasing area R to the creation of image data D for erasing the image.

  FIG. 14 is a diagram showing the image signal input at the time of erasing the image in correspondence with the display unit 5. As shown in FIG. 14, the high-level (H) image signal is input to an area obtained by expanding the image P1 by one pixel outward, and the low-level (L) image signal surrounds the image erasing area R. Is input.

In the pixel 40 (40A, 40B) to which the high level (H) image signal is input, the transmission gate TG1 (TG1a, TG1b) is in the on state, and the pixel to which the low level (L) image signal is input. At 40 (40C), the transmission gate TG2 (TG2c) is on.
When an image signal is input to the latch circuit 70 (70a, 70b, 70c), the potentials of the high potential power line 50 and the low potential power line 49 are set to image display potentials (VH, VL).

When the image signal for erasing the image is input as described above, a low level potential (VL) is supplied to the first control line 91 as shown in FIG. 8, and the second control line 92 is set to a high impedance state. The The common electrode 37 is supplied with a pulse signal that repeats a high level (VH) period and a low level (VL) period.
50 and the potential of the low-potential power line 49 are set to image display potentials (VH, VL).

  The pixel electrode 35 (35a, 35b) of the pixel 40 (40A, 40B), to which the high level (H) image signal is input to the latch circuit 70, is connected to the first control line 91 and is at the low level (VL). A potential is supplied. On the other hand, the pixel electrode 35 (35c) of the pixel 40 (40C), to which the low-level (L) image signal is input to the latch circuit 70, is connected to the second control line 92 and is brought into a high impedance state.

Then, in the pixel 40 (40A, 40B) constituting the image erasing region R to which the high level (H) image signal is input, the pixel is in the period when the high level (VL) potential is supplied to the common electrode 37. A voltage corresponding to the potential difference between the electrode 35 (35a, 35b) and the common electrode 37 is applied to the electrophoretic element 32. Thereby, in the image erasing region R, the black particles 26 move to the pixel electrode 35 side, the white particles 27 move to the common electrode 37 side, and the image P1 is erased.
At this time, since the pixel 40 (40B) bordering the contour of the image P1 is driven, the black particles 26 move to the pixel electrode 35 side and the white particles 27 are common electrodes even in the region swollen from the contour of the image P1. Since the image moves to the side 37, no afterimage is generated after the image P1 is erased.

  During a period when a low level (VL) potential is supplied to the common electrode 37, the pixel electrode 35 (35 a, 35 b) and the common electrode 37 are at the same potential, and the black particles 26 and the white particles 27 hardly move. Does not affect.

On the other hand, in the pixel 40 (40C) to which the low-level (L) image signal is input, the pixel electrode 35 (35c) is in a high impedance state, so even if a pulse is supplied to the common electrode 37, the black particles The white display is maintained with little influence on the motion of the white particles 26 and the white particles 27.
From the above, as shown in FIG. 9B, when the image P1 is erased, the display unit 5 is displayed in white over the entire area.

  Note that the same signal as the pulse input to the common electrode 37 may be input to the second control line 92. In this case, in the pixel 40 (40C) to which the low-level image signal is input, the pixel electrode 35 (35c) and the common electrode 37 have the same potential, and the movement of the black particles 26 and the white particles 27 is almost affected. Therefore, the white display of the background can be maintained.

  Here, as an example of the signal input to the common electrode 37 in the image erasing step S111, the high level potential (VH) is 15V, the low level potential (VL) is 0V, the pulse width and the number of pulses are 20 ms ×. 30 pulses and 200 ms × 4 pulses are continuous signals.

  When the image P1 is erased, as shown in FIG. 8, the first control line 91, the second control line 92, and the common electrode 37 are set in a high impedance state, and the process proceeds to the update image display step S121.

(Updated image display step)
The update image display step S121 is a step of displaying the update image P11 shown in FIG. The updated image display step S121 is driven in the same manner as the image display step S101 after the image signal for the updated image is input to the latch circuit 70 of each pixel 40.

  FIG. 15 is a diagram illustrating a potential relationship between the pixels 40A, 40B, and 40C in the updated image display step S121. FIG. 15 is a drawing corresponding to FIG. 10 and FIG. 12, and the same reference numerals are given to components common to these drawings.

When the process proceeds to the update image display step S <b> 121, the image data D for the update image is output from the control circuit 161 to the frame memory 165. In the frame memory 165, the image data D is developed into an image signal for each pixel 40, and then the image signal is input to the latch circuit 70 of each pixel 40.
Since the pixels 40A, 40B, and 40C are all the pixels 40 that form the updated image P11, as shown in FIG. 15, the latch circuits 70a, 70b, and 70c of the pixels 40A, 40B, and 40C have a high level (H ) Image signal is input.

  In these pixels 40 (40A, 40B, 40C) to which the high level (H) image signal is input to the latch circuit 70, the transmission gate TG1 (TG1a, TG1b, TG1c) is in the ON state. In the pixel 40 to which the low level (L) image signal is input to the latch circuit 70, the transmission gate TG2 is in the on state.

  When an image signal is input to the latch circuit 70, the potentials (Vdd, Vss) of the high potential power line 50 and the low potential power line 49 are set to image display potentials (VH, VL). Then, as shown in FIG. 8, a high level potential (VH) is supplied to the first control line 91, and a low level potential (VL) is supplied to the second control line 92. The common electrode 37 is supplied with a pulse signal that repeats a high level (VH) period and a low level (VL) period.

The pixel electrode 35 (35a, 35b, 35c) of the pixel 40 (40A, 40B, 40C), to which the high level (H) image signal is input to the latch circuit 70, is connected to the first control line 91 and is at the high level. A potential of (VH) is supplied.
The pixel electrode 35 of the pixel 40 to which the low level (L) image signal is input to the latch circuit 70 is connected to the second control line 92 and supplied with a low level (VL) potential.

Then, the pixels 40 (40A, 40B, 40C) to which the high-level (H) image signal is input are displayed in black, and the horizontally-long rectangular update image P11 shown in FIG. 9C is displayed. The pixel 40 to which the low level (L) image signal is input is displayed in white, and the background of the updated image P11 is displayed.
As shown in FIG. 9C, only the image P11 is displayed on the display unit 5, and the afterimage of the previous image P1 does not remain.

When the updated image P11 is displayed, the first control line 91, the second control line 92, and the common electrode 37 are brought into a high impedance state, and the updated image display step S121 is completed.
When the image is continuously updated, the image erasing step S111 and the updated image display step S121 may be repeatedly executed.

  According to the electrophoretic display device 100 provided with such a driving method, the following effects can be obtained.

  First, an image erasing region R is set, which includes pixels 40 (40A, 40B) that form the image P1 and pixels 40 (40C) that form a band-shaped region for one pixel that borders the outline of the image P1. Therefore, the number of pixels to be driven in the image erasing step S111 is minimized, and the image P1 can be erased without generating an afterimage while suppressing power consumption.

In addition, the image erasing region R is preferably set in accordance with the afterimage generation form that varies depending on the characteristics of the electrophoretic element 32.
For example, an area where the image P1 is expanded by two pixels or more may be set as the image erasing area R. In this case, since the number of pixels to be driven increases, the power consumption is inferior. However, since a wider range of pixels 40 are driven in the image erasing step S111, the afterimage can be prevented more reliably. .

  The product of the voltage of the pulse applied to the electrophoretic element 32 and the voltage application time may be changed as necessary depending on the operating temperature range, applied voltage, individual difference of the electrophoretic sheet, and the like.

[Electronics]
Next, a case where the electrophoretic display device 100 of the above embodiment is applied to an electronic device will be described.
FIG. 16 is a front view of the wrist watch 1000. The wrist watch 1000 includes a watch case 1002 and a pair of bands 1003 connected to the watch case 1002.
A display unit 1005 including the electrophoretic display device 100 of the above-described embodiment, a second hand 1021, a minute hand 1022, and an hour hand 1023 are provided on the front surface of the watch case 1002, and an operator is provided on the side surface of the watch case 1002. The crown 1010 and the operation button 1011 are provided. The crown 1010 is connected to a winding stem (not shown) provided inside the case, and is integrally provided with the winding stem so that it can be pushed and pulled in multiple stages (for example, two stages) and can be rotated. . The display unit 1005 can display a background image, a character string such as date and time, or a second hand, a minute hand, and an hour hand.

FIG. 17 is a perspective view illustrating a configuration of the electronic paper 1100. An electronic paper 1100 includes the electrophoretic display device 100 of the above embodiment in a display area 1101. The electronic paper 1100 is flexible and includes a main body 1102 made of a rewritable sheet having the same texture and flexibility as conventional paper.
FIG. 18 is a perspective view showing the configuration of the electronic notebook 1200. An electronic notebook 1200 is obtained by bundling a plurality of electronic papers 1100 shown in FIG. The cover 1201 includes display data input means (not shown) for inputting display data sent from an external device, for example. Thereby, according to the display data, the display content can be changed or updated while the electronic paper is bundled.

According to the wristwatch 1000, the electronic paper 1100, and the electronic notebook 1200 described above, since the electrophoretic display device according to the present invention is employed in the display unit, the image is erased without generating an afterimage while suppressing power consumption. It has become an electronic device that can.
Note that the electronic devices illustrated in FIGS. 16 to 18 are examples of the electronic device according to the present invention, and do not limit the technical scope of the present invention. For example, the electrophoretic display device according to the present invention can be suitably used for a display portion of an electronic device such as a mobile phone or a portable audio device.

1 is a schematic configuration diagram of an electrophoretic display device 100. FIG. 2 is a circuit configuration diagram of a pixel 40. FIG. 3 is a partial cross-sectional view of an electrophoretic display device 100 in a display unit 5. FIG. 2 is a schematic cross-sectional view of a microcapsule 20. FIG. FIG. 5 is an operation explanatory diagram of the electrophoretic element 20. 3 is a block diagram showing details of a controller 63. FIG. It is a flowchart figure concerning an image update. It is a timing chart figure concerning image updating. It is a figure which shows the change of the display image at the time of image update. It is a figure which shows the electric potential relationship of pixel 40A, 40B, 40C. It is a figure which shows the change of the display part 5 when the image P1 is selectively deleted. It is a figure which shows the electric potential relationship of pixel 40A, 40B, 40C. 5 is a diagram showing an image erasing region R. FIG. FIG. 6 is a layout diagram of image signals at the time of image erasure. It is a figure which shows the electric potential relationship of pixel 40A, 40B, 40C. 1 is a front view of a wrist watch 1000. FIG. 1 is a perspective view illustrating a configuration of electronic paper 1100. FIG. 1 is a perspective view illustrating a configuration of an electronic notebook 1200. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 5 ... Display part, 20 ... Microcapsule, 26 ... Black particle (electrophoretic particle), 27 ... White particle (electrophoretic particle), 32 ... Electrophoretic element, 35, 35a, 35b, 35c ... Pixel electrode, 37 ... Common Electrode, 40, 40A, 40B, 40C ... Pixel, 70, 70a, 70b, 70c ... Latch circuit, 100 ... Electrophoretic display device, 161 ... Control circuit (control unit), 167 ... Image erasure area setting circuit, D ... Image Data, P1... Image, P11... Update image, R... Image deletion area, S101... Image display step, S111.

Claims (5)

An electrophoretic display device driving method in which an electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates and a display unit including a plurality of pixels is provided.
In the image erasing step of erasing the image,
The pixel displaying a first gradation and forming an image component; and the pixel arranged adjacent to the pixel forming the contour of the image component and displaying a second gradation; A method for driving an electrophoretic display device, comprising: setting an image erasing area including at least a pixel, and selectively shifting the pixels constituting the image erasing area to the second gradation. In the image erasing step,
Setting the image erasing area comprising the pixels forming the image component and the pixels arranged adjacent to the pixel forming the contour of the image component and displaying the second gradation The method for driving an electrophoretic display device according to claim 1. An electrophoretic display device having an electrophoretic element including electrophoretic particles between a pair of substrates and having a display unit composed of a plurality of pixels and a control unit for controlling the display unit,
When erasing an image on the display unit, the control unit displays the first gradation and forms the image component adjacent to the pixel forming the contour of the image component. An image erasing area including at least the pixel arranged and displaying the second gradation is set, and the pixels constituting the image erasing area are selectively shifted to the second gradation. An electrophoretic display device.   The control unit, when erasing the image on the display unit, is arranged adjacent to the pixel forming the image component and the pixel forming the contour of the image component, and the second gradation is set. The electrophoretic display device according to claim 3, wherein the image erasing region including the pixel being displayed is set.   An electronic apparatus comprising the electrophoretic display device according to claim 3.

Images