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JP2010103279A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2010103279A
JP2010103279A JP2008272775A JP2008272775A JP2010103279A JP 2010103279 A JP2010103279 A JP 2010103279A JP 2008272775 A JP2008272775 A JP 2008272775A JP 2008272775 A JP2008272775 A JP 2008272775A JP 2010103279 A JP2010103279 A JP 2010103279A
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JP
Japan
Prior art keywords
screw
mounting portion
hole
lead frame
semiconductor device
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Pending
Application number
JP2008272775A
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Japanese (ja)
Inventor
Toshiyuki Tamate
登志幸 玉手
Yoshimiki Kikuchi
義幹 菊池
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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Priority to JP2008272775A priority Critical patent/JP2010103279A/en
Publication of JP2010103279A publication Critical patent/JP2010103279A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that is compact with improved efficiency of heat dissipation and prevents the occurrence of cracks. <P>SOLUTION: The semiconductor device 10 includes: a lead frame 12, where a chip mount 14 to which a semiconductor chip 11 is mounted, a mounting part 15 where a screw hole 18 is formed in a cutout shape at one end side of the chip mount, and a terminal for making connection to the outside at the other end side of the chip mount are formed integrally; and a semiconductor package 13 for exposing the chip of the terminal and sealing the lead frame by resin to have a screw through-hole according to the shape of the screw hole. In the semiconductor device, the cutout shape of the screw hole is such that an opening is closed incompletely. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は半導体装置に関し、特に取付け孔を備えた半導体装置に関するものである。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a mounting hole.

従来の半導体装置が樹脂封止半導体装置として特許文献１に開示されている。この半導体装置は、半導体チップ１と、該半導体チップ１が搭載されるリードフレームと、半導体チップが搭載されたリードフレームの一部を樹脂封止する半導体パッケージ（樹脂体７）と、を備える。   A conventional semiconductor device is disclosed in Patent Document 1 as a resin-encapsulated semiconductor device. This semiconductor device includes a semiconductor chip 1, a lead frame on which the semiconductor chip 1 is mounted, and a semiconductor package (resin body 7) for resin-sealing a part of the lead frame on which the semiconductor chip is mounted.

リードフレームは、チップ搭載部（リードフレームマウント部２）と、端子部（リード端子３）とを備えており、これらが一体的に形成されている。   The lead frame includes a chip mounting portion (lead frame mount portion 2) and a terminal portion (lead terminal 3), which are integrally formed.

端子部は、その先端が半導体パッケージの一端の側面から導出されるように当該半導体パッケージから露出しており、外部と半田を介して電気的に接続される。   The terminal portion is exposed from the semiconductor package such that the tip thereof is led out from the side surface of one end of the semiconductor package, and is electrically connected to the outside via solder.

また、半導体パッケージは、他端の表面から裏面に亘って貫通するネジ貫通孔（取付孔７１）が設けられている。   Further, the semiconductor package is provided with a screw through hole (mounting hole 71) penetrating from the surface of the other end to the back surface.

外部と電気的に接続する場合、半導体装置は、ネジ貫通孔にネジが挿入され、該ネジと螺合されることで放熱フィンなどに固定される。   When electrically connecting to the outside, the semiconductor device is fixed to a heat radiating fin or the like by inserting a screw into the screw through hole and screwing the screw into the screw.

ネジ貫通孔は、リードフレーム上のチップ搭載部と一体形成された取付け部のネジ孔に応じて樹脂形成されており、樹脂封止されるリードフレームの終端から離れた位置にネジ貫通孔が形成される。 The screw through hole is resin-formed according to the screw hole of the mounting part formed integrally with the chip mounting part on the lead frame, and the screw through hole is formed at a position away from the end of the lead frame sealed with resin. Is done.

ここで、ネジ孔が形成される取付け部について説明する。
例えば引用文献１の図２に於いて、リードフレームは、チップ搭載部と、端子部とを備えており、更に引用文献１の図２において具体的な名称が付されていない取付け部を備えている。 Here, the attachment part in which the screw hole is formed will be described.
For example, in FIG. 2 of the cited document 1, the lead frame includes a chip mounting portion and a terminal portion, and further includes a mounting portion that is not given a specific name in FIG. 2 of the cited document 1. Yes.

取付け部はチップ搭載部の一端側において延伸しており、チップ搭載部の他端側には端子部が延伸しており、取付け部にはネジ貫通孔の形状に応じたネジ孔が形成されている。   The mounting portion extends on one end side of the chip mounting portion, the terminal portion extends on the other end side of the chip mounting portion, and a screw hole corresponding to the shape of the screw through hole is formed in the mounting portion. Yes.

ところで、前記した取付け部を有しないリードフレームを備えた半導体装置が引用文献１の図１に開示されている。   By the way, a semiconductor device including a lead frame that does not have the above-described mounting portion is disclosed in FIG.

この半導体装置のネジ貫通孔の位置とリードフレームの関係を説明すると、リードフレームはチップ搭載部の一端側において、延伸して形成される取付け部が無い。従って、リードフレームにはネジ貫通孔に対応する取付け部が無く、半導体パッケージに形成されるネジ貫通孔は、リードフレームと絶縁されている。   The relationship between the position of the screw through hole of the semiconductor device and the lead frame will be described. The lead frame has no attachment portion formed by extending on one end side of the chip mounting portion. Therefore, the lead frame does not have a mounting portion corresponding to the screw through hole, and the screw through hole formed in the semiconductor package is insulated from the lead frame.

また、取付け部が無いことから、ネジ貫通孔の強度は半導体パッケージの有する固有の強度に依存するため、ネジ貫通孔の周囲が取り付け部で補強されることがなく、ネジ孔貫通孔に挿嵌されるネジの係合による押圧集中によるクラックの発生を危惧する余り、十分な螺合強度を得ることができない。
更に、取付け部が無いことから、半導体チップからの発熱はリードフレームのチップ搭載部と端子部へのみ伝導するため、取付け部を介した放熱伝導を得ることができず、結果として放熱効率が悪い。 In addition, since there is no mounting part, the strength of the screw through hole depends on the inherent strength of the semiconductor package, so the periphery of the screw through hole is not reinforced by the mounting part, and is inserted into the screw hole through hole. There is a concern about the occurrence of cracks due to pressure concentration due to the engagement of the screws, and sufficient screwing strength cannot be obtained.
Furthermore, since there is no mounting portion, heat generated from the semiconductor chip is conducted only to the chip mounting portion and the terminal portion of the lead frame, so heat conduction through the mounting portion cannot be obtained, resulting in poor heat dissipation efficiency. .

ところで、引用文献１の図２には、取付け部を有するリードフレームを備えた半導体装置が開示されている。   Incidentally, FIG. 2 of the cited document 1 discloses a semiconductor device including a lead frame having a mounting portion.

この構成の特徴は、ネジ貫通孔の強度が半導体パッケージの固有の強度と、封止されたリードフレームの取付け部の強度とで決定され、これらの強度により引用文献１の図１に示す半導体装置よりも、螺合強度を得ることができる。更に、半導体チップからの発熱はリードフレームのチップ搭載部と端子部とに加え、取付け部にも伝導させることができ、引用文献１の図１に示す半導体装置よりも、放熱面積を得ることができる。   The feature of this configuration is that the strength of the screw through hole is determined by the inherent strength of the semiconductor package and the strength of the mounting portion of the sealed lead frame, and the semiconductor device shown in FIG. As a result, screwing strength can be obtained. Further, heat generated from the semiconductor chip can be conducted to the mounting portion in addition to the chip mounting portion and the terminal portion of the lead frame, and a heat radiation area can be obtained as compared with the semiconductor device shown in FIG. it can.

しかし、前記した効果を得ることができるものの、リードフレームは取付け部の構成が必要となり、結果的に半導体装置の小型化を図ることができない。   However, although the above-described effects can be obtained, the lead frame requires a configuration of the mounting portion, and as a result, the semiconductor device cannot be reduced in size.

また、引用文献１の図３には、取付け部に切り欠きが施されたリードフレームを備えた半導体装置が開示されている。この切り欠きは、前記したネジ孔に相当しており、丸孔ではなくリードフレームの終端を開放するように矩形に切り欠いた形状を有している。これにより、矩形に切り欠いた部位にネジ貫通孔を形成することができ、もって半導体装置の小型化を図ることができる。   Further, FIG. 3 of the cited document 1 discloses a semiconductor device including a lead frame in which a mounting portion is notched. This notch corresponds to the above-described screw hole, and is not a round hole but has a shape notched into a rectangle so as to open the end of the lead frame. As a result, a screw through hole can be formed in a portion cut out in a rectangular shape, and the semiconductor device can be miniaturized.

しかし、前記した効果を得ることができるものの、矩形に切り欠くことで、ネジ貫通孔のためのネジ孔としての機能を十分に得ることができない。つまり十分な螺合強度を得ようとすると、クラックが発生し易く、更に矩形の切り欠が施された取付け部は、放熱のための面積が狭く、十分な放熱効果を得ることができない等の問題が生じる。   However, although the above-described effect can be obtained, the function as a screw hole for the screw through hole cannot be sufficiently obtained by cutting out into a rectangular shape. In other words, if sufficient screwing strength is obtained, cracks are likely to occur, and the mounting portion with a rectangular cutout has a small area for heat dissipation, and a sufficient heat dissipation effect cannot be obtained. Problems arise.

特許登録２５５５７３３号Patent registration 2555733

従って、本発明は上記した課題に鑑みてなされたものであり、本発明の目的は小型でありながら、放熱効率が良く、かつクラック発生の防止を図り得る半導体装置を提供することにある。   Accordingly, the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device that is small in size, has good heat dissipation efficiency, and can prevent the occurrence of cracks.

半導体チップが搭載されるチップ搭載部と該チップ搭載部の一端側にネジ孔が切り欠けられた形状に形成された取付け部と前記チップ搭載部の他端側に外部と接続するための端子部とが一体形成されたリードフレームと、前記端子部の先端が露出すると共に前記ネジ孔の形状に応じたネジ貫通孔を有するように前記リードフレームを樹脂封止する半導体パッケージと、を備えた半導体装置において、前記ネジ孔の切り欠けられた形状は、開口が不完全に閉塞することを特徴とする。   A chip mounting portion on which a semiconductor chip is mounted, a mounting portion formed in a shape in which a screw hole is cut out on one end side of the chip mounting portion, and a terminal portion for connecting to the outside on the other end side of the chip mounting portion And a semiconductor package in which the lead frame is resin-sealed so that the tip of the terminal portion is exposed and has a screw through hole corresponding to the shape of the screw hole. In the device, the notched shape of the screw hole is characterized in that the opening is incompletely closed.

前記取付け部は、前記ネジ孔の開口が不完全閉塞することでΩ字状の開口孔を有する形状であってもよい。   The mounting portion may have a shape having an Ω-shaped opening due to incomplete closing of the opening of the screw hole.

本発明の半導体装置によれば、小型化のためにリードフレームの取付け部をネジ孔で切り欠いた形状としても、ネジ孔の切り欠いた形状が不完全に閉塞しているため、ネジ孔の周囲のほとんどが取囲まれた状態の取り付け部となる。従って、従来の切り欠きの一端が完全に開放された形状と比較して放熱面積を得ることができ、もって放熱効率の向上を図ることができる。更に本発明の半導体装置によれば、小型化のためにリードフレームの取付け部にネジ孔を切り欠いた形状としても、取り付け部を樹脂封止する半導体パッケージにおいてネジ孔形状に応じて形成されるネジ孔貫通孔の周囲のほとんどが取囲まれる。このようにネジ孔が従来の切り欠きの一端が完全に開放された形状と比較して補強される。これにより、ネジ孔貫通孔に挿嵌されるネジの係合による押圧を分散することができ、もってクラックの発生を防止することができる。   According to the semiconductor device of the present invention, even if the mounting portion of the lead frame is notched with a screw hole for miniaturization, the notched shape of the screw hole is incompletely closed. It becomes an attachment part in a state where most of the surroundings are surrounded. Therefore, the heat radiation area can be obtained as compared with the conventional shape in which one end of the notch is completely opened, and thus the heat radiation efficiency can be improved. Further, according to the semiconductor device of the present invention, even if the screw hole is cut out in the lead frame mounting portion for miniaturization, the semiconductor package in which the mounting portion is resin-sealed is formed according to the screw hole shape. Most of the periphery of the screw hole through hole is surrounded. In this way, the screw hole is reinforced compared to the conventional shape in which one end of the notch is completely opened. Thereby, the press by the engagement of the screw inserted by the screw hole through-hole can be disperse | distributed, and it can prevent generation | occurrence | production of a crack.

以下、図面を用いて、本発明の印刷装置の実施の形態を詳細に説明するが、以下の説明では、各実施の形態に用いる図面について同一の構成要素は同一の符号を付し、かつ重複する説明は可能な限り省略する。   Hereinafter, embodiments of a printing apparatus according to the present invention will be described in detail with reference to the drawings. In the following description, the same components are denoted by the same reference numerals in the drawings used in the embodiments, and overlapped. The description to be omitted is omitted as much as possible.

本発明の半導体装置１０は、図１に示すように、トランジスタなどの半導体チップ１１、導電性を有するリードフレーム１２と、絶縁性を有する半導体パッケージ１３とを備える。   As shown in FIG. 1, the semiconductor device 10 of the present invention includes a semiconductor chip 11 such as a transistor, a conductive lead frame 12, and an insulating semiconductor package 13.

リードフレーム１２は、半導体パッケージ１３の成型までの工程に於いて、数個から数十個連ねるように、複数のリードフレーム１２がプレス加工によって連成される。リードフレーム１２の連成は、タイバーと称される外枠によって成されている。   In the process up to the molding of the semiconductor package 13, the lead frame 12 is formed by press working so that several to several tens of lead frames 12 are connected. The lead frame 12 is coupled by an outer frame called a tie bar.

前記したように連成されたリードフレーム１２は、半導体パッケージ１３の成型後に、プレス加工により外枠から切断して個別の半導体装置１０となる。   The lead frames 12 coupled as described above are cut from the outer frame by press working after the semiconductor package 13 is molded, and become individual semiconductor devices 10.

半導体パッケージ１３は、絶縁性の樹脂であり、電気的絶縁性、機械的強度、難燃性およびモールド成型性等を考慮して樹脂成分以外に骨材として配合されるフィラー材他、フィラーと樹脂の結合を強化するカップリング剤、樹脂を熱効果させる硬化剤（フェーノールノボラック樹脂）等が混合されたものであり、一般的にエポキシコンパウンドあるいはシリコーンコンパウンドなどと称されている。   The semiconductor package 13 is an insulating resin, a filler material that is blended as an aggregate in addition to the resin component in consideration of electrical insulation, mechanical strength, flame retardancy, moldability, and the like, filler and resin A coupling agent that reinforces the bonding of the resin, a curing agent (phenol novolac resin) that heats the resin, and the like are mixed, and is generally referred to as an epoxy compound or a silicone compound.

フィラー材は、電気的絶縁性が有り高熱伝導性且、低熱膨張率を有するシリカを多量に含有しており、このシリカ材は固形物で有りエポキシ樹脂に比べ非常に硬いのでトランスファーモールドにおける硬化後において骨材として作用する。これにより半導体パッケージ１３は、強度を得ることができ、もって熱膨張による半導体チップ１１への熱応力を低減する効果がある。   The filler material contains a large amount of silica that has electrical insulation, high thermal conductivity, and low coefficient of thermal expansion. This silica material is solid and very hard compared to the epoxy resin, so it is hardened after transfer molding. Acts as an aggregate. As a result, the semiconductor package 13 can obtain strength, and has the effect of reducing thermal stress on the semiconductor chip 11 due to thermal expansion.

前記した特性を有する半導体パッケージ１３は、リードフレーム１２の一部が露出するように封止する。   The semiconductor package 13 having the above-described characteristics is sealed so that a part of the lead frame 12 is exposed.

リードフレーム１２は、半導体チップ１１が搭載されて半田を介して電気的に接続されるチップ搭載部１４と、該チップ搭載部１４の一端側に延在する取付け部１５と、チップ搭載部１４の他端側で延在する端子部１６とを備えており、これらの構成が一体的に形成されている。   The lead frame 12 includes a chip mounting portion 14 on which the semiconductor chip 11 is mounted and electrically connected via solder, an attachment portion 15 extending to one end side of the chip mounting portion 14, and the chip mounting portion 14. The terminal part 16 extended in the other end side is provided, and these structures are integrally formed.

また、前記リードフレーム１２の作成には、打ち抜きや曲げ加工を行うことができるプレス機が用いられており、該プレス機により例えば導電性の板部材にプレス加工が施されて、取付け部１５、チップ搭載部１４および端子部１６が一体的に形成される。   The lead frame 12 is produced by using a press machine that can perform punching and bending, and the press machine performs press work on, for example, a conductive plate member, and the attachment portion 15, The chip mounting part 14 and the terminal part 16 are integrally formed.

プレス加工が施される板部材は、熱伝導性の高い銅材などである。また、鉄を数パーセント含有させ、強度を持たせても良い。   The plate member to be pressed is a copper material having high thermal conductivity. Moreover, iron may be contained in several percent to give strength.

リードフレーム１２の中央部にはチップ搭載部１４が設けられており、該チップ搭載部１４は、樹脂封止される半導体パッケージ１３において、該半導体パッケージ１３のほぼ中央に位置する。このチップ搭載部１４には、半田を介して半導体チップ１１を搭載するためにニッケルめっき等が施される。更に、このめっきはバリアメタルとして作用する。これによりリードフレーム１２の銅成分が半導体チップ１１へ拡散することを防止することができる。   A chip mounting portion 14 is provided in the center portion of the lead frame 12, and the chip mounting portion 14 is located substantially at the center of the semiconductor package 13 in the semiconductor package 13 to be resin-sealed. The chip mounting portion 14 is subjected to nickel plating or the like for mounting the semiconductor chip 11 via solder. Furthermore, this plating acts as a barrier metal. Thereby, the copper component of the lead frame 12 can be prevented from diffusing into the semiconductor chip 11.

また、チップ搭載部１４の周縁には、図示省略のV溝がプレス加工によって設けられており、該Ｖ溝により、その内側に配置される半導体チップ１１の接続に用いる半田の流れ、すなわち溶融時の半田流れを防止することができる。   Further, a V-groove (not shown) is provided in the peripheral edge of the chip mounting portion 14 by pressing, and the flow of solder used for connecting the semiconductor chip 11 disposed inside the V-groove, that is, at the time of melting. Solder flow can be prevented.

端子部１６はその先端がプレス加工により半導体パッケージ１３から露出するように作成されている。この端子部１６の先端は、リードフレーム１２の一部であり、該リードフレーム１２の中央部にはチップ搭載部１４がある。従って、チップ搭載部１４上に半田を介して接続される半導体チップ１１は、端子部１６と導電状態にあり、端子部１６を介して外部と電気的に接続することができる。   The terminal portion 16 is formed so that the tip thereof is exposed from the semiconductor package 13 by press working. The tip of the terminal portion 16 is a part of the lead frame 12, and the chip mounting portion 14 is at the center of the lead frame 12. Therefore, the semiconductor chip 11 connected to the chip mounting portion 14 via the solder is in a conductive state with the terminal portion 16 and can be electrically connected to the outside via the terminal portion 16.

ところで、前記した端子部１６と同様に外部と電気的に接続するための独立端子１７が図１に示されている。この独立端子１７は、リードフレーム１２と一体的に形成されており、リードフレーム１２と同様にプレスにより所望の形状に加工され、外枠から切り離されて個別に分割される。尚、独立端子１７は、その先端が露出するように半導体パッケージ１３に封止されている。   By the way, the independent terminal 17 for electrically connecting with the exterior similarly to the above-mentioned terminal part 16 is shown by FIG. The independent terminals 17 are formed integrally with the lead frame 12, and are processed into a desired shape by pressing in the same manner as the lead frame 12, separated from the outer frame, and individually divided. The independent terminal 17 is sealed in the semiconductor package 13 so that the tip thereof is exposed.

前記端子部１７の露出した表面並びに独立端子１７の露出した表面、すなわち一般的にアウターリードと称する箇所には、半田めっきまたは錫めっきがされており、半田付けの時に表面の酸化を防止することができ、良好な接続を得ることができる。   The exposed surface of the terminal portion 17 and the exposed surface of the independent terminal 17, that is, a portion generally referred to as an outer lead, is plated with solder or tin to prevent oxidation of the surface during soldering. And a good connection can be obtained.

リードフレーム１２の端子部１６および独立端子１７は、半導体パッケージ１３内における周縁近傍において、図示省略のＶ溝がプレス加工によって設けられている。これにより、Ｖ溝の凹みが封止樹脂との係合を補強するいわゆるモールドロックとして働く。このモールドロックは、封止樹脂とリードフレーム１２との界面の密着を得ることができ、もって半導体パッケージ１３外部からの水分の浸入防止を図ることができる。   The terminal portion 16 and the independent terminal 17 of the lead frame 12 are provided with a V-groove (not shown) in the vicinity of the periphery in the semiconductor package 13 by pressing. Thereby, the recess of the V-groove functions as a so-called mold lock that reinforces the engagement with the sealing resin. This mold lock can obtain close contact at the interface between the sealing resin and the lead frame 12, thereby preventing moisture from entering from the outside of the semiconductor package 13.

半導体チップ１１の表面および裏面には、接続のための電極（図示省略）が形成されている。例えば半導体チップ１１がＮＰＮトランジスタの場合、裏面の電極はコレクタ電極であり、表面の電極はベース電極およびエミッタ電極である。尚、これらの電極は、アルミまたはアルミ合金を蒸着またはスパッタにより作られている。   Electrodes for connection (not shown) are formed on the front and back surfaces of the semiconductor chip 11. For example, when the semiconductor chip 11 is an NPN transistor, the back electrode is a collector electrode, and the front electrode is a base electrode and an emitter electrode. These electrodes are made by vapor deposition or sputtering of aluminum or aluminum alloy.

前記した半導体チップ１１のベース電極およびエミッタ電極は、それぞれ個別の独立端子１７に接続される。この接続には、アルミワイヤーが用いられており、該アルミワイヤーの端部に超音波の振動を加える圧接である。   The base electrode and emitter electrode of the semiconductor chip 11 described above are connected to individual independent terminals 17 respectively. For this connection, an aluminum wire is used, and pressure welding is performed to apply ultrasonic vibration to the end of the aluminum wire.

リードフレーム１２の取付け部１５には、ネジ孔１８が設けられており、後述する挿嵌されるネジの形状に応じた丸孔を基調とした形状である。このネジ孔１８が形成される取付け部１５をより詳細に説明すると、ネジ孔１８により取付け部１５の先端の一辺が切り欠けられて、その切り欠きによる開口が不完全に閉塞する形状である。   A screw hole 18 is provided in the attachment portion 15 of the lead frame 12 and has a shape based on a round hole corresponding to the shape of a screw to be inserted, which will be described later. The mounting portion 15 in which the screw hole 18 is formed will be described in more detail. The screw hole 18 has a shape in which one side of the tip of the mounting portion 15 is notched and the opening due to the notch is incompletely closed.

換言すれば、取付け部１５に丸孔状のネジ孔１８を設けたリードフレーム１２をそのリードフレーム１２の一端からチップ搭載部に向かって短くするように切断し、ネジ孔の一部を省略したような形状である。従って、取付け部１５はネジ孔１８の開口が不完全閉塞し、Ω字状の開口孔を有する。尚、この形状は、プレス加工によって形成される。   In other words, the lead frame 12 provided with the round hole-shaped screw hole 18 in the mounting portion 15 is cut so as to be shortened from one end of the lead frame 12 toward the chip mounting portion, and a part of the screw hole is omitted. It is a shape like this. Therefore, the attachment portion 15 has an opening of the screw hole 18 incompletely closed and has an Ω-shaped opening hole. This shape is formed by press working.

ところで、半導体パッケージ１３には、ネジ貫通孔１９が形成されている。このネジ貫通孔１９は、前記ネジ孔１８の形状に応じて形成されており、トランスファーモールドにより形成される半導体パッケージ１３によって、ネジ孔１８が形成される取付け部１５と、ネジ貫通孔１９に挿入されるネジと、が絶縁性の封止樹脂により隔てられる。   Incidentally, a screw through hole 19 is formed in the semiconductor package 13. The screw through hole 19 is formed according to the shape of the screw hole 18, and is inserted into the mounting portion 15 in which the screw hole 18 is formed and the screw through hole 19 by the semiconductor package 13 formed by transfer molding. Are separated from each other by an insulating sealing resin.

封止樹脂により隔てられるネジ貫通孔１９には、ネジが挿嵌される。このネジのネジ径が例えば３ｍｍでネジの頭の直径が約６ｍｍのとき、ネジ貫通孔１９は直径が約３．２ｍｍに設定され、またネジ孔１８の直径は封止樹脂の絶縁性を考慮して約４．４ｍｍに設定される。   Screws are inserted into the screw through holes 19 separated by the sealing resin. When the screw diameter of this screw is, for example, 3 mm and the diameter of the screw head is about 6 mm, the diameter of the screw through hole 19 is set to about 3.2 mm, and the diameter of the screw hole 18 takes into account the insulating property of the sealing resin. Is set to about 4.4 mm.

次にネジ貫通孔１９と各部位の位置関係を説明する。
半導体パッケージ１３において、取付け部１５の在る側の先端（終端）から約３ｍｍ中央に寄った位置に、ネジ貫通孔１９の中心が位置するように形成されている。 Next, the positional relationship between the screw through hole 19 and each part will be described.
In the semiconductor package 13, the screw through-hole 19 is formed so that the center is located at a position about 3 mm from the tip (end) on the side where the mounting portion 15 exists.

以って、ネジの頭の直径が約６ｍｍのネジは、ネジの頭の外縁が半導体パッケージ１３の最も終端に近い位置に形成されている。   Therefore, a screw having a screw head diameter of about 6 mm is formed such that the outer edge of the screw head is closest to the end of the semiconductor package 13.

前記したようにネジおよびネジ貫通孔１９の位置関係は、リードフレーム１２の取付け部１５の形状によるものであり、ネジ孔１８により取付け部１５の先端の一辺が切り欠けられて、その切り欠きによる開口が不完全に閉塞している。
前記ネジ孔１８に前記開口を設けられていることで、リードフレーム１２の一端からチップ搭載部に向かって取付け部１５を短くすることができる。
これにより、本発明の半導体装置１０は、従来の切り欠きのない形状、例えば引用文献１の図２と比較して小型できる。 As described above, the positional relationship between the screw and the screw through-hole 19 depends on the shape of the mounting portion 15 of the lead frame 12, and one side of the tip of the mounting portion 15 is notched by the screw hole 18. The opening is incompletely blocked.
By providing the opening in the screw hole 18, the mounting portion 15 can be shortened from one end of the lead frame 12 toward the chip mounting portion.
Thereby, the semiconductor device 10 of the present invention can be reduced in size as compared with a conventional shape having no notch, for example, FIG.

また、半導体パッケージ１３に封止されるリードフレーム１２において、取付け部１５の先端は半導体パッケージ１３の終端から約０．８ｍｍ封止樹脂内に位置し、取付け部１５における絶縁性が考慮されている。   Further, in the lead frame 12 sealed by the semiconductor package 13, the tip of the attachment portion 15 is located within about 0.8 mm of sealing resin from the end of the semiconductor package 13, and the insulation in the attachment portion 15 is taken into consideration. .

ところで、ネジ孔１８の中心は、前記ネジ貫通孔１９の中心と同じに設定されており、ネジ孔１８の円周は取付け部１５の先端において、切り欠けられた形状となり、開口が不完全に閉塞するΩ字状に形成されている。Ω字状に形成される取付け部１５は、放熱効率の良い銅材であるため、これによりネジ孔１８の周囲の放熱を得ることができる。
従って本発明の半導体装置１０は、従来の切り欠きの一端が完全に開放された形状と比較して大きな放熱作用を得ることができる。 By the way, the center of the screw hole 18 is set to be the same as the center of the screw through-hole 19, and the circumference of the screw hole 18 is notched at the tip of the mounting portion 15, and the opening is incomplete. It is formed in a closed Ω shape. Since the attachment portion 15 formed in an Ω shape is a copper material having good heat dissipation efficiency, heat dissipation around the screw hole 18 can be obtained thereby.
Therefore, the semiconductor device 10 of the present invention can obtain a large heat radiation effect as compared with the conventional shape in which one end of the notch is completely opened.

更に、Ω字状に形成する取付け部１５は、所定の強度を有している。従って、この強度がネジ貫通孔１９の外周の封止の割れを防止することができる。   Further, the attachment portion 15 formed in an Ω shape has a predetermined strength. Therefore, this strength can prevent the sealing of the outer periphery of the screw through-hole 19 from cracking.

尚、平面視で見たとき、ネジ孔１８に挿嵌されるネジの頭がネジ孔１８が形成される取付け部１５に係るように各寸法が調整されている。これにより、ネジ孔貫通孔１９に挿嵌されるネジの係合による押圧の分散を図ることができる。
従って、従来の切り欠きの一端が完全に開放された形状と比較して、ネジ貫通孔１９に挿嵌されるネジの係合による押圧に耐えてクラックの発生を防止することができる。 When viewed in a plan view, each dimension is adjusted so that the head of the screw inserted into the screw hole 18 is related to the mounting portion 15 in which the screw hole 18 is formed. Thereby, the dispersion | distribution of the press by engagement of the screw inserted by the screw hole through-hole 19 can be aimed at.
Therefore, as compared with the conventional shape in which one end of the notch is completely opened, it is possible to withstand the pressing by the engagement of the screw inserted into the screw through hole 19 and to prevent the occurrence of cracks.

以上述べたように、本発明の半導体装置１０は、小型でありながら、放熱効率が良く、しかもクラック発生の防止を図ることができる。   As described above, the semiconductor device 10 of the present invention is small in size, has good heat dissipation efficiency, and can prevent cracks from occurring.

本発明の半導体装置を示す平面図である。It is a top view which shows the semiconductor device of this invention. 本発明の半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device of this invention. 従来の半導体装置を示す平面図および断面図である（引用文献１の図１）。It is the top view and sectional drawing which show the conventional semiconductor device (FIG. 1 of the cited reference 1). 従来の半導体装置を示す平面図および断面図である（引用文献１の図２）。It is the top view and sectional drawing which show the conventional semiconductor device (FIG. 2 of the cited reference 1). 従来の半導体装置を示す平面図および断面図である（引用文献１の図３）。It is the top view and sectional drawing which show the conventional semiconductor device (FIG. 3 of the cited reference 1).

符号の説明Explanation of symbols

１０ 半導体装置
１１ 半導体チップ
１２ リードフレーム
１３ 半導体パッケージ
１４ チップ搭載部
１５ 取付け部
１６ 端子部
１７ 独立端子
１８ ネジ孔
１９ ネジ貫通孔 DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor chip 12 Lead frame 13 Semiconductor package 14 Chip mounting part 15 Mounting part 16 Terminal part 17 Independent terminal 18 Screw hole 19 Screw through-hole

Claims (2)

半導体チップが搭載されるチップ搭載部と該チップ搭載部の一端側にネジ孔が切り欠けられた形状に形成された取付け部と前記チップ搭載部の他端側に外部と接続するための端子部とが一体形成されたリードフレームと、前記端子部の先端が露出すると共に前記ネジ孔の形状に応じたネジ貫通孔を有するように前記リードフレームを樹脂封止する半導体パッケージと、を備えた半導体装置において、
前記ネジ孔の切り欠けられた形状は、開口が不完全に閉塞することを特徴とする半導体装置。 A chip mounting portion on which a semiconductor chip is mounted, a mounting portion formed in a shape in which a screw hole is cut out on one end side of the chip mounting portion, and a terminal portion for connecting to the outside on the other end side of the chip mounting portion And a semiconductor package in which the lead frame is resin-sealed so that the tip of the terminal portion is exposed and has a screw through hole corresponding to the shape of the screw hole. In the device
The semiconductor device according to claim 1, wherein the notched shape of the screw hole closes the opening incompletely. 前記取付け部は、前記ネジ孔の開口が不完全閉塞することでΩ字状の開口孔を有することを特徴とする請求項1記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the mounting portion has an Ω-shaped opening due to an incomplete closing of the opening of the screw hole.
JP2008272775A 2008-10-23 2008-10-23 Semiconductor device Pending JP2010103279A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7675786B1 (en) 2023-11-24 2025-05-13 株式会社東芝 Semiconductor Device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02202044A (en) * 1989-01-31 1990-08-10 Nec Corp Resin-sealed semiconductor device
US5766985A (en) * 1991-12-05 1998-06-16 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Process for encapsulating a semiconductor device having a heat sink

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02202044A (en) * 1989-01-31 1990-08-10 Nec Corp Resin-sealed semiconductor device
US5766985A (en) * 1991-12-05 1998-06-16 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Process for encapsulating a semiconductor device having a heat sink

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7675786B1 (en) 2023-11-24 2025-05-13 株式会社東芝 Semiconductor Device
JP2025085164A (en) * 2023-11-24 2025-06-05 株式会社東芝 Semiconductor Device

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