JP2010102160A - Liquid crystal display device - Google Patents

Abstract

To realize a liquid crystal display device with a simple configuration and reduced flicker and display unevenness during image writing processing.
A liquid crystal display including a dot matrix type liquid crystal display element, drive circuits and 27 for passively driving pixels of the display element, and a multi-voltage power source for supplying a plurality of different drive voltages to the drive circuit. The driving circuit includes a common driver 26 that outputs a line selection voltage and a line non-selection voltage applied to the first electrode of the display element, and a data selection voltage and a data non-selection applied to the second electrode of the display element. A segment driver 27 that outputs a voltage, and the multi-voltage power supply generates a line selection voltage, a data selection voltage, and a data non-selection voltage with reference to the line non-selection voltage.
[Selection] Figure 13

Description

  The present invention relates to a liquid crystal display device having a dot matrix type liquid crystal display element.

  In recent years, development of electronic paper has been actively promoted at companies and universities as a rewritable display device that can retain display contents even when the power is turned off. There are various display methods for electronic paper, and one of the leading methods is a method using a liquid crystal display element. Among liquid crystals, cholesteric liquid crystals in particular have excellent characteristics such as semi-permanent display retention (memory property), vivid color display, high contrast, and high resolution. Hereinafter, a cholesteric liquid crystal display element will be described as an example.

  Cholesteric liquid crystals are sometimes referred to as chiral nematic liquid crystals, and by adding a relatively large amount (several tens of percent) of chiral additives (chiral materials) to nematic liquid crystals, the molecules of nematic liquid crystals are helical. It is a liquid crystal that forms a cholesteric phase.

  FIG. 1 is a diagram for explaining a state of a cholesteric liquid crystal. As shown in FIG. 1, the display element 10 using cholesteric liquid crystal includes an upper substrate 11, a cholesteric liquid crystal layer 12, and a lower substrate 13. A cholesteric liquid crystal has a planar state that reflects incident light as shown in FIG. 1A and a focal conic state that reflects incident light as shown in FIG. The state is stably maintained even in the absence of an electric field.

  In the planar state, light having a wavelength corresponding to the helical pitch of the liquid crystal molecules is reflected. The wavelength λ at which the reflection is maximum is expressed by the following formula from the average refractive index n of the liquid crystal and the helical pitch p.

λ = n · p
On the other hand, the reflection band Δλ varies greatly depending on the refractive index anisotropy Δn of the liquid crystal.

  In the planar state, incident light is reflected, so that a “bright” state, that is, white can be displayed. On the other hand, in the focal conic state, by providing a light absorption layer under the lower substrate 13, light transmitted through the liquid crystal layer is absorbed, so that a "dark" state, that is, black can be displayed. In addition, when an electric field having an intermediate strength is applied and the electric field is rapidly removed, a planar state and a focal conic state are mixed, and halftone display is possible.

  Display is performed using the above phenomenon.

  The color display element is realized by laminating three panels with reflection center wavelengths of blue, green and red, and providing a light absorption layer below the lowermost panel.

  When displaying on a display element using a memory-type liquid crystal such as cholesteric liquid crystal, after performing an initialization (reset) process that sets all pixels to the same initial state regardless of the previous display state, A writing process is performed to make a state corresponding to the gradation.

  In consideration of cost, a dot matrix type display device using a cholesteric liquid crystal display element adopts a panel having a simple matrix structure, uses a passive drive system, and a drive circuit is generally composed of a general-purpose STN driver. It is. The general-purpose driver is supplied with the selection voltage and non-selection voltage of the positive phase and the selection voltage and non-selection voltage of the negative phase, and can select and output either the selection voltage or the non-selection voltage in each polarity phase. In a liquid crystal display device, a current supplied by a driver of a driving circuit is not so large, and thus a voltage supplied to the driver is generally generated from a high voltage power source using an operational amplifier.

  A display panel of a simple matrix display device is provided with a plurality of strip electrodes in parallel to the upper substrate and the lower substrate of the liquid crystal display element, and the strip electrodes of the upper substrate and the lower substrate are arranged to cross each other. . Pixels are formed at the intersections of the upper strip electrode and the lower strip electrode. A driver that drives the strip electrode on one substrate is called a segment driver, and a driver that drives the strip electrode on the other substrate is called a common driver. The common driver applies a selection voltage to one electrode, applies a non-selection voltage to the remaining electrodes, and performs a scan that sequentially changes the position of the electrode to which the selection voltage is applied. The segment driver applies a selection voltage or a non-selection voltage to each pixel of the line to which the selection voltage is applied in accordance with the selection voltage applied by the common driver. Here, the electrode driven by the common driver is called a first electrode (scan line), and the electrode driven by the segment driver is called a second electrode (data line).

JP 2001-184035 A International Publication WO2007 / 110949A1

  A color display device using cholesteric liquid crystal can suppress manufacturing costs by stacking three panels of red, green, and blue and adopting a panel having a simple matrix structure. When driving a simple matrix structure, the driving power increases in proportion to the panel size, unlike an active matrix structure in which a switching element is provided for each pixel. In particular, in the case of a large-screen display device in which three panels of red, green, and blue are stacked, the power load during driving increases and the power supply voltage fluctuates.

  When passively driving a panel having a simple matrix structure, the common driver has only one electrode (line) to which a selection voltage is applied, and a non-selection voltage is applied to the remaining lines. As described above, since most of the lines to which the non-selection voltage is applied are present, the load of the power source that supplies the non-selection voltage of the common driver is larger than the loads of other power sources. For this reason, the power supply that supplies the non-selection voltage of the common driver is likely to cause voltage fluctuation.

  When passively driving a panel with a simple matrix structure, the non-selection voltage of the common driver, the selection voltage of the segment driver, and the non-selection voltage of the segment driver are applied to pixels other than the line to which the selection voltage of the common driver is applied. The difference voltage is applied. Therefore, when the non-selection voltage of the common driver fluctuates, the voltage applied to the pixels fluctuates over most of the screen, causing flicker. After the image writing process is completed, no voltage is applied to the electrodes (pixels), and thus flicker does not occur.

  Further, since the cholesteric liquid crystal has a memory property, the reflectance is lowered when a voltage higher than a desired voltage is applied during the writing process, and the lowered reflectance is not restored even when the application of the voltage is stopped. A difference voltage between the non-selection voltage of the common driver and the selection voltage and non-selection voltage of the segment driver is applied to lines other than the scan line. The voltage is set so that the reflectivity does not decrease depending on the difference voltage. However, if the non-selection voltage of the common driver during the writing process varies, the difference voltage applied to the pixel may increase. Since such a differential voltage is applied to lines other than the scan line for a long time, such a minute voltage excess may accumulate and cause a decrease in reflectance. This decrease in reflectivity results in an error in the brightness of the displayed image, resulting in display unevenness.

  The disclosed embodiment realizes a liquid crystal display device with a simple configuration and reduced flicker and display unevenness during image writing processing.

  A liquid crystal display device according to an embodiment includes a dot matrix type liquid crystal display element, a drive circuit that passively drives pixels of the display element, and a multi-voltage power supply that supplies a plurality of different drive voltages to the drive circuit. The driving circuit outputs a line selection voltage and a line non-selection voltage applied to the first electrode of the display element, and a data selection voltage and a data non-selection voltage applied to the second electrode of the display element. A multi-voltage power supply that generates a line selection voltage, a data selection voltage, and a data non-selection voltage with reference to the line non-selection voltage.

  In the liquid crystal display device according to the embodiment, flicker and display unevenness during image writing processing are reduced.

  First, a schematic configuration of the liquid crystal display device according to the embodiment and a related art will be described.

  In the description of the liquid crystal display device of the embodiment, the prior art described in Patent Document 2 is referred to and incorporated.

  FIG. 2 is a diagram showing an overall configuration of a liquid crystal display device according to an embodiment using a dot matrix type display element 10 having a memory-type display material such as cholesteric liquid crystal. For example, the display element 10 is A4 size XGA specification and has 1024 × 768 pixels. The power source 21 outputs a voltage of 3V to 5V, for example. The boosting unit 22 boosts the input voltage from the power source 21 to 36V to 40V by a regulator such as a DC-DC converter. The multi-voltage generation unit 23 generates a plurality of voltages to be supplied to the common driver 26 and the segment driver 27 from the boosted voltage. The clock source 24 outputs a clock used for controlling each unit. The driver control circuit 25 outputs several control signals to control the common driver 26 and the segment driver 27. Scanning line data SLD is data that the common driver 26 latches and sequentially shifts. The data capture clock XCLK is a clock for the segment driver 27 to transfer image data internally. The frame start signal DIO is a signal for instructing update of the display line. The pulse polarity control signal FR is a polarity inversion signal of the applied voltage. The scan shift signal LP_COM is a signal that instructs the common driver 26 to update the display line. / DSPOF is an applied voltage forced-off (OFF) signal. The data latch signal LP_SEG is a signal that instructs the segment driver 27 to update the display line. Image data is input to the segment driver 27.

  The common driver 26 drives 768 first electrodes (scan lines), and the segment driver 27 drives 1024 second electrodes (data lines). Since the image data given to each pixel of RGB is different, the segment driver 27 drives each data line independently. The common driver 26 drives the RGB lines in common. As the common driver 26 and the segment driver 27, general-purpose binary output STN drivers are used. Widely used driver ICs include a common driver IC and a segment driver IC. Further, there are ICs that can be used as a common driver or a segment driver depending on a voltage applied to a mode switching terminal.

  FIGS. 3A to 3C are diagrams showing driving examples when the liquid crystal display device of FIG. 2 is operated. In the example of FIG. 3A, the common driver 26 applies a scan pulse to the selected first scan line, and the segment driver 27 turns on / off voltage corresponding to the image data of the first scan line. Is output. In the example of FIG. 3B, the common driver 26 applies a scan pulse to the selected second scan line, and the segment driver 27 turns on / off voltage corresponding to the image data of the second scan line. Is output. In the example of FIG. 3C, the common driver 26 applies a scan pulse to the selected third scan line, and the segment driver 27 turns on / off voltage corresponding to the image data of the third scan line. Is output. The image data of the third scan line is a black line in all pixels, that is, a horizontal black line.

  4A shows the configuration of the general-purpose segment driver, and FIG. 4B shows the configuration of the general-purpose common driver.

  As shown in FIG. 4A, the segment driver includes a data register 31, a latch register 32, a voltage conversion unit 33 that converts a logic voltage into an LCD drive voltage, and an output driver 34. The latch register 32 captures data for one line from the data register 31 in response to the data latch signal LP_SEG. The voltage conversion unit 33 outputs the LCD drive voltage corresponding to the data fetched into the latch register 32 from the output driver 34 for one line at a time. Since the segment driver has a buffer for two lines of the data register 31 and the latch register 32, the data of the next line can be stored in the data register 31 while the data of the latch register 32 is being output.

  As illustrated in FIG. 4B, the common driver includes a shift register 41, a latch register 42, a voltage conversion unit 43, and an output driver 44. The shift register 41 shifts data indicating the scan line to be selected in accordance with the scan shift signal LP_COM. As a result, the screen is scanned line by line. The common driver does not have a function for receiving and storing data of the next line during voltage output unlike the segment driver for scanning.

  5A shows the output voltage of the general-purpose segment driver, and FIG. 5B shows the output voltage of the general-purpose common driver. As shown in FIG. 5A, the general-purpose segment driver outputs V0 when the data signal is “1” and the polarity control signal FR is “1”, and V5 when the polarity control signal FR is “0”. (Ground level (GND)) is output, V21 is output when the data signal is "0" and the polarity control signal FR is "1", and V34 is output when the polarity control signal FR is "0". Here, V0, V21, V34, and V5 are voltages supplied from the outside to the general-purpose segment driver, and it is necessary to satisfy the restriction condition of V0 ≧ V21 ≧ V34 ≧ V5 (GND).

  As shown in FIG. 5B, the general-purpose common driver outputs V5 (GND) when the data signal is “1” and the polarity control signal FR is “1”, and the polarity control signal FR is “0”. V0 is output when the data signal is "0" and V21 is output when the polarity control signal FR is "1" and V34 when the polarity control signal FR is "0". V0, V21, and V34 are voltages supplied from the outside to the general-purpose segment driver, and it is necessary to satisfy the restriction condition of V0 ≧ V21 ≧ V34 ≧ V5 (GND). Here, V21 and V34 output from the segment driver are expressed as V21S and V34S, and V21 and V34 output from the common driver are expressed as V21C and V34C.

  In a display device using cholesteric liquid crystal, the segment driver 27 and the common driver 26 output, for example, pulses as shown in FIG. 6A as gradation pulses to be applied to change from the planar state to the halftone level. . By applying such a pulse, a voltage as shown in FIG. 6B is applied to the pixel.

  The segment driver 27 is supplied with 20V as V0, 10V as V21S and V34S, and 0V as V5. As shown in FIG. 6A, a positive pulse is output in the positive phase (FR = 1), In the phase (FR = 0), a negative pulse is output.

  The common driver 26 is supplied with 20V as V0, 15V as V21C, 5V as V341C, and 0V as V5. As shown in FIG. 6A, a negative pulse is generated in the positive phase (FR = 1). However, a positive pulse is output in the negative phase (FR = 0).

  When a pulse as shown in FIG. 6A is applied, the scan line is selected (common is on) and the data line is also selected (segment is on). 20V is applied in the negative phase (FR = 0). When the scan line is selected (common is on) and the data line is not selected (segment is off), 10V is applied in the positive phase (FR = 1) and -10V is applied in the negative phase (FR = 0). The When the scan line is not selected (common is off) and the data line is selected (segment is on), 5 V is applied in the positive phase (FR = 1) and −5 V is applied in the negative phase (FR = 0). The When the scan line is in the non-selected state (common is off) and the data line is in the non-selected state (segment is off), -5V is applied in the positive phase (FR = 1) and 5V is applied in the negative phase (FR = 0). Is done.

  Accordingly, the waveform of the voltage pulse applied to each pixel of the scan line in the selected state is as shown in FIG. 7A, and the waveform of the voltage pulse applied to each pixel of the scan line in the unselected state is shown in FIG. 7B, in both cases, the waveform of the data line in the selected state is indicated by a solid line, and the waveform of the data line in the non-selected state is indicated by a dotted line. When the pulse width is narrow, the state of the liquid crystal, that is, the reflectivity changes when the voltage is ± 20 V, but the reflectivity does not change when the voltage is ± 10 V. Therefore, if the waveform is as described above, the scan line and the data line When both are ON, writing by the gradation pulse is performed, and in other cases, writing is not performed.

  FIG. 8 is a diagram showing a part of the configuration of the multi-voltage generation unit 23 of FIG. 2, in which (A) shows a circuit configuration for generating five types of voltages, and (B) shows a circuit of (A). 3 is a circuit diagram of a voltage generation circuit 52. FIG. As shown in FIG. 8B, the voltage generation circuit 52 is a voltage follower circuit using an operational amplifier.

  As shown in FIG. 8A, by dividing the reference voltage by the resistor string 51, four voltage levels are generated and amplified to obtain V0 (20V), V21C (15V), V21S and V34S. (10V) and V34C (5V) are generated. In addition, 36V used in the reset process for setting the planar state is also generated, but the illustration is omitted here. V5 (0V) uses the ground level as it is. As shown in FIG. 8A, the five types of voltages V0, V21C, V21S, V34S, and V34C are independently generated by the five voltage generation circuits 52. The five voltage generation circuits 52 are preferably composed of elements having a plurality of operational amplifiers in one chip for cost reduction, and the operational amplifiers constituting the five voltage generation circuits 52 have the same driving capability. Therefore, the current supply capability of each voltage is comparable.

  FIG. 9 is a diagram showing an equivalent circuit of a liquid crystal panel having a simple matrix structure. As shown in FIG. 9, each pixel functions as a capacitive element C. The strip electrodes (scan lines and data lines) 61 and 62 provided on the upper and lower substrates are arranged so as to intersect each other, and the capacitive element C is connected to the intersecting portion. Voltage pulses are applied to the strip electrodes 61 and 62 by the segment driver 26 and the common driver 27, respectively.

  FIG. 10 is a diagram illustrating an application state of the driving voltage in the positive phase during the writing process. The common driver applies a selection voltage V5 (0 V) to the selected line, and applies a non-selection voltage V21C (15 V) to the other non-selected lines. The segment driver applies the selection voltage V0 (20V) to the selected data line, and applies the non-selection voltage V21S (10V) to the other non-selected data lines. Thus, the selection voltage V5 (0V) is applied to only one selection line by the common driver, and the non-selection voltage V21C (15V) is applied to most other non-selection lines. For example, here, only one of 768 lines is a selected line, and the remaining 767 lines are non-selected lines. Therefore, the common driver 26 needs to apply a large current as the non-selection voltage V21C (15V), and the current applied as the selection voltage V5 (GND) may be relatively small. Similarly, in the negative phase, the common driver 26 needs to apply a large current as the non-selection voltage V34C (5V), and the current applied as the selection voltage V0 (20V) may be relatively small.

  As described above, since the current supply capability of each voltage is comparable, during the writing process, the current supply capability of the non-selection voltages V21C (15V) and V34C (5V) of the common driver 26 is insufficient, and the non-selection voltage V21C. A situation occurs in which (15V) and V34C (5V) fluctuate.

  FIG. 11 is a diagram for explaining the influence of fluctuations in the non-selection voltages V21C (15V) and V34C (5V). In the positive phase, the segment driver 27 outputs V0 (20V) as the selection voltage and V21S (10V) as the non-selection voltage. The common driver 26 outputs V5 (0 V) as the selection voltage and V21C (15 V) as the non-selection voltage. Therefore, a full selection voltage of 20 V is applied to the pixels that perform writing on the scan line, and a half selection voltage of 10 V is applied to the pixels that do not perform writing on the scan line. A difference voltage + 5V between V0 and V21C or a difference voltage −5V between V21S and V21C is applied as a non-selection voltage to pixels on lines other than the scan line. Therefore, when V21C fluctuates, the non-selection voltage applied to the pixels of most lines other than the scan line fluctuates and flickers.

  This is the same in the negative phase, and the difference voltage −5V between V5 (0V) and V34C (5V) or the difference voltage + 5V between V34S and V34C is applied as a non-selection voltage to pixels on lines other than the scan line. . Therefore, when V34C fluctuates, the non-selection voltage applied to the pixels on most lines other than the scan line fluctuates, causing flicker.

  This flicker does not occur since the voltage is not applied to the electrodes (pixels) after the image writing process is completed.

  FIG. 12 is a diagram illustrating the variation in reflectance during drawing when the non-selection voltage varies. In FIG. 12, the horizontal axis represents time, the vertical axis represents the reflectance of the non-scan line, the broken line represents the case where the non-selection voltage is ± 5 V, and the solid line represents the case where the non-selection voltage varies from ± 4 V to 6 V. Show. In the case of a panel with a large load such as a large screen panel, the non-selection voltage may vary from ± 4V to 6V. When the non-selection voltage is ± 5V, the reflectance fluctuation is ± 0.5% or less. However, when the non-selection voltage varies from ± 4V to 6V, the reflectance varies ± 1% or more. . This variation in reflectance causes the screen to flicker during drawing.

  Further, since the cholesteric liquid crystal has a memory property, the reflectance is lowered when a voltage higher than a desired voltage is applied during the writing process, and the lowered reflectance is not restored even when the application of the voltage is stopped. A difference voltage between the non-selection voltage of the common driver and the selection voltage and non-selection voltage of the segment driver is applied to lines other than the scan line. The voltage is set so that the reflectivity does not decrease depending on the difference voltage. However, when V34C fluctuates, a difference voltage applied to pixels on lines other than the scan line may increase. Since such a differential voltage is applied to lines other than the scan line for a long time, such a minute voltage excess may accumulate and cause a decrease in reflectance. This decrease in reflectivity results in an error in the brightness of the displayed image, resulting in display unevenness.

  In order to reduce fluctuations in the non-selection voltages V21C (15V) and V34C (5V), the current supply capability of the voltage generation circuit 52 that generates the non-selection voltages V21C and V34C is set to the current of the voltage generation circuit 52 that generates other voltages. It can be considered to be higher than the supply capacity. However, as described above, an element (IC) having a plurality of operational amplifiers on one chip is used for cost reduction, and the voltage generation circuit 52 that generates the non-selection voltages V21C and V34C is configured by a large number of operational amplifiers. Then, the number of ICs increases. Increasing the number of ICs used directly increases costs.

  In the liquid crystal display device of the embodiment, the multi-voltage generation unit 23 generates V0 and V21S with reference to the non-select voltage V21C supplied to the common driver 26, and uses the non-select voltage V34C supplied to the common driver 26 as a reference. Configure to generate V5 and V34S. Thereby, when V21C fluctuates, V0 and V21S also fluctuate similarly, and fluctuations in the differential voltage between V0 and V21C and the differential voltage between V21S and V21C can be suppressed. Further, when V34C varies, V5 and V34S also vary in the same manner, and variation in the difference voltage between V5 and V34C and the difference voltage between V34S and V34C can be suppressed. Since these difference voltages are applied to the pixels on the non-selected lines, fluctuations in the voltage applied to the pixels are small, and flicker is reduced.

  FIG. 13 is a diagram illustrating a configuration of the multi-voltage generation unit 23 of the liquid crystal display device of the embodiment. FIG. 14 is a diagram showing a subtraction circuit and an addition circuit used in the multi-voltage generation unit 23 of FIG.

  FIG. 14A shows a general subtraction circuit using an operational amplifier. In this subtraction circuit, when R1 = R2 = R3 = R4, a voltage of Vout = Vin1-Vin2 is output. FIG. 14B shows a general adder circuit using an operational amplifier. In this adder circuit, when R1 = R2 = R3 = R4, a voltage of Vout = Vin1 + Vin2 is output. The multi-voltage generation unit 23 in FIG. 13 uses a subtraction circuit and an addition circuit of R1 = R2 = R3 = R4.

  Returning to FIG. 13, the multi-voltage generation unit 23 divides the reference voltage Vref <b> 1 by the resistor string 71 to generate two voltage levels corresponding to V <b> 21 </ b> C and V <b> 34 </ b> C. The voltage follower circuit using the operational amplifiers 73 and 76 generates V21C (15V) and V34C (5V) based on two voltage levels, respectively. The reference voltage Vref2 sets a voltage to be added to or subtracted from V21C and V34C, and is 5V here.

  The adder circuit using the operational amplifier 72 adds Vref2 to V21C (15V) to generate V0 (20V). Therefore, the output voltage of this adding circuit is V21C + Vref2, and if Vref2 is constant, V0−V21C becomes Vref2 even if V21C fluctuates.

  Similarly, the subtraction circuit using the operational amplifier 74 subtracts Vref2 from V21C (15V) to generate V21S (10V). Therefore, the output voltage of this subtraction circuit is V21C-Vref2, and if Vref2 is constant, V21S-V21C becomes -Vref2 even if V21C fluctuates.

  The adder circuit using the operational amplifier 75 adds Vref2 to V34C (5V) to generate V34S (10V). Therefore, the output voltage of this adding circuit is V34C + Vref2, and if Vref2 is constant, V34S−V341C becomes Vref2 even if V34C fluctuates.

  Similarly, the subtraction circuit using the operational amplifier 77 generates V5 (0 V) by subtracting Vref2 from V34C (5 V). Therefore, the output voltage of this subtraction circuit is V34C-Vref2, and if Vref2 is constant, V5-V34C becomes -Vref2 even if V34C fluctuates.

  Therefore, for example, when V21C fluctuates from 15V to 14V in the positive polarity phase, it changes following V0 = 19V and V21S = 9V, and the non-selection voltages are V0−V21C = 5V, V21S−V21C = −5V. Thus, ± 5V is maintained. On the contrary, when V21C changes from 15V to 16V, it changes following V0 = 21V and V21S = 11V, and the non-selection voltages are V0−V21C = 5V, V21S−V21C = −5V, and ± 5V Is maintained.

  In the negative phase, when V34C changes from 5V to 4V, it changes following V34S = 9V and V5 = −1V, and the non-selection voltages are V34S−V34C = 5V, V5-V34C = −5V, ± 5V is maintained. On the contrary, when V34C changes from 5V to 6V, it changes following V34S = 11V and V5 = 1V, and the non-selection voltages are V34S-V34C = 5V, V5-V34C = -5V, and ± 5V Is maintained. Here, in order to make V5 0 V or less, the negative side power source of the operational amplifier is set to a negative power source.

  When a negative power supply is not used for cost reduction, Vref1 is set according to the load fluctuation. For example, when the fluctuation is 1V, if Vref1 is set so that V21C = 16V and V34C = 6V, V5 does not become a negative voltage, and there is no need to provide a negative power source.

  As described above, the multi-voltage generation unit 23 according to the embodiment generates other voltages with reference to V21C and V34C. When V21C and V34C fluctuate, other voltages also fluctuate accordingly, and V21C and V34C Thus, the non-selection voltage applied to the pixel is maintained, so that flicker due to fluctuations in the non-selection voltage during drawing can be prevented.

  FIG. 15 is a diagram illustrating a configuration of a modification of the multi-voltage generation unit 23 of the liquid crystal display device of the embodiment. In the modified multi-voltage generation unit 23, V21C and V34C are generated by a voltage follower circuit using operational amplifiers 82 and 85, as in the configuration of FIG.

  In the multi-voltage generation unit 23 according to the modification, V0 (20 V) is generated by a non-inverting amplifier circuit using the operational amplifier 81 and V21S (10 V) is generated by a non-inverting amplifier circuit using the operational amplifier 83 with V21C as a reference. V34S (10V) is generated by a non-inverting amplifier circuit using the operational amplifier 84. The amplification factor of the non-inverting amplifier circuit is set by selecting a resistance value. For example, in the non-inverting amplifier circuit using the operational amplifier 81, the resistance is set so that the amplification factor becomes 4/3, and V21C (15V) is multiplied by 4/3 to obtain V0 (20V). Similarly, in the non-inverting amplifier circuit using the operational amplifier 83, the amplification factor is 2/3, and V21C (15V) is multiplied by 2/3 to obtain V21S (10V). In the non-inverting amplifier circuit using the operational amplifier 84, the amplification factor is double, and V34C (5V) is doubled to obtain V34S (10V).

  In this modification, when V21C varies from 15V to 14V in the positive polarity phase, V0 = 18.66V and V21S = 9.33V, and the non-selection voltages are V0−V21C = 4.66V and V21S−V21C = 4. 67V, and the fluctuation amount is small and does not differ greatly from ± 5V. The same applies when V21C varies from 15V to 16V, and the variation in the non-selection voltage is reduced.

  In the negative phase, when V34C varies from 5V to 4V, V34S = 8V, and the non-selection voltages are V34S−V34C = 4V and V5-V34C = −4V, and do not vary more than ± 4V.

  The multi-voltage generation unit 23 of the modified example can have a simpler configuration than the multi-voltage generation unit 23 of FIG. 13 and can suppress a decrease in reflectance due to a non-selection voltage of 5 V or more being applied for a long time. Moreover, since the fluctuation | variation of the non-selection voltage which was 4-6V in the prior art example can be suppressed to 4-6V, the flicker during drawing can be suppressed.

  As described above, in the liquid crystal display device according to the embodiment, even when the driving voltage of the driver fluctuates due to the panel load, the fluctuation of the voltage applied to the pixel is suppressed by changing the other driving voltage. Thereby, the problem that the screen flickers at the time of drawing can be reduced. Further, such a configuration can be realized with a simple configuration.

  As described above, the liquid crystal display device using cholesteric liquid crystal has been described as the liquid crystal display device. However, the present invention is not limited to this, and any liquid crystal display device can be applied.

FIG. 1 is a diagram for explaining a planar state and a focal conic state of a cholesteric liquid crystal. FIG. 2 is a diagram illustrating a schematic configuration of the cholesteric liquid crystal display device of the embodiment. FIG. 3 is a diagram illustrating an example of driving in the display device. FIG. 4 is a diagram illustrating the configuration of the general-purpose segment driver and the general-purpose common driver. FIG. 5 is a diagram illustrating output voltages of the general-purpose segment driver and the general-purpose common driver. FIG. 6 is a diagram illustrating output pulses and applied voltages of the general-purpose segment driver and the general-purpose common driver in the liquid crystal display device. FIG. 7 is a diagram illustrating an example of a symmetric pulse applied to the liquid crystal. FIG. 8 is a diagram illustrating a partial configuration of a conventional multi-voltage generation unit (power supply). FIG. 9 is a diagram showing an equivalent circuit of a panel having a simple matrix structure. FIG. 10 is a diagram illustrating an application state of the driving voltage in the positive phase during the writing process. FIG. 11 is a diagram for explaining the influence of fluctuations in the non-selection voltages V21C (15V) and V34C (5V). FIG. 12 is a diagram illustrating the variation in reflectance during drawing when the non-selection voltage varies. FIG. 13 is a diagram illustrating a partial configuration of a multi-voltage generation unit (power supply) of the liquid crystal display device according to the embodiment. FIG. 14 is a diagram illustrating a configuration of a subtraction circuit and an addition circuit using an operational amplifier used in the multi-voltage generation unit (power supply) of the liquid crystal display device of the embodiment. FIG. 15 is a diagram illustrating a configuration of a modified example of the multi-voltage generation unit (power supply) of the liquid crystal display device of the embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Display element 11 Upper side board | substrate 12 Liquid crystal layer 13 Lower side board | substrate 21 Power supply 22 Booster part 23 Multi-voltage production | generation part 25 Driver control circuit 26 Common driver (RGB common)
27 Segment driver (RGB independent)
71 resistor array 72-77 operational amplifier

Claims (5)

A dot matrix type liquid crystal display element;
A drive circuit for passively driving pixels of the display element;
A multi-voltage power supply that supplies a plurality of different drive voltages to the drive circuit, and a liquid crystal display device comprising:
The drive circuit is
A common driver that outputs a line selection voltage and a line non-selection voltage applied to the first electrode of the display element;
A segment driver that outputs a data selection voltage and a data non-selection voltage applied to the second electrode of the display element,
The liquid crystal display device, wherein the multi-voltage power supply generates the line selection voltage, the data selection voltage, and the data non-selection voltage with reference to the line non-selection voltage.   The liquid crystal display device according to claim 1, wherein the multi-voltage power source includes a line non-selection voltage generation circuit that generates the line non-selection voltage corresponding to a reference potential.   The multi-voltage power supply includes an adding circuit that generates a voltage obtained by adding a first predetermined voltage value to the line non-selection voltage, and a subtracting circuit that generates a voltage obtained by subtracting a second predetermined voltage value from the line non-selection voltage; The liquid crystal display device according to claim 2, further comprising:   The liquid crystal display device according to claim 3, wherein the line non-selection voltage generation circuit, the addition circuit, and the subtraction circuit include an operational amplifier circuit.   The liquid crystal display device according to claim 3, wherein the first predetermined voltage value and the second predetermined voltage value are equal.

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