JP2010098065A - Integrated light power generation element and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated light power generation element for which the problem of performance decline to the exposure of a formed power generation layer in the air is solved, and to provide a method for manufacturing the same. <P>SOLUTION: The integrated light power generation element I<SB>0</SB>includes at least: a substrate 10; an insulation part 15 formed of an insulating material at an interval on the substrate 10; a back surface electrode layer 11 formed so as to be insulation-isolated by the insulation part 15; a power generation layer 12 formed using a compound semiconductor and divided from another adjacent cell by a division groove 16; and a transparent electrode layer 13, and is provided with a conductive part 14 which covers a part of the surface of the transparent electrode layer 13 and the end part on one side of the transparent electrode layer 13 and the power generation layer 12 respectively and electrically connecting the back surface electrode layer 11 of the other adjacent cell and the transparent electrode layer 13. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an integrated photovoltaic device, and more particularly to an integrated photovoltaic device using a compound semiconductor.

  Conventionally, when a thin film solar cell using a compound semiconductor such as a CIS system is used as a solar cell module to obtain a predetermined voltage, a thin film in which a substrate, a back electrode layer, a light absorption layer, and a transparent electrode layer are laminated in order is used for each unit cell. An integrated photovoltaic device is formed in which a plurality of these are connected in series. As a method for manufacturing such an integrated photovoltaic device, for example, Patent Document 1 discloses patterning P1 for dividing the back electrode layer, patterning P2 for dividing the light absorption layer or the buffer layer, and a window layer or light absorption. P2 and P3 are formed on the surface of the back electrode layer in the light absorption layer forming step when mechanically removing each constituent thin film layer with a metal needle to form a groove. A manufacturing method is described in which an ultrathin film layer produced by reaction with a chalcogen element is used as a solid lubricant.

JP 2005-191167 A

By the way, for example, a CIS thin film solar cell is usually manufactured by the following procedure.
FIG. 3 is a diagram illustrating a manufacturing process of a conventional CIS thin film solar cell. First, a strip-shaped back electrode layer 2 is formed by patterning on an insulating substrate 1 (FIG. 3A), and then a power generation layer 3 is formed by sputtering or the like (FIG. 3B). Then, a part of the power generation layer 3 is striped by the mechanical pattern method (FIG. 3C), and then the transparent electrode layer 4 is formed (FIG. 3D). Finally, the transparent electrode layer 4 Is divided into strips (FIG. 3E).

  However, in the manufacturing process of the solar cell module having the integrated structure as described above, it is necessary to form the back electrode layer, the power generation layer, and the transparent electrode layer by separate patterning processes. For this reason, there is a problem in that the surface of the power generation layer or the like that has been formed is exposed to the atmosphere, causing interface oxidation, dust adhesion, and the like, thereby reducing the performance of the solar cell. In addition, the mechanical patterning process requires a long time and increases the manufacturing cost.

  An object of the present invention is to provide an integrated photovoltaic device that solves the problem of performance degradation caused by exposure of a deposited power generation layer to the atmosphere and a method for manufacturing the integrated photovoltaic device.

  Thus, according to the present invention, there is provided an integrated photovoltaic device having a plurality of cells provided on a common substrate, the cells comprising the substrate and the insulating portion formed on the substrate with an interval by an insulating material. And a back electrode layer formed on the substrate so as to be insulated and separated by an insulating portion, and formed using a compound semiconductor on the formed back electrode layer, and separated from other adjacent cells by a dividing groove At least a power generation layer and a transparent electrode layer formed on the power generation layer, respectively covering a part of the surface of the transparent electrode layer and one end of the transparent electrode layer and the power generation layer, and adjacent to each other An integrated photovoltaic device comprising a conductive portion that electrically connects the back electrode layer of the cell and the transparent electrode layer is provided.

  Here, in the integrated photovoltaic device to which the present invention is applied, the compound semiconductor of the power generation layer is preferably a Cu—In—Se based semiconductor having a chalcopyrite structure.

  Next, according to the present invention, there is provided a method for manufacturing an integrated photovoltaic device having a plurality of cells, wherein a plurality of insulating materials are applied by applying an insulating paste containing an insulating material at intervals on a substrate. A first paste applying step for forming the insulating portion, and a back electrode layer forming step for forming a plurality of back electrode layers on the substrate on which the plurality of insulating portions are formed so as to be insulated and separated by the insulating portion; A power generation layer forming step for forming a power generation layer on the formed back electrode layer; a transparent electrode layer formation step for forming a transparent electrode layer on the formed power generation layer; A patterning process in which a part of the power generation layer and the transparent electrode layer is removed and electrically divided and a part of the back electrode layer is exposed, and a conductive material containing a conductive material in a part of the surface of the divided transparent electrode layer Apply an adhesive paste to cover the edge of the transparent electrode layer and the edge of the divided power generation layer. And a second paste application step for forming a conductive portion for electrically connecting a part of the exposed back electrode layer of another adjacent cell and the transparent electrode layer. A method for manufacturing a power generation element is provided.

Here, in the method for manufacturing an integrated photovoltaic device to which the present invention is applied, it is preferable to form the back electrode layer, the power generation layer, and the transparent electrode layer by sputtering.
The insulating paste is preferably a glass paste or a ceramic paste.

ADVANTAGE OF THE INVENTION According to this invention, the integrated photovoltaic device which solved the problem of the performance fall which arises by a mechanical patterning process is obtained.
According to the present invention, the opportunity for the power generation layer including the compound semiconductor to be exposed to the air is reduced, thereby preventing a decrease in the performance of the solar cell.
According to the present invention, it is possible to prevent a decrease in mass productivity by reducing the mechanical scribe process.

  Hereinafter, embodiments of the present invention will be described in detail. In addition, this invention is not limited to the following embodiment, It can implement by changing variously within the range of the summary. Further, the drawings to be used are for explaining the present embodiment and do not represent the actual size.

FIG. 1 is a diagram illustrating an example of an integrated photovoltaic device to which the present embodiment is applied.
As shown in FIG. 1, the integrated photovoltaic element I ₀ includes a common substrate 10 and a plurality of unit cell elements (cells) (Ia, Ib, Ic, Id,...) Formed on the substrate 10. Have. These unit cell elements are separated by a predetermined interval by the dividing groove 16.

  Next, each of the plurality of unit cell elements (Ia, Ib, Ic, Id,...) Includes a plurality of insulating portions 15 formed on the substrate 10 at intervals with an insulating material, and a plurality of insulating portions. The back electrode layer 11 formed so as to be insulated and separated by 15 and the power generation formed on each of the formed back electrode layers 11 using the compound semiconductor and divided by the adjacent grooves and the dividing grooves 16 The layer 12 and the transparent electrode layer 13 formed on the power generation layer 12 are provided.

Further, as shown in FIG. 1, a part of the surface of the transparent electrode layer 13 and end portions on one side of the transparent electrode layer 13 and the power generation layer 12 in each unit cell element (Ia, Ib, Ic, Id,...). And a conductive portion 14 that electrically connects the back electrode layer 11 of the other adjacent cell and the transparent electrode layer 13 to each other. In the present embodiment, a part of the conductive portion 14 fills the second dividing groove 17 provided by removing a part of the transparent electrode layer 13 and the power generation layer 12 by a patterning process to be described later, and an adjacent unit. The back electrode layer 11 and the transparent electrode layer 13 of the cell element are electrically connected.
In the present embodiment, on each insulating portion 15, a thin film laminate made of materials constituting the back electrode layer 11, the power generation layer 12, and the transparent electrode layer 13 formed by a film forming operation described later is formed. Has been. As shown in FIG. 1, the conductive portion 14 that covers a part of the surface of the transparent electrode layer 13 covers the thin film laminate formed on the insulating portion 15, while the back electrode layer 11, the transparent electrode layer 13, Are electrically connected.

As shown in FIG. 1, the insulating portion 15 of the integrated photovoltaic device I ₀ has a height and width of the extent capable of insulating separating at least the back electrode layer 11. In the present embodiment, the insulating portion 15 has a height enough to insulate and separate the back electrode layer 11 and the power generation layer 12 and further reach a part of the transparent electrode layer 13.
Although the height and width of the insulating part 15 are not particularly limited, in the present embodiment, the height of the insulating part 15 is usually 1 μm to 20 μm, preferably 8 μm to 12 μm. Moreover, the width | variety of the insulation part 15 is 30 micrometers-120 micrometers normally, Preferably it is 40 micrometers-60 micrometers. When the height and width of the insulating portion 15 are excessively small, the back electrode layer 11 and the power generation layer 12 tend not to be insulated and separated. Moreover, when too large, there exists a tendency for the electrical resistance of the back surface electrode layer 11 and the transparent electrode layer 13 by the electroconductive part 14 to increase.
In addition, the shape of the insulating portion 15 is not particularly limited as long as it has a shape capable of insulating and separating at least the back electrode layer 11. As shown in FIG. 1, in the present embodiment, the insulating portion 15 is formed so that the cross-sectional shape is a convex shape having a trapezoid. In this case, it can be said that the back electrode layer 11, the power generation layer 12, and the transparent electrode layer 13 are divided so as to form a step at a portion where the convex insulating portion 15 is formed on the substrate 10.

Next, the configuration elements of the integrated photovoltaic device I _0.
As a material which comprises the board | substrate 10, metal films, such as stainless steel, an organic film, glass etc. are mentioned, for example. Although the magnitude | size of the board | substrate 10 is not specifically limited, In this Embodiment, length x width is 10 cm x 10 cm, and thickness is 0.5 mm.
The material constituting the back electrode layer 11 is preferably a metal, for example, at least one metal selected from Mo, Ti, Cr, Al, Ag, Au, Cu and Pt, or an alloy thereof. The back electrode layer 11 is a metal thin film having a thickness of about 0.3 μm in the present embodiment. The back electrode layer 11 is formed on the substrate 10 by, for example, vapor deposition, sputtering, CVD (chemical vapor deposition), or the like.

Examples of the power generation layer 12 include chalcopyrite type compound semiconductors containing elements of the IB group, IIIB group, and VIB group of the periodic table. In this embodiment mode, it is preferably formed using a Cu—In—Se semiconductor material having a chalcopyrite structure including copper (Cu), indium (In), and selenium (Se).
Here, when a Cu—In—Se based semiconductor material is employed, a p-type semiconductor forming precursor layer made of a mixture of Cu and Se that easily forms a p-type semiconductor is formed on the back electrode layer 11 side. Next, it is preferable to form an n-type semiconductor forming precursor layer made of a mixture of In and Se that easily forms an n-type semiconductor on the transparent electrode layer 13 side. The p-type semiconductor forming precursor layer and the n-type semiconductor forming precursor layer melt and diffuse to each other, thereby generating the power generation layer 12 having good crystallinity and forming a pn junction.
In the present embodiment, the thickness of the power generation layer 12 is in the range of 0.3 μm to 5 μm.

In the present embodiment, the transparent electrode layer 13 is preferably formed by sputtering or vapor deposition using a metal material containing at least one selected from ITO (Indium Tin Oxide), SiO ₂ , and ZnO. The thickness of the transparent electrode layer 13 is about 0.6 μm in the present embodiment.
A buffer layer can be provided between the power generation layer 12 and the transparent electrode layer 13. Although the material which comprises a buffer layer is not specifically limited, For example, CdS, ZnS, ZnMgO etc. are mentioned. By providing a buffer layer between the power generation layer 12 and the transparent electrode layer 13, defects generated at the interface between the power generation layer 12 and the transparent electrode layer 13 can be suppressed.

The material which comprises the electroconductive part 14 will not be specifically limited if it is a material which can electrically connect the back surface electrode layer 11 and the transparent electrode layer 13. In the present embodiment, as will be described later, the conductive portion 14 is formed by applying a conductive paste on the transparent electrode layer 13.
Here, as the conductive paste used to form the conductive portion 14, a resin such as a thermoplastic polyester resin, an acrylic resin, or an epoxy resin is usually used as a binder, and a fine metal such as silver, copper, or aluminum is used. It is defined as one prepared by adding conductive fine powder such as powder or carbon black, and dissolving and dispersing these binder and conductive fine particles in various organic solvents. As the metal fine powder, for example, a composite metal powder in which a part of the surface of copper particles, nickel particles, aluminum particles or the like is coated with another metal such as silver or gold is also used. Among them, for silver, for example, particulate silver compounds such as first silver oxide, second silver oxide, silver carbonate, silver acetate, and acetylacetone silver complex are preferable.

  As such a conductive paste, a conventionally known paste that is commercially available can be used. In the present embodiment, for example, Doutite FA-408 (manufactured by Fujikura Kasei Co., Ltd.) is used.

The material constituting the insulating portion 15 is not particularly limited as long as it is a material capable of insulating and separating at least the back electrode layer 11. In the present embodiment, as will be described later, the insulating portion 15 is formed by applying an insulating paste on the substrate 10.
Examples of the insulating paste include a glass paste obtained by adding a glass powder, an organic binder such as an ultraviolet curable resin, and a solvent; and a ceramic paste obtained by adding a ceramic powder, an organic binder, and a solvent.

Examples of the glass powder in the glass paste include SiO ₂ —BaO—Al ₂ O ₃ system, SiO ₂ —B ₂ O ₃ system, SiO ₂ —B ₂ O ₃ —Al ₂ O ₃ system, and SiO ₂ —Al ₂ O. Examples include ₃ -alkali metal oxide systems, and compositions in which alkali metal oxides, ZnO, PbO, Pb, ZrO ₂ , TiO _{2 and the} like are blended with these systems. Furthermore, Bi ₂ O ₃ , SiO ₂ , B ₂ O ₃ , ZrO ₂ , Al ₂ O ₃ , ZnO, TiO ₂ and CaO, MgO, SrO, BaO and the like mixed with a predetermined composition ratio are mixed in a bismuth-based lead-free glass. Etc.
Examples of the ceramic powder in the ceramic paste include Al ₂ O ₃ , SiO ₂ , forsterite, cordierite, mullite, AlN, Si ₃ N ₄ , SiC, MgTiO ₃ , and CaTiO ₃ . In addition, at least SiO ₂ and BaO, CaO, SrO, ceramic material or the like to be fired below 1,100 ° C. mixtures with metal oxides containing alkaline earth metal oxides such as MgO.
Examples of the organic binder include an oligomer or a polymer having at least one unsaturated bond. Specific examples include polyester acrylate, polyester methacrylate, epoxy acrylate, and epoxy methacrylate.
Examples of the organic solvent include ethyl carbitol acetate, butyl carbitol acetate, butyl cellosolve, and 3-methoxybutyl acetate.

  As such an insulating paste, a conventionally known paste that is commercially available can be used. In the present embodiment, for example, lead-free glass paste LY32 (manufactured by Nippon Yamamura Glass Co., Ltd.) is used.

Next, a manufacturing method of the integrated photovoltaic device will be described.
Figure 2 is a diagram illustrating an embodiment of a manufacturing method of an integrated photovoltaic device I _0. The same components as those in FIG.
First, as shown in FIG. 2A, a substrate 10 made of the above-described material is prepared. Next, as shown in FIG. 2B, an insulating paste is applied on the substrate 10 at a predetermined interval to form a plurality of insulating portions 15 (first paste applying step).
A method for applying the insulating paste is not particularly limited, but a screen printing method is employed in the present embodiment. The conditions for curing the insulating paste applied on the substrate 10 are not particularly limited, but in the present embodiment, the conditions are 500 ° C. and 10 minutes.

Next, as shown in FIG. 2C, a plurality of back electrode layers 11 are formed on the substrate 10 on which the plurality of insulating portions 15 are formed so as to be insulated and separated by the insulating portions 15 (back electrode layers). Film formation step), a power generation layer 12 is formed on the formed back electrode layer 11 (power generation layer film formation step), and a transparent electrode layer 13 is formed on the formed power generation layer 12 (transparent electrode). Layer deposition step). In the present embodiment, the back electrode layer 11, the power generation layer 12, and the transparent electrode layer 13 are continuously and continuously formed on the substrate 10 by sputtering.
As shown in FIG. 2C, in the present embodiment, the material constituting the back electrode layer 11, the power generation layer 12, and the transparent electrode layer 13 formed on each insulating portion 15 by a film forming operation. A thin film laminate is formed.

Here, in the present embodiment, the power generation layer 12 is formed by laminating a plurality of semiconductor layers made of a compound semiconductor containing a group IB element, a group IIIB element, and a group VIB element on the back electrode layer 11, and the plurality of semiconductor layers. It is preferable to form by melting and diffusing each other by heat treatment. That is, in this embodiment, a Cu-In-Se-based semiconductor material is used as the compound semiconductor, and a p-type semiconductor forming precursor made of a mixture of Cu and Se that can easily form a p-type semiconductor on the back electrode layer 11 side. The body layer is formed, and then an n-type semiconductor forming precursor layer made of a mixture of In and Se that easily forms an n-type semiconductor is formed on the transparent electrode layer 13 side. The power generation layer 12 made of a semiconductor having good crystallinity can be formed by melting and diffusing semiconductor layers with each other by heat treatment.
The operation of melting and diffusing a plurality of semiconductor layers with each other by heat treatment may be performed after the plurality of semiconductor layers are stacked on the back electrode layer 11 or after the transparent electrode layer 13 is formed. Also good. In the present embodiment, after forming the transparent electrode layer 13, a plurality of semiconductor layers are melted and diffused to each other by heat treatment to form the power generation layer 12 made of a semiconductor having good crystallinity.

Subsequently, as shown in FIG. 2D, a part of the power generation layer 12 and the transparent electrode layer 13 continuously formed are removed by patterning, and the power generation layer 12 and the transparent electrode layer 13 are divided into a plurality of divisions. While dividing | segmenting by the groove | channel 16, a part of back surface electrode layer 11 is exposed (patterning process).
In the present embodiment, the patterning step employs a mechanical scribing method in which a part of the power generation layer 12 and the transparent electrode layer 13 is cut into a strip shape using, for example, a metal blade, a cutter knife, a metal needle, or a needle. Yes.
In the present embodiment, as shown in FIG. 2D, a second dividing groove 17 is provided on the lateral side of the dividing groove 16 so as to be parallel to the dividing groove 16.

Next, as shown in FIG. 2E, a conductive paste containing a conductive material is applied to a part of the surface of the transparent electrode layer 13 divided by the patterning step described above, and the end of the transparent electrode layer 13 is applied. And a conductive portion 14 that covers the edge of the divided power generation layer 12 and electrically connects the transparent electrode layer 13 to a part of the back electrode layer 11 of another adjacent cell exposed by the patterning process described above. (Second paste applying step), and the conductive paste is cured, whereby an integrated photovoltaic power generation comprising a plurality of unit cell elements (Ia, Ib, Ic, Id,...) Connected in series. Element I ₀ is obtained.
A method for applying the conductive paste is not particularly limited, but a screen printing method is employed in the present embodiment. The condition for curing the conductive paste applied to a part of the surface of the transparent electrode layer 13 is not particularly limited, but in this embodiment, it is 150 ° C. and 10 minutes.

  Here, the conductive paste applied to a part of the surface of the transparent electrode layer 13 fills the second divided grooves 17 formed together with the divided grooves 16 by the patterning process described above, and also includes adjacent unit cell elements. It is necessary to have a viscosity enough to reach the back electrode layer 11. In addition, by providing the 2nd division groove 17, it is suppressed that the conductive paste apply | coated to a part of surface of the transparent electrode layer 13 flows more than needed, and the unit cell element adjacent to the flowing-out conductive paste is carried out. Can be prevented from contacting.

As described above, the manufacturing method of the integrated photovoltaic device I ₀ which this embodiment is applied, compared with the manufacturing process of the CIS thin film solar cell is conventional, without a mechanical scribing process, Since the back electrode layer 11, the power generation layer 12, and the transparent electrode layer 13 can be continuously and consistently formed, the opportunity for the power generation layer including the compound semiconductor to be exposed to the air is reduced, and the performance degradation of the solar cell is prevented. The Further, it is possible to prevent a decrease in mass productivity by reducing a mechanical scribing process that usually takes a long time. Furthermore, deterioration from the cut end face that occurs after mechanical scribing is suppressed.

In addition, the above description is only an example for demonstrating embodiment of this invention, and this invention is not limited to this embodiment.
The present invention can be applied to a photovoltaic device including a semiconductor layer composed of a plurality of elements and two electrode layers sandwiching the semiconductor layer, and a method for manufacturing a photovoltaic device having such a structure. For example, a III-V group semiconductor typified by a Cd-Te system, an I-III-VI group semiconductor typified by a Cu-In-Se system, and an I-II typified by a Cu-Zn-Sn-S system compound The present invention can also be applied to an IV group semiconductor composed of two or more elements such as an -IV-VI group semiconductor, an II-IV-V group semiconductor, and a Si-Ge group.

It is a figure explaining an example of the integrated photovoltaic device to which this Embodiment is applied. It is a figure explaining embodiment of the manufacturing method of an integrated photovoltaic device. It is a figure explaining the manufacturing process of the conventional CIS thin film type solar cell.

DESCRIPTION OF SYMBOLS 1,10 ... Board | substrate, 2,11 ... Back electrode layer, 3,12 ... Electric power generation layer, 4,13 ... Transparent electrode layer, 14 ... Conductive part, 15 ... Insulating part, 16 ... Dividing groove, 17 ... Second division Groove, I ₀ ... Integrated photovoltaic device

Claims (5)

An integrated photovoltaic device having a plurality of cells provided on a common substrate,
The cell is
A substrate,
An insulating part formed on the substrate with an insulating material spaced apart;
A back electrode layer formed on the substrate so as to be insulated and separated by the insulating portion;
A power generation layer that is formed using a compound semiconductor on the formed back electrode layer and is divided by other adjacent cells and dividing grooves;
A transparent electrode layer formed on each of the power generation layers,
Covers a part of the surface of the transparent electrode layer and the end of one side of the transparent electrode layer and the power generation layer, and electrically connects the back electrode layer of another adjacent cell and the transparent electrode layer. An integrated photovoltaic device comprising a conductive portion.   The integrated photovoltaic device according to claim 1, wherein the compound semiconductor of the power generation layer is a Cu-In-Se based semiconductor having a chalcopyrite structure. A method of manufacturing an integrated photovoltaic device having a plurality of cells,
A first paste application step of applying an insulating paste containing an insulating material at intervals on a substrate to form a plurality of insulating portions made of the insulating material;
A back electrode layer film forming step of forming a plurality of back electrode layers on the substrate on which the plurality of insulating parts are formed so as to be insulated and separated by the insulating part;
A power generation layer forming step of forming a power generation layer on the formed back electrode layer;
A transparent electrode layer film forming step of forming a transparent electrode layer on the power generation layer formed;
A patterning step of removing a part of the deposited power generation layer and the transparent electrode layer to electrically divide and exposing a part of the back electrode layer;
Applying a conductive paste containing a conductive material to a part of the surface of the divided transparent electrode layer, covering the edge of the transparent electrode layer and the edge of the divided power generation layer, and other adjacent A second paste applying step for forming a conductive portion that electrically connects a part of the back electrode layer exposed in the cell and the transparent electrode layer;
A method of manufacturing an integrated photovoltaic device, comprising:   The method for manufacturing an integrated photovoltaic device according to claim 3, wherein the back electrode layer, the power generation layer, and the transparent electrode layer are formed by sputtering.   The method for manufacturing an integrated photovoltaic device according to claim 3 or 4, wherein the insulating paste is a glass paste or a ceramic paste.

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