JP2010080741A - Semiconductor light-emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element having luminous efficiency improved by surely utilizing a surface plasmon. <P>SOLUTION: In the semiconductor light-emitting element, a first lower layer containing an n-type semiconductor, a second lower layer containing a p-type semiconductor, an active layer, and an upper layer containing an n-type semiconductor are sequentially formed on a substrate. A first electrode for n-type is provided which is in contact with the substrate or the first lower layer, and a second electrode for n-type is provided which is in contact with the upper layer. The upper layer has a thickness of 40 nm or less. The interface of the second electrode for n-type which is in contact with the upper layer contains metal in which a surface plasmon can be excited by light generated in the active layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor light emitting device, and more particularly to a technique for improving the light emission efficiency of a semiconductor light emitting device using surface plasmons.

  In recent years, attempts have been made to improve luminous efficiency by utilizing surface plasmons in semiconductor light emitting devices.

  The schematic cross-sectional view of FIG. 5 shows a nitride semiconductor light-emitting diode element using surface plasmons disclosed in Japanese Patent Application Laid-Open No. 2005-108982 of Patent Document 1. In this nitride semiconductor light-emitting diode element, a plurality of n-type GaN layers 502 (layer thickness: about 5 μm) and n-type AlGaN cladding layers 503 (layer thickness: about 0.15 μm) stacked alternately on a substrate 501. Multi-quantum well active layer 504 including GaN layer and InGaN layer, undoped GaN protective layer 505 (layer thickness: about 10 nm), p-type AlGaN cladding layer 506 (layer thickness: about 0.15 μm), and p-type GaN contact layer 507 (layer thickness: about 0.3 μm) is formed in this order.

  On the p-type GaN contact layer 507, a Pd first electrode layer 508 (layer thickness: about 1 nm), an Ag second electrode layer 509 (layer thickness: about 2 nm), and an Au protective layer 510 (layer thickness: about 1 nm) A plurality of island-shaped electrodes for p-type having a three-layer structure including the same is formed. These island-shaped p-type electrodes are two-dimensionally periodically arranged, and specifically, are arranged at the closest hexagonal two-dimensional lattice points. Each p-type electrode has a circular planar shape. On the other hand, an n-type electrode 511 is formed on the lower surface of the substrate 501.

  The surface plasmon frequency of Ag corresponds to the vicinity of the 430 nm band of the light wavelength, and the surface plasmon can be excited by light of a slightly longer wavelength blue region. According to Patent Document 1, surface plasmons and light waves at the Ag layer interface can be coupled by arranging electrodes at a required period with respect to light in the blue region emitted from the light emitting layer of the nitride semiconductor light emitting diode element. Thus, an attempt is made to obtain a luminous efficiency enhancement effect.

  Here, the Pd first electrode layer 508 included in the p-type electrode is provided because the Ag layer 509 cannot obtain ohmic contact with the p-type nitride semiconductor. That is, the Pd first electrode layer 508 is a layer for improving the contact of the p-type electrode, and is formed very thin so as not to inhibit surface plasmon excitation at the interface of the Ag layer 509.

In Non-Patent Document 1, Applied Physics Letters, Vol. 87, 071102 (2005), in a nitride semiconductor light emitting diode element, surface plasmon and light are obtained by disposing an Ag-semiconductor interface in the near field of an active layer. A technique for effectively performing the coupling is disclosed. That is, this technique produces an effect by setting the thickness of the semiconductor layer between the active layer and the Ag layer to a very thin 10 nm. In Non-Patent Document 1, it is reported that an increase in spontaneous emission rate was actually observed in light emission from the active layer by optical pumping.
JP 2005-108982 A K. Okamoto et al., “Surface plasmon enhanced spontaneous emission rate of InGaN / GaN quantum wells probed by time-resolved photoluminescence spectroscopy”, Applied Physics Letters, Vol. 87, 071102 (2005).

  In the light emitting diode element disclosed in Patent Document 1, an effective light emission efficiency enhancement effect by surface plasmon has not been obtained yet. This is because it is practically difficult to sufficiently combine surface plasmons and light at the interface of the Ag layer 509. More specifically, in order to obtain ohmic contact with the p-type GaN contact layer 507, the Pd metal layer 508 must be interposed under the Ag layer 509. This Pd layer 508 absorbs light from the active layer 504, thereby reducing surface plasmon excitation at the interface of the Ag layer 509 (see FIG. 5).

  On the other hand, in Non-Patent Document 1, it is necessary to reduce the thickness of the semiconductor layer on the active layer to about 10 nm or less in order to place the Ag layer in the near field of the active layer. The light emission itself is difficult. The reason is that in Non-Patent Document 1, the p-type semiconductor layer and the Ag layer are in direct contact with each other, and the problem that the ohmic contact pointed out in Patent Document 1 cannot be obtained has not been solved. In addition, in doping a p-type impurity in a nitride semiconductor, it is difficult in the first place to obtain a sufficiently high carrier concentration. And since it is difficult to dope a high p-type carrier concentration to an extremely thin nitride semiconductor layer up to a thickness of about 10 nm, the p-type layer itself is very thin, so that holes for light emission are formed. It cannot be sufficiently supplied to the active layer. As described above, in the technique of arranging the Ag layer in the near field of the active layer, a device structure that can satisfactorily inject current has not yet been realized.

  In view of the state of the prior art as described above, an object of the present invention is to provide a semiconductor light emitting device having improved luminous efficiency by reliably utilizing surface plasmons.

  In the semiconductor light emitting device according to the present invention, the first lower layer including the n-type semiconductor, the second lower layer including the p-type semiconductor, the active layer, and the upper layer including the n-type semiconductor are stacked in this order on the substrate. A first n-type electrode is provided in contact with the substrate or the first lower layer, a second n-type electrode is provided on the upper layer, and the upper layer has a thickness of 40 nm or less. And the interface of the second n-type electrode in contact with the upper layer includes a metal capable of exciting surface plasmons by light generated from the active layer.

  The metal whose surface plasmon can be excited by light generated from the active layer preferably contains any one of Ag, Au, and Al as a main component. The first n-type electrode may be an anode electrode and the second n-type electrode may be a cathode electrode.

  Further, the semiconductor light emitting device may be a nitride semiconductor light emitting device. It is preferable that an intermediate layer is further included between the first lower layer and the second lower layer, and this intermediate layer includes a tensile strain due to a lattice constant difference between the first lower layer and the second lower layer. Furthermore, the substrate may be an n-type conductive substrate, and the first n-type electrode is preferably provided in contact with the n-type conductive substrate.

  In the semiconductor light emitting device according to the present invention, carriers can be injected well into the active layer, and a light emission enhancement effect using surface plasmons can be obtained, thereby realizing high light emission efficiency.

  FIG. 1 is a schematic cross-sectional view showing a nitride semiconductor light emitting device according to an embodiment of the present invention. The light-emitting element includes a first lower layer 102 of nitride semiconductor, an intermediate layer 103 of nitride semiconductor, a second lower layer 104 of nitride semiconductor, an active layer 105 of nitride semiconductor, which are sequentially stacked on a substrate 101, and A top layer 106 of nitride semiconductor is included.

  A first n-type electrode 110 is formed on the partially exposed surface of the first lower layer 102. A second n-type electrode 109 is formed on the upper layer 106.

  The first lower layer 102 includes one or a plurality of nitride semiconductor layers and has n-type conductivity as a whole. Here, having n-type conductivity as a whole mainly includes an n-type conductivity layer, and even if a thin undoped layer or the like is disposed in the middle or at the end, electrons are mainly conducted as a whole. It represents having a property. The second lower layer 104 includes one or a plurality of nitride semiconductor layers and has p-type conductivity as a whole. Here, “having p-type conductivity as a whole” mainly includes a p-type conductivity layer, and even if a thin undoped layer or the like is disposed in the middle or at the end, holes are generally conducted as a whole. It represents having a property. The upper layer 106 includes one or a plurality of nitride semiconductor layers and has n-type conductivity as a whole.

  The first n-type electrode 110 is used as an anode, and the second n-type electrode 109 is used as a cathode. That is, during the operation of the light emitting element, a positive voltage is applied to the first n-type electrode 110 from the outside, and a negative voltage is applied to the second n-type electrode 109. Therefore, the current path from the positive voltage to the negative voltage is from the first n-type electrode 110 to the first lower layer 102 having the n-type conductivity as a whole, the intermediate layer 103, and the first having the p-type conductivity as a whole. (2) A path is formed from the lower layer 104, the active layer 105, and the upper layer 106 to the second n-type electrode 109.

  By applying a bias to the light emitting element in this manner, a forward bias is applied to the pn junction formed by the p-type conductive second lower layer 104 and the n-type conductive upper layer 106 as a whole with the active layer 105 interposed therebetween. The light is emitted by the operation of a normal light emitting diode. As for the p-type conductive second lower layer 104 as a whole, the thickness and doping amount are not limited due to the coupling of surface plasmon and light. Therefore, the second lower layer 104 can be doped with a sufficiently high concentration, and sufficient holes can be supplied to the active layer during the operation of the light emitting device.

  Overall, the n-type conductive upper layer 106 needs to be limited to a thickness of at least 40 nm or less in order to couple light from the light emitting layer and the surface plasmon of the second n-type electrode 109. However, doping of the n-type impurity in the nitride semiconductor is easier than in the case of the p-type.

  More specifically, in a nitride semiconductor, a p-type impurity (usually Mg) needs to be doped with an excessive amount of impurity in order to obtain a desired carrier (hole) concentration, and Mg is easily diffused. It is difficult to generate sufficient p-type carriers only in a very thin layer of 40 nm or less. In the nitride semiconductor light emitting device, if Mg diffuses (or is added) into the active layer, the quality of the active layer also deteriorates. However, the carriers generated in the very thin upper layer 106 having a thickness of 40 nm or less are electrons, and the problem as in the case of holes is much less likely to occur.

  That is, in a nitride semiconductor, n-type impurities (usually Si) can generate carriers (electrons) that are almost equivalent to the doping amount, and even if Si diffuses into the active layer, the quality of the active layer is reduced. Less likely to cause problems. On the contrary, there is a report that the luminous efficiency is improved by adding Si to the active layer (Jpn. J. Appl. Phys., Vol. 37 (1998) pp. L362-L364). There is no inconvenience even if the active layer itself is doped with an n-type impurity. In this case, it is not necessary to quickly switch the doping during the growth of a plurality of layers of crystals, and the manufacture of the light emitting device is facilitated. In this specification, the active layer means from the bottom well layer to the top well layer when it is a multiple quantum well, and only the well layer when it is a single quantum well. Means.

  On the other hand, in the light emitting device of FIG. 1, a reverse bias is applied to the additional pn junction formed by the second p-type conductive lower layer 104 and the first n-type conductive lower layer 102 as a whole with the intermediate layer 103 interposed therebetween. Is applied. Here, if a normal pn junction is used, it is difficult for a current to flow in the reverse bias direction. However, by using a configuration (tunnel junction) that allows a tunnel current to flow effectively, a current can be efficiently passed through an additional pn junction. it can. For this purpose, it is preferable that the additional pn junction sandwiching the intermediate layer has a special configuration as exemplified later.

  In the second n-type electrode 109, the interface where it contacts the semiconductor layer is made of Ag. The upper layer 106 is set to a thickness of 40 nm or less. Thus, the semiconductor-Ag interface is disposed in the near field of the active layer 105 so that light from the active layer 105 can be easily coupled with surface plasmons at the Ag interface. The thickness of the upper layer 106 is preferably 20 nm or less, and 10 nm can be a typical value.

  1 as described above, holes and electrons can be efficiently injected into the active layer 105 during current injection operation, and surface plasmon polariton (SPP) in which light from the active layer is combined with surface plasmons. Can be formed at the Ag interface. That is, in the light-emitting element of FIG. 1, SPP can be effectively generated by current injection, an increase in the spontaneous emission rate as in Non-Patent Document 1 can be realized, and improved luminous efficiency can be obtained.

  Note that the Ag layer formed on the nitride semiconductor layer is usually not homogeneous and microscopically includes grain boundaries or has minute irregularities at the interface. Therefore, the generated SPP is modulated and converted into light again while propagating along the interface, and the light is extracted outside. Considering this phenomenon, the Ag layer may be artificially provided with irregularities and patterns. Further, since the Ag layer can form a good ohmic contact with the upper layer 106 of the n-type nitride semiconductor, it is an improvement over the prior art that carriers can be injected well into the active layer.

  Regarding the combination of the emission wavelength of the active layer 105 and the second n-type electrode 109, the following can be considered. Since surface polaritons generated in the second n-type electrode 109 by light from the active layer 105 are related to the surface plasmon frequency of the metal, when using an Ag layer (corresponding wavelength of the surface plasmon frequency is about 440 nm) This is particularly effective for an active layer that emits light in the blue region (wavelength 440 to 500 nm), and an effect can be expected for light having a slightly longer wavelength (wavelength 500 to 600 nm).

  Further, when an Al layer (corresponding to a surface plasmon frequency of about 230 nm) is used, it is particularly effective for an active layer that emits light in the deep ultraviolet region (wavelength 230 nm to 300 nm). The effect can be expected for light up to 300-400 nm.

  Furthermore, when an Au film (corresponding to a surface plasmon frequency of about 540 nm) is used, it is particularly effective for an active layer that emits light in the green to red region (wavelength 540 to 600 nm). The effect can be expected with respect to light on the side (wavelength 600 to 700 nm).

  As for Al and Au, since both of them can form a good ohmic contact with the n-type nitride semiconductor, a good current injection effect can be obtained as in the case of Ag described above. In addition, since Ag, Al, and Au can form good ohmic contact not only with nitride semiconductors but generally with n-type layers of compound semiconductors, other compound semiconductors other than nitride semiconductors can be formed. Is also useful.

  Further, in the case of an alloy in which Ag is the main component and other components are mixed, it is difficult to predict how the surface plasmon frequency changes because there are many unclear points, but the second component containing Ag as the most abundant component. The effect of the present invention can be expected with the n-type electrode 109. Therefore, in the present invention, an Ag alloy layer (Ag atom concentration of 50% or more) can be used for the second n-type electrode 109. The same applies to the case where an Al alloy layer or an Au alloy layer is used for the second n-type electrode 109. In addition to this, the metal that excites surface plasmons can be appropriately selected according to the emission wavelength.

  Next, an additional pn junction will be considered. First, using a hexagonal crystal substrate such as a sapphire substrate, a nitride semiconductor substrate, or a silicon carbide substrate as the substrate 101, a first lower layer 102, an intermediate layer 103, and a C-plane ({0001} plane) When the second lower layer 104 is sequentially epitaxially grown by MOCVD (Metal Organic Chemical Vapor Deposition) method or the like, the surfaces of these epitaxial layers also become C-planes. Such a C-plane orientation is most common in nitride semiconductor light emitting devices.

  Here, in the intermediate layer 103 parallel to the C-plane of the nitride semiconductor, when lattice distortion occurs due to lattice mismatch with the upper and lower layers, a piezoelectric field due to piezoelectric polarization is generated, and the polarization direction is Along the C-axis direction (<0001> direction). As a result, the C plane of the intermediate layer 103 exhibits different electrical properties on the + C axis side and the −C axis side, and the intermediate layer 103 has a lower interface and an upper interface having different polarities. The lower interface is an interface between the n-type conductive first lower layer 102 and the intermediate layer 103, and the upper interface is an interface between the intermediate layer 103 and the p-type conductive second lower layer 104.

  In this way, when the intermediate layer 103 has a polar surface, if the intermediate layer 103 has a laminated structure that receives a tensile stress, the energy band of the intermediate layer 103 is bent, and the first lower layer 102 and the second lower layer 104 are separated. The width of the depletion layer can be reduced. As a result, a tunnel current easily flows in an additional pn junction to which a reverse bias is applied between the first lower layer 102 and the second lower layer 104, and compared with a case where the intermediate layer 103 is not included, the light emitting device. The driving voltage can be reduced. As such a laminated structure, for example, the first lower layer 102 and the second lower layer 104 can be formed of GaN or low Al concentration AlGaN, and the intermediate layer 103 can be formed of AlN or high Al concentration AlGaN. is there. This is because in AlGaN, the lattice constant decreases as the Al concentration increases.

  Further, a hexagonal crystal substrate is used as the substrate 101, and the first lower layer 102 and the intermediate layer 103 are formed on a semipolar plane such as the R plane ({1-102} plane) or {11-22} plane of the substrate 101. , And the second lower layer 104 may be sequentially epitaxially grown by MOCVD or the like. In this case, the surface of the intermediate layer 103 is also a semipolar plane such as an R plane ({1-102} plane) or a {11-22} plane. Thus, even in the intermediate layer 103 having a semipolar surface such as an R-plane ({1-102} plane) or {11-22} plane on the surface, when lattice distortion occurs due to lattice mismatch or the like, Piezoelectric fields are generated by piezoelectric polarization, and the semipolar surfaces on both sides of the intermediate layer 103 exhibit different electrical properties.

  Furthermore, the main surface of the nitride semiconductor substrate may be a surface having an off angle with respect to the C plane or the R plane. In this case, the off angle may be in the range of 0 ° ≦ off angle <45 °. Further, the main surface of the nitride semiconductor substrate may be a surface having an off angle with respect to the nonpolar surface of the M surface ({10-10} surface) or the A surface ({11-20} surface). The off angle in this case may be within the range of 0 degree <off angle <45 degrees. Also in these cases, the driving voltage of the nitride semiconductor light emitting element can be reduced as in the case where the main surface of the substrate is the C plane.

On the other hand, as a configuration for facilitating a reverse bias current to flow through the additional pn junction, it is also effective to perform high-concentration doping at the junction. For example, at least in the vicinity of the junction, the n-type impurity concentration of the first lower layer 102 is preferably set to about 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ within the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ^3. The p-type impurity concentration of the second lower layer 104 is preferably about 3 × 10 ^{19 to} 3 × 10 ²⁰ / cm ³ within the range of 10 ¹⁹ to 10 ²¹ / cm ³ . In this case, the intermediate layer 103 having the composition as described above may be provided to obtain an additive effect, or only the effect of high concentration doping may be used without providing or providing an intermediate layer having a different composition. May be. Here, the vicinity of the junction means a range from the junction interface that can promote a tunnel current by doping to about 50 nm.

  FIG. 2 is a schematic cross-sectional view of a nitride semiconductor light emitting device according to another embodiment of the present invention. Compared to the light emitting device of FIG. 1, the light emitting device of FIG. 2 uses an n-type conductive hexagonal nitride semiconductor substrate 201 and a first n-type electrode 210 is formed on the lower surface of the substrate. It differs only in being.

  That is, the nitride semiconductor light emitting device of FIG. 2 includes a first lower layer 202, an intermediate layer 203, a second lower layer 204, an active layer 205, and an upper layer 206 sequentially stacked on an n-type substrate 201. . A first n-type electrode 210 is formed on the lower surface of the n-type substrate 201, and a second n-type electrode 209 is formed on the upper layer 206. In the light emitting device of FIG. 2, the current path from the positive voltage to the negative voltage is from the first n-type electrode 210 to the n-type substrate 201, the first lower layer 202 having n-type conductivity as a whole, the intermediate layer. 203, the second n-type electrode 209 is formed in this order through a second lower layer 204, an active layer 205, and an upper layer 206 having p-type conductivity as a whole. This is the same as the light emitting element.

  In the semiconductor light emitting device of the present invention, particularly when a nitride semiconductor layer is stacked, a hexagonal semiconductor crystal substrate such as a sapphire substrate, a nitride semiconductor substrate, or a silicon carbide substrate is used as the substrate as described above. Can do. In particular, when a nitride semiconductor substrate is used, the difference in lattice constant between the substrate and the nitride semiconductor layer formed thereon is reduced, and the properties of the substrate and the growth layer are the same. Good crystallinity is obtained.

As the nitride semiconductor substrate, a nitride semiconductor crystal substrate represented by Al _x0 Ga _y0 In _z0 N (0 ≦ x0 ≦ 1, 0 ≦ y0 ≦ 1, 0 ≦ z0 ≦ 1, x0 + y0 + z0 = 1) is used. it can. The layer formed on the substrate is a nitride semiconductor crystal represented by Al _x1 In _{y1 Gaz1} N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1). The layer can be grown. As the n-type impurity, silicon and / or germanium can be used, and group VI elements such as O and Se can also be used. As the p-type impurity, magnesium and / or zinc can be used. The active layers 105 and 205 may have a conventionally known single quantum well (SQW) structure or multiple quantum well (MQW) structure.

  As the first n-type electrodes 110 and 210 in the semiconductor light emitting device of the present invention, a known metal capable of forming an ohmic contact with the n-type first lower layer 102 or the n-type substrate 202 is used. Can do. In the nitride semiconductor light emitting device shown in FIGS. 1 and 2, the upper layers 106 and 206 are formed after the active layers 105 and 205 are formed. Even when the upper layers are formed at a low temperature, the upper layers 106 and 206 are formed. Since this is an n-type nitride semiconductor layer, it is possible to suppress the increase in resistance and significant deterioration in crystallinity. That is, since the upper layers 106 and 206 can be formed at a low temperature, the thermal damage to the active layers 105 and 205 can be reduced.

In particular, it is known that a nitride semiconductor crystal containing In has a considerably lower decomposition temperature than a nitride semiconductor crystal containing no In. For example, nitride semiconductor crystals that do not contain In, such as GaN, AlN, and mixed crystals thereof, are relatively stable even at a high temperature of about 1000 ° C., but InN decomposes even at a low temperature of about 600 to 700 ° C. Therefore, for example, a nitride semiconductor crystal represented by In _y Ga _1-y N generally deteriorates in crystallinity at temperatures exceeding 1000 ° C., although it depends on the In composition ratio y. When light in a long wavelength region such as green light or red light is generated in the active layers 105 and 205, the In composition ratio y of the nitride semiconductor crystal represented by In _y Ga _1-y N is set to 0. It is necessary to set a high value of about 15 to 0.4. In this case, as the concentration of In contained in the nitride semiconductor crystal increases, the tendency of deterioration of crystallinity due to temperature becomes more remarkable. However, in the nitride semiconductor light emitting device of the present invention, since the n-type upper layers 106 and 206 can be grown at a relatively low temperature, deterioration of the active layers 105 and 205 containing In can be suppressed. is there.

<Example 1>
FIG. 3 is a schematic cross-sectional view showing a nitride semiconductor light-emitting diode device according to Example 1 of the present invention. This nitride semiconductor light-emitting diode element includes a 5 μm thick n-type GaN first lower layer 302, a 2.5 nm thick AlN intermediate layer 303, and a second lower lower layer, which are sequentially stacked on a sapphire substrate 301 having a thickness of 150 μm. It includes a layer 304, a multiple quantum well active layer 305, and a top layer 306 of n-type GaN having a thickness of 10 nm.

Here, the second lower layer 304 includes a p-type GaN layer 304a having a thickness of 0.3 μm, a p-type Al _0.1 Ga _0.9 N carrier blocking layer 304b having a thickness of 10 nm, and a non-doped GaN layer 304c having a thickness of 60 nm, which are sequentially stacked. And a non-doped In _0.02 Ga _0.98 N layer 304d having a thickness of 8 nm. The non-doped GaN layer 304c and the non-doped In _0.02 Ga _0.98 N layer 304d on the p-type carrier block layer 304b are for forming a good active layer 305 on the Al-containing carrier block layer 304b having a relatively small lattice constant. It plays the role of preventing the diffusion of Mg from the p-type carrier block layer 304b to the active layer 305, since it may serve as a buffer layer, and if the Mg diffuses into the active layer 305, the luminous efficiency may decrease. Yes.

The multi-quantum well active layer 305 has a laminated structure in which a Si-doped InGaN well layer having a thickness of 4 nm, a Si-doped In _0.02 Ga _0.98 N barrier layer having a thickness of 8 nm, and a Si-doped InGaN well layer having a thickness of 4 nm are sequentially deposited. Have.

  A first n-type electrode 310 is formed on the partially exposed surface of the n-type GaN first lower layer 302, and a second n-type electrode 309 is formed on the n-type GaN upper layer 306. Is formed. The first n-type electrode 310 is formed in direct contact with the first lower layer 302 of n-type GaN, and an Hf layer (thickness 30 nm), an Al layer (stacked in order from the n-type GaN layer side) 200 nm thick), Mo layer (30 nm thick), Pt layer (50 nm thick), and Au layer (200 nm thick).

  On the other hand, the second n-type electrode 309 is formed in direct contact with the n-type GaN upper layer 306, and an Ag layer (thickness 30 nm) and a Pt layer are sequentially stacked from the n-type GaN layer side. (Thickness 50 nm) and an Au layer. In this way, the surface plasmon polariton is generated at the interface between the Ag layer and the upper layer 306 of n-type GaN.

The nitride semiconductor light-emitting diode device of FIG. 3 can be manufactured as follows. First, the first lower layer 302 to the upper layer 306 are sequentially epitaxially grown on the C surface, which is the main surface of the sapphire substrate 301 having a diameter of 2 inches and a thickness of 400 μm, using an MOCVD film forming apparatus. Here, ammonia is used as the nitrogen source, TMG (trimethylgallium) is used as the gallium source, TMI (trimethylindium) is used as the indium source, TMA (trimethylaluminum) is used as the aluminum source, and p-type impurities. As the magnesium source, Cp ₂ Mg (biscyclopentadienyl magnesium) is used, and silane is used as the silicon source of n-type impurities.

The carrier density in the first lower layer 302 of n-type GaN and the upper layer 306 of n-type GaN is about 1 × 10 ¹⁸ cm ⁻³ in both cases. In the AlN intermediate layer 303, neither p-type impurities nor n-type impurities are intentionally doped. The carrier density of the p-type GaN layer 304a included in the second lower layer is about 4 × 10 ¹⁷ cm ⁻³ .

The first lower layer 302 of n-type GaN is deposited by setting the temperature of the sapphire substrate 301 to 1125 ° C., and the AlN intermediate layer 303, the p-type GaN layer 304 a, and the p-type Al _0.1 Ga _0.9 N carrier block layer 304 b are subsequently 1125. Deposited at a substrate temperature of 0C.

Thereafter, the non-doped GaN layer 304c, the non-doped In _0.02 Ga _0.98 N layer 304d, and the multiple quantum well active layer 305 are deposited with the substrate temperature lowered to 750 ° C. The n-type GaN upper layer 306 is then deposited at a substrate temperature of 850 ° C. Thus, even when the upper layer 306 is formed at a relatively low substrate temperature of about 850 ° C. after forming the multiple quantum well active layer 305, the upper layer 306 is an n-type GaN layer, so Resistance and remarkable deterioration of crystallinity can be suppressed. Even when the upper layer of n-type GaN is about 10 nm thin, good n-type impurity doping is possible.

  If the upper layer provided on the active layer is formed of a p-type layer, crystal growth that gives p-type conductivity is difficult at a low temperature of about 850 ° C., and conversely has p-type conductivity. Therefore, if the growth temperature is raised, the well layer will deteriorate due to the temperature rise. In this case, if the thickness of the upper layer is not limited, it is possible to provide a layer for preventing evaporation on the well layer. However, under conditions where only a thickness of about 40 nm is allowed at most, evaporation is not possible. It is difficult to provide a prevention layer.

  On the other hand, a nitride semiconductor layer doped with Mg does not exhibit p-type conductivity unless it is deposited at a high temperature of 1000 ° C. or more, whereas a nitride semiconductor layer doped with Si is deposited at a low temperature of less than 1000 ° C. Even n-type conductivity is exhibited. Therefore, even if the substrate temperature is as low as about 800 ° C., the n-type GaN upper layer 306 can be formed by optimizing the deposition conditions.

  A second n-type electrode 309 is formed on the n-type GaN upper layer 306 by EB (Electron Beam) evaporation. Subsequently, a mask for vapor phase etching is formed on the upper layer 306 and the second n-type electrode 309, and the thickness of the first lower layer 302 is halfway using an ICP (Inductively Coupled Plasma) etching method. Etching is performed. Then, a first n-type electrode 310 is formed on the partially exposed surface of the first lower layer 302 by using an EB vapor deposition method and a sputtering method.

  Thereafter, the thickness of the sapphire substrate 301 is reduced to about 150 μm by general grinding and polishing, and then divided into chips having a square plane with a side of 350 μm by scribing to obtain the nitride semiconductor light-emitting diode device of Example 1. .

  In the nitride semiconductor light-emitting diode device of Example 1, a voltage is applied using the first n-type electrode 310 as an anode and the second n-type electrode 309 as a cathode, whereby a multiple quantum well active layer 305 is applied. To blue light (peak wavelength of about 460 nm) is emitted. In this light-emitting element, a driving voltage when light is emitted by injecting a current of 20 mA is 4 V, and the emitted light is extracted to the outside through the substrate and side surfaces of the element. When the internal quantum efficiency of light emission in this case was estimated, it was 90% or more at 20 mA operation, and an extremely high value was obtained. This is based on the light emission enhancement effect (increase in spontaneous emission rate) due to surface plasmon coupling, and indicates that the spontaneous emission rate is increased so that non-radiative recombination does not become a problem at room temperature.

<Example 2>
In the nitride semiconductor light emitting diode device according to Example 2 of the present invention, the peak emission wavelength of the active layer 305 is set to 550 nm, and accordingly, the metal layer on the semiconductor interface side in the second n-type electrode 309 is changed from Ag to Au. Except for this, the procedure is the same as in the first embodiment.

  When the internal quantum efficiency of light emission in the light emitting device of Example 2 was estimated, it was 50% or more at the time of 20 mA operation, and a high value was obtained.

  When a nitride semiconductor active layer is used, it is known that the most efficient light emission is easily obtained at a wavelength of about 400 nm, and the conventional internal quantum efficiency related to light emission in the green region of a wavelength of about 550 nm is reduced to about ¼. Therefore, 50% is a very good value. That is, also in Example 2, it was confirmed that the light emission efficiency was improved by the light emission enhancing effect by the surface plasmon coupling.

<Example 3>
FIG. 4 is a schematic cross-sectional view showing a nitride semiconductor light-emitting diode device according to Example 3 of the present invention. This nitride semiconductor light-emitting diode element has a 5 μm thick n-type AlGaN first lower layer 402, a 4 nm thick n-type InAlGaN intermediate layer 403, which are sequentially stacked on a 200 μm thick n-type AlGaN substrate 401, It includes a second lower layer 404, a multiple quantum well active layer 405, and an upper layer 406 of n-type AlGaN with a thickness of 20 nm.

  Here, the second lower layer 404 includes a p-type AlGaN layer 404a having a thickness of 0.3 μm, a p-type AlGaN carrier block layer 404b having a thickness of 10 nm, a non-doped InAlGaN layer 404c having a thickness of 60 nm, and a thickness, which are sequentially stacked. It includes an 8 nm non-doped InAlGaN layer 404d. The non-doped InAlGaN layer 404c and the non-doped InAlGaN layer 404d on the p-type carrier block layer 404b are like buffer layers for forming a good active layer 405 on the Al-containing carrier block layer 404b having a relatively small lattice constant. It plays a role of preventing Mg from diffusing from the p-type carrier block layer 404b to the active layer 405 because Mg may diffuse into the active layer 405 and the luminous efficiency may be lowered.

  The multiple quantum well active layer 405 has a stacked structure in which a Si-doped InAlGaN well layer having a thickness of 3 nm, a Si-doped InAlGaN barrier layer having a thickness of 4 nm, and a Si-doped InAlGaN well layer having a thickness of 3 nm are sequentially stacked.

  A first n-type electrode 410 is formed on the lower surface of the n-type AlGaN substrate 401, and a second n-type electrode 409 is formed on the upper layer 406 of the n-type AlGaN.

  The first n-type electrode 410 is formed in direct contact with the n-type AlGaN substrate 410. The second n-type electrode 409 is formed in direct contact with the upper layer 406 of n-type GaN, and is composed of an Al layer (thickness 300 nm). Thus, the surface plasmon polariton is generated at the interface between the Al layer 409 and the upper layer 406 of n-type GaN.

  In the nitride semiconductor light-emitting diode element of Example 3, the drive voltage when driven by 20 mA current injection was 8V. In this case, ultraviolet light (peak wavelength: about 270 nm) is emitted from the multiple quantum well active layer 305. Then, the ultraviolet light is extracted outside through the substrate and the side surface of the light emitting element. When the internal quantum efficiency of this light emission was estimated, it became 10% or more at the time of 20 mA operation, and it showed a very high value as a light emitting diode having a wavelength of 270 nm. This improvement in internal quantum efficiency is based on the light emission enhancement effect (increase in spontaneous emission rate) due to surface plasmon coupling, and that such an effect is realized by current injection in the configuration of the light emitting device of the present invention. Show.

  The above-described embodiments and examples relating to the present invention disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the embodiments or examples described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The light-emitting element of the present invention has high luminous efficiency. For example, it is suitable for communication use in the infrared region, illumination use and display use in the visible region, and sterilization and water purification in the ultraviolet light-emitting device. Can be used.

1 is a schematic cross-sectional view of a light emitting diode device according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a light emitting diode device according to another embodiment of the present invention. 1 is a schematic cross-sectional view of a light emitting diode device according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a light emitting diode device according to another embodiment of the present invention. It is a typical sectional view of the conventional light emitting diode element using the surface polariton effect.

Explanation of symbols

  101, 301 substrate, 201, 401 n-type conductive substrate, 102, 202, 302, 402 as a whole n-type conductive first lower layer, 103, 203, 303, 403, intermediate layer, 104, 204, 304, 404, p-type conductive second lower layer, 105, 205, 305, 405 active layer, 106, 206, 306, 406 n-type conductive upper layer, 109, 209, 309, 409 second n-type electrode 110, 210, 310, 410 First n-type electrode.

Claims (6)

A first lower layer including an n-type semiconductor, a second lower layer including a p-type semiconductor, an active layer, and an upper layer including an n-type semiconductor are stacked in this order on the substrate.
A first n-type electrode is provided in contact with the substrate or the first lower layer;
A second n-type electrode is provided on and in contact with the upper layer;
The upper layer has a thickness of 40 nm or less;
The interface of the second n-type electrode in contact with the upper layer contains a metal whose surface plasmon can be excited by light generated from the active layer.   The semiconductor light emitting element according to claim 1, wherein the metal whose surface plasmon can be excited by light generated from the active layer contains Ag, Au, or Al as a main component.   3. The semiconductor light emitting device according to claim 1, wherein the first n-type electrode is an anode electrode, and the second n-type electrode is a cathode electrode.   4. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is a nitride semiconductor light emitting device.   The intermediate layer further includes an intermediate layer between the first lower layer and the second lower layer, and the intermediate layer includes a tensile strain due to a lattice constant difference between the first lower layer and the second lower layer. The semiconductor light-emitting device according to claim 4, wherein   6. The substrate according to claim 1, wherein the substrate is an n-type conductive substrate, and the first n-type electrode is provided in contact with the n-type conductive substrate. Semiconductor light emitting device.

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