JP2010073880A - Thin-film field effect transistor and method for manufacturing the same - Google Patents

Abstract

An object of the present invention is to provide a manufacturing method of a thin film field-effect transistor using an amorphous oxide semiconductor that can be easily refined and has excellent productivity.
A substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, an amorphous oxide semiconductor layer formed on the gate insulating film, and the amorphous oxide A method of manufacturing a thin film field effect transistor having a source electrode and a drain electrode on a physical semiconductor layer, wherein the source electrode and the drain electrode are formed of a metal that can be electrochemically oxidized, A thin film transistor having a patterning step of patterning the source electrode and the drain electrode by transforming a region that forms a channel portion between the drain electrode and a metal oxide by an electrochemical reaction and removing the metal oxide by etching Production method.
[Selection figure] None

Description

  The present invention relates to a thin film field effect transistor using an amorphous oxide semiconductor for an active layer and a method for manufacturing the same.

2. Description of the Related Art In recent years, flat and thin image display devices (Flat Panel Displays: FPD) have been put into practical use due to advances in liquid crystal and electroluminescence (EL) technologies. In particular, an organic electroluminescent device using a thin film material that emits light when excited by passing an electric current (hereinafter sometimes referred to as “organic EL device”) can emit light with high luminance at a low voltage. Expected to be thinner, lighter, smaller, and save power in a wide range of fields including mobile phone displays, personal digital assistants (PDAs), computer displays, automotive information displays, TV monitors, or general lighting. Has been.
These FPDs are thin film field effect transistors using an amorphous silicon thin film or a polycrystalline silicon thin film provided on a glass substrate as an active layer (in the following description, they may be referred to as Thin Film Transistors or TFTs). It is driven by an active matrix circuit.

On the other hand, in order to further reduce the thickness, weight, and breakage resistance of these FPDs, an attempt has been made to use a lightweight and flexible resin substrate instead of a glass substrate.
However, the manufacture of the transistor using the above-described silicon thin film requires a relatively high temperature thermal process and is generally difficult to form directly on a resin substrate having low heat resistance.
Therefore, an amorphous oxide semiconductor that can be formed at a low temperature, for example, a TFT using InGaZnO, can be formed at room temperature and can be formed on a film, so that it is expected to be a flexible display TFT. ing. In particular, since an oxide semiconductor can obtain high mobility, it is expected as a pixel driving TFT of an organic EL element (see, for example, Patent Document 1).

  As a configuration of the TFT, a bottom gate type configuration is known in which a gate electrode, a gate insulating film, a semiconductor layer, and a source electrode and a drain electrode are arranged on a semiconductor layer in this order. When an amorphous oxide is used for a semiconductor layer, the amorphous oxide is easily dissolved in an acid etching solution. Therefore, it is difficult to use an acid wet etching method for patterning the source electrode and the drain electrode in a bottom gate configuration. The lift-off method is generally used. However, the lift-off method has problems such as difficulty in high-definition patterning and poor production yield.

  The etching rate depends on the metal composition of an oxide containing In, Ga, and Zn (abbreviated as IGZO), an oxide containing In and Zn (abbreviated as IZO), and an oxide containing In and Ga (abbreviated as IGO). It is disclosed that the semiconductor layer and the source electrode and the drain electrode are selectively etched using the difference. For example, an etching method is disclosed in which a semiconductor layer is made of IGO, a source electrode and a drain electrode are made of IGZO, and etching is performed with an alkaline etchant (see, for example, Patent Document 1). However, in this etching method, the difference in etching rate between the semiconductor layer and the source and drain electrodes is not sufficiently large, and it is difficult to control the etching conditions, and it is difficult to use IZGO for the semiconductor layer.

On the other hand, an atomic force microscope lithography method (AFM lithography method) is known as a precision processing means for oxides. For example, the Mo lift-off method is disclosed (for example, refer nonpatent literature 1).
JP 2008-141113 A J. et al. Voc. Jpn. vol. 51, no. 1, 37-43 (2008)

  An object of the present invention is to provide a thin film field effect transistor using an amorphous oxide semiconductor and a method for manufacturing the same. In particular, it is an object of the present invention to provide a thin film field effect transistor which can be easily refined and has excellent productivity, and a method for manufacturing the same.

The above-described problems of the present invention have been solved by the following means.
<1> A substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, an amorphous oxide semiconductor layer formed on the gate insulating film, and the amorphous oxide A method of manufacturing a thin film field effect transistor having a source electrode and a drain electrode on a semiconductor layer, wherein the source electrode and the drain electrode are formed of a metal that can be electrochemically oxidized, and the source electrode and the drain of the metal are formed. A thin film field effect including a patterning step of patterning the source electrode and the drain electrode by transforming a region forming a channel portion between the electrodes into a metal oxide by an electrochemical reaction and removing the metal oxide by etching Type transistor manufacturing method.
<2> The method for producing a thin film field effect transistor according to <1>, wherein the etching is performed by washing with water.
<3> The thin film field effect according to <1> or <2>, wherein the amorphous oxide semiconductor layer includes at least one selected from the group consisting of In, Ga, and Zn, or a composite oxide thereof. Type transistor manufacturing method.
<4> The method for producing a thin film field effect transistor according to <2> or <3>, wherein the metal is Mo.
<5> The method for producing a thin film field effect transistor according to any one of <1> to <4>, wherein the electrochemical reaction is caused by an electrode substrate.
<6> The method for producing a thin film field effect transistor according to any one of <1> to <4>, wherein the electrochemical reaction is performed by an atomic force microscope (AFM).
<7> A thin-film field effect transistor manufactured by the manufacturing method according to any one of <1> to <6>.

  According to the present invention, it is possible to provide a manufacturing method in which high definition of a thin film field effect transistor using an amorphous oxide semiconductor is easy and excellent in productivity. In particular, in the thin film field effect transistor and the method for manufacturing the same according to the present invention, the source electrode and the drain electrode can be patterned by etching, so that productivity is high and high definition is easy.

1. Thin Film Field Effect Transistor A thin film field effect transistor according to the present invention includes at least a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and the gate insulating film. The amorphous oxide semiconductor layer is formed, and the source electrode and the drain electrode are formed on the amorphous oxide semiconductor layer and made of an electrochemically oxidizable metal. Furthermore, the source electrode and the drain electrode are patterned by electrochemical patterning and etching. That is, the metal in the region between the source electrode and the drain electrode that forms the channel portion is converted into a metal oxide by an electrochemical reaction, and the metal oxide is removed by etching.
Preferably, the metal oxide modified by the electrochemical reaction is etched by washing with water.
Preferably, the metal that can be electrochemically oxidized is Mo.
Preferably, electrochemical oxidation is performed by an atomic force microscope (AFM). In another preferred embodiment, electrochemical oxidation is performed by the electrode substrate.

The thin film field effect transistor of the present invention is manufactured by a manufacturing method including at least the following steps.
Gate electrode formation process on substrate → Gate insulating film formation process → Amorphous oxide semiconductor layer formation process → Source electrode and drain electrode film formation process → Patterning process by electrochemical reaction of source electrode and drain electrode → Etching process

Next, the present invention will be described in detail with reference to the drawings.
1 and 2 are schematic views showing the method of manufacturing the thin film field effect transistor of the present invention in the order of steps. A gate electrode 2 is formed on the substrate 1 and patterned using a photolithography method and an etching method (FIG. 1a). One is an electrode for gate wiring. A gate insulating film 3 and a semiconductor layer 4 are formed on the gate electrode (FIG. 1b). Next, the channel formation region on the gate electrode is covered with a resist R by photolithography (FIG. 1c). The portion not protected by the resist is removed by etching (FIG. 1d).

After stripping the resist (FIG. 1e), contact holes for conduction are formed in the gate insulating film 3 by photolithography and etching methods (FIG. 1f), and then the source / drain electrodes 5 are formed as Mo. Is deposited (FIG. 1g). At this stage, the source / drain electrodes are not isolated. Subsequently, in order to pattern the source / drain electrodes, Mo at the location to be removed is electrochemically oxidized and transformed into oxide (MoO ₃ ) by the AFM electrode tip (FIG. 1h). Etching is performed by washing with water, and the portions oxidized to MoO ₃ are eluted and removed to form patterned source and drain electrodes (FIG. 1i). Next, a protective film 7 is formed, and a drain electrode and a contact hole for gate wiring are formed.

FIG. 3 is a schematic view showing another patterning method. The patterned electrode substrate 10 has electrode probes 14 processed into an inverse pattern shape on the electrode block 12. This is brought into contact with the Mo electrode surface of the intermediate material that has undergone the steps (1a) to (1g) in FIG. 2, and the portion in contact with the electrode probe is oxidized by an electrochemical reaction to be transformed into MoO ₃ . Thereafter, etching is performed by washing with water, and the portions oxidized to MoO ₃ are eluted and removed to form patterned source and drain electrodes. Next, a protective film is formed, and contact holes for the drain electrode and the gate wiring are formed.

1) Electrochemically oxidized metal The source electrode and the drain electrode in the present invention are formed of an electrochemically oxidized metal.
The electrochemically oxidized metal used in the present invention forms a metal oxide by oxidation. Since the metal oxide is eluted by the etching solution, a fine pattern can be formed by bringing the microelectrode probe into contact with only the portion to be removed.
The etching solution is a solution that elutes the metal oxide, and when the metal oxide is water-soluble, it is water or an aqueous solution containing salts. It is also preferable to contain an elution promoter such as a metal chelating agent.

<Metal>
Examples of metals that can be used as source / drain electrodes include Mo, Ag, Mg, V, SI, Ti, Al, and composite metals thereof. Preferably, it is Mo. Since Mo forms water-soluble MoO ₃ by an electrochemical reaction, it can be etched with water, so that the source / drain electrodes can be patterned without damaging the semiconductor layer, and thus Mo is a particularly preferable material.

<Film formation method>
The metal film forming method is not particularly limited, such as a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, an ion plating method, a CVD method, a plasma CVD method, or the like. The film can be formed according to a method selected appropriately in consideration of suitability with the material from among chemical methods. For example, when Mo is used, it can be performed according to a direct current magnetron sputtering method, a vacuum deposition method, an ion plating method, or the like.

  The thickness of the metal film is preferably 2 nm or more and 1000 nm or less, more preferably 10 nm or more and 200 nm or less, and still more preferably 20 nm or more and 100 nm or less.

<Electrode probe>
An electrode probe for electrochemically oxidizing a metal is a microprobe known by an atomic force microscope (AFM) lithography method (may be referred to as “AFM lithography method” in the following description). Can be used. The probe can be reduced to a diameter of about several nm, and fine processing from about 10 nm to several tens of μm is possible. Alternatively, it is possible to employ a method in which an electrode block is finely processed, an electrode probe having a reverse pattern shape is processed on the surface, and this is brought into contact with a non-pattern surface. In the former case, necessary patterning can be performed by scanning the electrode probe by setting a drawing program in the computer. However, when the area is large, there is a disadvantage that drawing takes a long time. In the latter case, since the electrochemical oxidation is performed in one step by surface contact, the processing time does not increase even when the size is increased. However, in the latter case, there is a disadvantage that high-definition patterning is difficult due to restrictions on electrode processing accuracy. Therefore, it is preferable to use appropriate means depending on the required fineness and size.

  For example, in the case of Mo, the electrode probe can be oxidized by applying a bias voltage of several volts to several tens of volts.

2) Amorphous oxide semiconductor layer The amorphous oxide semiconductor layer in the present invention (which may be simply referred to as “semiconductor layer” in the following description) is formed by applying a voltage between the source electrode and the drain electrode. Providing a channel conducting. The current is controlled by a voltage applied to the gate electrode and performs a switching function.

<Material>
An amorphous oxide semiconductor is used for the active layer used in the present invention. Since an amorphous oxide semiconductor can be formed at a low temperature, it can be formed on a flexible resin substrate such as a plastic. Good amorphous oxide semiconductors that can be manufactured at low temperatures include oxides containing In, oxides containing In and Zn, and oxides containing In, Ga, and Zn. As the composition structure, InGaO ₃ (ZnO ) _M (m is a natural number of less than 6) is known to be preferable. These are n-type semiconductors whose carriers are electrons. Of course, a p-type oxide semiconductor such as ZnO.Rh ₂ O ₃ , CuGaO ₂ , or SrCu ₂ O ₂ may be used for the active layer. An oxide semiconductor disclosed in JP-A-2006-165529 can also be used.

  In the present invention, an amorphous oxide semiconductor containing at least one selected from the group consisting of In, Ga, Zn, and Sn is preferable. More preferably, it is an amorphous oxide semiconductor containing In. More preferably, it is an amorphous oxide semiconductor further containing Zn or Ga in addition to In. Most preferably, the amorphous oxide semiconductor further contains Ga and Zn in addition to In.

Specifically, the amorphous oxide semiconductor according to the present invention includes In—Ga—Zn—O, and the composition in the crystalline state is represented by InGaO ₃ (ZnO) _m (m is a natural number of less than 6). A physical semiconductor is preferred. In particular, InGaZnO ₄ is more preferable.

<Configuration>
The semiconductor layer in the present invention may be a single layer or a laminate of a plurality of layers. Preferably, it is composed of at least an active layer close to the gate insulating film and a resistance layer close to the source and drain electrodes.
Preferably, the ratio of the electrical conductivity of the active layer to the electrical conductivity of the resistive layer (the electrical conductivity of the active layer / the electrical conductivity of the resistive layer) is 10 ¹ or more and 10 ¹⁰ or less, more preferably 10 ^2. 10 ⁸ or less. Preferably, the electric conductivity of the active layer is 10 ⁻⁴ Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ . More preferably, it is 10 ⁻¹ Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ .
The electric conductivity of the resistance layer is preferably 10 ⁻² Scm ⁻¹ or less, more preferably 10 ⁻⁹ Scm ⁻¹ or more and 10 ⁻³ Scm ⁻¹ or less.

<Thickness of active layer and resistance layer>
The resistance layer is preferably thicker than the active layer. More preferably, the ratio of the thickness of the resistance layer to the thickness of the active layer is more than 1 and 100 or less, more preferably more than 1 and 10 or less.
The thickness of the active layer is preferably 1 nm to 100 nm, more preferably 2.5 nm to 30 nm. The thickness of the resistance layer is preferably 5 nm or more and 500 nm or less, and more preferably 10 nm or more and 100 nm or less.

By using the active layer and the resistance layer having the above structure, a transistor characteristic having an ON / OFF ratio of 10 ⁶ or more can be realized with a TFT having a high mobility of 10 cm ² / (V · sec) or more.

<Measuring means for electrical conductivity>
As a means for adjusting electric conductivity, the following means can be cited when the active layer and the resistance layer are oxide semiconductors.
(1) Adjustment by oxygen defect It is known that when an oxygen defect is formed in an oxide semiconductor, carrier electrons are generated and electric conductivity is increased. Therefore, the electric conductivity of the oxide semiconductor can be controlled by adjusting the amount of oxygen defects. Specific methods for controlling the amount of oxygen defects include oxygen partial pressure during film formation, oxygen concentration and treatment time during post-treatment after film formation, and the like. Specific examples of post-treatment include heat treatment at 100 ° C. or higher, oxygen plasma, and UV ozone treatment. Among these methods, a method of controlling the oxygen partial pressure during film formation is preferable from the viewpoint of productivity. JP-A 2006-165529 discloses that the electric conductivity of an oxide semiconductor can be controlled by adjusting the oxygen partial pressure during film formation, and this technique can be used.

(2) Adjustment by composition ratio It is known that the electrical conductivity changes by changing the metal composition ratio of an oxide semiconductor. For example, Japanese Patent Laid-Open No. 2006-165529 discloses that in InGaZn _1-X Mg _X O ₄ , the electrical conductivity decreases as the Mg ratio increases. In addition, in the oxide system of (In ₂ O ₃ ) _1-X (ZnO) _X , it has been reported that when the Zn / In ratio is 10% or more, the electrical conductivity decreases as the Zn ratio increases. ("New development of transparent conductive film II", CMC Publishing, P.34-35). As specific methods for changing these composition ratios, for example, in a film formation method by sputtering, targets having different composition ratios are used. Alternatively, it is possible to change the composition ratio of the film by co-sputtering with a multi-target and adjusting the sputtering rate individually.

(3) Adjustment by impurities By adding an element such as Li, Na, Mn, Ni, Pd, Cu, Cd, C, N, or P to an oxide semiconductor as an impurity, the electron carrier concentration is reduced. It is disclosed in Japanese Patent Application Laid-Open No. 2006-165529 that electric conductivity can be reduced. As a method for adding an impurity, an oxide semiconductor and an impurity element are co-evaporated, an ion of the impurity element is added to the formed oxide semiconductor film by an ion doping method, or the like.

(4) Adjustment by oxide semiconductor material In the above (1) to (3), the method for adjusting the electric conductivity in the same oxide semiconductor system has been described. Of course, the electric conductivity can be changed by changing the oxide semiconductor material. You can change the degree. For example, it is generally known that a SnO ₂ oxide semiconductor has a lower electrical conductivity than an In ₂ O ₃ oxide semiconductor. By changing the oxide semiconductor material in this manner, the electric conductivity can be adjusted. Particularly known oxide materials with low electrical conductivity include oxide insulator materials such as Al ₂ O ₃ , Ga ₂ O ₃ , ZrO ₂ , Y ₂ O ₃ , Ta ₂ O ₃ , MgO, and HfO _3. These can also be used.
As means for adjusting the electrical conductivity, the above methods (1) to (4) may be used alone or in combination.

<Method for forming active layer and resistance layer>
As a method for forming the active layer and the resistance layer, a vapor phase film formation method is preferably used with a polycrystalline sintered body of an oxide semiconductor as a target. Among vapor deposition methods, sputtering and pulsed laser deposition (PLD) are suitable. Furthermore, the sputtering method is preferable from the viewpoint of mass productivity.

  For example, the film is formed by controlling the degree of vacuum and the oxygen flow rate by RF magnetron sputtering deposition. The greater the oxygen flow rate, the smaller the electrical conductivity.

The formed film can be confirmed to be an amorphous film by a known X-ray diffraction method.
The film thickness can be determined by stylus surface shape measurement. The composition ratio can be determined by fluorescent X-ray (XRF) analysis or RBS (Rutherford backscattering) analysis.

<Electrical conductivity>
The electrical conductivity of the active layer and the resistance layer in the present invention will be described.
The electrical conductivity is a physical property value indicating the ease of electrical conduction of a substance. When the carrier concentration n of the substance is e, the elementary charge is e, and the carrier mobility is μ, the electrical conductivity σ of the substance is expressed by the following equation. expressed.
σ = neμ
When the active layer or the resistance layer is an n-type semiconductor, the carriers are electrons, the carrier concentration indicates the electron carrier concentration, and the carrier mobility indicates the electron mobility. Similarly, when the active layer is a p-type semiconductor, the carrier is a hole, the carrier concentration indicates the hole carrier concentration, and the carrier mobility indicates the hole mobility. The carrier concentration and carrier mobility of the substance can be obtained by Hall measurement.

<How to find electrical conductivity>
By measuring the sheet resistance of a film whose thickness is known, the electrical conductivity of the film can be determined. Although the electrical conductivity of a semiconductor varies with temperature, the electrical conductivity described in the text indicates the electrical conductivity at room temperature (20 ° C.).

3) Gate insulating film As the gate insulating film, at least two or more insulators such as SiO ₂ , SiN _x , SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , and HfO ₂ are used. A mixed crystal compound is used. A polymer insulator such as polyimide can also be used as the gate insulating film.

The thickness of the gate insulating film is preferably 10 nm to 10 μm. The gate insulating film needs to be thickened to some extent in order to reduce leakage current and increase voltage resistance. However, increasing the thickness of the gate insulating film results in an increase in the driving voltage of the TFT. Therefore, it is more preferable that the film thickness of the gate insulating film is 50 nm to 1000 nm for an inorganic insulator and 0.5 μm to 5 μm for a polymer insulator. In particular, it is particularly preferable to use a high dielectric constant insulator such as HfO ₂ for the gate insulating film because TFT driving at a low voltage is possible even if the film thickness is increased.

4) Gate electrode Examples of the gate electrode in the present invention include metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, alloys such as Al-Nd and APC, tin oxide, zinc oxide, indium oxide, Preferable examples include metal oxide conductive films such as indium tin oxide (ITO) and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures thereof.
The thickness of the gate electrode is preferably 10 nm or more and 1000 nm or less.

  The method for forming the gate electrode is not particularly limited, and is a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a CVD method, a plasma CVD method, or the like. It can be formed on the substrate according to a method appropriately selected in consideration of suitability with the material from among the chemical methods described above. For example, when ITO is selected, it can be performed according to a direct current or high frequency sputtering method, a vacuum deposition method, an ion plating method, or the like. When an organic conductive compound is selected as the material for the gate electrode, it can be performed according to a wet film forming method.

5) Etching Method In the present invention, the patterning of the source electrode and the drain electrode is performed by an etching method. Etching in the present invention elutes a metal oxide generated by an AFM lithography method, and an etching solution is a solution for eluting the metal oxide, and the corresponding etching depends on the dissolution characteristics of the metal oxide. It is preferable to select a liquid. In addition, the etching solution preferably does not affect the characteristics of the semiconductor layer or damage the semiconductor layer.
For example, when the metal oxide is water-soluble, the etching solution is water or an aqueous solution. In the case where the metal oxide has sufficient water solubility, water, particularly pure water is preferable from the viewpoint of less damage to the semiconductor layer. In order to accelerate etching, a small amount of a salt such as an alkali metal or alkaline earth metal, a chelating agent that forms a complex with a metal ion, or a surfactant may be added.

6) Substrate The substrate used in the present invention is not particularly limited. For example, YSZ (zirconia stabilized yttrium), inorganic materials such as glass, polyethylene terephthalate, polybutylene terephthalate, polyethylene naphthalate Synthetic resins such as polyester such as polyester, polystyrene, polycarbonate, polyethersulfone, polyarylate, allyl diglycol carbonate, polyimide, polycycloolefin, norbornene resin, poly (chlorotrifluoroethylene), etc. Organic materials, and the like. In the case of the said organic material, it is preferable that it is excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, or low hygroscopicity.

  In the present invention, a flexible substrate is particularly preferably used. The material used for the flexible substrate is preferably an organic plastic film having a high transmittance. For example, polyesters such as polyethylene terephthalate, polybutylene phthalate, and polyethylene naphthalate, polystyrene, polycarbonate, polyethersulfone, polyarylate, polyimide, polycyclo Plastic films such as olefin, norbornene resin, and poly (chlorotrifluoroethylene) can be used. In addition, if the insulating property is insufficient for the film-like plastic substrate, the insulating layer, the gas barrier layer for preventing the transmission of moisture and oxygen, the flatness of the film-like plastic substrate and the adhesion with the electrode and active layer It is also preferable to provide an undercoat layer or the like for improvement.

  Here, the thickness of the flexible substrate is preferably 50 μm or more and 500 μm or less. This is because it is difficult for the substrate itself to maintain sufficient flatness when the thickness of the flexible substrate is less than 50 μm. Further, when the thickness of the flexible substrate is more than 500 μm, it is difficult to bend the substrate itself freely, that is, the flexibility of the substrate itself is poor.

7) Protective film If necessary, a film made of an insulating material may be provided on the TFT as a protective film (sometimes referred to as a protective insulating film). The protective insulating film has a purpose of protecting the semiconductor layer of the active layer or the resistance layer from deterioration due to the atmosphere and a purpose of insulating the electronic device manufactured on the TFT.

Specific examples thereof include MgO, SiO, SiO ₂ , Al ₂ O ₃ , GeO, NiO, CaO, BaO, Fe ₂ O ₃ , Y ₂ O ₃ , or metal oxides such as TiO ₂ , SiN _x , SiN _x. Metal nitride such as O _y , metal fluoride such as MgF ₂ , LiF, AlF ₃ , or CaF ₂ , polyethylene, polypropylene, polymethyl methacrylate, polyimide, polyurea, polytetrafluoroethylene, polychlorotrifluoroethylene, polydichloro Difluoroethylene, a copolymer of chlorotrifluoroethylene and dichlorodifluoroethylene, a copolymer obtained by copolymerizing a monomer mixture containing tetrafluoroethylene and at least one comonomer, and a cyclic structure in the copolymer main chain Fluorine-containing copolymer having water absorption of 1% or more And moisture-proof substances having a water absorption rate of 0.1% or less.

  The method for forming the protective insulating film is not particularly limited. For example, the vacuum evaporation method, the sputtering method, the reactive sputtering method, the MBE (molecular beam epitaxy) method, the cluster ion beam method, the ion plating method, the plasma polymerization method ( High-frequency excitation ion plating method), plasma CVD method, laser CVD method, thermal CVD method, gas source CVD method, coating method, printing method, or transfer method can be applied.

8) Post-treatment If necessary, heat treatment may be performed as a post-treatment of the TFT. The heat treatment is performed at a temperature of 100 ° C. or higher in the air or in a nitrogen atmosphere. As a process of performing the heat treatment, the semiconductor layer may be formed after the film formation or may be performed at the end of the TFT manufacturing process. By performing the heat treatment, there are effects such as suppression of in-plane variation in TFT characteristics and improvement in driving stability.

2. Display Device The thin film field effect transistor of the present invention is preferably used for an image display device using a liquid crystal or an EL element, particularly a flat panel display (FPD). More preferably, it is used for a flexible display device using a flexible substrate such as an organic plastic film as the substrate. In particular, the thin film field effect transistor of the present invention is most preferably used for a display device using an organic EL element and a flexible organic EL display device because of its high mobility.

(application)
A thin film field effect transistor obtained by the present invention is used as a switching element and a driving element of the above-described display device, in particular, an FPD. Alternatively, it is applied in a wide range of fields including general lighting.
In addition to the display device, the thin film field effect transistor of the present invention is widely used for IC cards, ID tags, etc. by forming the thin film field effect transistor of the present invention on a flexible substrate such as an organic plastic film. Application is possible.

  Hereinafter, the thin film field effect transistor and the manufacturing method of the present invention will be described with reference to examples, but the present invention is not limited to these examples.

Example 1
1. Production of TFT Element 1 A TFT element 1 was produced according to the steps shown in FIGS.
As the substrate, an alkali-free glass plate (Corning, product number NO. 1737) was used. On the substrate that had been subjected to ultrasonic cleaning in the order of 15 minutes of pure water → 15 minutes of acetone → 15 minutes of pure water, a film of Mo was formed to a thickness of 40 nm as a gate electrode. The Mo film was formed by a DC magnetron sputtering method (sputtering conditions: DC power 350 W, sputtering gas Ar = 13 sccm, pressure 0.35 Pa, target diameter 3 inches). Patterning was performed by photolithography + etching. As the etching solution, Al etching solution (phosphoric acid / nitric acid / acetic acid mixed solution) manufactured by Kanto Chemical Co., Ltd. was used.

Next, the following gate insulating film was formed on the gate electrode.
Gate insulating film: ₂₀₀ nm of SiO ₂ by RF magnetron sputtering vacuum deposition method (conditions: target SiO ₂ , sputtering gas Ar / O ₂ = 13/2 sccm, RF power 400 W, film forming pressure 0.4 Pa, target diameter 3 inches) And a gate insulating film was provided.

Next, a semiconductor layer made of IGZO was provided to a thickness of 50 nm on the gate insulating film under the following conditions.
Semiconductor layer: Using a polycrystalline sintered body having a composition of InGaZnO ₄ as a target, an RF flow rate of 97 sccm, an O ₂ flow rate of 1.8 sccm, an RF power of 200 W, a pressure of 0.37 Pa, and a target diameter of 3 inches by RF magnetron sputtering. I went there.

Next, a resist pattern was formed in the channel formation region of the semiconductor layer on the gate electrode by a photolithography method. Thereafter, the semiconductor layer in the region not protected by the resist was dissolved and removed with the following etching solution.
Etching solution: ITO-6N (manufactured by Kanto Chemical Co., Ltd., oxalic acid 6N solution)

  Next, after removing the resist with a stripping solution, a contact hole was formed in the gate insulating film portion on the gate electrode for the gate insulating film wiring (by a photolithography method and an etching method using buffered hydrofluoric acid).

  Next, Mo was formed as a source electrode and a drain electrode to a thickness of 30 nm by RF magnetron sputtering (conditions: sputtering gas Ar = 13 sccm, RF power 350 W, film forming pressure 0.35 Pa, target diameter 3 inches). At this stage, the source electrode and the drain electrode are an integral continuous vapor deposition body and are not separated into the source electrode and the drain electrode.

  Next, a bias voltage of 11 V is applied to an AFM electrode chip having a diameter of 2 μm by an AFM lithography method in an environment with a relative humidity of 60% RH, so that a source electrode forming portion, a drain electrode forming portion, and a wiring extraction electrode portion Mo other than was oxidized electrochemically. Thereafter, it was immersed in pure water and subjected to etching treatment for 10 minutes while applying ultrasonic waves.

Subsequently, the following protective film was formed and patterned.
Protective film: SiO ₂ is formed to 400 nm by RF magnetron sputtering vacuum deposition method (conditions: target SiO ₂ , sputtering gas Ar / O ₂ = 13/2 sccm, RF power 400 W, deposition pressure 0.4 Pa, target diameter 3 inches) Then, a protective film was provided.
Patterning method: Photolithographic method and buffered hydrofluoric acid etching method.

2. Observation of Patterning Shape When the obtained TFT element 1 was observed, Mo at the electrochemically oxidized portion of the source / drain electrode was completely removed, and the source electrode and the drain electrode were patterned into a desired shape.

3. TFT performance As a result of evaluating the transfer characteristics of the TFT element 1 having the channel length L = 2 μm and the channel width W = 10 μm manufactured in Example 1 with the drain voltage Vd = 10 V, the mobility was 12 cm ² / Vs and the threshold voltage was 1.1 V. Excellent TFT characteristics with an ON / OFF ratio of 3.0 × 10 ⁷ were obtained.

Example 2
1. Production of TFT Element 2 A TFT element 2 was produced in the same manner as in Example 1 except that the patterning step by AFM lithography in Example 1 was performed using an electrode substrate 10 as shown in FIG.
The electrode substrate 10 has a convex shape having a pattern opposite to the source / drain electrode pattern to be patterned on the surface of the electrode block 12. This was brought into contact with the source / drain electrode surface, and a bias voltage of 20 V was applied under a relative humidity of 70% RH.

2. Observation of Patterning Shape When the obtained TFT element 2 was observed, Mo at the electrochemically oxidized portion of the source / drain electrode was completely removed, and the source electrode and the drain electrode were patterned into a desired shape.

3. TFT performance As a result of evaluating the transfer characteristics of the TFT element 1 manufactured in Example 1 having a channel length L = 5 μm and a channel width W = 25 μm with a drain voltage Vd = 10 V, the mobility is 14 cm ² / Vs and the threshold voltage is 1.2 V. Excellent TFT characteristics with an ON / OFF ratio of 5.0 × 10 ⁷ were obtained.

Example 3
1. Production of TFT Element 3 In the element 1 of the present invention of Example 1, the semiconductor layer was composed of the following two layers of active layer and resistance layer.
Active layer: A layer facing the gate insulating film side, and formed to a thickness of 10 nm under the following conditions.
Using a polycrystalline sintered body having a composition of InGaZnO ₄ as a target, by an RF magnetron sputtering vacuum deposition method, an Ar flow rate of 97 sccm, an O ₂ flow rate of 0.8 sccm, an RF power of 200 W, a pressure of 0.37 Pa, and a target diameter of 3 inches. went.
Resistive layer: A layer facing the source and drain electrodes, and formed to a thickness of 40 nm under the following conditions.
Similar to the active layer, except that the O ₂ flow rate was changed to 2.0 sccm.

2. Observation of Patterning Shape When the obtained TFT element 3 was observed, Mo in the electrochemically oxidized portion of the source / drain electrode was completely removed, and the source electrode and the drain electrode were patterned into a desired shape.

3. TFT performance As a result of evaluating the transfer characteristics of the TFT element 3 having the channel length L = 2 μm and the channel width W = 10 μm manufactured in Example 3 with the drain voltage Vd = 10 V, the mobility is 22 cm ² / Vs, and the threshold voltage is 0.8 V. TFT characteristics with an On / Off ratio of 1.0 × 10 ⁸ were obtained.
Compared with the TFT element 1, the mobility was high and the ON / OFF ratio was high.

It is a schematic diagram which shows the order of a process about the manufacturing method of the TFT element of this invention. It is a schematic diagram which shows the next process order about the manufacturing method of the TFT element of this invention. It is a schematic diagram which shows another aspect of the manufacturing method of the TFT element of this invention.

Claims (7)

  A substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, an amorphous oxide semiconductor layer formed on the gate insulating film, and the amorphous oxide semiconductor layer A method of manufacturing a thin film field effect transistor having a source electrode and a drain electrode on the substrate, wherein the source electrode and the drain electrode are formed of a metal that can be oxidized electrochemically, and the source electrode and the drain electrode of the metal A thin film field effect transistor having a patterning step of patterning the source electrode and the drain electrode by transforming a region that forms a channel portion into a metal oxide by an electrochemical reaction and removing the metal oxide by etching. Production method.   2. The method of manufacturing a thin film field effect transistor according to claim 1, wherein the etching is performed with water washing. 3. The thin film field effect transistor according to claim 1, wherein the amorphous oxide semiconductor layer includes at least one selected from the group consisting of In, Ga, and Zn, or a composite oxide thereof. Production method.   The method of manufacturing a thin film field effect transistor according to claim 2 or 3, wherein the metal is Mo.   The method for manufacturing a thin film field-effect transistor according to claim 1, wherein the electrochemical reaction is based on an electrode substrate.   The method of manufacturing a thin film field effect transistor according to any one of claims 1 to 4, wherein the electrochemical reaction is performed by an atomic force microscope (AFM).   A thin film field effect transistor manufactured by the manufacturing method according to claim 1.