JP2010063047A - Class-d amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a class-D amplifier which prevents a load-driving waveform from being distorted, even when a target value for the pulse width of a PWM (pulse width modulation) pulse to be generated becomes less than a minimum pulse width. <P>SOLUTION: In a pulse width modulation circuit 10, when a PWM pulse P, having a pulse width less than a minimum pulse width, is output if conforming to a pulse width value output by a transformation section 11 is made, a correction section 12 reduces the frequency of outputting the PWM pulse P less than the minimum pulse width from a pulse generation section 13, in comparison with the case where a stream of PWM pulses P each having the pulse width of a pulse width value, and corrects for the pulse width value to be supplied to the pulse generation section 13 so as to perform driving approximate to driving of a load 40 to be achieved, by outputting the stream of PWM pulses P, each having the pulse width of the pulse width value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a class D amplifier suitable for a power amplifier of audio equipment.

  The class D amplifier is an amplifier that generates a pulse width modulated (PWM) pulse in accordance with an input signal and drives a load with the PWM pulse. This class D amplifier is often used as a power amplifier for driving a speaker in audio equipment or the like.

  By the way, in the class D amplifier, in order to reduce the distortion generated in the drive waveform of the load, the PWM pulse train which accurately reflects the input signal waveform by controlling the pulse width of the PWM pulse with high resolution over a wide range. The ability to generate is required. However, in a class D amplifier, an output buffer that drives a load based on a PWM pulse has a lower limit (hereinafter referred to as a minimum pulse width) for the pulse width of the PWM pulse that can be transmitted to the load. For this reason, when a PWM pulse less than the minimum pulse width is generated in the class D amplifier, such a PWM pulse is not effectively transmitted to the load via the output buffer, causing distortion in the drive waveform of the load. .

  The present invention has been made in view of the circumstances described above, and prevents distortion in the drive waveform of the load even when the target value of the pulse width of the PWM pulse to be generated is less than the minimum pulse width. It is an object of the present invention to provide a class D amplifier that can be used.

The present invention includes a pulse width modulation circuit that generates a PWM pulse that is pulse width modulated by an input signal, and an output buffer circuit that drives a load in accordance with the PWM pulse, and the pulse width modulation circuit outputs If the target value of the pulse width of the power PWM pulse is equal to or greater than the minimum pulse width that is the lower limit value of the PWM pulse width that can cause the output buffer circuit to drive the load effectively, When a PWM pulse having a pulse width is output and the target value of the pulse width of the PWM pulse to be output is less than the minimum pulse width, a PWM pulse having a pulse width according to the target value is output. PWM pulses having a pulse width corrected from the pulse width corresponding to the target value so that driving similar to the driving of the load to be realized is performed. Providing class D amplifier characterized by force.
According to this invention, the pulse width modulation circuit is realized by outputting a PWM pulse train having a pulse width according to the target value when the target value of the pulse width of the PWM pulse to be output is less than the minimum pulse width. A PWM pulse having a pulse width corrected from the pulse width corresponding to the target value is output so that the driving approximate to the driving of the load to be performed is performed. Therefore, the drive waveform applied to the load is in accordance with the input signal, and the drive waveform can be prevented from being distorted.

Embodiments of the present invention will be described below with reference to the drawings.
<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a class D amplifier according to the first embodiment of the present invention. As shown in FIG. 1, the class D amplifier includes a pulse width modulation circuit 10, a pre-driver 20, and an output buffer 30. A signal value of the input audio signal is input to the pulse width modulation circuit 10 at a constant sampling period. The pulse width modulation circuit 10 is a circuit that generates a PWM pulse P having a pulse width corresponding to the signal value input in this way for each sampling period and supplies the PWM pulse P to the pre-driver 20. The pre-driver 20 is a circuit that drives the output buffer 30 based on the PWM pulse P. In this example, the output buffer 30 includes a P-channel field effect transistor 31 and an N-channel field effect transistor 32. Here, the source of the P-channel field effect transistor 31 is connected to the power supply VDD, and the source of the N-channel field effect transistor 32 is connected to the ground line. The P-channel field effect transistor 31 and the N-channel field effect transistor 32 are connected to each other to serve as an output terminal OUT of the class D amplifier. Between the output terminal OUT and the ground line, For example, a load 40 including a speaker and a low-pass filter is inserted. The pre-driver 20 sets the P-channel field effect transistor 31 to the ON state and the N-channel field effect transistor 32 to the OFF state during the period in which the PWM pulse P supplied from the pulse width modulation circuit 10 is at the H level. During the L level period, the P-channel field effect transistor 31 is turned off and the N-channel field effect transistor 32 is turned on.

  In the present embodiment, the pulse width modulation circuit 10 includes a conversion unit 11, a correction unit 12, and a pulse generation unit 13. Here, the converter 11 is a circuit that converts the signal value of the input audio signal into a pulse width value according to a conversion table stored in advance. This pulse width value is a numerical value obtained by dividing the target value of the pulse width of the PWM pulse P output from the pulse generator 13 by the resolution of the pulse width. The sequence of pulse width values output from the conversion unit 11 is supplied to the pulse generation unit 13 through the processing of the correction unit 12. The pulse generator 13 receives one pulse width value for each sampling period, and outputs a PWM pulse P having a pulse width indicated by the pulse width value.

  The feature of this embodiment resides in the correction unit 12 interposed between the conversion unit 11 and the pulse generation unit 13. The correction unit 12 determines whether the pulse generation unit 13 generates a PWM pulse P having a pulse width less than the minimum pulse width when the pulse width value sequence output from the conversion unit 11 is sent to the pulse generation unit 13 as it is. Determine whether. Here, the minimum pulse width is a lower limit value of the pulse width of the PWM pulse P that allows the output buffer 30 to drive the load 40 effectively. When the PWM pulse P having a pulse width less than the minimum pulse width is output according to the pulse width value output from the conversion unit 11, the correction unit 12 outputs a PWM pulse P having a pulse width equal to the pulse width value. Compared with the case of outputting a series of pulses, the frequency of outputting PWM pulses P less than the minimum pulse width from the pulse generator 13 is reduced, and a series of PWM pulses P having a pulse width according to the pulse width value is outputted. Thus, the pulse width value to be supplied to the pulse generator 13 is corrected so that the driving approximate to the driving of the load 40 to be realized is performed. Although various modes of this correction can be considered, the correction unit 12 in the present embodiment is configured so that the pulse width value obtained by adding two pulse width values when the pulse width value is less than the minimum pulse width twice in succession. And a pulse width value having a value of “0” is output.

  Next, the operation of this embodiment will be described with reference to FIG. In this example, the positive minimum pulse width value is “3” as shown in FIG. When the pulse width value corresponding to the signal value is “3” or more, the PWM pulse P having such a pulse width is effectively transmitted to the load 40 via the output buffer 30. Is not corrected (see FIGS. 2B to 2D). However, when the pulse width value corresponding to the signal value is, for example, “2” which is less than the minimum pulse width value, ideally, the PWM pulse P as illustrated in FIG. In contrast, in practice, the PWM pulse P disappears in the process of being transmitted through the output buffer 30 as illustrated in FIG. Therefore, in order to prevent such a problem, in the present embodiment, the correction unit 12 corrects the pulse width value. 2E illustrates the waveform of the PWM pulse P output from the output buffer 30 when the pulse width value sequence corrected by the correction unit 12 is sent to the pulse generation unit 13. FIG. In this example, “2” after the pulse width value “2” appearing twice in succession in the pulse width value sequence output from the conversion unit 11 is set to “0”, and instead the previous pulse width value “ “2” is increased by “2” to “4”. That is, in this example, instead of outputting two PWM pulses P having a pulse width value “2” from the output buffer 30, one PWM pulse P having a pulse width value “4” is output. In this case, the PWM pulse P having a pulse width value “4” is transmitted to the load 40 via the output buffer 30. However, since the load 40 includes a speaker and a low-pass filter, a substantial drive voltage is temporarily applied to the load 40. This approximates the drive voltage that would be obtained when two PWM pulses P having a pulse width value “2” are transmitted via the output buffer 30. Accordingly, it is possible to prevent the drive waveform of the load 40 from being distorted.

  Although the case where the positive PWM pulse P is output has been described above, the same applies to the case where the negative PWM pulse P is output. For example, as shown in FIG. 2F, it is assumed that the negative minimum pulse width value is “3”. When the pulse width value of the negative PWM pulse P corresponding to the signal value is “3” or more, the PWM pulse P having such a pulse width is effectively transmitted to the load 40 via the output buffer 30. Therefore, the pulse width value is not corrected (see FIG. 2 (g)). However, when the pulse width value of the negative PWM pulse P corresponding to the signal value is, for example, “2” which is less than the minimum pulse width value, ideally the PWM pulse P as illustrated in FIG. In contrast to the output from the buffer 30, the PWM pulse P actually disappears in the process of being transmitted through the output buffer 30 as illustrated in FIG. 2 (h) '. Therefore, in order to prevent such a problem, in the present embodiment, the correction unit 12 corrects the pulse width value. In the example shown in FIG. 2 (h) ″, instead of outputting two negative PWM pulses P with a pulse width value “2” from the output buffer 30, a negative PWM pulse P with a pulse width value “4” is output. Is output.

  As described above, according to the present embodiment, when the pulse width of the PWM pulse P corresponding to the signal value is less than the minimum pulse width, the PWM pulse P having the pulse width is not output and output in the immediately preceding sampling period. Since the correction is performed so that the pulse width of the PWM pulse P to be increased is increased by the pulse width of the PWM pulse P that is not output, it is possible to prevent distortion in the drive waveform applied to the load 40.

<Second Embodiment>
FIG. 3 is a circuit diagram showing a configuration of a class D amplifier according to the second embodiment of the present invention. As shown in FIG. 3, the class D amplifier includes a pulse width modulation circuit 50, a pre-driver 60, and an output buffer 70. The pulse width modulation circuit 50 receives the signal value of the input audio signal every fixed sampling period, and alternately pre-drivers the first PWM pulse P1 and the second PWM pulse P2 that have been subjected to pulse width modulation by this signal value. 60. Here, in the pulse width modulation performed by the pulse width modulation circuit 50, the change in the pulse width of the first PWM pulse P1 and the change in the pulse width of the second PWM pulse P2 with respect to the change in the signal value of the input audio signal are reversed. It is. When the signal value of the input audio signal increases by ΔI from the reference value I0, for example, the pulse width of the first PWM pulse P1 increases from the reference pulse width W0 corresponding to the reference value I0 to an increase proportional to the signal value increase ΔIN. It increases by ΔW to become W0 + ΔW, and the pulse width of the second PWM pulse P2 decreases from the reference pulse width W0 corresponding to the reference value I0 by a decrease ΔW proportional to the increase ΔIN of the signal value to become W0−ΔW. . The pre-driver 60 is a circuit that drives the output buffer 70 based on the first PWM pulse P1 and the second PWM pulse P2.

  The output buffer 70 includes P channel field effect transistors 71 and 73 and N channel field effect transistors 72 and 74. Here, the sources of the P-channel field effect transistors 71 and 73 are connected to the power supply VDD, and the sources of the N-channel field effect transistors 72 and 74 are connected to the ground line. The drain of the P-channel field effect transistor 71 and the drain of the N-channel field effect transistor 72 are connected to each other, and the connection point serves as the output terminal OUTP of the class D amplifier. The drains of the channel field effect transistors 74 are connected to each other, and the connection point is the output terminal OUTM of the class D amplifier. A load 80 composed of, for example, a speaker and a low-pass filter is interposed between the output terminals OUTP and OUTM.

  The pre-driver 60 turns on the P-channel field effect transistor 71 and the N-channel field effect transistor 74 while the first PWM pulse P1 supplied from the pulse width modulation circuit 50 is at the H level, and the P-channel field effect transistor 73 and the N-channel field effect transistor 72 are turned off. Accordingly, the output buffer 70 drives the load 80 with the first polarity in which the output terminal OUTP side has a high potential and the output terminal OUTM side has a low potential. In addition, the pre-driver 60 turns on the P-channel field effect transistor 73 and the N-channel field effect transistor 72 during the period in which the second PWM pulse P2 supplied from the pulse width modulation circuit 50 is at the H level, The effect transistor 71 and the N-channel field effect transistor 74 are turned off. Thus, the output buffer 70 drives the load 80 with a polarity opposite to the first polarity, that is, drives the load 80 with the second polarity with the output terminal OUTM side having a high potential and the output terminal OUTP side having a low potential. Do.

  In the present embodiment, the pulse width modulation circuit 50 includes a conversion unit 51, a correction unit 52, and a pulse generation unit 53. Here, the converter 51 is a circuit that converts the signal value of the input audio signal into a pulse width value of the first PWM pulse P1 and a pulse width value of the second PWM pulse P2 in accordance with a conversion table stored in advance. The sequence of pulse width values of the first PWM pulse P1 and the sequence of pulse width values of the second PWM pulse P2 output from the conversion unit 51 are supplied to the pulse generation unit 53 through the processing of the correction unit 52. . The pulse generator 53 receives a set of the pulse width value of the first PWM pulse P1 and the pulse width value of the second PWM pulse P2 for each sampling period, and has a pulse width corresponding to each pulse width value. The first PWM pulse P1 and the second PWM pulse P2 are sequentially output.

  In this embodiment, the correction unit 52 sends the pulse width value sequence of the first PWM pulse P1 and the pulse width value sequence of the second PWM pulse P2 output from the conversion unit 51 to the pulse generation unit 13 as they are. In this case, it is determined whether or not the pulse generator 53 generates the PWM pulse P1 or P2 having a pulse width less than the minimum pulse width. For example, when the PWM pulse P1 having a pulse width less than the minimum pulse width is generated, the correction unit 52 does not generate the PWM pulse P1 having a pulse width less than the minimum pulse width. The pulse width value to be supplied to the pulse generator 53 is corrected so that driving similar to the driving of the load 80 to be realized by generating the PWM pulse P1 having a pulse width less than the width is performed. Specifically, the correction unit 52 corrects the pulse width value sequence that decreases the pulse width of the PWM pulse P2 that is not less than the minimum pulse width by the pulse width of the PWM pulse P1 that is not generated. On the other hand, when PWM pulses P1 and P2 having a pulse width according to the pulse width value sequence output from the converter 51 are generated, a PWM pulse P2 having a pulse width less than the minimum pulse width is generated in a certain sampling period. The unit 52 does not generate the PWM pulse P2 having a pulse width less than the minimum pulse width in the sampling period, and instead, does not generate the PWM pulse P2 that is not less than the minimum pulse width by the pulse width of the PWM pulse P2 that is not generated. Correction of the pulse width value sequence for decreasing the pulse width of the pulse P1 is performed.

  Next, the operation of this embodiment will be described with reference to FIG. In this example, the minimum pulse width value of the PWM pulses P1 and P2 is “3”. In this example, in order to prevent the complexity of FIG. 4, the pulse width value of the pulse width W0 corresponding to the reference value I0 is set to “5”, and 1/5 of the pulse width W0 is set to the pulse width. Although the control resolution is used, the pulse width is actually controlled with a resolution much finer than this. In FIG. 4 (1a), (1b), and (1c), the pulse width values of the PWM pulses P1 and P2 corresponding to the signal values are all “5”. In this case, since both pulse width values are equal to or greater than the minimum pulse width value “3”, correction by the correction unit 52 is not performed, and the pulses output by the conversion unit 51 are output as shown in FIGS. 4 (1a) and (1b). PWM pulses P 1 and P 2 having a width of “5” are generated and are effectively transmitted to the load 80 via the output buffer 70. As a result, as shown in FIG. 4 (1c), a positive pulse corresponding to the PWM pulse P1 and a negative pulse corresponding to the PWM pulse P2 appear in the waveform of the drive voltage OUTP-OUTM applied to the load 80. Since these positive and negative pulses both have a pulse width corresponding to the pulse width value “5”, the average value of the drive voltages OUTP-OUTM throughout one sampling period is “5” − “5” = “ 0 ".

  4 (2a), (2b), and (2c), the pulse width value of the PWM pulse P1 corresponding to the signal value is “3”, and the pulse width value of the PWM pulse P2 is “7”. Also in this case, since both pulse width values are equal to or greater than the minimum pulse width value “3”, the correction by the correction unit 52 is not performed, and the conversion unit 51 outputs as shown in FIGS. 4 (2a) and (2b). PWM pulses P1 and P2 having a pulse width corresponding to the pulse width value are generated and are effectively transmitted to the load 80 via the output buffer 70. As a result, as shown in FIG. 4 (2c), a positive pulse corresponding to the PWM pulse P1 and a negative pulse corresponding to the PWM pulse P2 appear in the waveform of the drive voltage OUTP-OUTM applied to the load 80. Here, since the positive pulse has a pulse width corresponding to the pulse width value “3” and the negative pulse has a pulse width corresponding to the pulse width value “7”, driving through one sampling period is performed. The average value of the voltage OUTP-OUTM corresponds to “3” − “7” = “− 4”.

  4 (3a), (3b), and (3c), the pulse width value of the PWM pulse P1 corresponding to the signal value is “2”, and the pulse width value of the PWM pulse P2 is “8”. In this case, since the pulse width value “2” of the PWM pulse P1 is less than the minimum pulse width value “3”, correction by the correction unit 52 is performed. If this correction is not performed and PWM pulses P1 and P2 having the same pulse width as that output from the converter 51 are generated as shown in FIGS. 4 (3a) and (3b), the pulse width value The “2” PWM pulse P 1 is not effectively transmitted to the load 80 via the output buffer 70. As a result, as shown in FIG. 4C, a negative pulse corresponding to the PWM pulse P2 appears in the waveform of the drive voltage OUTP-OUTM applied to the load 80, but a positive pulse corresponding to the PWM pulse P1. Does not appear. If both the PWM pulse P1 having the pulse width value “2” and the PWM pulse P2 having the pulse width value “8” are effectively transmitted to the load 80 via the output buffer 70, the drive voltage OUTP applied to the load 80 is assumed. In the waveform of −OUTM, a positive pulse with a pulse width corresponding to the pulse width value “2” and a negative pulse with a pulse width corresponding to the pulse width value “8” appear, and the drive voltage OUTP throughout one sampling period The average value of −OUTM should correspond to “2” − “8” = “− 6”. However, since the PWM pulse P1 having the pulse width value “2” is not effectively transmitted to the load 80, the average value of the drive voltage OUTP-OUTM throughout one sampling period corresponds to “0” − “8” = “− 8”. Will be. Therefore, if no measures are taken, the waveform of the drive voltage OUTP-OUTM is distorted.

  However, in this embodiment, when the pulse width value of the PWM pulse P1 or the pulse width value of the PWM pulse P2 corresponding to the signal value is less than the minimum pulse width value, correction by the correction unit 52 is performed. For example, as shown in FIGS. 4 (3a) and (3b), when the pulse width value of the PWM pulse P1 corresponding to the signal value is “2” and the pulse width value of the PWM pulse P2 is “8”, the correction unit 52 The pulse width value of the PWM pulse P1 is “0”, and the pulse width value of the PWM pulse P2 is “8” − “2” = “6”. Then, the pulse generator 53 does not output the PWM pulse P1 according to the pulse width value corrected by the correcting unit 52, as shown in FIGS. 4 (3a) ′ and (3b) ′, and the pulse width value “6”. Only the PWM pulse P2. Then, only the PWM pulse P 2 having the pulse width value “6” is effectively transmitted to the load 80 via the output buffer 70. As a result, a negative pulse having a pulse width corresponding to the pulse width value “6” appears in the waveform of the drive voltage OUTP-OUTM applied to the load 80, and the average value of the drive voltage OUTP-OUTM throughout one sampling period is This corresponds to “0” − “6” = “− 6”. This is obtained when it is assumed that both the PWM pulse P1 having the pulse width value “2” and the PWM pulse P2 having the pulse width value “8” before correction are effectively transmitted to the load 80 via the output buffer 70. This is the same value as the average value of the driving voltage OUTP-OUTM. Accordingly, no distortion occurs in the waveform of the drive voltage OUTP-OUTM.

  As described above, also in the present embodiment, the correction of the pulse width value performed by the correction unit 52 can prevent the drive waveform applied to the load 80 from being distorted.

  Although the first and second embodiments of the present invention have been described above, other embodiments can be considered other than this. For example:

(1) In the first embodiment, the correction unit 12 corrects the pulse width value sequence when the pulse width value sequence output from the conversion unit 11 includes the minimum pulse width value. This operation may be performed in the previous stage. For example, in a section in which a signal value converted into a pulse width value less than the minimum pulse width continues, the signal value may be doubled and the signal value may be set to 0 every other value. Also in this aspect, the same effect as the first embodiment can be obtained.

(2) In the first embodiment, when one of the target values of the pulse widths of two consecutive PWM pulses is less than the minimum pulse width and the other is greater than or equal to the minimum pulse width, Instead of outputting two PWM pulses, the pulse width modulation circuit 10 may be configured to output one PWM pulse having a pulse width obtained by adding the target values of the pulse widths of the two PWM pulses. More specifically, when one of the pulse width target values of two consecutive PWM pulses is less than the minimum pulse width and the other is greater than or equal to the minimum pulse width, the pulse width modulation circuit 10 is less than the minimum pulse width. Instead of outputting a PWM pulse with a pulse width equal to the target value, instead of a PWM pulse with a pulse width equal to or greater than the minimum pulse width, a pulse with a pulse width less than the minimum pulse width to a target value greater than the minimum pulse width A PWM pulse having a pulse width obtained by adding the width target value is output. To explain with a specific example, when the pulse width value of the minimum pulse width is “3”, the converter 11 in FIG. 1 sets “2” and “3” as the pulse width values of two consecutive PWM pulses. ”Is output, the correction unit 12 corrects the pulse width value“ 2 ”that is less than the minimum pulse width to“ 0 ”, and instead sets the pulse width value“ 3 ”that is equal to or greater than the minimum pulse width to“ 5 ”. It is corrected and output. By adopting this mode, it is possible to further reduce the distortion of the drive waveform of the load.

(3) In the first and second embodiments, a minimum pulse other than “0” is obtained by a two-step procedure of converting a signal value of an input signal into a pulse width value and correcting the converted pulse width value. A pulse width value sequence not including a pulse width value less than the width value was generated. However, instead of following such a two-step procedure, a conversion table for directly converting the signal value of the input signal into the corrected pulse width value is stored in the conversion unit 11 or 51, and the correction unit 12 or 52 is stored. May be omitted. For example, in the second embodiment, a conversion table is provided for associating the signal value with a set of the pulse width value of the PWM pulse P1 and the pulse width value of the PWM pulse P2, and the above-described FIGS. 4 (3a), (3b), (3c) and (3a ) In the situations shown in '(3b)' (3c) ', the pulse width values of the PWM pulses P1 and P2 corresponding to the same signal values as assumed in these situations are “2” and “8”. Instead, “0” and “6” are defined in the conversion table. In this way, the correction unit 52 can be omitted. That is, in the present invention, “outputting a PWM pulse train with a corrected pulse width” not only generates a pulse width value from a signal value and then corrects the pulse width value as a process, but also makes such a correction. Therefore, it should be interpreted as a broad concept including directly generating a PWM pulse having a pulse width with a desired correction state directly from a signal value without performing any special post-processing.

1 is a circuit diagram showing a configuration of a class D amplifier according to a first embodiment of the present invention. FIG. It is a wave form diagram which shows the operation | movement of the embodiment. It is a circuit diagram which shows the structure of the class D amplifier which is 2nd Embodiment of this invention. It is a wave form diagram which shows the operation | movement of the embodiment.

Explanation of symbols

10, 50 ... Pulse width modulation circuit, 20, 60 ... Pre-driver, 30, 70 ... Output buffer, 40, 80 ... Load, 11, 51 ... Conversion part, 12, 52 ... Correction part, 13 , 53... Pulse generator, 31, 71, 73... P-channel field effect transistor, 32, 72, 74.

Claims (4)

A pulse width modulation circuit that generates a PWM pulse that is pulse width modulated by an input signal;
An output buffer circuit for driving a load in response to the PWM pulse,
In the pulse width modulation circuit, the target value of the pulse width of the PWM pulse to be output is not less than the minimum pulse width that is the lower limit value of the pulse width of the PWM pulse that can cause the output buffer circuit to drive the load effectively. If the target pulse width of the PWM pulse to be output is less than the minimum pulse width, the PWM pulse having the target pulse width is output. A PWM pulse having a pulse width corrected from a pulse width corresponding to a target value is output so that driving similar to the driving of the load to be realized is performed by outputting the PWM pulse having Class D amplifier.   When the target value of the pulse width of the PWM pulse is less than the minimum pulse width twice in succession, the pulse width modulation circuit outputs 2 PWM pulses having a pulse width as the target value instead of outputting two PWM pulses. 2. The class D amplifier according to claim 1, wherein one PWM pulse having a pulse width obtained by adding a target value of the pulse width of each PWM pulse is output.   The pulse width modulation circuit has a pulse width equal to the target value when one of the pulse width target values of two consecutive PWM pulses is less than the minimum pulse width and the other is greater than or equal to the minimum pulse width. The class D according to claim 1, wherein instead of outputting two PWM pulses, one PWM pulse having a pulse width obtained by adding a target value of the pulse width of the two PWM pulses is output. amplifier. The output buffer circuit drives the load with a first polarity in response to the application of the first PWM pulse, and the first polarity corresponds to the application of the second PWM pulse. Driving the load with a second polarity of opposite polarity,
The pulse width modulation circuit sets the pulse width of each target value on condition that the target value of each pulse width of the PWM pulse to be output does not become less than the minimum pulse width at each output timing for outputting the PWM pulse. The first PWM pulse and the second PWM pulse are alternately output, and the target value of the pulse width of one of the first PWM pulse or the second PWM pulse is the minimum at a certain output timing. If the pulse width is less than the pulse width, at the output timing, one of the first PWM pulse or the second PWM pulse whose pulse width target value is less than the minimum pulse width is not output, The target value of the pulse width is not less than the minimum pulse width, and the other PWM pulse of the first PWM pulse or the second PWM pulse is not Class D amplifier according to claim 1, wherein the performing correction to reduce the pulse width.

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