JP2010062260A - Laminated chip component and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer chip component which is advantageous for miniaturization by improving performance while suppressing an increase in the number of elements formed in a chip. An insulating film a made of a ceramic material and a conductor pattern made of a conductive material A chip body is formed by laminating b in an appropriate order. Conductive patterns b are formed on the insulating film layers, respectively, which are a capacitive element C and an inductive element L, and have a two-stage LC filter configuration. On the insulating film layer a <b> 2, band-like patterns b <b> 23, b <b> 24, b <b> 25 are provided in a protruding shape on the capacitive element pattern to form a capacitive element C <b> 61 for characteristic adjustment. On the insulating film layer a6, band-shaped patterns b63 and b64 are provided as inductive element patterns to form a capacitor C62 for adjusting characteristics. Vias 6 and 7 are formed in a zigzag shape in the stacking direction between the LC filter stages to form an inductive element L3 for characteristic adjustment.
[Selection] Figure 1

Description

  The present invention relates to a multilayer chip component and a method of manufacturing the same, and more specifically, a capacitor element and an inductive element for a chip body in which an insulating film of a ceramic material and a conductor pattern of a conductive material are laminated in an appropriate order. The present invention relates to an improvement in the arrangement of conductor patterns.

  As is well known, an electronic component called a chip component is directly soldered by contacting an electrode formed on the surface of a chip body, which is miniaturized into small pieces without providing a lead terminal, for use in surface mounting, and contacting the substrate surface. Will be attached. As a chip component, an insulating film and a conductor pattern are laminated in an appropriate order to form a chip body in which an internal electrode of a conductor pattern is built. By taking an appropriate pattern / arrangement layout of the conductor pattern, the internal electrode constitutes a capacitive element or an inductive element. Therefore, the chip component may be configured as a single functional element such as a capacitor (C: capacitive element) or an inductor (L: inductive element) depending on the form of the internal electrode. In addition, a capacitor element and an inductive element are appropriately incorporated in the chip body to form a low-pass filter or the like.

In the manufacture of this chip component (chip body), for example, a ceramic material is used for the insulating film, and a sheet lamination method in which a conductive pattern is formed on an insulating sheet and stacked, or an insulating paste and a conductive paste are alternately used. There are several methods such as printing and laminating. In any case, a conductor pattern forming a capacitive element and an inductive element and a lead pattern thereof are formed inside the chip body, and the chip body is sintered at a predetermined temperature after completing the lamination.
JP 2002-204136 A

  In recent years, there has been a strong demand for downsizing, high performance, and high frequency with respect to the electronic components that make up electronic devices such as mobile phones, which are thinner, lighter, and more functional. Along with this, we want to reduce the size of multilayer chip parts, but even in that case, if the performance as a functional element deteriorates, it becomes a problem that it can not be used for circuit elements. There is a strong demand for high performance as an element.

  In the case of the low-pass filter, there is a demand for not only a small size but also a good attenuation characteristic for a desired frequency and obtaining as much attenuation as possible. Therefore, in order to obtain a large attenuation, the filter circuit needs to have a multi-stage configuration. However, since the number of elements formed in the multi-stage circuit increases, the chip size inevitably increases. It is a conflicting problem.

  The present invention solves the above-described problems, and its purpose is to reduce the size of the chip by improving the performance while suppressing the increase in the number of elements formed inside the chip body. It is an object of the present invention to provide a multilayer chip component that can improve the attenuation characteristic, obtain a large attenuation, and increase the frequency, and a manufacturing method thereof.

  In order to achieve the above-described object, a multilayer chip component according to the present invention includes: (1) a chip body is formed by laminating an insulating film of a ceramic material and a conductor pattern of a conductor material in an appropriate order; A laminated chip component having at least a film layer forming a capacitive element and a film layer forming an inductive element, wherein the conductor pattern connects the inductive element in series between the input and output, and the output side of the inductive element grounds the capacitive element The LC filter is connected in two stages, and a band pattern is provided on each of the conductor pattern connected to the input side electrode and the conductor pattern connected to the output side electrode, and these band patterns provide a capacitive element for adjusting the resonance pole. It is set as the structure to form.

  In addition, (2) a plurality of belt-like patterns may be provided, and a configuration in which the belt-like pattern is alternately adjacent to the other side may be employed. This strip pattern may be provided in (3) a film layer for forming an inductive element, or (4) provided in a film layer for forming a capacitive element.

  Further, (5) when the LC filter is connected in two stages with respect to the conductor pattern, the vias connecting the upper and lower sides of the film layer between the LC filter stages are formed in a zigzag shape in the stacking direction. The inventions of (1) to (4) can be combined with the invention of (5).

  Further, the method for manufacturing a multilayer chip component according to the present invention includes: (6) a chip body is formed by laminating an insulating film of a ceramic material and a conductor pattern of a conductor material in an appropriate order, and the conductor pattern is formed inside the chip body. The chip body is laminated by a printing lamination method in which an insulating paste and a conductor paste are alternately applied, and the conductor pattern is formed of an inductive element in the printed lamination. The inductive element is connected in series and the output side of the inductive element has a configuration in which the LC filter that connects the capacitive element to the ground is connected in two stages. The conductor pattern that is connected to the input side electrode and the conductor pattern that is connected to the output side electrode Are provided with band-shaped patterns, and these band-shaped patterns form capacitive elements for adjusting the resonance poles.

  Further, in the method for manufacturing a multilayer chip component according to the present invention, (7) when a configuration in which the LC filter is connected in two stages for the conductor pattern in the print lamination, the upper and lower layers of the film layer are connected between the LC filter stages. The vias are formed in a zigzag shape in the stacking direction.

  Therefore, in the present invention, since a band-like pattern is provided in the corresponding film layer, a capacitive element can be formed. Since the capacitive element extends between input and output, the resonance pole can be adjusted for the two-stage LC filter. The band-shaped pattern may be provided in a film layer for forming an inductive element or in a film layer for forming a capacitive element. This does not require the addition of a new film layer, can be built into the film layer for the original configuration, the element configuration inside the chip remains as a two-stage LC filter, and the addition is for adjusting the resonance pole Since it is only a capacitive element, it is advantageous for downsizing.

  By forming the vias connecting the upper and lower sides of the film layers between the stages of the LC filter in a zigzag shape in the stacking direction, since the zigzag shape is formed, the portion exhibits inductivity and can function as an inductive element. This inductive element is located between the stages of the LC filter. Therefore, the frequency characteristics of the resonance pole can be adjusted. Since the zigzag-shaped via extends in the stacking direction, the stack height of the chip body is somewhat increased, but the size of the mounting surface can be kept as it is, and the chip size reduction is not impaired.

  In the multilayer chip component according to the present invention, the capacitor element and the inductive element can be formed in the film layer for the original structure in order to adjust the characteristics of the original structure, and no additional film layer is required. Therefore, the performance can be improved while suppressing an increase in the number of elements formed inside the chip, and the chip can be reduced.

  Therefore, in the case of adopting a low-pass filter configuration, it is possible to improve the attenuation characteristic for a desired frequency by the adjustment capacitive element and the inductive element, and to obtain a large attenuation and to increase the frequency.

  1 to 5 show a preferred embodiment of the present invention. In the multilayer chip component of this embodiment, the chip body 1 is formed by laminating an insulating film a made of a ceramic material and a conductor pattern b made of a conductive material in an appropriate order. The chip body 1 has at least a film layer that forms a capacitive element and a film layer that forms an inductive element, and a low-pass filter is configured by connecting these elements to each other. The chip body 1 is formed in a substantially rectangular small piece as shown in FIG. 2, and the input electrode 2 and the output electrode 3 are provided on the two opposing surfaces of the chip body 1, respectively, and the ground electrodes 4 and 5 are provided on the side surfaces. Provided.

  The low-pass filter inside the chip body 1 is as shown in FIG. This is basically equivalent to a distributed constant type configuration in which the LC integration circuit shown in FIG. 4 is connected in two stages. However, a capacitive element C6 is arranged between the input and output, and the induction element L1 and the induction element L2 are connected to each other. The inductive element L3 is arranged between the capacitive elements C4, C1, and C2 between the stages. That is, the configuration of the low-pass filter is basically as shown in FIG. 4, in which the inductive element L1 is connected in series between the input and output, and the output side of the inductive element L1 is grounded via the capacitive element C4. And Similarly, in the second stage, the induction element L2 is connected in series, and the output side is grounded via the capacitive element C5. Capacitance elements C1 and C2 are connected in parallel to the induction element L1 and the induction element L2, respectively, the capacitance element C3 is connected to the input electrode 2 side, and the other end is grounded. In the present invention, as shown in FIG. 3, a capacitive element C6 is connected between the input and output. Further, the induction element L3 is connected between the capacitive elements C4, C1, and C2 between the stages of the induction element L1 and the induction element L2. As will be described later, the capacitive element C6 includes two capacitive elements C61 and C62, and is a combination of parallel capacitors.

  The chip body 1 is formed using a printing lamination method. That is, the insulating paste made of the ceramic material and the conductor paste made of the conductive material are alternately screen-printed. Since these pastes are printed (applied) once and have a thickness of, for example, 3 to 5 μm, they are applied, dried and stacked. In the manufacture of chip parts, a workpiece laminate having a plurality of sizes is manufactured as a workpiece from the viewpoint of productivity, and the workpiece laminate is sufficiently dried and then cut into individual pieces and fired.

  As the ceramic material, for example, dielectric ceramics added with glass and sintered at a low temperature is used. For example, a dielectric material in which a borosilicate glass is mixed with alumina in a volume ratio of 70:30 is used, and a mixture of ethyl cellulose, terpineol, a dispersant, and a plasticizer is mixed and kneaded as a vehicle. Insulating paste for printing. In addition, for example, magnetic ceramics such as ferrite may be used as the ceramic material. A silver paste is used as the conductor paste and is mixed with the vehicle described above. The conductor paste may be silver palladium.

  Specifically, the insulating film a is a seven layer from a1 to a7 shown in FIG. 1 and a plurality of layers in the via portion, and no conductive pattern is formed on the uppermost layer a7, but the first insulating film layer Conductive patterns b are formed for the first to sixth insulating film layers a6.

  On the insulating film layer a1, a conductor pattern b11 serving as a ground side electrode of the capacitive elements C3 and C5 is formed in a substantially square shape, and the conductor pattern b11 has projecting portions (stubs) on both sides, and the ground electrodes 4 and 5 respectively. Reached the side edge.

  On the insulating film layer a <b> 2, a conductor pattern b <b> 21 serving as the electrodes of the capacitive elements C <b> 3 and C <b> 1 is formed in a substantially square shape on the input electrode 2 side, and an overhanging portion reaching the edge on the input electrode 2 side is provided. Further, on the output electrode 3 side, a conductor pattern b22 serving as the electrodes of the capacitive elements C5 and C2 is formed in a substantially square shape, and an overhanging portion reaching the edge on the output electrode 5 side is provided. The conductor pattern b21 is provided with belt-like patterns b23 and b24 on the center side of the film layer so as to project toward the conductor pattern b22 side, and the conductor pattern b22 is provided with a belt-like pattern b25 on the center side of the film layer. The strip pattern b23, b24, b25 is arranged so as to be alternately adjacent to the counterpart side. As a result, the strip-like patterns b23, b24, and b25 form a capacitive element C61, and the capacitive element C61 extends between the input and output, and thus becomes a capacitive element for adjusting the resonance pole.

  On the insulating film layer a3, a conductor pattern b31 serving as the electrodes of the capacitive elements C1, C2, and C4 is formed in a substantially rectangular shape, and a via 6 is provided in the center to be connected. The via 6 is formed in a zigzag shape, which is formed by laminating a conductor pattern b on the insulating film a in a step shape as shown in FIG. Thereby, since the via 6 has a zigzag shape, the via 6 shows inductivity and becomes a lower portion of the inductive element L3.

  On the insulating film layer a4, a conductor pattern b41 serving as a ground side electrode of the capacitive element C4 is formed in a substantially square shape, and the conductor pattern b41 has projecting portions on both sides, and the edges on the ground electrodes 4 and 5 side, respectively. Has reached the department. A via 7 is provided in the central portion insulated from the conductor pattern b41 and connected to the lower layer side. The via 7 is also formed in a zigzag shape and extended like the lower layer side, and is inductive due to the zigzag shape, and becomes an upper part of the inductive element L3.

  On the insulating film layer a5, a lead conductor pattern b51 is formed which becomes a coil portion of the induction elements L1 and L2. The lead conductor pattern b51 has a central portion connected to the via 7 from the lower layer side, extends to the input side and the output side, and the tip on the input electrode 2 side is connected to the conductor pattern b61 of the upper layer a6 by the via to output electrode The tip on the 3 side is connected to the conductor pattern b62 of the upper layer a6 by a via. On the insulating film layer a6, lead-out conductor patterns b61 and b62 are formed as coil portions following the induction elements L1 and L2. The leading end of the routing conductor pattern b61 is connected to the via on the input electrode 2 side, and the other end that is substantially turned reaches the edge on the input electrode 2 side. The leading end of the routing conductor pattern b62 is connected to the via on the output electrode 3 side, and the other end that is substantially turned reaches the edge on the output electrode 3 side.

  The routing conductor pattern b61 is provided with a strip pattern b63 on the center side of the film layer so as to follow the routing conductor pattern b61, and the routing conductor pattern b62 is also provided with a strip pattern b64 on the center side of the membrane layer. The strip patterns b63 and b64 are arranged along each other. As a result, the strip-like patterns b63 and b64 form a capacitive element C62, and the capacitive element C62 extends between the input and output, so that it becomes a capacitive element for adjusting the resonance pole. The capacitive element C62 and the capacitive element C61 may be handled as a capacitive element C6, which is a combination of parallel capacitors (C62 + C61 = C6) across the input and output.

  The capacitive element C62 is provided on the insulating film layer a6, that is, the film layer a6 for forming the inductive element, and the capacitive element C61 is provided on the insulating film layer a2, that is, the film layer a2 for forming the capacitive element. Yes. Only one of these two may be configured, and the configuration can be selectively changed in accordance with a desired capacitance value and characteristics.

  When the numerical analysis was performed on the configuration of the low-pass filter according to the present invention, that is, the equivalent circuit shown in FIG. 3, attenuation characteristics as shown in FIGS. 6 and 7 were obtained. FIGS. 6 and 7 also plot the attenuation characteristics (indicated by dotted lines) in the equivalent circuit of the basic configuration shown in FIG.

  As is clear from FIG. 6, the capacitance element C6 has an attenuation of only about 46 dB with the basic configuration of the low-pass filter. However, with the configuration of the low-pass filter according to the present invention, about 50 dB can be obtained. It was confirmed that the resonance pole can be satisfactorily adjusted by the element C6. As is clear from FIG. 7, the inductive element L3 has a damping frequency of only about 4.4 GHz in the basic configuration of the low-pass filter, but can be shifted to a higher frequency side in the configuration of the low-pass filter according to the present invention. It was confirmed that about 4.7 GHz can be obtained, and that the frequency of the resonance pole can be satisfactorily adjusted by the inductive element L3.

  As described above, since the band-like patterns b23, b24, b25, b63, and b64 are provided in the corresponding film layers, the capacitive elements C61 and C62 can be formed. The pole can be adjusted.

  The band-like patterns b23, b24, b25, b63, and b64 may be provided on a film layer for forming an inductive element or provided on a film layer for forming a capacitive element. In this way, it is not necessary to add a new film layer, and it can be built in the film layer for the original configuration, the element configuration inside the chip is the same as the two-stage LC filter, and the addition is the resonance pole adjustment For this reason, only the capacitance element C6 is advantageous for downsizing.

  By forming the vias 6 and 7 connecting the upper and lower layers of the LC filter between the LC filter stages in a zigzag shape in the stacking direction, the portion is inductive and functions as the inductive element L3 because of the zigzag shape. Can do. This inductive element L3 is located between the stages of the LC filter. Therefore, the frequency characteristics of the resonance pole can be adjusted.

  Since the zigzag-shaped vias 6 and 7 extend in the stacking direction, the stack height of the chip body 1 is somewhat increased. However, the occupied size of the mounting surface can be maintained as it is, and the reduction of the chip size is impaired. Absent.

  In the present invention, the capacitance element C6 and the inductive element L3 can be added to adjust the characteristics of the original configuration, which can be built into the film layer for the original configuration. Does not require addition. For this reason, an increase in the number of elements formed in the chip can be suppressed and the performance can be improved, so that a small chip can be achieved.

  Therefore, in the configuration of the low-pass filter, the adjustment capacitive element C6 and the inductive element L3 can improve the attenuation characteristic for the desired frequency, and can obtain a large attenuation and increase the frequency. For example, in applications such as mobile phones, it is important to block harmonics. Therefore, according to the present invention, since only the element for adjusting the resonance pole is added to the chip body 1, the chip size can be reduced, and the second harmonic and the third harmonic can be significantly attenuated. Further, the values of the adjusting capacitive element and the inductive element can be appropriately set by changing the pattern or the like, and the attenuation characteristic and the frequency characteristic can be easily obtained as desired.

FIG. 2 is a perspective view showing an embodiment of the multilayer chip component according to the present invention, with each layer separated. It is a perspective view explaining the external appearance of the multilayer chip component shown in FIG. FIG. 2 is an equivalent circuit diagram illustrating an electrical configuration of the multilayer chip component shown in FIG. 1. It is an equivalent circuit diagram explaining the basic composition of a low pass filter. It is sectional drawing explaining a via | veer. It is a graph which shows the attenuation | damping characteristic of the multilayer chip component which makes | forms a low-pass filter, and demonstrates the characteristic which concerns on the capacitive element C6. It is a graph which shows the attenuation | damping characteristic of the multilayer chip component which makes | forms a low-pass filter, and demonstrates the characteristic which concerns on the induction element L3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Chip body 2 Input electrode 3 Output electrode 4, 5 Ground electrode 6, 7 Via a Insulating film a1 1st insulating film layer a2 2nd insulating film layer a3 3rd insulating film layer a4 4th insulating film layer a5 5th insulating film layer a6 6th insulating film layer a7 7th insulating film layer b Conductor pattern b21, b22, b31, b41 Conductor pattern b23, b24, b25, b63, b64 Strip pattern b51, b61, b62 Leading conductor Patterns C1, C2, C3, C4, C5, C61, C62, C6 Capacitance elements L1, L2, L3 Inductive elements

Claims (7)

A chip body is formed by laminating an insulating film of a ceramic material and a conductor pattern of a conductor material in an appropriate order, and the chip body is a multilayer chip component having at least a film layer forming a capacitive element and a film layer forming an inductive element. And
The conductor pattern has a configuration in which the inductive element is connected in series between the input and output, and the output side of the inductive element has a configuration in which the LC filter that connects the capacitive element to the ground is connected in two stages, and is connected to the input side electrode A multilayer chip component comprising a conductor pattern and a conductor pattern connected to an output side electrode, each of which is provided with a belt-like pattern, and the belt-like pattern forms a capacitive element for adjusting a resonance pole.   2. The multilayer chip component according to claim 1, wherein a plurality of the belt-like patterns are provided and are arranged alternately adjacent to the other side.   3. The multilayer chip component according to claim 1, wherein the strip pattern is provided in a film layer for forming the inductive element.   The multilayer chip component according to claim 1, wherein the strip pattern is provided in a film layer for forming the capacitor element. A chip body is formed by laminating an insulating film of a ceramic material and a conductor pattern of a conductor material in an appropriate order, and the chip body is a multilayer chip component having at least a film layer forming a capacitive element and a film layer forming an inductive element. And
The conductor pattern has a configuration in which the inductive element is connected in series between the input and output, and the output side of the inductive element is configured to connect the LC filter that connects the capacitive element to the ground in two stages. A laminated chip component, wherein vias connecting between the upper and lower sides of the film layer are formed in a zigzag shape in the laminating direction. A chip body is formed by laminating an insulating film of a ceramic material and a conductor pattern of a conductor material in an appropriate order, and a manufacturing method of a multilayer chip component in which an electrode body with the conductor pattern is built in the chip body,
The chip body is laminated by a printing lamination method in which an insulating paste and a conductor paste are alternately applied. In the printing lamination, the conductor pattern connects the inductive elements in series between the input and output and the inductive elements. The output side has a structure in which the LC filter that connects the capacitive element to the ground is connected in two stages, and a strip pattern is provided on each of the conductor pattern connected to the input side electrode and the conductor pattern connected to the output side electrode, and these band patterns resonate. A method of manufacturing a laminated chip component, comprising forming a capacitor element for pole adjustment. A chip body is formed by laminating an insulating film of a ceramic material and a conductor pattern of a conductor material in an appropriate order, and a manufacturing method of a multilayer chip component in which an electrode body with the conductor pattern is built in the chip body,
The chip body is laminated by a printing lamination method in which an insulating paste and a conductor paste are alternately applied. In the printing lamination, the conductor pattern connects the inductive elements in series between the input and output and the inductive elements. The output side has a configuration in which the LC filter that connects the capacitive element between the grounds is connected in two stages, and vias that connect the upper and lower sides of the film layer between the stages of the LC filter are formed in a zigzag shape in the stacking direction. A method of manufacturing a multilayer chip component characterized by the above.

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