JP2010039521A - Calculation method for interconnect capacitance, and design support device for wiring pattern - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a calculation method of interconnect capacitance by which the interconnect capacitance of a wiring pattern including oblique wiring, whose layout has been prepared, is correctly obtained at high speed, and to provide a design support device of the wiring pattern. <P>SOLUTION: The calculation method of the interconnect capacitance includes: a first step of dividing a circuit region including the wiring region of a wiring pattern designed to include oblique wiring into a plurality of unit regions by prescribed grids; a second step of considering each unit region is either a wiring existence region or a wiring non-existence region according to the coverage of the wiring pattern in each unit region, and converting the oblique wiring section into a pseudo-wiring pattern including only basic cells having the shape of the unit region; a third step of carrying out pattern matching with a capacity table configured by associating the basic wiring pattern with the capacity about the obtained pseudo wiring pattern; and a fourth step of calculating an interconnect capacitance about the pseudo-wiring pattern based on the result of pattern matching. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an inter-wiring capacitance calculation method and a wiring pattern design support apparatus.

  In general, in the design process of an electronic circuit, first, after designing a circuit for designing a logic circuit, a layout for drawing a wiring pattern based on the logic circuit is performed. The wiring pattern has a shape corresponding to a photomask pattern used when wiring is formed on a substrate such as a semiconductor, and a photoresist pattern to which the photomask pattern is transferred. After that, the parasitic capacitance, wiring resistance, and wiring inductance of each laid out wiring are extracted from the layout data, and the extracted capacitance value, resistance value, and inductance value are added to the logic circuit, respectively. Logic verification is performed to confirm the signal. At this time, the circuit drive state (propagation signal) closer to the actual product is obtained by correctly estimating the capacitance value, resistance value, and inductance value of each laid out wiring, and adding these values to each wiring to perform logic verification. Can be estimated.

  As a method for extracting the inter-wiring capacitance, for example, there is a method disclosed in Patent Document 1. In Patent Document 1, a rule table that stores values such as the capacitance of wiring corresponding to parameters such as the distance between wirings of adjacent wirings and the facing area is created in advance. In addition, it is described that the value read from the rule table is read from the rule table by matching the parameter read from the layout data of the wiring pattern with the parameter of the rule table. Such a method is called a lookup table method.

  However, when the lookup table method is used to estimate the capacity of wiring (diagonal wiring) arranged in an oblique direction other than the 0 ° direction, 45 ° direction, and 90 ° direction with respect to the reference direction, In general, the estimation accuracy of the obtained inter-wiring capacitance is extremely lowered. In general, rule tables are created only for wirings arranged in the 0 ° direction, 45 ° direction, and 90 ° direction, and the inter-wiring capacities other than those described above are referred to with reference to these rule tables. This is because the estimation is performed approximately. The reason for not creating a rule table for diagonal wiring is that, for example, when two wirings are arranged so as to cross each other, creating a rule table for all the corners formed by these two wirings means that the required memory This is because it is very difficult considering the amount and effort.

  Further, Patent Document 2 describes a method of extracting inter-wiring capacitance even when diagonal wiring is arranged. Specifically, when wiring (main wiring) arranged in the reference direction (main direction) and wiring arranged obliquely with respect to the main wiring (diagonal wiring) are arranged adjacent to each other, diagonal wiring Is divided into a plurality of wiring portions, each of these wiring portions is separated from the main wiring by a predetermined distance, and is replaced so as to be parallel to the main wiring, and then the capacitance value is estimated based on each distance and the like. Thus, it is described that the capacity of the entire wiring is approximately estimated.

  Such inter-wiring capacitance has a structure in which the GND substrate is not disposed directly under the wiring and there is almost no ground capacitance, for example, a TFT (thin film transistor) structure in which the lower substrate is a glass substrate. Has become dominant. Here, Non-Patent Documents 1 and 2 describe that the capacitance between wirings is dominant in the case of a TFT or the like.

  It is necessary to estimate the inter-wiring capacitance even in an LSI (Large Scale Integrated Circuit) in which the ground capacitance between the wiring and the GND substrate arranged immediately below the wiring is dominant. Then, it is important to estimate the capacitance between wires.

In addition, since the wiring patterns are connected to each other at a short distance by arranging the diagonal wiring in the wiring pattern layout, the resistance of the wiring is reduced and the space of the layout is saved. In addition, the resistance of the wiring is reduced by increasing the wiring width.
JP 2005-228008 A JP 2005-242681 A Yoshihiro Uchida: Reduction of inter-wiring capacity of system-on-panel by ground plane and shield wiring and facilitating capacity estimation, IPSJ Transactions, 2006, 47, 6, 1665-1673 Yoshihiro Uchida: Wiring capacity extraction method for system liquid crystal, Journal of Information Processing Society of Japan, 2005, 46, 6, pp. 1395-1403

  However, in the method of Patent Document 1, the inter-wiring capacitance is obtained by approximating the diagonal wiring to any one of the wirings arranged in the 0 ° direction, the 45 ° direction, and the 90 ° direction. There is a problem that the estimation error of the capacity becomes large.

  Further, in the method of Patent Document 2, the interval between the diagonal wiring and the main wiring that are actually arranged, and each partial wiring when the diagonal wiring is divided and replaced with a plurality of partial wirings parallel to the main wiring, The distance from the main wiring is deviated. For this reason, there is a problem that the accuracy of estimating the capacitance of the wiring is lowered.

  FIG. 18 shows a capacitance value between a plurality of wirings. Here, FIG. 18A shows a capacity existing between a plurality of wirings, and FIG. 18B shows a capacity value between the wirings. As shown in FIG. 18A, the wiring W1, the wiring W2, the wiring W3, and the wiring W4 are arranged with an interval S1, an interval S2, and an interval S3, respectively. In this case, when paying attention to the wiring W1, the inter-adjacent wiring capacitance C1 exists between the wiring W2, the inter-wiring capacitance C2 exists between the wiring W3, and the inter-wiring capacitance C3 exists between the wiring W4. Exists. In such wirings W1 to W4, electromagnetic field simulation is performed and the inter-wiring capacitances C1 to C3 are estimated, as shown in FIG. 18B, and the inter-wiring capacitance C2 is approximately equal to the adjacent inter-wiring capacitance C1. 20%. For this reason, in the TFT structure, it is necessary to obtain the inter-wiring capacitance with higher accuracy than in the LSI structure. That is, in the TFT structure, since there is almost no ground capacitance, it is necessary to obtain the inter-wiring capacitance by adding the inter-wiring capacitances C2 and C3 in addition to the inter-wiring capacitance C1.

  The present invention has been made in view of such a problem, and an object of the present invention is to calculate an inter-wiring capacitance that makes it possible to easily and accurately obtain an inter-wiring capacitance of a wiring pattern including an oblique wiring for which a layout has been created. The object is to provide a method and a wiring pattern design support apparatus.

  The inter-wiring capacitance calculation method according to the present invention includes a first step of dividing a circuit area including a wiring pattern arrangement area designed to include diagonal wiring in an electric circuit into a plurality of unit areas by a predetermined lattice. In addition, depending on the occupancy rate of the wiring pattern in each unit area, each unit area is regarded as either a wiring existing area or a wiring non-existing area, so that the diagonal wiring portion is composed only of basic cells having the shape of the unit area. A second step of converting into a pseudo wiring pattern; a third step of performing pattern matching with a capacitance table configured by associating a basic wiring pattern and a capacity with respect to the obtained pseudo wiring pattern; and pattern matching And a fourth step of calculating the interwiring capacitance for the pseudo wiring pattern based on the result of the above.

  A wiring pattern design support apparatus according to the present invention includes a layout processing unit that performs a process related to a layout work of a wiring pattern including an oblique wiring part in an electric circuit, a capacity calculation unit that calculates a capacitance between wirings related to the created wiring pattern, An operation check processing unit for checking the operation of the electric circuit by applying the obtained inter-wiring capacitance, and the capacitance calculating unit divides the circuit region including the wiring pattern arrangement region into a plurality of units by a predetermined lattice. By considering each unit area as either a wiring existing area or a wiring non-existing area according to the first process of dividing into areas and the wiring pattern occupancy in each unit area, the oblique wiring portion A second process of converting into a pseudo wiring pattern consisting only of basic cells having a shape, and the basic wiring pattern and capacity of the obtained pseudo wiring pattern; A third process for performing pattern matching with a capacitance table configured by associating with each other, and a fourth process for calculating inter-wiring capacitance for a pseudo wiring pattern based on the result of pattern matching It is.

  In such an inter-wiring capacity calculation method or wiring pattern design support apparatus, the entire wiring pattern including the oblique wiring portion is converted into a pseudo wiring pattern including only basic cells having the shape of the unit region. Thereby, the part which was originally the diagonal wiring part is replaced with a basic cell aggregate in which the edges of the opposing wiring parts are parallel to each other. Such pseudo wiring patterns are subjected to pattern matching with a capacity table, and based on the result of the pattern matching, wiring capacity is obtained.

  In the wiring pattern design support apparatus according to the present invention, the inter-wiring capacity of the wiring pattern created in the layout processing section is calculated by the capacity calculating section, and the operation confirmation processing section uses the obtained inter-wiring capacity. The circuit operation is confirmed.

  According to the inter-wiring capacity calculation method and the wiring pattern design support apparatus of the present invention, by converting the entire wiring pattern into a pseudo wiring pattern, the portion that was the diagonal wiring portion is changed to the edge of the opposing wiring portion. After replacing with basic cell aggregates that are parallel to each other, pattern matching with the capacitance table was performed, and the inter-wiring capacitance was obtained based on the result of this pattern matching. The inter-wiring capacitance can be obtained easily and accurately.

  Further, according to the wiring pattern design support apparatus of the present invention, since the logic operation of the circuit operation is verified using the accurately obtained inter-wiring capacitance, the influence of the parasitic capacitance of the wiring can be taken into account more accurately. Therefore, it is possible to perform a circuit operation simulation with higher accuracy.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows the whole wiring pattern design process to which the inter-wiring capacitance calculation method according to an embodiment of the present invention is applied. As shown in FIG. 1, the wiring pattern design process includes circuit diagram creation (S1), logic verification (S2), layout creation (S3), capacitance value extraction (S4), and logic considering capacitance values. Each step of verification (S5) is included in order.

  First, in a circuit diagram creation step (S1), a netlist, which is connection information data between terminals in an electric circuit, is created using a netlist creation tool. As a specific example, a net list is created based on an equivalent circuit diagram drawn using an EDA (Electronic Design Automation) tool. The netlist describes the sizes of transistors, capacitors, resistors, etc., and which terminals (nodes) each component is connected to.

  Next, in the logic verification step (S2), logic verification is performed using a circuit simulator. Specifically, circuit simulation is performed using the created netlist, and if the waveform propagating through the circuit is desired, the logic verification is terminated.

  Next, in the layout creation step (S3), a wiring pattern actually used (for example, the wiring pattern 20 in FIG. 4) is created based on the net list. Here, it is assumed that the wiring pattern is designed so that the diagonal wiring and the main wiring are included. Here, the main wiring means wiring extending in the reference direction (main direction), and the diagonal wiring means wiring other than the main wiring, that is, wiring extending in a direction other than the main direction. Such a wiring pattern has a shape corresponding to the pattern of the photomask used when manufacturing the wiring and the pattern of the etching mask formed by transferring the photomask pattern to the photoresist applied on the substrate. It is what has.

  Next, the inter-wiring capacity for the created wiring pattern is estimated (calculated) (S4). The specific contents will be described later.

Next, a final logic verification process is performed in consideration of the obtained inter-wiring capacitance value (S5).
Specifically, it is confirmed whether or not the circuit operation when the wiring capacitance obtained in S4 is taken into account is desired (S410).

  Next, the capacitance value extracting step (S4) in FIG. 1 will be described in detail with reference to FIG. FIG. 2 shows details of each step in the inter-wiring capacitance extraction process.

  In the capacity value extracting step (S4), first, a capacity table as a matching table is created (S401). For example, as shown in FIG. 3B, the capacity table is for extracting the inter-wiring capacity based on a predetermined parameter obtained from the wiring pattern, and includes the basic wiring pattern and the capacity per unit length. Are associated with each other. As this capacity table, a table generated in advance can be used.

  As a specific example of the basic wiring pattern, as shown in FIG. 3A, a wiring 11 having a wiring width W1 and a wiring 12 having a wiring width W2 are arranged with an interval S therebetween. As shown in FIG. 3B, the capacitance table based on the basic wiring pattern 10 is for each set in which the values of the wiring width W1 [μm], the wiring width W2 [μm], and the interval S [μm] are combined. And a capacitance value [fF / m] per unit length.

  Next, as shown in FIG. 4, the circuit area including the arrangement area of the wiring pattern 20 produced in S3 is divided into a plurality of unit areas 21 by a grid 22 (S402). At this time, it is determined whether or not to rotate the coordinate axis of the grid 22 with respect to the layout of the wiring pattern (S403). When the grid 22 is rotated, it is further determined how much the grid 22 is rotated. The coordinate axis of the grid 22 can be rotated at an arbitrary angle with respect to the layout of the wiring pattern 20. In the case shown in FIG. 4, it is not rotated.

  Next, the shape or size of the unit region 21 is adjusted according to the shape or size of the wiring pattern 20 (S404). In the case shown in FIG. 4, the unit areas 21 are all squares of the same size. For example, the size of the unit area 21 (one side of the square) depends on the inclination angle of the oblique wiring, the wiring width, the wiring interval, or the like. May be arbitrarily changed.

  Next, a threshold value is set for each unit area 21 (S405). The threshold value is a determination criterion for determining whether the wiring pattern 20 occupies or does not occupy the unit region 21, and an arbitrary value can be set. For example, when the occupation ratio of the wiring pattern 20 in the unit area 21 is 50% or more, the unit area 21 is regarded as occupied by the wiring pattern 20 (wiring existence area), and when it is less than 50%, the unit area 21 is set so that the wiring pattern 20 does not occupy (a wiring non-existing region).

  Note that S402 to S405 described above correspond to a specific example of the first step of the method for calculating the inter-wiring capacitance in the present invention.

  Next, the wiring pattern 20 is converted into the pseudo wiring pattern 24 (S406). Specifically, first, in order to represent the layout of the wiring pattern 20 by the basic cells 23 having the same shape as the unit region 21, the presence or absence of the wiring pattern 20 is determined for each unit region 21 based on a threshold value. For example, as shown in FIG. 5, a “wiring existence area” or “wiring non-existence area” for the unit area 21 (the hatched portion) where the longitudinal side edge 20 a of the wiring pattern 20 is arranged is based on the threshold value. Judgment is considered to be any of the above. For example, when the threshold value is set to 50%, if the wiring pattern 20 occupies more than half the area of the unit area 21, it is determined that the unit area 21 is a wiring existence area. The unit area 21 is determined to be a wiring absence area.

  In this way, as shown in FIG. 6, the circuit area including the arrangement area of the wiring pattern 20 can be represented by an assembly of basic cells 23. Such an assembly of basic cells 23 constitutes a pseudo wiring pattern 24 (pseudo layer) for capacity calculation. The outline of the pseudo wiring pattern 24 (wiring existence area 26) is composed of only the outline extending in the reference direction (coordinate axis direction). For this reason, when viewed for each basic cell 23, all the pseudo wirings that face away from each other are parallel to each other. This S406 corresponds to a specific example of the second step of the method for calculating the interwiring capacitance in the present invention.

  Next, pattern matching is performed using the capacity table (FIG. 3B) (S407). First, as parameters of the wiring pattern 20, the wiring width and the wiring interval are obtained from the pseudo wiring pattern 24. Specifically, as shown in a part of the pseudo layer in FIG. 7, the pseudo wiring pattern 24 is divided into sections (arrows A, B, C, D, E) having the same wiring interval and the basic cell group 25 is divided. The wiring widths W1 and W2 and the wiring interval S are obtained for each basic cell group 25.

  Next, a combination of the obtained combination of the wiring width and the wiring interval and the combination of the wiring width and the wiring interval as the reference parameters of the capacitance table (FIG. 3B) is selected, and the selected wiring width and wiring are selected. The capacity value per unit length corresponding to the interval is read from the capacity table. As a specific example, when the obtained wiring width W1 is 2 [μm], the wiring width W2 is 1 [μm], and the interval S is 1 [μm], the capacitance table as shown in FIG. A reference parameter set that matches a set of numerical values (parameters) is selected, and a capacity of 12 [fF / m] per unit length corresponding to the reference parameter is extracted. Here, “matching” is a concept that includes not only the case where the numerical values of the parameters of the wiring pattern 20 and the reference parameter of the capacitance table completely match, but also the case where the numerical values substantially match. This S407 corresponds to a specific example of the third step of the method for calculating the capacitance between wires in the present invention.

  Next, the capacity value per unit length is multiplied by the length of one side of the basic cell 23 (unit region 21) to obtain the capacity value for each basic cell group 25, and then the capacity of each basic cell group 25 is determined. The inter-wiring capacitance value is obtained by adding the values (S408). This S408 corresponds to a specific example of the fourth step of the inter-wiring capacitance calculation method according to the present invention.

  Thereafter, the obtained inter-wiring capacitance is added as a parasitic capacitance of each wiring pattern 20 to the circuit diagram created in S1 (layed wiring pattern 20) (S409). This is the end of the inter-wiring capacitance extraction step (S4).

  Next, the effect | action of the calculation method of the capacity | capacitance between wiring in this Embodiment is demonstrated. Here, first, as a comparative example, a conventional method for calculating the inter-wiring capacitance using the look-up table method will be described.

  FIG. 17 shows a wiring pattern in which wirings with non-constant widths are arranged in the center. In the layout example shown in FIG. 17, three wirings 50, 50, 51 are arranged. Of these, the wirings (interlaced wirings) 50, 50 arranged on the left and right of the drawing are diagonal wirings, and the center The wiring (center wiring) 51 arranged in the main line is a main wiring. The wiring 51 has a different width in the longitudinal direction.

  In such a wiring pattern, the side edges in the longitudinal direction of the central wiring 51 are not parallel to each other. For this reason, when the capacitance (inter-interconnection capacitance) A between the two wirings 50 is to be obtained by the conventional method (Patent Document 2), even if the wirings 50 are rotated to be parallel to each other, The distance between the wiring 50 and the central wiring 51 is different along the longitudinal direction (the edges are not parallel between the opposing wirings), and the inter-wire capacitance A cannot be obtained accurately.

  On the other hand, in the method for calculating the inter-wiring capacitance according to the present embodiment, all the wirings 50, 50, 51 are replaced with the pseudo wiring pattern 24 including only the basic cells 23, and then the pseudo wiring pattern 24 is used as the basic wiring pattern. Dividing each cell group 25 to obtain the wiring width and wiring interval, pattern matching with the capacity table is performed for each basic cell group 25, and based on the result of this pattern matching, the capacity between the interlaced wirings for the pseudo wiring pattern A is calculated. Therefore, in the present embodiment, the capacitance A between the jump wirings can be accurately obtained.

  An apparatus for supporting design of such a wiring pattern is as follows. FIG. 8 illustrates a schematic configuration block of the wiring pattern design support apparatus 1. The wiring pattern design support apparatus 1 includes a layout processing unit 2, a capacity calculation unit 3, and an operation confirmation processing unit 4. The layout processing unit 2 performs processing such as layout creation of the wiring pattern 20, and specifically performs the processing of S1 to S3 shown in FIG. The capacity calculation unit 3 performs a process of calculating the inter-wiring capacity, and specifically performs a part of the process of S4 shown in FIG. The operation confirmation processing unit 4 adds the interwiring capacitance obtained in the capacitance calculation unit 3 to the circuit for logic verification, and confirms the operation of the circuit. A part of the processing of S4 shown in FIG. The process of S5 is performed.

  In the calculation method of inter-wiring capacitance and the design support apparatus 1 in the present embodiment, the wiring pattern 20 including the diagonal wiring is replaced with the pseudo wiring pattern 24 extending in the 0 ° direction or the 90 ° direction. The edges of the pattern 24 are parallel to each other. Further, the parameter set obtained from the pseudo wiring pattern 24 and the reference parameter set in the capacity table are selected to match, the capacity value per unit length corresponding to the selected reference parameter is read, and the basic cell 23 The inter-wiring capacitance is obtained by multiplying the length of. Therefore, even if the wiring pattern includes an oblique wiring, the inter-wiring capacitance can be accurately obtained by replacing it with the pseudo wiring pattern 24. In addition, since the capacity table to be prepared can be the same as that used conventionally, no special effort or cost is required.

  If the circuit operation is logically verified in consideration of the inter-wiring capacitance thus accurately obtained, the parasitic capacitance of the wiring pattern 20 and the influence of the operation delay caused thereby can be grasped more accurately. Simulation can be performed more accurately.

  Further, by replacing the pseudo wiring pattern 24 with each other, not only the adjacent pseudo wirings but also the jumping pseudo wirings become parallel to each other, so that not only the capacity between the adjacent wirings but also the capacity between the jumping wirings can be accurately obtained.

  While the present invention has been described with reference to the embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made.

  For example, the shape of the unit region 21 is not limited to a square and can be a rectangle. Furthermore, the shape of the unit region 21 is not limited to a rectangle, but may be a polygon such as a triangle or a hexagon. The unit area 21 may be a combination of a plurality of sizes or shapes in one circuit area including the arrangement area of the wiring pattern 20. In this case, the size or shape of the basic cell 23 varies depending on the size or shape of the unit region 21.

  In particular, as shown in FIG. 9, when the inclination and width of the diagonal wiring are changed halfway, according to the width of the wiring pattern 20 or the inclination of the wiring pattern 20 as shown in FIG. The size of the unit area 21 can be changed. That is, the unit area 21 may be set small in the area a where the wiring width is thin or the wiring inclination is large, and the unit area 21 may be set large in the area b where the wiring width is large or the wiring inclination is small. When the size of the unit area 21 is set in this way, the pseudo wiring pattern 24 becomes as shown in FIG.

  Also, as shown in FIG. 10, when the inclination of the diagonal wiring is changed halfway, depending on the width of the wiring pattern 20 or the inclination of the wiring pattern 20 as shown in FIG. Not only the size of the unit region 21 but also the shape can be changed. That is, in the area c where the wiring width is thin or the wiring inclination is large, the unit area 21 is set to be small, and in the area d where the wiring width is large or the wiring inclination is small, the unit area 21 is set to be large. To do. When the unit area 21 of the area d is set to be large, the shape of the unit area 21 in the area c may be different. In the case shown in FIG. 10A, the shape of each unit region 21 in the region c and the region d is different. The unit area 21 in the area d has a rectangular shape with long sides in the extending direction of the diagonal wiring. When the shape and size of the unit region 21 are set in this way, the pseudo wiring pattern 24 becomes as shown in FIG.

  As described above, when the size and shape of the unit region 21 (basic cell 23) are set according to the wiring pattern 20, the inter-wiring capacitance can be obtained more accurately and at high speed. For example, if the unit area 21 is set small in an area where the wiring width is narrow or the wiring inclination is large, the wiring pattern is accurately replaced by the pseudo wiring pattern 24. Therefore, by performing calculation after pattern matching of the capacitance table is performed. This is because an accurate wiring capacitance can be obtained. In addition, if the unit area 21 is set large in an area where the wiring width is large or the inclination of the wiring is small, threshold processing performed for each unit area 21 can be reduced compared to the case where the unit area 21 is set small. Capacitance between wires can be obtained at higher speed, and the burden on the microprocessor can be reduced.

  In the present embodiment, whether or not to rotate the grid 22 is determined in S403. For example, in the case of a wiring pattern as shown in FIG. 11A, the coordinate axis of the grid 22 along the main direction (vertical direction and horizontal direction in the drawing) is set as an oblique wiring as shown in FIG. It is preferable to rotate in accordance with 30.

  When a plurality of diagonal wirings 30 are extended, the grid 22 may be rotated so that the coordinate axis of the grid 22 coincides with any one of the plurality of diagonal wirings 30. . As a specific example, when two diagonal wirings 30 are arranged as shown in FIG. 12A, as shown in FIG. 12B, the longitudinal side edge of one diagonal wiring 30 is shown. The grid 22 is rotated so that the coordinate axis of the grid 22 follows the part 30a. Here, when each longitudinal direction side edge 30a in one diagonal wiring 30 is not parallel, either one longitudinal direction side edge 30a is aligned with the coordinate axis of the grid 22 or each longitudinal direction side. The grid 22 can be rotated so that the coordinate axis of the grid 22 is along the average direction of the direction in which the edge 30a extends.

  Here, as shown in FIG. 13A, when the grid 22 is not rotated according to the diagonal wiring 30, the side edge of the pseudo wiring pattern 24 is a basic cell (as shown in FIG. 13B). Since the wiring existence area 26 and the wiring absence area 27) are stepped, a more accurate inter-wiring capacitance cannot be obtained. On the other hand, as shown in FIG. 13C, when the coordinate axis of the grid 22 is rotated along the longitudinal side edge 30a of the diagonal wiring 30, as shown in FIG. Since the side edges of the wiring pattern 24 are not stepped by the basic cells (the wiring existing area 26 and the wiring non-existing area 27) but are linear, the inter-wiring capacitance can be obtained more accurately.

  Another method for rotating the grid 22 is to rotate the grid 22 so that the coordinate axes of the grid 22 coincide with the average extending direction of the plurality of diagonal wirings 30 when a plurality of the diagonal wirings 30 extend. can do. As a specific example, when two diagonal wirings 30 are arranged as shown in FIG. 14A, the coordinate axis of the grid 22 is one diagonal wiring as shown in FIG. 14B. The grid 22 is rotated so as to face the extending direction in which the extending direction of 30 and the extending direction of the other diagonal wiring 30 are averaged. Here, in the case where each longitudinal side edge 30a in at least one of the one and other diagonal wirings 30 is not parallel, each longitudinal side edge in one (other) diagonal wiring 30 After obtaining the average extending direction of the direction in which 30a extends, the coordinate axes of the grid 22 are made to coincide with the direction in which the average extending direction in one diagonal wiring 30 and the average extending direction in the other diagonal wiring 30 are further averaged. In addition, the grid 22 may be rotated.

  In the above-described embodiment, the layout of the wiring 30 is divided into a plurality of unit areas 21 as S402, and then it is performed in the order of determining whether to rotate the grid 22 as S403. After rotating with respect to the layout of the wiring 30, the layout of the wiring 30 may be divided into a plurality of unit regions 21.

  According to the inter-wiring capacity calculation method and the wiring pattern design support apparatus 1 according to the present embodiment, the inter-wiring capacity of wirings arranged in different layers can also be obtained. FIG. 15 shows an example in which the inter-wiring capacity (overlap capacity) of the diagonal wirings 40 arranged at different levels is obtained. Here, FIG. 15A shows the diagonal wiring 40, and FIG. 15B shows the basic wiring pattern in which the region surrounded by the alternate long and short dash line shown in FIG. 15A is enlarged. ) Represents a capacity table.

  As shown in the cross-sectional view of FIG. 15B, the wiring pattern is such that a lower diagonal wiring 40, an interlayer insulating film 42, and an upper diagonal wiring 40 are sequentially stacked on a substrate 41. Then, as shown in the plan view of FIG. 15B, the width of the portion of the upper diagonal wiring 40 that does not overlap with the lower diagonal wiring 40 is W1, and the width of the lower diagonal wiring 40 that does not overlap with the upper diagonal wiring 40 Assuming that the wiring pattern in which the width of the wiring pattern 20 is W2 and the width of the overlapping portion of the wiring patterns 20 is W3 is a basic wiring pattern, the capacity table for this is as shown in FIG. Here, the capacitance value per unit length shown in the capacitance table takes into consideration the thickness of the interlayer insulating film 42, the thickness of the interlayer insulating film 42, the dielectric constant, and the like. As a result, as shown in FIG. 15A, the capacitance table shown in FIG. 15C is used even in the inter-wiring capacity of the diagonal wirings 40 arranged in different layers. Can be obtained by the look-up method.

  Further, according to the inter-wiring capacity calculation method and the wiring pattern design support apparatus 1 in the present embodiment, the wiring capacity (cross capacity) of the portion where the wiring 45 intersects as shown in FIG. 16 is also obtained. Can do. As shown in FIG. 16A, in the wiring 45 intersecting, in addition to the overlap capacitance generated in the portion where the wiring 45 intersects, there is also a parasitic between the longitudinal side edges 45a of the wirings 45. Capacitances B1 to B4 are generated. As a capacitance table in this case, as shown in FIG. 16B, the width W1 of one wiring 45, the width W2 of the other wiring 45, and the angle θ at which the wiring 45 intersects are used as parameters of the wiring 45 to overlap. A configuration in which a capacitance per unit length including a capacitance and parasitic capacitances B1 to B4 is associated with a parameter is used.

  Here, with respect to the parasitic capacitances B1 to B4, a capacitance value table closer to the actual measurement can be easily created by calculating the capacitance between wirings of different layers orthogonal to each other and adding them. The parasitic capacitances B1 to B4 obtained by approximation by this method do not cause a large error even if they intersect at any angle due to the object of the structure. Further, by adding an angle θ for the cross wiring and adding this to the table, a more accurate capacity table can be created. The capacitance value per unit length shown in the capacitance table takes into account the thickness of the interlayer insulating film (not shown), the dielectric constant of the interlayer insulating film, and the like. As a result, even if the inter-wiring capacitances of the wirings 45 intersecting each other as shown in FIG. 16A, the look using the capacitance table shown in FIG. It can be determined by the up method.

  In addition, in the calculation method of the inter-wiring capacitance and the wiring pattern design support apparatus 1 in the present embodiment, in addition to the wiring width and the wiring interval, the thickness of the interlayer insulating film, the dielectric constant of the interlayer insulating film, etc. It may be a parameter. Thereby, it is possible to estimate the inter-wiring capacity of the wiring patterns 20 arranged in different layers.

  Further, in the method for calculating the inter-wiring capacitance and the wiring pattern design support apparatus 1 in the present embodiment, the threshold value may be changed for each unit region 21 in accordance with the inclination angle of the oblique wiring. In this case, the threshold value set in the corresponding unit region 21 may be set to a large value at a location where the change is large such that the inclination angle of the diagonal wiring is large. When the threshold value is increased in this manner, the wiring capacity is estimated to be large, so that the circuit design has a margin. When the wiring pattern 20 is produced at this time, it is difficult for the circuit to be defective.

  Note that although the case where the inter-wiring capacitance is calculated using the capacitance table has been described in this embodiment, the present invention is not limited to this, and the wiring resistance can also be obtained.

For example, when obtaining the wiring resistance, the thickness of the laid out wiring pattern 20 and the wiring width obtained from the pseudo wiring pattern 24 can be obtained from the following formula (1) using the parameters as parameters.
R = (ρ / t) × (l / w) (1)
(Ρ: sheet resistance value, t: wiring pattern thickness, l: wiring pattern length, w: wiring width)

It is a flowchart showing the design process of a wiring pattern. It is a flowchart showing the extraction process of the capacity | capacitance between wiring. It is a figure showing a basic wiring pattern and a capacity table. It is a figure when a grid is created with respect to the layout of a wiring pattern. It is a figure which shows the grid located in the boundary of a wiring pattern. It is a figure of the pseudo | simulation layer showing a wiring pattern. It is a figure when extracting the capacitance value of a wiring pattern. It is a block diagram explaining the structure of the design support apparatus of a wiring pattern. It is an example of the figure which showed the layout of the wiring pattern by the unit area | region, and the pseudo | simulation layer when changing the magnitude | size of a grid. It is another example of the figure which showed the layout of the wiring pattern in the unit area | region when changing the magnitude | size of a grid, and the figure which shows a pseudo | simulation layer. It is a figure when a grid is rotated with respect to the layout of a wiring pattern, and a figure which shows a pseudo layer. It is an example of the figure when a grid is rotated with respect to the layout of a wiring pattern, and the figure which shows a pseudo layer. It is a figure which shows the effect when rotating the coordinate axis of a grid. It is another example of the figure when a grid is rotated with respect to the layout of a wiring pattern, and the figure which shows a pseudo layer. It is a figure of the wiring pattern with which wirings overlap, and the figure showing a capacity | capacitance table. It is a figure of the wiring pattern where wirings crossed, and a figure showing a capacity table. It is a top view of the wiring pattern which has arrange | positioned wiring in which the width | variety is not constant in the center. It is a figure showing the capacitance value between several wiring.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Design support apparatus, 2 ... Layout processing part, 3 ... Capacity calculation part, 4 ... Operation | movement confirmation processing part, 10 ... Basic wiring pattern, 20 ... Wiring, 21 ... Unit area | region, 22 ... Grid, 23 ... Basic cell, 26 ... wiring existence area, 27 ... wiring absence area, 34 ... pseudo wiring pattern, 30 ... diagonal wiring.

Claims (9)

A first step of dividing a circuit region including an arrangement region of a wiring pattern designed to include oblique wiring in an electric circuit into a plurality of unit regions by a predetermined lattice;
Depending on the occupancy rate of the wiring pattern in each unit area, each unit area is regarded as either a wiring existing area or a wiring non-existing area, so that the oblique wiring portion can be obtained only from the basic cell having the shape of the unit area. A second step of converting into a pseudo wiring pattern
A third step of performing pattern matching with a capacitance table configured by associating a basic wiring pattern and a capacitance with respect to the obtained pseudo wiring pattern;
And a fourth step of calculating an interwiring capacitance for the pseudo wiring pattern based on the result of the pattern matching. The inter-wiring capacity calculation method according to claim 1, wherein the capacity table is a table configured by associating inter-wiring capacities for each combination of the wiring width and wiring spacing in two parallel wirings forming a pair. . The inter-wiring capacitance calculation method according to claim 1, wherein in the first step, the shape or size of the unit region is changed according to the shape or size of the wiring pattern. 4. The wiring according to claim 3, wherein when the wiring pattern includes a plurality of diagonal wiring portions having different shapes or sizes, the shape or size of the unit region is changed according to the shape or size of each diagonal wiring portion. 5. Capacity calculation method. The inter-wiring capacitance calculation method according to claim 1, wherein, in the first step, the circuit area is divided into a plurality of unit areas after rotating the coordinate axis of the lattice in accordance with the oblique wiring portion. The inter-wiring capacitance calculation method according to claim 5, wherein when a plurality of the oblique wiring portions extend, the coordinate axis is rotated so as to coincide with an average extending direction of the plurality of oblique wiring portions. The inter-wiring capacitance according to claim 5, wherein when a plurality of the diagonal wiring portions extend, the coordinate axis is rotated so as to coincide with one of the plurality of diagonal wiring portions. Calculation method. The inter-wiring capacitance calculation method according to claim 1, wherein the wiring pattern includes a plurality of oblique wiring portions arranged at different levels. A layout processing unit that performs processing related to layout work of a wiring pattern including an oblique wiring portion in an electric circuit;
A capacity calculation unit for calculating the inter-wiring capacity related to the created wiring pattern;
An operation confirmation processing unit for confirming the operation of the electric circuit by applying the obtained inter-wiring capacitance,
The capacity calculation unit
A first process of dividing a circuit area including a wiring pattern arrangement area into a plurality of unit areas by a predetermined lattice;
Depending on the occupancy rate of the wiring pattern in each unit area, each unit area is regarded as either a wiring existing area or a wiring non-existing area, so that the oblique wiring portion can be obtained only from the basic cell having the shape of the unit area. A second process for converting the pseudo wiring pattern to
A third process for pattern matching with a capacitance table configured by associating a basic wiring pattern and a capacitance with respect to the obtained pseudo wiring pattern;
A wiring pattern design support apparatus that performs a fourth process of calculating an inter-wiring capacitance for the pseudo wiring pattern based on the pattern matching result.

Images