JP2010039505A - Controller device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a controller device handling input/output signals more in number than signal terminals of a controller. <P>SOLUTION: A unit 7 configured of a conversion device 4, an input terminal 5, and an output terminal 6 is mounted between two input signal lines and one signal terminal so that signals 3 more in number than the terminals of a terminal stand 2 is inputted to the controller. Signals input to the input terminals 5 are converted into pulse pattern signals corresponding to the respective input terminals by the conversion device 4, and a signal with two overlapped pulse patterns is outputted from the output terminal 6. The controller 1 recognizes that the signal with the overlapped pulse patterns inputted to one signal terminal includes the signal of each pulse pattern, then, decomposes it into the two signals. Thus, the input signals more in number than the signal terminals of the controller are handled. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a controller device that processes input signals and outputs processed signals.

  Conventionally, the number of signal points to be input / output to / from a controller that processes an input signal or outputs a processed signal is determined. For this reason, the terminal block provided in the controller for inputting and outputting signals is directly connected to the portion that actually takes the signal into the controller, so the number of terminals on the terminal block is equal to the maximum number of signals to be input and output.

For example, a signal conversion device described in Patent Document 1 that converts an input signal to a predetermined signal level, or a signal input to a lower-level signal conversion unit described in Patent Document 2 is a telephone line. Also, the number of terminals of the terminal block is the same as or larger than the number of signals to be input / output, as is conventional.
JP 2000-174673 A JP-A-8-251304

  A disadvantage of the above-described conventional general controller is that an interface exceeding the number of signal terminals prepared in the controller is impossible.

  For example, as shown in FIG. 5, when more signals (6 in the figure) than the number of signal terminals (5 in the figure) of the terminal block 2 of the controller 1 are input, among these signals, the signal terminals The same number of signals 3 can be handled because they can be connected to the signal terminals of the terminal block 2, but the remaining signals 8 exceeding the number of signal terminals cannot be handled because there are no signal terminals that can be connected to the terminal block 2. If it is going to cope with the remaining signals 8 exceeding the number of signal terminals, it is necessary to add a new unit or controller.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a controller device that can cope with a larger number of input / output signals than the number of signal terminals of the controller.

  In order to achieve the above object, a controller device according to the present invention is provided between a plurality of input signal lines and one signal terminal of the controller, and receives a plurality of signals input from the plurality of input signal lines. And a means for superimposing the converted pulse pattern signals and supplying the converted pulse pattern signals to one signal terminal of the controller as an overlapped pulse pattern signal. And means for resolving into a plurality of signals by identifying whether or not the pulse pattern signals corresponding to each of the plurality of signals are included in the overlapped pulse pattern signals inputted from one signal terminal. To do.

  The controller device according to the present invention is provided in a controller that outputs a plurality of signals from one signal terminal to a plurality of output signal lines, and converts the plurality of signals into pulse pattern signals corresponding to the plurality of signals, respectively. A means for converting and superimposing the converted pulse pattern signals and supplying them to one signal terminal as an overlapped pulse pattern signal, and provided between one signal terminal of the controller and a plurality of output signal lines; The overlapped pulse pattern signal output from one signal terminal of the signal is decomposed into a plurality of signals by identifying whether or not a pulse pattern signal corresponding to each of the plurality of signals is included. And a means for supplying a signal to a plurality of output signal lines.

  According to the present invention, it is possible to realize a controller device that can handle a larger number of input / output signals than the number of signal terminals of the controller.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a controller device according to an embodiment of the present invention.

  This embodiment is an embodiment in which an input signal is taken into a controller. As shown in the figure, in order to cause the controller 1 to which the terminal block 2 is attached to input signals 3 equal to or more than the number of signal terminals of the terminal block 2. The unit 7 composed of the conversion device 4, the input terminal 5 and the output terminal 6 is attached between two input signal lines and one signal terminal. (Note that the top signal line among the plurality of signal lines of signal 3 in the figure is a power supply line.)

  The configuration and function of the unit 7 will be further described with reference to FIG. As shown in the figure, the unit 7 includes a terminal block 23 having input terminals 21 and 22, a conversion device 24, and a terminal block 26 having an output terminal 25. When pulse signals are respectively input to the input terminals 21 and 22, the converter 24 converts the signals into pulse pattern signals corresponding to the input terminals 21 and 22 as shown in FIG. Then, the pulse pattern signal is output from the output terminal 25. The pulse pattern of the output signal is output as a pulse pattern obtained by superimposing two pulse patterns.

  That is, the unit 7 has a function of converting the input pulse signal into a pulse pattern signal, but outputs two or more signals as one point signal, so there are cases where the pulse signals overlap with each other as they are. Yes, the signals cannot be distinguished. Therefore, the conversion device 24 has a unique pulse pattern that allows each pulse signal to be distinguished from other signals (as will be described later, a unique pulse pattern that can be distinguished from the superimposed pulse patterns). This problem is solved by converting to a pulse pattern signal. When the pulse pattern signal generated by the converter 24 is output from the output terminal 25, if it is output for each pulse pattern, it takes time for the generated pulse pattern. Therefore, by superimposing the pulse patterns, a plurality of pulse patterns are input to the controller 1 with a cycle time of one pulse pattern, and the transmission time can be shortened. Also, as described above, when pulse patterns are overlapped, some pulses may overlap, but they do not coincide completely, so that each signal can be distinguished and decomposed into each signal.

  Since the controller 1 receives the overlapping pulse pattern signals from the unit 7, it has a function of identifying each pulse pattern signal and decomposing it into each signal.

  The function of discriminating each pulse pattern signal from the overlapped pulse pattern signal when this overlapped pulse pattern signal is input to one signal terminal of the controller 1 will be described with reference to FIG. FIG. 3 shows a pulse pattern for one cycle.

  When pulse signals are simultaneously input to the input terminals 21 and 22 of the unit 7, these pulse signals are converted into pulse pattern signals as shown in, for example, A and B of FIG. From 25, a pulse pattern signal indicated by C where these pulse patterns overlap is output, and this signal is input to one signal terminal of the controller 1.

  In order to identify that the pulse pattern signal A is included in the signal C in which the pulse pattern overlaps, the identification signal D1 and the signal C are ANDed using the identification signal D1 having the same pattern as A. Since the pulse pattern signal A is included in the signal C, the result shown in E of FIG. 3 is obtained. On the other hand, when the pulse pattern signal A is not included in the signal input to one signal terminal of the controller 1 and only the pulse pattern signal B is input, the AND output of this signal B and the identification signal D1 is The result shown in F of FIG. 3 is obtained. From this, when the result shown in E of FIG. 3 is obtained, it can be identified that the pulse pattern signal A is included in the signal input to one signal terminal of the controller 1. (Note that if one period consists of four pulse patterns, the identification signal D2 delayed by one pulse from the identification signal D1, the identification signal D3 delayed by two pulses (not shown), and delayed by three pulses The identification signal D4 (not shown) is ANDed to identify whether the pulse pattern signal A is included.)

  Similarly, in order to identify that the pulse pattern signal B includes the pulse pattern signal B, the identification signal G1 having the same pattern as B is used to identify the pulse pattern signal B. When the AND operation is performed, since the pulse pattern signal B is included in the signal C, the result shown in FIG. On the other hand, if the pulse pattern signal B is not included in the signal input to one signal terminal of the controller 1 and only the pulse pattern signal A is input, the AND output of this signal A and the identification signal D1 is The result shown in I of FIG. 3 is obtained. From this, when the result shown in H of FIG. 3 is obtained, it can be identified that the pulse pattern signal B is included in the signal input to one signal terminal of the controller 1. (Note that if one period consists of four pulse patterns, an identification signal G2 (not shown) delayed by one pulse from the identification signal G1 and an identification signal G3 (not shown) delayed by two pulses, An identification signal G4 (not shown) delayed by 3 pulses is ANDed to determine whether the pulse pattern signal B is included.)

  In FIG. 3, the case where the pulse signals are simultaneously input to the input terminals 21 and 22 of the unit 7 has been described. However, for example, the input of the pulse signal to the input terminal 22 is slightly delayed from the input of the pulse signal to the input terminal 21. In this case, these pulse signals are converted by the conversion device 24, for example, as shown in FIGS. 4A and 4B, the signal B becomes a pulse pattern signal delayed by one pulse from the case of FIG. The pulse pattern signal indicated by C where these pulse patterns overlap is output, and this signal is input to one signal terminal of the controller 1.

  In order to identify that the pulse pattern overlapped signal C includes the pulse pattern signal A, similarly to the case of FIG. 3, the identification signal D1 is used to include the pulse pattern signal A in the signal C. Although it is understood that the pulse pattern signal B includes the pulse pattern signal B, the identification of the identification signal G2 delayed by one pulse from the identification signal G1 is ANDed. It can be identified that the result shown in H of FIG. 4 is obtained and the pulse pattern signal B is included.

  When the input of the pulse signal to the input terminal 22 is further delayed than the input of the pulse signal to the input terminal 21, the signal B becomes a pulse pattern signal delayed by 2 pulses or 3 pulses from the signal A, and the controller 1 Then, it can be identified that the pulse pattern signal B is included by taking an AND with the identification signal G3 or the identification signal G4 from the pulse pattern signal shown in C where the pulse patterns overlap.

  As described above, the input portion of the controller 7 can receive a plurality of pulse patterns at a single input terminal. Therefore, it is possible to input as many signals as possible to create a pulse pattern to the controller 1.

  Therefore, according to this embodiment, when the number of signal terminals on the controller terminal block is smaller than the number of input signals required for processing by the controller, a unit is attached between the input signal line and the signal terminal. The problem that the number of signal terminals on the terminal block is insufficient can be solved.

  The above description is for the case where the input signal is taken into the controller, but when the output signal is output from the controller, it can be realized with a configuration in which the function of the unit is reversed. That is, a unit composed of one input terminal and two output terminals is attached between one signal terminal and two output signal lines in order to output signals equal to or more than the number of signal terminals on the controller terminal block. . That is, in this unit, one point is input in a state where a plurality of pulse patterns are overlapped, the signals of the respective pulse patterns are identified, decomposed into two signals, and output from the output terminal corresponding to each signal. For this reason, the same processing as that of the conversion device 4 of the unit 7 described above is performed inside the controller to convert the two signals into corresponding pulse pattern signals, and the controller terminal in a pattern in which the two patterns are overlaid. Output from the signal terminal of the base. Then, in the unit that receives the signal of the overlapping pulse pattern, the signal of the pulse pattern is identified by the same function as the function of identifying the signal of the pulse pattern in the controller 1 described above, and is converted into two signals. Disassemble and output from the output terminal corresponding to each signal of the unit.

  With this configuration, when the number of signal terminals on the controller terminal block is less than the number of signals to be output, a unit is installed between the output signal line and the signal terminal, and a pulse processing function is added to the controller. It is possible to solve the problem that the number of signal terminals on the terminal block is insufficient.

1 is a circuit diagram showing a configuration of a controller device according to an embodiment of the present invention. The figure which shows the structure and function of the unit which are the principal parts of one Embodiment of this invention. The wave form diagram for demonstrating operation | movement of one Embodiment of this invention. The wave form diagram for demonstrating another operation | movement of one Embodiment of this invention. The circuit diagram which shows the structure of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Controller 2 ... Terminal block 3 ... Signal 4 ... Converter 5 ... Input terminal 6 ... Output terminal 7 ... Unit 21, 22 ... Input terminal 23 ... Terminal block 24 ... Converter 25 ... Output terminal 26 ... Terminal block

Claims (2)

  Provided between a plurality of input signal lines and one signal terminal of the controller, and converts a plurality of signals input from the plurality of input signal lines into pulse pattern signals corresponding to each of the plurality of signals, and converts them Means for superimposing the generated pulse pattern signals and supplying them to one signal terminal of the controller as an overlapping pulse pattern signal, and the overlapping pulse pattern signals provided in the controller and inputted from the one signal terminal And a means for decomposing the signal into a plurality of signals by identifying whether or not a pulse pattern signal corresponding to each of the plurality of signals is included.   Provided in a controller that outputs a plurality of signals from one signal terminal to a plurality of output signal lines, converts the plurality of signals into pulse pattern signals corresponding to each of the plurality of signals, and converted pulse pattern signals Are provided between the one signal terminal of the controller and the plurality of output signal lines, and one signal terminal of the controller. The overlapped pulse pattern signal output from is divided into a plurality of signals by identifying whether or not a pulse pattern signal corresponding to each of the plurality of signals is included, and the plurality of decomposed signals are output to the plurality of outputs And a controller for supplying the signal line.

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