JP2010034813A - Cds circuit of solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CDS circuit of a solid-state imaging element, which has a configuration hardly increasing a device area while improving offset to be generated in reading in a horizontal signal line in a CDS circuit for each column even in the solid-state imaging element such as a multi-pixel CMOS sensor. <P>SOLUTION: A signal outputted to a C-point charges a capacitor C4 during a period when a switch SW5 is in an on-state. Then the capacitor C5 is reset by VREF through a SW8, and the terminal voltage of the capacitor C5 is outputted to a horizontal signal line 13 through an amplifier 12 and a SW9. The terminal voltage of the capacitor C4 is transferred to the capacitor C5 after resetting through a SW 6, charged, and then, outputted to the horizontal signal line 13. A circuit part 15 supplies a signal with kTC noise suppressed therein to a CDS circuit part 14 at the end of the horizontal signal line. The CDS circuit part 14 performs CDS processing to subtract the output voltages of the horizontal signal line 13 at prescribed time intervals, thereby achieving offset correction. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a CDS circuit of a solid-state image sensor, and in particular, an offset generated at the time of reading to a horizontal signal line used in a solid-state image sensor such as a CMOS (Complementary Metal-Oxide Semiconductor) type image sensor (hereinafter referred to as a CMOS sensor). The present invention relates to a CDS circuit for a solid-state imaging device.

  Conventionally, the pixel output of a CMOS sensor is output separately for each pixel, and a signal is often taken out in the vertical direction and processed by a CDS circuit (correlated double sampling circuit) at a time in units of horizontal lines. This CDS circuit is prepared for each vertical signal (each column) so that the operation of the CDS circuit need not be performed at high speed.

  FIG. 11 shows a configuration diagram of an example of the CMOS sensor. In the figure, a plurality of pixels 1 are arranged in a two-dimensional matrix, and an arbitrary pixel is selected using a vertical selection circuit 2 and a horizontal selection circuit 3. A signal is output from the selected pixel to the CDS circuit 4 for each horizontal line, and the CDS circuit 4 provided for each column performs a correlated double sampling operation simultaneously with the horizontal line. The signal subjected to CDS processing by the CDS circuit 4 is finally output for each pixel through an amplifier (AMP) 5.

  FIG. 12 shows an equivalent circuit diagram of an example of the pixel 1. As shown in the figure, one pixel includes a photodiode PD1 and three MOS transistors Tr11, Tr12, Tr13. For reading from the pixel, the input signal ROWS1 to the gate of the MOS transistor Tr13 is set to the HIGH voltage to turn on the MOS transistor Tr13, and the voltage generated at PD1 is changed from the source of the MOS transistor Tr12 constituting the source follower to the MOS. The output voltage Vsout is output to the terminal Sout through the transistor Tr13. This Vsout is input as a signal to the CDS circuit 4 of FIG.

  Next, the reset signal PDRST1 is applied to the gate of the MOS transistor Tr11 to turn on the MOS transistor Tr11, so that Vdd is applied to the cathode of the photodiode PD1 via the drain and source of the MOS transistor Tr11 and PD1 is applied. Reset. Subsequently, similarly to the above, the MOS transistor Tr13 is turned on to be in a selected state, and the signal Vrout is output to the terminal Sout via the source-follower MOS transistor Tr12 and the MOS transistor Tr13.

  Here, the signal output Vsout after the light is converted into a voltage is expressed by the following equation.

Vsout = Vpd1-Vth12-Von13 (1)
Vpd1: Optical signal voltage converted by PD1
Vth12: threshold voltage of Tr12
Von13: ON voltage of Tr13 The signal output Vrout after PD1 reset is expressed by the following equation.

Vrout = Vdd−Vth11−Vth12−Von13 (2)
Vdd: power supply voltage
Vth11: Tr11 threshold voltage
Vth12: threshold voltage of Tr12
Von13: ON voltage of Tr13 Here, when the CMOS sensor is a multi-pixel of HD (High Definition) class, it is necessary to increase the output from the pixel in a configuration in which one CDS circuit is provided for each pixel. The amplifier arranged in the pixel becomes complicated. In this case, there is a limit to increasing the pixel reading speed, and there is a problem that the frame rate cannot be increased when used for moving images. Therefore, in general, by providing the CDS circuit 4 for each column as shown in FIG. 11, sufficient time for CDS processing is taken, and high-speed operation is possible.

  The CDS circuit 4 for each column is composed of only (1) a capacitor and a switch, and the column outputs a signal to the horizontal signal line without calculating the difference, and calculates the difference at the end of the horizontal signal line (2 A configuration is known in which an amplifier is arranged for each column, and a CDS process is performed by calculating a signal difference.

  However, in the CDS circuit for each column having the configuration (1), the offset voltage added to the signal from the pixel and the offset voltage added to the reset signal from the pixel are different for each column. There is a problem that the offset voltage varies, and this becomes a vertical stripe-shaped fixed pattern noise (FPN) to deteriorate the image quality.

  On the other hand, in the CDS circuit for each column configured as described in (2) above, the difference in offset generated in the CDS circuit for each column generates vertical stripe-shaped FPN as in the CDS circuit for each column configured as described in (1) above. In addition, there arises a problem that the gain variation of the CDS circuit or the like for each column becomes vertical stripe noise. Further, the CDS circuit having the configuration shown in (2) has a gain of 1 or less, so that the S / N is deteriorated, and further, the CDS operation is performed by a differential amplifier provided at the end of the horizontal signal line. There is also a problem that it cannot operate at high speed. In some cases, the buffer amplifier is configured in the form of an operational amplifier instead of the source follower. In either case, an offset due to element variation occurs, which remains as a vertically striped FPN.

  Therefore, conventionally, in order to solve these problems, the CMOS sensor has one CDS circuit at the output portion of the horizontal signal line, and the offset is suppressed by the DDS circuit configuration that performs the CDS operation again, or the optical sensor of the CMOS sensor. When a black level signal is read out, the signal is converted into a digital signal as an offset signal for the circuit for each column and then stored in the memory, and when the actual signal is read out, digital subtraction is performed to suppress the offset. (For example, refer to Patent Document 1 and Non-Patent Document 1). In addition, a method of performing readout for each column called a charge region difference method has been proposed. This method is a method in which the difference between the pixel signal and the reset signal of the pixel portion is measured by electric charge, and is a method in which the influence of the offset does not appear in reading by the CDS.

Japanese Patent No. 3540341 Kazuya Yonemoto, “Basics and Applications of CCD / CMOS Image Sensors”, CQ Publishing Co., Ltd., p. 195-199

  However, the above measures have the following problems. In the case of a DDS circuit that suppresses offset, it is necessary to perform the second CDS operation at the end of the horizontal signal line at a high speed, but there is a limit to the speed, and it is difficult to realize it with an HD class multi-pixel solid-state imaging device.

  In addition, when the signal of the optical black level, that is, the light-shielded pixel is read, the signal is digitally held in the memory as an offset signal of the CDS circuit for each column, and is subtracted digitally when the actual signal is read. In a conventional CDS circuit configured to perform and suppress, there is a possibility that the scale of a digital circuit may increase due to an increase in chip area due to an increase in the circuit, and in some cases, it is necessary to add a circuit outside the imaging device. It may be a cost issue. Furthermore, the charge region difference method is difficult to operate, and random noise at the time of charge injection may increase.

  The present invention has been made in view of the above points, and even in a solid-state imaging device such as a multi-pixel CMOS sensor, an offset generated in reading out to a horizontal signal line in a CDS circuit for each column is reduced. An object of the present invention is to provide a CDS circuit of a solid-state imaging device that can be improved with a configuration that hardly increases.

  In order to achieve the above object, the present invention reads out from pixels arranged in the column direction among a plurality of pixels of a solid-state imaging device in which a plurality of pixels each having photoelectric conversion means are regularly arranged. A first holding unit that holds a signal as a charge, a second holding unit that holds a pixel reset signal at the time of resetting pixels arranged in the column direction, and a charge transferred from the second holding unit Signals from the third holding means and the first pixels arranged in the column direction are held by the first holding means and read out from the first pixels obtained by differential amplification using an amplifier. After the difference between the received signal and the pixel reset signal from the first pixel is held by the second holding unit, the first holding unit is set to a specific potential and held by the second holding unit. A first transfer means for transferring the charge to the third holding means; a first transfer means; After the charge transfer by the means, the signal read from the second pixel adjacent to the first pixel in the column direction is held by the first holding means, and then obtained by differential amplification using an amplifier. The difference between the signal read from the second pixel and the pixel reset signal from the second pixel is held by the second holding unit, and then the first holding unit is set to a specific potential. A second transfer means for transferring the charge held in the second holding means to the third holding means and adding to the charge transferred by the first transfer means held in the third holding means; A fourth holding means for holding the potential of the third holding means in which charges are added and held by charge transfer by the second transfer means; and a first switch means for transferring the potential held in the fourth holding means. And transferred through the first switch and held in the fourth holding means. A fifth holding means for holding the position, a reset means for resetting the fifth holding means to a predetermined potential before the fifth holding means holds the potential held by the fourth holding means, and a horizontal signal A correction circuit unit that is provided at the end of the line and performs a subtraction operation of the input signal, and a period from the start of resetting the fifth holding unit by the reset unit until the potential held in the fourth holding unit is held, And a second switch means for supplying the holding potential of the holding means 5 to the horizontal signal line and supplying it to the correction circuit section as an input signal.

  Here, the first to fifth holding means, the first and second transfer means, the first and second switch means, and the reset means of the above invention are provided in the same integrated circuit. The correction circuit unit may be provided outside the integrated circuit.

  According to the present invention, the offset can be corrected even in an HD class multi-pixel solid-state imaging device without increasing the size of the digital circuit and the area of the device so much as compared with the conventional one. The generated vertical stripe FPN can be suppressed, the image quality can be improved, and the S / N of the output signal can be improved by reducing kTC noise and the like.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a circuit diagram of a main part of an embodiment of a CDS circuit of a solid-state imaging device according to the present invention. In FIG. 1, one vertical signal line commonly connected to a plurality of pixels arranged in the column direction (vertical direction) such as the pixel 1a and the pixel 1b is branched into two, one of which is an operational amplifier 11 via a switch SW1. The other is connected to the inverting input terminal of the operational amplifier 11 through the switch SW2 and the capacitor C2 in series. Here, the pixel 1a and the pixel 1b are pixels on any two adjacent horizontal lines. Further, the non-inverting input terminal of the operational amplifier 11 is grounded via the capacitor C1, and the reference voltage VREF is applied via the switch SW7. Further, the output terminal of the operational amplifier 11 is feedback-connected to the inverting input terminal through a series circuit of the switch SW4 and the capacitor C3 and the switch SW3 in parallel. Furthermore, the output terminal of the operational amplifier 11 is connected to the horizontal signal line 13 via the circuit unit 15 and the switch SW9. The horizontal signal line 13 is further connected to the CDS circuit unit 14.

  The circuit unit 15 includes switches SW5, SW6 and SW8, a capacitor C4 connected between the connection point of the switches SW5 and SW6 and the ground, and a non-inverting input terminal of the output of the operational amplifier 11 via the switches SW6 and SW5. The operational amplifier 12 is connected in series to the terminal, and the capacitor C5 is connected to the connection point between the non-inverting input terminal of the operational amplifier 12 and the switch SW6. A reference voltage VREF is applied to one end of the switch SW8. One end of the capacitor C5 is grounded. The operational amplifier 12 has a voltage follower in which an output terminal is feedback-connected to an inverting input terminal. The output terminal of the operational amplifier 12 is connected to the horizontal signal line 13 through the switch SW9. It should be noted that the switches SW1 to SW9 basically perform an operation of turning off after holding a signal in an on state.

  The CDS circuit 10 according to the present embodiment includes a first CDS circuit unit and a second CDS circuit unit that are configured by a circuit unit from a point A which is a common connection point of the switches SW1 and SW2 to a point C of the output terminal of the operational amplifier 11. There are 14 CDS circuit sections in total. The CDS circuit 10 according to this embodiment is characterized by a circuit including a circuit unit 15, a switch SW9, and a CDS circuit unit 14.

  Next, the operation of the first CDS circuit section in the CDS circuit 10 of the present embodiment will be described with reference to the timing chart of FIG.

It is assumed that signal voltages from the pixels 1a and 1b arranged in the same column direction change as shown in FIG. The signal voltage VS1 from the selected pixel 1a is held in the capacitor C1 when the switch SW1 is turned on at time t1, as schematically shown at a high level in FIG. Thereby, the charge Q1 charged in the capacitor C1 is expressed by the following equation. Note that Cx (x is a number) in each of the following mathematical expressions represents the capacitance value of the capacitor Cx.
Q1 = C1 × VS1 (3)

  Next, the pixel reset signal VR1 shown in FIG. 2A after resetting the pixel 1a in the state where the switch SW1 is in the OFF state as schematically shown at the low level in FIG. At the same time as reading, the switches SW2, SW4, and SW3 are turned on as schematically shown at high levels in FIGS. 2C, 2D, and 2E, respectively, and the capacitor C2 is charged with the signal VR1. At this time, voltages Va, Vb, Vc, and Vd at points A, B, C, and D shown in FIG.

Va = VR1 (4)
Vb = Vc = Vd = VS1 (5)
Note) At this time, it is considered that the operational amplifier 11 is an ideal operational amplifier and has no offset.

Further, the charges Q2 and Q3 charged in the capacitors C2 and C3 are respectively expressed by the following equations.
Q2 = C2 × (VS1-VR1) (6)
Q3 = C3 × 0 = 0 (7)

  Next, in a state where the switch SW3 is in an OFF state as schematically shown at low level in FIG. 2E, it is schematically shown at high level in FIGS. 2B, 2C, 2D, and 2F. As shown, the switches SW1, SW2, SW4, and SW7 are turned on at time t3, and the reference voltage VREF is applied to the point D. At this time, all the electric charge of the capacitor C2 is transferred to the capacitor C3 via SW4, and a signal obtained by multiplying the difference between the signal VS1 output from the pixel 1a and the pixel reset signal VR1 by a gain determined by the capacitance values of the capacitors C2 and C3. (Differentially amplified signal) appears at point C of the output terminal of the operational amplifier 11. The voltages Va ′, Vb ′, Vc ′, and Vd ′ at the points A, B, C, and D at this time are respectively expressed by the following equations.

Va ′ = Vb ′ = Vd ′ = VREF (8)
Vc ′ = (C2 / C3) × (VS1-VR1) −VREF (9)
Further, the charge Q3 ′ transferred to the capacitor C3 is as follows.
Q3 ′ = Q2 = C2 × (VS1-VR1) (10)

Next, the pixel 1b on the horizontal line next to the pixel 1a is selected at time t4 as shown in FIG. 2A, and the signal VS2 is output from the pixel 1b. This signal VS2 is taken as a charging voltage by the capacitor C1. That is, as schematically shown at a high level in FIG. 2B, the switch SW1 is turned on at time t4 to charge the capacitor C1 with the signal VS2. Thereby, the charge Q1 ′ of the capacitor C1 is expressed by the following equation.
Q1 ′ = C1 × VS2 (11)

  Next, the pixel reset signal VR2 shown in FIG. 2A after resetting the pixel 1b is read at time t5, and the switches SW2, SW2 and SW2 are schematically shown at high levels in FIGS. SW3 is turned on to charge the capacitor C2. At this time, voltages Va ″, Vb ″, Vc ″, and Vd ″ at points A, B, C, and D shown in FIG. 1 are respectively expressed by the following equations.

Va ″ = VR2 (12)
Vb ″ = Vc ″ = Vd ″ = VS2 (13)
Here, since the switch SW4 is in the OFF state as schematically shown in FIG. 2D at a low level, the charge of the capacitor C3 remains Q3 ′ that has been charged first. As a result, the charges Q2 ′ and Q3 ′ charged in the capacitors C2 and C3 are expressed by the following equations.
Q2 ′ = C2 × (VS2-VR2) (14)
Q3 ′ = C2 × (VS1-VR1) (15)

Next, as schematically shown at a high level in FIGS. 2B, 2C, 2D, and 2F, the switches SW1, SW2, SW4, and SW7 are turned on at time t6, and the point D Is applied with a reference voltage VREF. At this time, the charge Q2 ′ of the capacitor C2 is all transferred to the capacitor C3, and a signal obtained by multiplying the difference between the signal VS2 output from the pixel 1b and the reset pixel reset signal VR2 by a gain determined by the capacitance values of the capacitors C2 and C3. Is output to point C of the output terminal of the operational amplifier 11. At this time, the voltages Va ′, Vb ′, and Vd ′ at the points A, B, and D are expressed by the above equation (8), and the voltage Vc ′ ″ at the point C is expressed by the following equation.
Vc ′ ″ = (C2 / C3) × (VS1−VR1 + VS2−VR2) −VREF (16)

Further, the charge Q3 ″ moved to the capacitor C3 is expressed by the following equation.
Q3 "= Q2 '+ Q3'
= C2 × (VS1-VR1 + VS2-VR2) (17)

  Here, the output voltage Vc ′ ″ of the first CDS circuit unit expressed by the above equation (16) is used to charge a capacitor whose one end is grounded through a switch that is turned on immediately after time t6. When the charging voltage is output to the horizontal signal line 13 by turning on the switch SW9 provided for each column through the buffer amplifier, the offset voltage for each column is added to the voltage output to the horizontal signal line 13. Is done. This offset voltage varies from column to column, and becomes vertical stripe-shaped fixed pattern noise (FPN) as described above, deteriorating image quality.

  Therefore, the inventor previously connected, for example, the offset correction circuit shown in FIG. 8 or FIG. 9 to the position of the circuit portion 15 on the output side of the first CDS circuit portion according to Japanese Patent Application No. 2007-141845. A CDS circuit for correcting the offset voltage was proposed.

  FIG. 8 shows a circuit diagram of an example of the offset correction circuit proposed above. In FIG. 1, point C in FIG. 1 is connected to the gate of an N-channel MOS transistor Tr7 through switches SW11 and SW12 in series. A reference voltage VREF is input to the connection point between the switch SW12 and the gate of the N-channel MOS transistor Tr7 via the switch SW13. The source of the MOS transistor Tr7 is connected to the signal output terminal, the current source 31, and one end of the switch SW16. The signal output terminal is connected to the horizontal signal line 13 via the switch SW9 in FIG.

  The other end of the switch SW16 is grounded via the capacitor 21 and is connected to the non-inverting input terminal of the buffer amplifier 30. The output terminal of the buffer amplifier 30 is connected to a connection point between the switches SW11 and SW12 through the switch SW15 and the capacitor C22, and is connected to a power supply terminal to which the reference voltage VREF is input through the switch SW15 and the switch SW14. Yes.

  FIG. 9 shows a circuit diagram of another example of the offset correction circuit proposed above. In the figure, the same circuit portions as those in FIG. 8 are denoted by the same reference numerals, and the description thereof is omitted. FIG. 9 shows a configuration in which the switch SW16, capacitor C21, and buffer amplifier 30 in FIG. 8 are omitted, and the source of the MOS transistor Tr7 is directly connected to the switch SW15. Each of the offset correction circuits shown in FIGS. 8 and 9 is an offset correction circuit having an output source follower configuration.

  Next, the operation of the offset correction circuit shown in FIGS. 8 and 9 will be described with reference to the timing chart shown in FIG. The timing chart of FIG. 10 also includes the ON / OFF operation of the switch of the first CDS circuit section shown in FIG. Among these, FIGS. 10A to 10G are timing charts of the respective circuit portions in FIG. 1 which are the same as FIGS. 2A to 2G, and the description thereof is omitted. Since the operations in FIGS. 8 and 9 are basically the same, in the following description, the operation will be described using the circuit in FIG. 9 as a representative.

As schematically shown at high level in FIG. 10 (H), as schematically shown at high level in FIG. 10 (I) at the same timing as when the switch SW11 in FIG. 9 is turned on at time ta. In addition, the switch SW13 and the switch SW15 are turned on. At this time, the switches SW12 and SW15 are in the OFF state. Then, the voltage Vc ′ ″ at the point C shown in FIG. 1 is applied to the SW11 side terminal of the capacitor C22 via the switch SW11 of FIG. Further, the reference voltage VREF is applied to the gate of the MOS transistor Tr7 in FIG. 9 via the switch SW13, and the source voltage Vstr7 expressed by the following equation is output to the source of Tr7.
Vstr7 = VREF−Vth7 (18)
Vth7: threshold voltage of Tr7

This source voltage Vstr7 is applied to the SW15 side terminal of the capacitor C22 via the switch SW15 in the ON state. At this time, the voltage Vc ′ ″ at the point C is applied to the SW11 side terminal of the capacitor C22 via the switch SW11. Accordingly, the voltage Vc22 expressed by the following equation is held in the capacitor C22.
Vc22 = Vc ′ ″ − Vstr7 = Vc ′ ″ − VREF + Vth7 (19)

  Next, at time tb, the switches SW11, SW13, and SW15 are turned off as schematically shown at low levels in FIGS. 10 (H) and (I), and schematically at high level in FIG. 10 (J). As shown, the switches SW12 and SW14 are turned on. Thereby, since the reference voltage VREF is applied to the SW15 side terminal of the capacitor C22 via the switch SW14, the reference voltage is applied from the capacitor C22 to the gate of the MOS transistor Tr7 via the switch SW12 as shown in the following equation. VREF is applied as a voltage Vgtr7 from which cancellation has been eliminated.

Vgtr7 = VREF + Vc22
= VREF + Vc '''-VREF + Vth7
= Vc '''+ Vth7 (20)
Therefore, the source voltage Vstr7 ′ of Tr7 at this time is expressed by the following equation when arranged using equation (20).

Vstr7 ′ = Vgtr7−Vth7 = Vc ′ ″ (21)
Therefore, Vth7 of the MOS transistor Tr7 is removed, and only the signal voltage Vc ″ ′ output from the point C in the CDS circuit of FIG. 1 is obtained. The source voltage Vstr7 ′ (= Vc ′ ″) is the horizontal signal for the period shown in FIG. 10K when the switch SW9 in FIG. 1 is turned on as shown in FIG. 10G at time td. Output to line 13.

  However, in the CDS circuit previously proposed by the inventor, the actual readout is performed by connecting the horizontal signal line readout SW (SW9 in FIG. 1) after the signal output in FIG. Since the constant current source 31 shown in FIG. 9 is provided for each column, the current value is different from that of the external constant current source connected to the horizontal signal line 13 and the current is small in terms of power consumption. It has become. Therefore, there is a possibility that Vth7 in equation (18) and Vth7 in equation (21) may be different, and Vth7 may not be completely suppressed.

  Further, in the CDS circuit proposed above, kTC noise is generated when the gate of the MOS transistor Tr7 is driven using the SW12 of FIG. 9 when reading a signal to the horizontal signal line. This noise is difficult to suppress with the above circuit configuration and operation.

  Therefore, in the embodiment shown in FIG. 1, in order to solve the problems in the CDS circuit previously proposed by the present inventor together with the conventional problems, the output side of the first CDS circuit section, the switch SW9, The correction circuit unit 15 is provided between the two. Next, the operation of the offset correction circuit unit including the circuit unit 15 and the switch SW9 after the first CDS circuit unit of the embodiment shown in FIG. 1 will be described with reference to the timing chart of FIG.

As described above, by turning on the switches SW1, SW2, SW4, and SW7 at time t6 in FIG. 2, the voltage Vc ′ ″ shown in the equation (16) is output to the point C. Here, until the period of time t7 after the above-described time t6, the switch SW5 in FIG. 1 is in the ON state as schematically shown in FIG. 2G and the switch SW6 is in FIG. Since it is in the OFF state as schematically shown at (J) at the low level, the voltage Vc ′ ″ is charged to the capacitor C4 via the switch SW5. Accordingly, the charging voltage Ve of the capacitor C4 at this time is expressed by the following equation.
Ve = Vc ′ ″ = (C2 / C3) × (VS1−VR1 + VS2−VR2)
-VREF (22)

  Subsequently, as schematically shown at a high level in FIGS. 2 (H) and (I) at time t8, the switches SW9 and SW8 are turned on, so that the capacitor C5 is connected to the reference voltage VREF via the switch SW8. And the terminal voltage of the capacitor C5 is output to the horizontal signal line 13 through the amplifier 12 of the voltage follower and the switch SW9. Since the reference voltage VREF basically does not change for each column, the offset for each column is corrected.

  Subsequently, at time t9, as schematically shown at a high level in FIGS. 2H and 2J, the switch SW9 continues to be in the ON state, and the switch SW6 is in the ON state. Since the switch SW8 changes to the OFF state as schematically shown at 2 (I) at a low level, the terminal voltage Ve of the capacitor C4 is transferred to the capacitor C5 after reset through the switch SW6 and charged. . The terminal voltage of the capacitor C5 is output to the horizontal signal line 13 through the amplifier 12 of the voltage follower and the switch SW9. This output state is performed until the switch SW9 is turned off at time t10, as schematically shown at a low level in FIG. FIG. 2K shows the output voltage of the horizontal signal line 13.

  The output voltage of the horizontal signal line 13 is supplied to the second CDS circuit unit 14 at the end of the horizontal signal line. As will be described later, kTC noise generated by switching of the switches SW5 to SW8 is suppressed and output to the output voltage output from the circuit unit 15 to the horizontal signal line 13. The second CDS circuit unit 14 performs CDS processing for subtracting the output voltage of the horizontal signal line 13 during the period of time t9 to t10 from the output voltage of the horizontal signal line 13 during the period of time t8 to t9. , A signal in which the offset due to the threshold voltage of the switch SW9 being different for each column is corrected is output.

  Next, each embodiment of the offset correction circuit unit after the first CDS circuit of the embodiment shown in FIG. 1 will be described in more detail. FIG. 3 shows a circuit diagram of an embodiment of the offset correction circuit unit of the main part of the present invention. In FIG. 1, point C in FIG. 1 is connected to the gate of an N-channel MOS transistor Tr1 through a switch S1, a buffer amplifier 21, and a switch S2 in series. A capacitor C11 is connected to a connection point between the switch S1 and the buffer amplifier 21. Further, a capacitor C12 and a switch S3 are connected to a connection point between the switch S2 and the gate of the transistor Tr7. A reference voltage VREF is applied to the other ends of the capacitors C11 and C12 and the other end of the switch S3.

  The source of the MOS transistor Tr1 is connected to the signal output terminal and the current source 22 through the horizontal selection switch S4. The signal output terminal is connected to the second-stage CDS circuit unit 24 in the large-scale semiconductor integrated circuit (LSI) via the horizontal signal line in FIG. The CDS circuit unit 24 includes a capacitor C13, a switch S5, and an operational amplifier 23. The operational amplifier 23 constitutes a voltage follower in which a capacitor C13 and a switch S5 are connected to the non-inverting input terminal, and an output terminal is connected in feedback to the inverting input terminal. A reference voltage VREF 'is applied to one end of the switch S5.

  Here, the switches S1, S2, S3, and S4 in FIG. 3 correspond to the switches SW5, SW6, SW8, and SW9 in FIG. 3 corresponds to the CDS circuit unit 14 of FIG. Further, the capacitors C11 and C12 in FIG. 3 correspond to the capacitors C4 and C5 in FIG. The source follower MOS transistor Tr1 in FIG. 3 corresponds to the amplifier 12 of the voltage follower in FIG. Note that the buffer amplifier 21 of FIG. 3 is not shown in FIG.

  Further, each end of the capacitors C4 and C5 in FIG. 1 is grounded (connected to GND), whereas each end of the capacitors C11 and C12 in FIG. 3 is connected to the power supply terminal of the reference voltage VREF. (This also applies to FIGS. 5 and 6 described later). However, whether the reference voltage side of the capacitor is set to GND as shown in FIG. 1 or VREF is set as shown in FIG. 3 or FIGS. 5 and 6 to be described later, in the actual case, the DC voltage of VREF or the VREF side There may be a difference in performance depending on the impedance, but there is no theoretical difference in performance.

  Next, the operation of the embodiment of FIG. 3 will be described with reference to the timing chart of FIG. First, when a voltage Vc ′ ″ at a point C, which is a signal from the first CDS circuit portion shown in FIG. 1, is input after time t11 as shown in FIG. 4A, FIG. As shown schematically at the high level, the switch S1 is turned on at time t12, and the switch S2 is turned off as schematically shown at the low level in FIG. C11 is charged with the voltage Vc ′ ″ and held. FIG. 4C shows a signal held in the capacitor C11.

  Next, at time t13, the switch S4 is turned on as schematically shown at a high level in FIG. 4G, and the switch S2 is continuously turned off as schematically shown at a low level in FIG. 4D. And the switch S3 is turned on as schematically shown at a high level in FIG. Thereby, the reference voltage VREF is applied to the capacitor C12 via the switch S3 and charged. That is, the capacitor C12 is reset by the reference voltage VREF. The reset voltage of the capacitor C12 is output to the horizontal signal line through the gate and source of the source follower transistor Tr1 and the switch S4. Here, one switch S4 is provided in one column, and the switches S4 are selected one by one so as to scan with the output of the horizontal drive circuit. Although FIG. 3 shows that only a signal for one column is output to the horizontal signal line, actually, the signal for one column is continuously output.

The reset voltage output to the horizontal signal line charges the capacitor C13 in the CDS circuit unit 24 as a reference voltage. Here, the switch S5 in the CDS circuit unit 24 is in an ON state during a period from time t13 to time t14 schematically shown at a high level in FIG. 4I, and the reference voltage VREF ′ is applied during the ON state. The voltage is applied to the operational amplifier 23 side terminal of the capacitor C13. Therefore, the charging voltage Vc13 of the capacitor C13 in the period from the time t13 to the time t14 when the switch S4 and the switch S5 are in the ON state is expressed by the following equation.
Vc13 = VREF−Vth2−VREF ′ (23)
Vth2: Tr1 threshold voltage
VREF: reference voltage of the column CDS circuit 10
VREF ′: reference voltage of the CDS circuit unit 24 at the end of the horizontal signal line

  Next, at time t14 when the switch S4 is in the ON state, the switch S2 is turned on as schematically shown at the high level in FIG. 4D, and schematically at the low level in FIG. 4F. As shown, the switch S3 is turned off. As a result, the signal from the first CDS circuit unit held in the capacitor C11 is transferred to the capacitor C12 through the buffer amplifier 21. At this time, since the switch S3 is in the OFF state, the terminal voltage Vc12 of the capacitor C12 is expressed by the following equation.

Vc12 = {C11 / (C11 + C12)} × (VS1-VREF) + VREF
(24)
VS1-VREF: signal voltage of GND input from the first CDS circuit section Here, it is considered that there is no buffer amplifier 21 in FIG. 3, and the capacitor C11 and the switch S2 are directly connected. FIG. 4E shows a signal held in the capacitor C12.

  The voltage Vc12 is output to the horizontal signal line through the gate and source of the source follower transistor Tr1 and the switch S4 as shown in FIG. The voltage Vc12 output to the horizontal signal line charges the capacitor C13. Here, the switch S5 in the CDS circuit section 24 is in the OFF state during the period from time t14 to t15 schematically shown at low level in FIG. 4I, and the operational amplifier 23 of the capacitor C13 during this OFF state period. The terminal voltage Vc13 ′ of the side terminal is expressed by the following equation.

Vc13 ′ = (Vc12−Vth2) −Vc13
= Vc12-Vth2- (VREF-Vth2-VREF ')
= {C11 / (C11 + C12)} × (VS1-VREF) + VREF ′ (25)
If the buffer amplifier 21 is included in the offset correction circuit section of the CDS circuit for each column as shown in FIG. 3, the signal is not distributed by the capacitors C11 and C12, so the input signal VS1 becomes Vc12 as it is. Therefore, in this case, equation (25) is expressed by the following equation.

Vc13 ′ = VS1−VREF + VREF ′ (26)
The terminal voltage Vc13 ′ represented by the above expression (25) or (26) is output as an output signal of the CDS circuit 24 through the operational amplifier 23 of the voltage follower.

  In this way, the CDS circuit unit 24 performs the subtraction process on the signals (Vc12−Vth2) and Vc13 input via the horizontal signal line during the ON period of the switch S4 from time t13 to time t15, and (25) The signal Vc13 ′ expressed by the equation (26) is output.

  Here, as can be seen from the equations (25) and (26), the output signal Vc13 ′ of the CDS circuit section 24 does not include the threshold voltage Vth2, and the reference voltages VREF and VREF in the output signal Vc13 ′ are included. 'Basically does not change from column to column, so the output signal Vc13' of the operational amplifier 23 is corrected for the offset for each column. FIG. 4J shows the signal Vc13 ′ in which the offset output from the CDS circuit unit 24 is corrected.

  Next, a circuit of another embodiment of the offset correction circuit unit of the main part of the present invention will be described. FIG. 5 shows a circuit diagram of another embodiment of the offset correction circuit unit of the main part of the present invention. In the figure, the same components as those in FIG.

  In the offset correction circuit unit of the embodiment of FIG. 5, the CDS circuit unit 14 of FIG. 1 is not formed in the LSI as shown in FIG. 3, but the external CDS circuit unit 26 connected to the signal output terminal 25 is provided outside the LSI. The example used is shown. The external CDS circuit unit 26 can be substituted with a CDS circuit or the like included in an analog front end used in, for example, a CCD (Charge Coupled Devise). The operation of the offset correction circuit unit of FIG. 5 is represented by the timing chart of FIG. 4 which is the same as the operation of the offset circuit unit of FIG.

  By the way, in the offset correction circuit unit shown in FIGS. 3 and 5, kTC noise is generated not only by the offset but also by the switch operations of the switches S1, S2, and S3. However, of these kTC noises, the kTC noise generated by the switch operation of the switch S3 can be suppressed together with the offset voltage by the operation of the CDS circuit unit 24 and the external CDS circuit unit 26 at the end of the horizontal signal line.

  Further, kTC noises Vns1 and Vns2 generated by the switch operations of the switches S1 and S2 are expressed by the following equations.

Vns1 = √ (kT / C11) (27)
Vns2 = √ (kT / C12) (28)
In equations (27) and (28), k represents Boltzmann's constant, and T represents absolute temperature.

  However, if the capacitance values of the capacitors C11 and C12 are increased to about pF, the kTC noises Vns1 and Vns2 generated by the switch operations of the switches S1 and S2 can be made extremely small to 100 μV or less. As a result, in the offset correction circuit unit shown in FIGS. 3 and 5, the S / N degradation of the signal due to the kTC noise can be brought to a level with no problem.

  Next, a first embodiment of the CDS circuit of the solid-state imaging device according to the present invention will be described with reference to the drawings. FIG. 6 shows a circuit diagram of Embodiment 1 of the CDS circuit of the solid-state imaging device according to the present invention. In the figure, the same components as those in FIG.

  In FIG. 6, one vertical signal line commonly connected to a plurality of pixels arranged in the column direction (vertical direction) such as the pixel 1a and the pixel 1b is branched into two, one of which is an N-channel MOS transistor TR1 and a capacitor. 2 is connected to the drains of the N-channel MOS transistors TR3 and TR4 and the gate of the P-channel MOS transistor TR7, and the other is connected to the gate of the P-channel MOS transistor TR8 and the N-channel MOS transistor TR11 via the N-channel MOS transistor TR2. The source and the capacitor C1 are connected. The source of the transistor TR3 is connected to the common connection point of the P-channel MOS transistors TR14, TR16 and TR17 through the capacitor C3 together with the source of the transistor TR4. Here, the pixel 1a and the pixel 1b are pixels on any two adjacent horizontal lines. Transistors TR1, TR2, TR3, TR4, TR11 correspond to the switches SW2, SW1, SW4, SW3, SW7 shown in FIG.

  The transistors TR7 and TR8, a P-channel MOS transistor TR5 whose source is connected to the drains of the TR7 and TR8, P-channel MOS transistors TR6 and TR13 constituting a current mirror circuit, and a current mirror circuit. P-channel MOS transistors TR15 and TR16, two N-channel MOS transistors TR12 and TR9 connected in series to the source side of the transistor TR15, and connected in series to the source side of the transistor TR16, and the transistors TR12 and TR9, respectively. The two N-channel MOS transistors TR14 and TR10 having the gates connected in common constitute a CMOS folded cascode type operational amplifier corresponding to the operational amplifier 11 of FIG. It is. The source of the transistor TR7 is connected to the common connection point of the transistors TR14 and TR10. The source of the transistor TR8 is connected to the common connection point of the transistors TR12 and TR9.

  Further, the common connection point between the capacitor C3 and the transistors TR4, TR16, and TR14 is connected to the source of the N-channel MOS transistor TR19 and the gate of the N-channel MOS transistor TR20 via the N-channel MOS transistors TR17 and TR18 in series. Yes. The source common connection point of the transistors TR18 and TR19 is connected to the power supply terminal of the reference voltage VREF via the capacitor C5. The common connection point of the transistors TR17 and TR18 is connected to the power supply terminal of the reference voltage VREF via the capacitor C4. Furthermore, the source of the transistor TR20 is connected to the horizontal signal line 17 via the drain and source of the N-channel MOS transistor TR21. A constant current source 16 is also connected to the horizontal signal line 17.

  The transistors TR17, TR18, TR19, TR20 correspond to the switches SW5, SW6, SW8, and the buffer amplifier 12 shown in FIG. 1, and the transistor TR21 corresponds to the switch SW9 shown in FIG. The horizontal signal line 17 corresponds to the horizontal signal line 13 shown in FIG.

  Next, the operation of this embodiment will be described with reference to the timing chart of FIG. In FIG. 7A, VS1 and VR1 are the output signal voltage and reset signal voltage of the pixel 1a in FIG. 6, and VS2 and VR2 are the output signal voltage and reset signal voltage of the pixel 1b. 7B shows the gate input voltage SHS of the transistor TR2, and FIG. 7C shows the gate input voltage SHR of the transistor TR1. 7 (D), (E), (F), (G), (H) are switching signals a, b, applied to the gates of the switching transistors TR3, TR4, TR11, TR17, TR21. c, d, and H1 are shown. During the high level period of the switching signal, the transistor to which the switching signal is applied to the gate is controlled to be in the ON state.

  7 (I) and 7 (J) show switching signals e and f applied to the gates of the switching transistors TR18 and TR19. During the high level period of the switching signals e and f, the transistors TR18 and TR19 to which the switching signals e and f are applied to the gates are controlled to be in the ON state. FIG. 7K shows the signal voltage output to the horizontal signal line 17.

  The operation of the present embodiment is basically the same as the operation described with reference to FIG. 1. In the circuit of FIG. 6, reading from the pixel 1a and reading from the pixel 1b of the next horizontal line are performed, and the capacitor C3 Charge addition. Finally, a signal Vt16s represented by the following equation is output to the drain side output of the output transistor TR16 of the operational amplifier.

Vt16s = (C2 / C3) x (VS1-VR1 + VS2-VR2) -VREF (29)
After the signal Vt16s is read, the signal Vt16s is held in the capacitor C4 during the period in which the transistor TR17 is turned on by the switching signal d shown in FIG. Here, the voltage Vc4u at the TR15 side terminal of the capacitor C4 is expressed by the following equation.

Vc4u = Vt16s (30)
On the other hand, the lower voltage Vc41 of the capacitor C4 is expressed by the following equation.

Vc4l = VREF (31)
Therefore, the voltage Vc4 held in the capacitor C4 is expressed by the following equation.

Vc4 = Vc4u-Vc4l = Vt16s-VREF (32)
Next, at time t7, as shown in FIG. 7G, the switching signal d is set to the low level to turn off the transistor TR17. At time t8, the switching signal H1 is set high as shown in FIG. The transistor TR21 is turned on as a level, and the switching signal f is turned high as shown in FIG. Accordingly, the reference voltage VREF is output to the horizontal signal line 17 via the drain and source of the transistor TR19, the gate and source of the transistor TR20 of the source follower, and the drain and source of the transistor TR21. The voltage of the horizontal signal line 17 at this time is expressed by the following equation.

Vr17 = VREF−Vth20 (33)
Vth20: threshold voltage of TR20 Also, at this time, the capacitor C5 is charged by the reference voltage VREF and reset.

  Subsequently, at time t9 when the transistor TR17 is in the OFF state and the transistor TR21 is in the ON state, the transistor TR19 is turned off, and the switching signal e is set to the high level as shown in FIG. When the transistor TR18 is turned on, the charge held in the capacitor C4 is distributed to the capacitor C5 through the drain and source of the transistor TR18. As a result, a terminal voltage Vc5 expressed by the following equation is generated on the TR18 and TR19 side of the capacitor C5.

Vc5 = {C4 / (C4 + C5)} × (Vt16s−VREF) + VREF
= {C4 / (C4 + C5)} × [{(C2 / C3) × (VS1-VR1
+ VS2-VR2) -VREF} -VREF] + VREF (34)
This terminal voltage Vc5 is supplied to the base of the transistor TR20 of the source follower and output from the source. At this time, the source voltage Vt20s of the transistor TR20 is expressed by the following equation.

Vt20s = Vc5-Vth20
= {C4 / (C4 + C5)} × {(C2 / C3) × (VS1-VR1 + VS2)
−VR2) −VREF} −VREF + VREF−Vth20 (35)
The source voltage Vt20s is output to the horizontal signal line 17 during the period when the transistor TR21 is in the ON state (t9 to t10). As a result, the output signal to the horizontal signal line 17 becomes as shown in FIG.

Further, the output signal of the horizontal signal line 17 is supplied to the CDS circuit unit 14 shown in FIG. 1, the CDS circuit unit 24 shown in FIG. 3, or the external CDS circuit unit 26 shown in FIG. Is output. The output voltage Vout of the CDS circuit section 14, 24 or 26 at this time is expressed by the following expression from the expressions (33) to (35), when the ON voltage of the transistor TR 21 is ignored.
Vout = Vr17−Vt20s
= VREF-Vth20- (Vc5-Vth20)
= VREF-Vc5
= − {C4 / (C4 + C5)} × {(C2 / C3) × (VS1-VR1)
+ VS2−VR2) −2 × VREF} (36)

  Therefore, according to the first embodiment, as can be seen from the equation (36), Vth20 in the output signal Vout can be removed, so that the offset of Vth20 for each column can be suppressed and the FPN can be suppressed. . Further, according to the first embodiment, the kTC noise generated in the signal generated by the same expression as Expressions (28) and (29) and suppressing the FPN of the pixel portion is the capacitors C4 and C5 as described above. If each capacitance value is increased to about pF, S / N deterioration of the output signal Vout can be suppressed.

  As described above, according to the embodiment and Example 1 described above, the CDS circuit units 14, 24, and 26 provided at the end of the horizontal signal line subtract and suppress the offset of the read signal in the normal read state. In addition, the kTC noise on the signal in which the FPN of the pixel portion is suppressed by the CDS circuit (first CDS circuit portion) for each column can be read as much as possible, so that the S / N degradation can be suppressed.

  Further, the CDS circuit portions 14, 24, and 26 provided at the end of the horizontal signal line need to operate at high speed. However, in an HD class multi-pixel sensor, it is basically necessary to have a plurality of readout channels. It is possible to reduce the readout speed per channel. Therefore, according to the above embodiment and Example 1, the CDS circuit portions 14 and 24 provided at the ends of the horizontal signal lines are provided even if the readout speed per channel is about 20 MHz in order to improve the performance of the CMOS sensor. 26 can be performed without any problem. As a result, according to the above-described embodiment and Example 1, it is difficult for the DDS circuit or the like to operate the second stage CDS circuit at high speed, and thus it is difficult to perform offset correction. The image sensor can also correct the offset, and as a result, the vertical stripe FPN generated for each column can be suppressed, the image quality can be improved, and the S / N of the output signal can be improved.

  Further, according to the above embodiment and Example 1, four transistors (S2 to S5 in FIGS. 3 and 5), one current source 22, and further one buffer amplifier 21 as necessary. By adding it, it is possible to correct the offset and suppress the kTC noise, and the device area can be increased little compared to the conventional case. Further, according to the above embodiment and Example 1, the increase in device area can be made smaller than the correction by the digital circuit.

  Further, according to the embodiment shown in FIG. 5, offset correction can be realized by using a CDS circuit in the analog front end for CCD as the second stage external CDS circuit unit 26 provided outside the LSI. Therefore, it is very practical from the viewpoint of image quality when the ADC is not provided in the sensor chip.

It is a circuit diagram of the principal part of one Embodiment of the CDS circuit of the solid-state image sensor of this invention. 2 is a timing chart for explaining the operation of FIG. 1. It is a circuit diagram of one embodiment of an offset correction circuit section of the main part of the present invention. 4 is a timing chart for explaining the operation of FIG. 3. It is a circuit diagram of other embodiment of the offset correction circuit part of the principal part of this invention. It is a circuit diagram of Example 1 of the CDS circuit of the solid-state imaging device of the present invention. 7 is a timing chart for explaining the operation of FIG. 6. It is a circuit diagram of an example of the offset correction circuit previously proposed by the inventor. It is a circuit diagram of the other example of the offset correction circuit which this inventor proposed previously. 10 is a timing chart for explaining the operation of FIGS. 8 and 9. It is a block diagram of an example of a CMOS sensor. FIG. 12 is an equivalent circuit diagram of one pixel in FIG. 11.

Explanation of symbols

1a, 1b Pixel 10 CDS circuit 11, 12, 23 Operational amplifier 13, 17 Horizontal signal line 14, 24 Second CDS circuit unit 15 Offset correction circuit unit 21 Buffer amplifier 22 Current source 26 External CDS circuit unit SW1 to SW9, S1 S5 switches C1 to C5, C11 to C13 capacitors Tr1, TR20 MOS transistors constituting source followers TR1 to TR4, TR11, TR17 to TR19, TR21 MOS transistors for switching TR5 to TR10, TR12 to TR16 Constructing a folded cascode type operational amplifier MOS transistor

Claims (2)

First holding that holds, as a charge, a signal read from the pixels arranged in the column direction among the plurality of pixels of the solid-state imaging device in which a plurality of pixels each having photoelectric conversion means are regularly arranged. Means,
Second holding means for holding a pixel reset signal at the time of resetting the pixels arranged in a column direction;
Third holding means for holding the charge transferred from the second holding means;
The signal from the first pixel arranged in the column direction is held by the first holding means, and the signal read from the first pixel obtained by differential amplification using an amplifier and the first After the difference from the pixel reset signal from one pixel is held by the second holding unit, the first holding unit is set to a specific potential and is held by the second holding unit. First transfer means for transferring charge to the third holding means;
After the charge transfer by the first transfer means, the signal read from the second pixel adjacent to the first pixel in the column direction is held by the first holding means, and then the amplifier is used. The difference between the signal read from the second pixel obtained by differential amplification and the pixel reset signal from the second pixel is held by the second holding means, and then the second The first holding unit is set to a specific potential, and the electric charge held in the second holding unit is transferred to the third holding unit, and the first holding unit holds the first holding unit. Second transfer means for adding to the charge transferred by the transfer means;
Fourth holding means for holding the potential of the third holding means in which charges are added and held by charge transfer by the second transfer means;
First switch means for transferring the potential held in the fourth holding means;
Fifth holding means for holding the potential transferred through the first switch and held in the fourth holding means;
Reset means for resetting the fifth holding means to a predetermined potential before the fifth holding means holds the potential held by the fourth holding means;
A correction circuit unit that is provided at the end of the horizontal signal line and performs a subtraction operation of the input signal;
The holding potential of the fifth holding unit is output to the horizontal signal line during a period from the start of resetting the fifth holding unit by the reset unit to the holding of the potential held by the fourth holding unit. And a second switch unit for supplying the correction circuit unit as the input signal.   The first to fifth holding means, the first and second transfer means, the first and second switch means, and the reset means are provided in the same integrated circuit, and 2. The CDS circuit for a solid-state imaging device according to claim 1, wherein the correction circuit unit is provided outside the integrated circuit.

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