JP2010021172A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device having an electrode conductor film. <P>SOLUTION: A contact hole CH is formed in an interlayer dielectric IL of a silicon substrate 1 where an n-type MIS transistor Qn is formed (steps s03 to s07), and the electrode conductor film E1 is formed filling the contact hole (steps s11 to s14). The electrode conductor film E1 is deposited in twice as a first conductor film E1a of 1 to 3 μm and a second conductor film E1b of 1 to 3 μm (steps s12 and s14), wherein a silicon substrate 1 is made to temporarily stand-by (step s13) during the steps of depositing them, and the first conductor film E1a is deposited at a faster deposition speed than the second conductor film E1b. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a method for forming an electrode conductor film.

  As a semiconductor device, one of semiconductor elements (semiconductor devices) formed on a semiconductor substrate is a power device. The power device is an element for handling a high voltage and a large current. For example, a field effect transistor (hereinafter simply referred to as a MIS transistor) having a MIS (Metal Insulator Semiconductor) structure has a high breakdown voltage specification. The power MIS transistor includes a planar type having a structure in which a channel is formed along a substrate surface and a trench type having a structure in which a channel is formed along a direction intersecting the substrate surface. 2. Description of the Related Art In recent years, demands for trench type power MIS transistors having a structure suitable for miniaturization have increased due to technological trends of high performance due to miniaturization and high integration of semiconductor elements.

  As described above, the electrode conductor film of a power MIS transistor that handles high voltage and large current has a wiring width wider than that of other semiconductor elements and has a structure that also serves as an electrode pad. Various connection methods for electrically connecting to the power MIS transistor from the outside are conceivable. For this reason, the electrode conductor film of the power MIS transistor has a relatively thick structure of, for example, 3 to 6 μm so as to withstand the connection.

  Further, the connection hole (contact hole) for connecting the electrode conductor film to the terminal of the power MIS transistor is not a hole shape but a slit shape (groove shape, line and space shape) in plan view. There is something. That is, in the electrode conductor film of the power MIS transistor, it is necessary to normally embed the conductor film in the slit-like connection hole. The process of embedding a conductor film in the connection hole so as not to generate voids and to have a flat surface requires more advanced technology as the element is miniaturized.

  For example, in JP-A-10-64902 (Patent Document 1), in order to embed aluminum in a hole-shaped contact hole having a high aspect ratio, a thin wettability improving film is formed, and then aluminum is divided into two layers. A forming technique is disclosed.

  Further, for example, in Japanese Patent Laid-Open No. 10-125778 (Patent Document 2), a base thin film having high wettability is formed in a connection hole, and a seed wiring layer made of an aluminum-based material is formed thereon by high-temperature sputtering. Techniques to do this are disclosed.

Further, for example, in Japanese Patent Application Laid-Open No. 2008-45219 (Patent Document 3), an aluminum base thin film is formed in a hole at a temperature of 150 ° C. or lower, and then an aluminum film is formed by sputtering at a temperature of about 300 ° C. However, a technique for producing a reflow thin film by reflowing is disclosed.
JP-A-10-64902 JP-A-10-125778 JP 2008-45219 A

  In the power MIS transistor as described above, the inventors have found that the following problems are associated with the technology for forming the electrode conductor film.

  In the power MIS transistor investigated by the present inventors, the electrode conductor film is made of aluminum (Al) by sputtering so that the connection hole is embedded in an interlayer insulating film patterned so as to have a slit-like connection hole. ) Is deposited. At that time, it is necessary to deposit an electrode conductor film having a thickness of 3 to 6 μm. Then, it was found that the semiconductor substrate is heated by radiant heat while the thick electrode conductor film is deposited by sputtering.

  Further investigation by the present inventors has revealed that heating of the semiconductor substrate when depositing a thick electrode conductor film has the following effects.

  Usually, in order to prevent the aluminum of the electrode conductor film from diffusing into the substrate or the interlayer insulating film, molybdenum silicide (MoSi), titanium (Ti), titanium tungsten (TiW), or titanium nitride (TiN) is interposed therebetween. ) Or the like is formed. That is, these barrier conductor films are formed so as to cover the inner walls of the connection holes before depositing aluminum. Thereafter, it was found that when the semiconductor substrate is heated when aluminum is deposited, the barrier conductor film and the semiconductor substrate undergo a chemical reaction and are alloyed.

  It has been found that such an alloy layer of the barrier conductor film and the semiconductor substrate is strong against dry etching of the upper aluminum layer and dry etching of the barrier conductor film itself. That is, it was found that when the alloy layer as described above is formed, etching residue of the alloy layer occurs when the electrode conductor film is patterned. Such etching residue causes one of the subsequent peeling of the electrode conductor film. The peeling off of the electrode conductor film formed as the wiring and the electrode is one factor that hinders the improvement of the reliability of the semiconductor device including the power MIS transistor.

  Further, it has been found that the above-described barrier conductor film is locally thinly formed, for example, at a step portion of the connection hole. When aluminum is deposited from above, aluminum can diffuse into the semiconductor substrate through the thin portion of the barrier conductor film. At this time, it was found that when the semiconductor substrate is heated by radiant heat, the semiconductor substrate and aluminum undergo a chemical reaction and are alloyed.

  If an alloy layer of aluminum and the semiconductor substrate is formed in an unintended region in the semiconductor substrate, a junction leak or the like due to junction breakdown may occur. Such an unexpected failure in electrical characteristics is one factor that hinders the improvement of the reliability of a semiconductor device including a power MIS transistor.

  From the above viewpoints, it has been found that it is difficult to normally form a contact structure of an electrode conductor film due to a temperature rise due to radiant heat when depositing a thick electrode conductor film, and as a result, a semiconductor device It has been found that this is one cause of lowering the reliability.

  As another phenomenon, voids may occur when the connection hole of the interlayer insulating film is filled with the electrode conductor film. Such voids contain air and moisture and cause a poor conduction in the wiring. In addition, among these, when a void that reaches the surface of the electrode conductor film is generated, the electrode conductor film is eroded by the influence of a process (such as photolithography or wet etching) to be performed on the surface of the electrode conductor film later. This causes one cause such as defective breakdown voltage.

  On the other hand, in order to fill the connection hole of the interlayer insulating film with the electrode conductor film without generating voids, it has been found that a method of depositing the electrode conductor film while reflowing at a certain high temperature is suitable. However, from the viewpoint of heating the semiconductor substrate during the step of depositing the electrode conductor film, as described above, there is a problem that leads to a decrease in reliability due to the barrier conductor film or the alloying of aluminum and the semiconductor substrate. Has been found. Further, from the viewpoint of the allowable amount of leakage current of the actually formed power MIS transistor, the temperature rise of the semiconductor substrate in each process is limited.

  As described above, further investigation by the present inventors reveals that the temperature rise of the semiconductor substrate for eliminating voids is in a trade-off relationship with the request to avoid the formation of an unintended alloy layer. became. As described above, formation of a parasitic alloy layer and generation of a void cause peeling of the electrode conductor film, causing one cause such as junction leakage, poor conduction, or poor breakdown voltage. As a result, it has been found that it is difficult to improve the reliability of the semiconductor device by the electrode conductor film forming method studied by the present inventors.

  Accordingly, an object of the present invention is to provide a technique for improving the reliability of a semiconductor device having an electrode conductor film.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  In the present application, a plurality of inventions are disclosed. An outline of one embodiment of the inventions will be briefly described as follows.

  A semiconductor element is formed on the main surface of the semiconductor substrate, an interlayer insulating film is formed so as to cover it, a connection hole reaching the main surface of the semiconductor substrate is formed in the interlayer insulating film, and the connection hole is formed by an electrode conductor film. A method of manufacturing a semiconductor device including a step of embedding, wherein in the step of embedding a connection hole with an electrode conductor film, a first conductor film of 1 to 3 μm that is a conductor film mainly composed of aluminum and a second conductor of 1 to 3 μm. The electrode conductor film is deposited separately from the conductor film. In particular, the temporary semiconductor substrate is put on standby during the process of depositing each, and the first conductor film is deposited at a higher deposition rate than the second conductor film. To do.

  Of the plurality of inventions disclosed in the present application, effects obtained by the above-described embodiment will be briefly described as follows.

  That is, the reliability of a semiconductor device having an electrode conductor film can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
The method for manufacturing the semiconductor device according to the first embodiment will be described in detail with reference to the drawings.

  FIG. 1 is an explanatory diagram for illustrating a planar structure and a cross-sectional structure of a power MIS transistor formed by the method of manufacturing a semiconductor device according to the first embodiment. In the plan view, hatching is given for convenience. Further, in the plan view, for convenience, only the interlayer insulating film IL and the silicon substrate 1 are shown, and descriptions of other components are omitted.

  The semiconductor device according to the first embodiment has the following configuration. First, it has an n-channel type MIS transistor (semiconductor element) Qn (hereinafter referred to as an n-type MIS transistor Qn) formed on a silicon substrate (semiconductor substrate) 1. Second, it has an electrode conductor film E1 that is electrically connected to the n-type MIS transistor. Third, it has an interlayer insulating film IL formed to insulate the main part of the n-type MIS transistor Qn from the electrode conductor film E1. Each detailed structure is demonstrated below.

  The n-type MIS transistor Qn includes the following elements arranged in the n-type element region nw formed on the main surface f1 of the n-type silicon substrate 1. In the n-type element region nw, a gate electrode GE is formed that is disposed in a groove shape in the depth direction from the main surface f1 of the silicon substrate 1. The gate electrode GE and the n-type element region nw are insulated by the gate insulating film GI. A p-type well region pw is formed in the n-type element region nw between the trench-shaped gate electrodes GE so as to be in contact with the gate insulating film GI. An n-type source region ns is formed on the main surface f1 of the silicon substrate 1, which is the surface of the p-type well region pw. A p-type contact region pc is formed in the p-type well region pw.

  The n-type element region nw has an n-type impurity concentration lower than that of the n-type silicon substrate 1. The n-type source region ns has a higher n-type impurity concentration than the n-type element region nw. The p-type contact region pc has a higher p-type impurity concentration than the p-type well region pw.

  Of the above configuration, the n-type source region ns constitutes the source terminal of the n-type MIS transistor Qn, and the n-type element region nw constitutes the drain terminal of the n-type MIS transistor Qn. Then, in the p-type well region pw in the region in contact with the gate insulating film GI, a channel region corresponding to the electric field effect due to voltage application to the gate electrode GE is formed.

  In addition, mainly to apply a voltage to the n-type source region ns, an electrode conductor film E1 is formed. The electrode conductor film E1 is integrally formed on the main surface f1 of the silicon substrate 1 so as to be electrically connected to the n-type source region ns and the p-type contact region pc. A barrier conductor film BE is formed as a base of the electrode conductor film E1 so that the electrode conductor film E1 does not diffuse into the structure of the silicon substrate 1 or the n-type MIS transistor Qn. A voltage can be applied to the n-type source region ns through such an electrode conductor film E1. Similarly, a voltage can be applied to the p-type well region pw through the electrode conductor film E1 and the p-type contact region pc.

  The electrode conductor film E1 is a conductor film mainly containing aluminum and containing about 1% of silicon (Si), copper (Cu), or both. In the first embodiment, an aluminum film containing about 1% silicon is used. Hereinafter, unless otherwise specified, aluminum and Al indicate aluminum containing about 1% silicon. The barrier conductor film BE is a conductor film made of titanium, titanium tungsten, titanium nitride, or a laminated film thereof.

  As described above, the electrode conductor film E1 is a component for applying a voltage to the n-type source region ns and the p-type contact region pc, and needs to be insulated from the gate electrode GE. Therefore, an interlayer insulating film IL is formed on the main surface f1 of the silicon substrate 1 so as to cover the gate electrode GE. A contact hole (connection hole) CH is formed in the interlayer insulating film IL so as to expose the n-type source region ns and the p-type contact region pc of the main surface f1 of the silicon substrate 1. Then, by forming the electrode conductor film E1 so as to fill the contact hole CH, a voltage can be applied to the n-type source region ns through the electrode conductor film E1. Similarly, a voltage can be applied to the p-type well region pw through the electrode conductor film E1 and the p-type contact region pc.

  The contact hole CH is not a hole shape in a plan view but a so-called slit shape in which grooves extending in a specific direction are arranged at equal intervals. Such a shape is also referred to as a line and space shape.

  The contact hole CH has a first hole h1 formed in the interlayer insulating film IL to expose the n-type source region ns and a main surface f1 of the silicon substrate 1 to expose the p-type contact region pc. The second hole h2 is further recessed. The configuration of the contact hole CH will be described in more detail in the description of the manufacturing method later.

  The n-type MIS transistor Qn having the above configuration can be applied as a power MIS transistor. Hereinafter, a method for manufacturing the semiconductor device of the first embodiment having the n-type MIS transistor Qn will be described in detail.

  First, a semiconductor manufacturing apparatus used in the manufacturing method of the first embodiment will be described in detail with reference to FIGS.

  FIG. 2 is an overall top view of the semiconductor manufacturing apparatus 2 (cluster apparatus) used in the manufacturing method of the first embodiment. The semiconductor manufacturing apparatus 2 includes a sputtering apparatus (Mo-based sputtering chamber 3, Al-based sputtering chamber 4, Ti-based sputtering chamber 5), a heat treatment apparatus (heat treatment chamber 6), and an etching apparatus (dry etching chamber 7). The semiconductor manufacturing apparatus 2 has a load port 9 that accommodates a plurality of wafer cassettes 8 under normal pressure. The wafer-like silicon substrate 1 accommodated in the load port 9 is converted into a vacuum through one of the two load lock chambers 10 and supplied to the processing chambers 3 to 7 through the vacuum transfer chamber 11. The opposite is true when discharging.

  FIG. 3 is a front sectional view showing a detailed structure of the Al-based sputtering chamber 4 (or Ti-based sputtering chamber 5) in the semiconductor manufacturing apparatus 2 in particular. The silicon substrate 1 is placed on an electrostatic chuck (ESC) 13 on a wafer stage 12 with the film deposition surface facing up. An excitation electrode 14 is provided above the sputtering chambers 4 and 5, and a sputtering target 15 is installed on the lower surface thereof. Further, the Al-based sputtering chamber 4 is provided with a gas supply system 16, which is a mechanism capable of supplying argon (Ar) gas and other necessary gases.

  FIG. 4 is a front sectional view showing a detailed structure of the dry etching chamber 7 in the semiconductor manufacturing apparatus 2 in particular. The silicon substrate 1 is placed on the wafer stage 18 on the lower electrode 17 with the surface to be etched facing up. A radio frequency (RF) power source 19 is connected to the lower electrode 17. On the other hand, an upper electrode 20 is provided above the dry etching chamber 7. Further, the dry etching chamber 7 is provided with a gas supply system 16 similar to the above.

  FIG. 5 is a flowchart showing the method for manufacturing the semiconductor device of the first embodiment. The manufacturing method of the first embodiment will be described below with reference to the flow of FIG. 5 and the manufacturing apparatus of FIGS. 6 and subsequent drawings show cross-sectional views of main parts during the manufacturing process of the semiconductor device of the first embodiment.

  As shown in FIG. 6, an n-type MIS transistor (semiconductor element) Qn is formed on a silicon substrate (semiconductor substrate) 1 (step s01 in FIG. 5). Below, the process is demonstrated more concretely.

  The silicon substrate 1 is a planar thin plate (called a wafer) made of high-purity single crystal silicon as a base material, and includes a substrate containing a high concentration of n-type impurities so as to have a sufficiently low resistance. . The n-type impurity is a group V phosphorus (P), arsenic (As), or the like that serves as a donor in group IV silicon (the same applies hereinafter). An n-type element region nw having a thickness of about several μm is formed on the silicon substrate 1. The n-type element region nw is a semiconductor region made of single crystal silicon containing an n-type impurity, and is formed by, for example, epitaxial growth. The n-type impurity concentration of the n-type element region nw is lower than the n-type impurity concentration of the silicon substrate 1. In some cases, the substrate material includes the n-type element region nw on the silicon substrate 1. In the following description, the surface of the n-type element region nw on the silicon substrate 1 is described as the main surface f1 of the silicon substrate 1.

  Subsequently, a trench (groove) tr extending in the thickness direction from the main surface f1 of the silicon substrate 1 is formed by a photolithography method, a dry etching method, or the like. Thereafter, a gate insulating film GI is formed on the inner surface of the trench tr. For this purpose, for example, the main surface f1 of the silicon substrate 1 including the inner surface of the trench tr is thermally oxidized to form the gate insulating film GI made of an insulating film mainly composed of silicon oxide. Subsequently, a gate electrode GE is formed so as to cover the gate insulating film GI and fill the trench tr. For this purpose, for example, polycrystalline silicon (polysilicon) is formed on the main surface f1 of the silicon substrate 1 including the inside of the trench tr by a chemical vapor deposition (CVD) method. Thereafter, the unnecessary portion of the polycrystalline silicon film is removed by a photolithography method, a dry etching method, or the like, thereby forming the gate electrode GE.

  Thereafter, a p-type well region pw is formed in a region sandwiched between the gate structures (trench tr, gate insulating film GI, and gate electrode GE) formed above in the main surface f1 of the silicon substrate 1. For this purpose, for example, a p-type well region pw is formed by ion-implanting a p-type impurity into the main surface f1 of the silicon substrate 1 and then performing heat treatment (annealing) for activation and diffusion. . The p-type impurity is, for example, group III boron (B) serving as an acceptor in group IV silicon (the same applies hereinafter). Here, the p-type well region pw is adjusted so that the depth from the main surface f1 does not become deeper than the trench tr.

  Subsequently, an n-type source region ns is formed in the main surface f1 of the silicon substrate 1 in the vicinity of the surface of the p-type well region pw. For this purpose, for example, an n-type impurity region is ion-implanted into the main surface f1 of the silicon substrate 1, and then heat treatment for activation and diffusion is performed to form the n-type source region ns. Here, the n-type impurity concentration of the n-type source region ns is formed to be higher than the n-type impurity concentration of the n-type element region nw. If the conditions of the heat treatment step for activating and diffusing the implanted impurities are the same in the step of forming the p-type well region pw and the main step of forming the n-type source region ns, both May be shared. Thereby, a process can be simplified.

  Through the above process, the gate structure including the trench tr, the gate insulating film GI and the gate electrode GE, the n-type source region ns serving as the source terminal, the n-type element region nw serving as the drain terminal, and the channel region A p-type well region pw was formed. That is, the basic configuration of the n-type MIS transistor Qn is formed on the main surface f1 of the silicon substrate 1 by this process.

  Next, as shown in FIG. 7, an interlayer insulating film IL is formed on the main surface f1 of the silicon substrate 1 so as to cover the gate electrode GE of the n-type MIS transistor Qn (step s02 in FIG. 5). For this purpose, an interlayer insulating film IL made of an insulating film mainly composed of silicon oxide is formed by, eg, CVD. Further, for example, a two-layered silicon oxide film in which SOG (spin on glass) of about 100 nm is formed on a CVD-PSG (phospho silicate glass) film of about 600 nm may be used as the interlayer insulating film IL.

  In subsequent steps, contact holes (connection holes) CH as shown in FIG. 1 are formed in the interlayer insulating film IL (steps s03 to s07 in FIG. 5). That is, a contact hole CH is formed through the interlayer insulating film IL so as to reach the main surface of the silicon substrate 1 on which the n-type MIS transistor Qn is formed. Below, the process is demonstrated in detail.

  First, as shown in FIG. 8, a photoresist film 21 is formed on the interlayer insulating film IL. The photoresist film 21 has an opening pattern that exposes a portion of the interlayer insulating film IL to be removed by etching in a later step. This is formed by patterning the photoresist film 21 coated on the entire surface by a photolithography method or the like.

  Next, as shown in FIG. 9, by performing anisotropic dry etching on the interlayer insulating film IL using the photoresist film 21 as an etching mask, a portion of the interlayer insulating film exposed to the opening of the photoresist film 21 is formed. Remove IL. In this manner, a first hole h1 that penetrates to the main surface f1 of the silicon substrate 1 and has substantially the same planar pattern as the opening of the photoresist film 21 is formed in the interlayer insulating film IL (FIG. 5). Step s03). By this step, the first hole h1 is formed in a part of the interlayer insulating film IL so that the main surface f1 of the silicon substrate 1 (particularly a part of the n-type source region ns) which is a part of the n-type MIS transistor Qn is exposed. Form. Thereafter, the photoresist film 21 is removed.

  Next, as shown in FIG. 10, by performing anisotropic dry etching on the silicon substrate 1 using the interlayer insulating film IL as an etching mask, a portion of the silicon exposed in the first hole h1 of the interlayer insulating film IL. The substrate 1 is removed. In this way, the portion of the main surface f1 of the silicon substrate 1 exposed in the first hole h1 of the interlayer insulating film IL is shaved to form a second hole h2 lower than the main surface f1 of the other portion ( Step s04 in FIG. As described above, the second hole h2 of the main surface f1 of the silicon substrate 1 is formed by anisotropic etching using the interlayer insulating film IL as an etching mask. Therefore, the second hole h2 of the silicon substrate 1 is formed so that the planar contour shape thereof overlaps with the first hole h1 of the interlayer insulating film IL. Furthermore, in this step, the depth of the second hole h2 from the main surface f1 of the silicon substrate 1 is deeper than that of the n-type source region ns, and the bottom is positioned in the p-type well region pw. .

  Through the above steps, the basic configuration of the contact hole CH having the first hole h1 and the second hole h2 is formed. On the other hand, the shape of the contact hole CH is changed by performing the subsequent steps described in detail below. Finally, the contact hole CH of the first embodiment is completed at the stage where the step s07 in FIG. 5 is completed. To do.

  In the subsequent process, a p-type contact region pc is formed in a region near the bottom surface of the second hole h2 of the silicon substrate 1 in the p-type well region pw. For this purpose, a p-type contact region pc, which is a p-type semiconductor region, is formed by ion-implanting a p-type impurity into the silicon substrate 1 using the interlayer insulating film IL as an ion implantation mask and performing heat treatment.

  Since the p-type well region pw to be ion-implanted is already a p-type semiconductor region, the p-type contact region pc formed by further introducing p-type impurities becomes a region having a higher p-type impurity concentration. . That is, the p-type contact region pc has a lower resistance value than the p-type well region. The p-type contact region pc having a low resistance is formed in order to realize ohmic connection between the electrode conductor film E1 (see FIG. 1) and the p-type well region pw.

Subsequently, the process proceeds to the step of forming the electrode conductor film E1 so as to fill the contact hole. Here, a natural oxide film is formed on the surface of the silicon substrate 1 subjected to the above-described various processes such as dry etching and ion implantation. Such a natural oxide film has a high resistance value and needs to be removed before forming the electrode conductor film E1. Therefore, in the manufacturing method of the first embodiment, the surface oxide film on the silicon substrate 1 is removed (referred to as pre-sputtering cleaning) (step s05 in FIG. 5). Here, the silicon substrate 1 is mixed with a mixed liquid (buffered hydrofluoric acid, for example, a weight ratio of 1:20) of hydrofluoric acid (hydrofluoric acid, HF) and ammonium fluoride (NH ₄ F) that serves as an etchant for the silicon oxide film. Isotropic wet etching is performed on the silicon substrate 1. Thereby, the silicon substrate 1 is cleaned.

  At this time, as shown in FIG. 11, the interlayer insulating film IL made of a silicon oxide film is also subjected to the wet etching and isotropically removed according to the etching time. That is, by the isotropic wet etching in this process, the planar outline of the first hole h1 of the interlayer insulating film IL is larger than the planar outline of the second hole h2 of the silicon substrate 1. fall back. As an example, isotropic wet etching is performed on the interlayer insulating film IL so as to retreat about 80 nm from the contour of the first hole h1 to the contour of the second hole h2.

  Here, since the outline of the first hole h1 of the interlayer insulating film IL has receded from the outline of the second hole h2 of the silicon substrate 1, it is the main surface f1 of the silicon substrate 1, and the surface of the n-type source region ns is Some are exposed. In other words, at the stage where this step is performed, the n-type source region ns has a part of the surface exposed in addition to the side wall portion of the second hole h2. This exposed portion later becomes a connection portion with the electrode conductor film E1. That is, the surface area of the n-type source region ns in contact with the electrode conductor film E1 is further increased, which is a more preferable structure for the n-type MIS transistor Qn as a power device that handles a large current.

  In FIG. 5, the pre-sputtering cleaning step s05 is shown as a part of the contact hole CH forming step, but the pre-sputtering cleaning step s05 itself removes the natural oxide film formed on the surface of the silicon substrate 1. The purpose is that. However, as described with reference to FIG. 11, the contour shape of the first hole h1 constituting the contact hole CH is determined by the pre-sputtering cleaning step s05. Accordingly, FIG. 5 shows that the pre-sputtering cleaning step s05 is part of the contact hole CH forming step.

  After performing the pre-sputtering cleaning step (step s05 in FIG. 5), the silicon substrate 1 is put into the semiconductor manufacturing apparatus 2 described with reference to FIG. Hereinafter, in each element of the semiconductor manufacturing apparatus 2, reference is made to FIG. 2 to FIG. First, degassing (preheating) is performed by transferring the silicon substrate 1 to the heat treatment chamber 6 and performing heat treatment (step s06 in FIG. 5). Here, for example, the temperature is set to about 400 degrees Celsius and heated for about 50 seconds. Thereafter, the silicon substrate 1 is transferred to the dry etching chamber 7 and a sputtering etching process is performed in an argon atmosphere (step s07 in FIG. 5). More specifically, argon sputtering is performed at a high frequency power of 400 W for about 30 seconds.

  The structure formed by this process will be described in detail with reference to FIGS. 12 is a cross-sectional view of the main part similar to FIGS. 6 to 11, and FIG. 13 is an enlarged cross-sectional view showing the main part p100 of FIG. The end portion p101 of the second hole h2 of the silicon substrate 1 is processed into a tapered shape by the sputtering etching process as described above.

  Here, processing into a tapered shape means processing so that the cross-section of the silicon substrate 1 has a gentle curve when the shape of the end portion p101 of the second hole h2 of the silicon substrate 1 is viewed. That means. In other words, when viewed along the direction away from the gate electrode GE on the surface of the n-type source region ns, which is the main surface of the silicon substrate 1, the surface remains flat in the second hole h2 that is the end. Instead of reaching, it is processed into a shape that gently inclines and reaches the second hole h2. This is due to a phenomenon in which the edge of the terrace-shaped second hole h2 is preferentially shaved by utilizing the fact that the protruding portion is more susceptible to etching in argon sputtering etching.

  As described above, the contact hole (connection hole) CH having the first hole portion h1 and the second hole portion h2 is completed as in the steps of FIGS. 8 to 12 (steps s03 to s07 in FIG. 5). . In particular, in the method of manufacturing the semiconductor device according to the first embodiment, the effect of processing the end of the second hole h2 that is a component of the contact hole CH into a tapered shape as described above will be described in detail later. .

  In the subsequent process, the silicon substrate 1 is transferred to the Ti-based sputtering chamber 5. Then, as shown in FIG. 14, a barrier conductor film BE is deposited on the main surface f1 of the silicon substrate 1 so as to cover the inner wall of the contact hole CH (step s08 in FIG. 5). More specifically, in the Ti-based sputtering chamber 5, a conductor film mainly composed of titanium is deposited by sputtering to a thickness of about 10 nm, and subsequently a conductor film mainly composed of titanium nitride is deposited by about 70 nm. In addition, the barrier conductor film BE may be a conductor film mainly composed of molybdenum silicide or a conductor film mainly composed of titanium tungsten.

  As shown in FIG. 15 which is an enlarged view of the main part p200 of FIG. 14, according to the manufacturing method of the first embodiment, the barrier conductor film BE is formed so as to uniformly cover the inner wall of the contact hole CH. Can be formed. This will be described in more detail later.

  In the subsequent process, the silicon substrate 1 is taken out of the semiconductor manufacturing apparatus 2 and transferred to another heat treatment apparatus (for example, a furnace body). Therefore, for example, heat treatment is performed in a nitrogen atmosphere of normal pressure at 550 to 650 degrees Celsius for about 10 minutes (step s09 in FIG. 5). By this step, a silicidation reaction occurs at a position where the barrier conductor film BE having the titanium film formed above and the silicon substrate 1 are in contact with each other, and a metal silicide layer (in this case, a titanium silicide layer) having a lower resistance value is formed. Is done. Thereby, the resistance value of the interface between the barrier conductor film BE and the silicon substrate 1 (particularly, the n-type source region ns and the p-type contact region pc) is lowered, and the adhesion is improved.

  Subsequently, the silicon substrate 1 is put into the semiconductor manufacturing apparatus 2 again. First, degassing (preheating) is performed by transferring the silicon substrate 1 to the heat treatment chamber 6 and performing heat treatment (step s10 in FIG. 5). Here, for example, the temperature is set to about 250 degrees Celsius and heated for about 45 seconds.

  Thereafter, the silicon substrate 1 is transferred to the Al-based sputtering chamber 4. In subsequent steps, an electrode conductor film E1 (see FIG. 1 above) made of a conductor film mainly composed of aluminum is deposited in the Al-based sputtering chamber 4 by sputtering (steps s11 to s14 in FIG. 5). . Thereby, the contact hole CH on the silicon substrate 1 is filled with the electrode conductor film E1. Below, this process is demonstrated in detail.

  First, as shown in FIG. 16, a wetting film E1w is deposited so as to cover the barrier conductor film BE (step s11 in FIG. 5). That is, in this step, the wetting film E1w is formed so as to cover the inner wall of the contact hole CH via the barrier conductor film BE. For this purpose, a wetting film E1w made of a conductor film mainly composed of aluminum is deposited by sputtering in the Al-based sputtering chamber 4. More specifically, the wetting film E1w is deposited on the silicon substrate 1 under the following conditions. That is, the sputtering rate is set to 150 to 155 nm / kW and 18 to 22 nm / sec. Further, the silicon substrate 1 is not subjected to predetermined heating. The thickness of the wetting film E1w is set to be 0.1 to 0.5 μm. As an example, a wetting film E1w is deposited on the silicon substrate 1 so as to have a thickness of about 0.2 μm under the above conditions.

  The reason why the wetting film E1w is formed in this step is to improve wettability and improve embedding by forming a film of the same material in advance when an aluminum film is further deposited on the upper layer. From this point of view, by sputtering without applying predetermined heating to the silicon substrate 1, the movement of aluminum during deposition can be suppressed and the wetting film E1w can be formed uniformly. Further, when the wetting film E1w is formed in this step, the temperature rise of the silicon substrate 1 can be further suppressed by turning off the electrostatic chuck 13 of FIG.

  Next, as shown in FIG. 17, the first conductor film E1a is deposited so as to fill the contact hole CH through the barrier conductor film BE and the wetting film E1w (step s12 in FIG. 5). For this purpose, a first conductor film E1a made of a conductor film mainly composed of aluminum is deposited by sputtering in the Al-based sputtering chamber 4. More specifically, the first conductor film E1a is deposited on the silicon substrate 1 under the following conditions. That is, the sputtering rate is set to 150 to 155 nm / kW and 18 to 22 nm / sec. Further, the temperature of the silicon substrate 1 is set to 400 to 500 degrees Celsius at the actual temperature. Moreover, it sets so that the film thickness of the 1st conductor film E1a may be 1-3 micrometers. As an example, the first conductor film E1a is deposited on the silicon substrate 1 so as to have a thickness of about 1.55 μm under the above conditions.

  In the subsequent step, the silicon substrate 1 is put on standby without performing a predetermined step (step s13 in FIG. 5). During standby, the silicon substrate 1 may be left in the Al-based sputtering chamber 4 or may be transferred to the load lock chamber 10. In any case, the silicon substrate 1 is handled in a vacuum environment without being exposed to the atmosphere while the silicon substrate 1 is on standby in this step.

  Next, as shown in FIG. 18, a second conductor film E1b is deposited so as to cover the first conductor film E1a (step s14 in FIG. 5). For this purpose, a second conductor film E1b made of a conductor film mainly composed of aluminum is deposited by sputtering in the Al-based sputtering chamber 4. More specifically, the second conductor film E1b is deposited on the silicon substrate 1 under the following conditions. That is, the sputtering rate is set to 190 to 200 nm / kW and 15 to 18 nm / sec. Further, the temperature of the silicon substrate 1 is set to 400 to 500 degrees Celsius at the actual temperature. The film thickness of the second conductor film E1b is set to 1 to 3 μm. As an example, the second conductor film E1b is deposited on the silicon substrate 1 so as to have a thickness of about 1.75 μm under the above conditions.

  As described above, the electrode conductor composed of the wetting film E1w, the first conductor film E1a, and the second conductor film E1b on the silicon substrate 1 by the steps s11 to s14 of FIG. 5 described with reference to FIGS. A film E1 is deposited. That is, according to the manufacturing method of the first embodiment, the electrode conductor film E1 having a relatively large thickness of 2 to 6 μm is deposited while being divided into two layers of first and second conductor films E1a and E1b of 1 to 3 μm. Thus, the effect of depositing the thick electrode conductor film E1 in two or more steps will be described in detail later. In the above example, the electrode conductor film E1 is deposited on the silicon substrate 1 so as to have a thickness of about 3.5 μm.

  In the manufacturing method of the first embodiment, during the step of depositing the electrode conductor film E1, the steps are performed in a vacuum environment without exposing the silicon substrate 1 to the atmosphere. In the manufacturing method according to the first embodiment, as described above, the lower first conductor film E1a is deposited at a higher deposition rate than the upper second conductor film E2b. These effects will also be described in detail later.

  In subsequent steps, the electrode conductor film E1 is processed into a desired shape by photolithography and various etching methods (step s15 in FIG. 5). Then, it continues to formation of a back electrode, a cutting-out process, a packaging process, and the like.

  Here, the actions and effects brought about by the respective elements constituting the manufacturing method of the first embodiment described above will be described in detail.

  In the method of manufacturing the semiconductor device according to the first embodiment, when the contact hole CH is formed, the end of the second hole h2 of the silicon substrate 1 has a cross section as described with reference to FIGS. It is processed so as to have a curved taper shape. Below, the effect is demonstrated.

  For example, the present inventors have studied a method in which the subsequent process is performed in a state where the end of the second hole h2 of the silicon substrate 1 is not processed into a tapered shape without performing the sputtering etching in the process s07 in FIG. FIG. 19 shows a cross-sectional view in the process of forming the barrier conductor film BE without processing the end of the second hole h2 into a tapered shape. FIG. 20 is an enlarged view of the main part p300 in the vicinity of the contact hole CH in the same process.

  If the end portion of the second hole h2 is not tapered and has a stepped portion having a linear cross section, the barrier conductor film BE is formed in a bowl shape at the end portion p301 (over). hang). When the barrier conductor film BE starts to be formed in a bowl shape in this way, the barrier conductor film BE is hardly formed under the bowl, and as a result, a portion where the barrier conductor film BE is locally thin is formed. That is, the coverage of the barrier conductor film BE with respect to the inner wall of the contact hole CH is lowered.

  In the thin portion of the barrier conductor film BE, the material of the electrode conductor film E1 deposited later may cause an electrical characteristic modulation or the like due to the silicon substrate 1 entering. This is a cause of reducing the reliability of the manufactured semiconductor device. In addition, when the electrode conductor film E1 material enters the n-type source region ns of the silicon substrate 1 and is heated according to the process, alloying of both occurs (generation of alloy pits). Thus, when an alloy layer having a low resistance value is formed, it causes a decrease in reliability of the semiconductor device, such as an increase in junction leakage.

  On the other hand, in the manufacturing method of the semiconductor device according to the first embodiment, the end of the second hole h2 is processed into a taper shape having a curved cross section. Thereby, when the barrier conductor film BE is formed in the steps of FIGS. 14 and 15, overhang can be made difficult to occur (end portion p <b> 201 in FIG. 15). Therefore, it is possible to make a structure in which it is easy to avoid modulation of electrical characteristics due to penetration of the electrode conductor film E1 formed later into the silicon substrate 1 and increase in junction leakage due to alloying. As a result, the reliability of the semiconductor device having the electrode conductor film can be improved.

  Further, in the method of manufacturing the semiconductor device of the first embodiment, when the electrode conductor film E1 is deposited, as described with reference to FIGS. 17 and 18, the first conductor film E1a and the second conductor film E1b. The electrode conductor film E1 is deposited in two layers. Below, the effect is demonstrated.

  When a relatively thick electrode conductor film E1 of 2 to 6 μm is deposited on the silicon substrate 1 by sputtering, as described above, the contact structure of the electrode conductor film E1 is normally formed by the temperature rise by radiant heat during the deposition. Has been found to be difficult. On the other hand, according to the manufacturing method of the semiconductor device of the first embodiment, the electrode conductor film E1 is deposited in two layers, and there is a step of temporarily waiting between the steps of depositing each layer. The temperature rise due to simple deposition can be suppressed. As a result, the etching residue of the alloy layer between the barrier conductor film BE and the silicon substrate 1 and the alloying between the electrode conductor film E1 material and the silicon substrate 1 hardly occur. As a result, the reliability of the semiconductor device having the electrode conductor film can be further improved.

  Further, in the manufacturing method of the first embodiment, in the step of forming the electrode conductor film E1, the lower first conductor film E1a is deposited at a higher deposition rate than the upper second conductor film E2b. In particular, a method of depositing the first conductor film E1a at 18 to 22 nm / sec and depositing the second conductor film E1b at 15 to 18 nm / sec was shown. In this way, by depositing the lower-layer first conductor film E1a at a higher deposition rate, the burying property with respect to the contact hole CH can be improved. Further, by depositing the upper second conductive film E1b at a slower deposition rate, the reflow property is improved, and the electrode conductive film E1 can be deposited so that the surface becomes flatter. Due to these effects, it is possible to reduce the generation of voids that cause the erosion of the electrode conductor film E1 itself and the deterioration of electrical characteristics in the subsequent steps. As a result, the reliability of the semiconductor device having the electrode conductor film can be further improved. In particular, since an element of the method that brings about the above effect is a method of controlling the deposition rate of the first conductor film E1, generation of voids can be reduced without requiring excessive heating of the silicon substrate 1. That is, it is a method capable of obtaining an effect while eliminating the trade-off relationship between the above-mentioned temperature rise of the semiconductor substrate for eliminating voids and the desire to avoid the formation of an unintended alloy layer. .

  Further, in the method of manufacturing the semiconductor device according to the first embodiment, the vacuum environment can be obtained without exposing the silicon substrate 1 to the atmosphere including the standby step (step s13 in FIG. 5) during the step of forming the electrode conductor film E1. Handle below. Thereby, the production | generation of the oxide film in the middle of completing the electrode conductor film E1 can be suppressed. For example, since the silicon substrate 1 is not exposed to the atmosphere after the first conductor film E1a is deposited and then the second conductor film E1b is deposited, generation of an oxide film on the surface of the first conductor film E1a can be suppressed. In the n-type MIS transistor Qn as a high-current, high-voltage power device, the generation of an oxide film having a high resistance value in the electrode conductor film E1 reduces the current driving capability and the reliability of the semiconductor device. It becomes one cause. From this point of view, according to the manufacturing method of the semiconductor device of the first embodiment, it is possible to form the electrode conductor film E1 that is difficult to generate an oxide film, and as a result, the reliability of the semiconductor device having the electrode conductor film is improved. It can be improved further.

  Further, for example, when the first conductor film E1a and the second conductor film E1b are formed on the silicon substrate 1 under different heating conditions, extra time is required for the temperature increase and decrease. In order to omit the time, a method of introducing a different chamber can be considered. On the other hand, according to the manufacturing method of the first embodiment, the first conductor film E1a and the second conductor film E1b are deposited under the same heating condition of the silicon substrate 1, so that it takes time to raise and lower the temperature. In addition, the deposition can be performed in the same Al-based sputtering chamber 4. Thereby, the manufacturing apparatus of the semiconductor device which has an electrode conductor film can be reduced in size. In addition, the productivity of a semiconductor device having an electrode conductor film can be improved.

  Further, in the method of manufacturing the semiconductor device of the first embodiment, the wetting film E1w is formed in the lowermost layer as the conductor film constituting the electrode conductor film E1. As described above, the manufacturing method for reducing voids generated in the electrode conductor film E1 without depending on the temperature raising step may be a manufacturing method including the step of depositing the electrode conductor film E1 in two layers as an element. It is effective enough. On the other hand, as a manufacturing method of the semiconductor device of the first embodiment, it is more preferable to form the wetting film E1w as the lowermost layer of the electrode conductor film E1. The reason is as follows. That is, the formation of the wetting film E1w in the lower layer has the effect of improving the wettability when the first conductor film E1a made of the same material (aluminum) is deposited in the upper layer and improving the embedding property. Thereby, when embedding the electrode conductor film E1 in the contact hole CH, it is possible to make a void less likely to occur. As a result, the reliability of the semiconductor device having the electrode conductor film can be further improved.

  Further, from this same viewpoint, the movement of aluminum during deposition can be suppressed by sputtering the silicon substrate 1 without performing predetermined heating. Further, when the wetting film E1w is formed in this step, the temperature rise of the silicon substrate 1 can be further suppressed by turning off the electrostatic chuck 13 of FIG. By doing so, a more uniform wetting film E1w can be formed. Thereby, when embedding the electrode conductor film E1 in the contact hole CH, it is possible to make a void less likely to occur. As a result, the reliability of the semiconductor device having the electrode conductor film can be further improved.

(Embodiment 2)
A method for manufacturing the semiconductor device according to the second embodiment will be described in detail. In the second embodiment, the same processes as those of the semiconductor device manufacturing method of the first embodiment are performed except for the manufacturing processes described below. That is, a process is performed based on the flow described with reference to FIG. 5 using the semiconductor manufacturing apparatus 2 described with reference to FIGS. First, the n-type MIS transistor Qn, the interlayer insulating film IL, the contact hole CH, and the barrier conductor film BE are formed on the silicon substrate 1 in the same manner as described with reference to FIGS.

  In the subsequent process, the electrode conductor film E1 is deposited so as to fill the contact hole CH through the barrier conductor film BE. Hereinafter, a plurality of kinds of deposition methods will be described with respect to the deposition method of the electrode conductor film E1.

  As the first deposition method of the electrode conductor film E1, there is the deposition method described in the process of the first embodiment. Here, first, a thin wetting film E1w is deposited, and a first conductor film E1a is deposited thereon under sputtering conditions with a relatively high deposition rate, and then the temporary silicon substrate 1 is put on standby, followed by a deposition rate. The second conductor film E1b was deposited under relatively slow sputtering conditions. The temperature of the silicon substrate 1 when depositing the first conductor film E1a and the second conductor film E1b was set such that the actual temperature was 400 to 500 degrees Celsius. The effect of forming the electrode conductor film E1 in this manner is as described in the first embodiment.

  In the method of manufacturing the semiconductor device according to the second embodiment, the following points regarding the second and third deposition methods of the electrode conductor film E1 are the same as those of the first deposition method. That is, the first conductor film E1a in the first layer is deposited under conditions that provide a deposition rate faster than the deposition rate of the second conductor film E1b in the second layer. Therefore, the sputtering rate conditions for depositing the first and second conductor films E1a and E1b are the same as described above. Accordingly, the same effect can be obtained with respect to the effect obtained by depositing the first and second conductor films E1a and E1b at such a deposition rate.

  A second deposition method of the electrode conductor film E1 will be described as a step subsequent to the steps described with reference to FIGS. In the second deposition method of the electrode conductor film E1, the same processes as those described in FIGS. 16 to 18 are performed except for the following points. In the second deposition method of the electrode conductor film E1, the first and second conductor films E1a and E1b are deposited by heating under the condition that the temperature of the silicon substrate 1 is 280 to 320 degrees Celsius at the actual temperature. (Step s12 and step s14 in FIG. 5). That is, in the second deposition method of the electrode conductor film E1, the temperature of the silicon substrate 1 is set lower than that in the first deposition method, and the first and second conductor films E1a and E1b are formed. accumulate. As an example, the film thicknesses of the first and second conductor films E1a and E1b are each about 2.75 μm, and the electrode conductor film E1 is deposited so as to have a film thickness of about 5.5 μm.

  Thus, by depositing the first and second conductor films E1a and E1b with the temperature of the silicon substrate 1 set low, the first conductor film E1a in the first layer can be deposited more evenly. If the lower first conductor film E1a can be deposited more evenly, the upper second conductor film E1b can also be deposited more evenly. The flatness of the laminated conductor film is effective for improving the stability of device characteristics and for improving the adhesion of a passivation film deposited on the upper layer. As a result, the reliability of the semiconductor device having the electrode conductor film can be further improved.

  Further, in the second deposition method of the electrode conductor film E1, the heating conditions of the silicon substrate 1 are different from those in the first deposition method, but the first conductor film E1a and the second conductor film E1b are made of the same silicon. The same is true in that deposition is performed under the heating condition of the substrate 1. The effect of depositing the first conductor film E1a and the second conductor film E1b under the heating condition of the same silicon substrate 1 is the same as described in the first embodiment.

  In addition, the second deposition method of the electrode conductor film E1 is sufficiently effective as described above, but it is more preferable to perform heat treatment (post heat) after depositing the second conductor film E1b. More specifically, after performing step s14 for depositing the second conductor film E1b, the silicon substrate 1 is transferred to the heat treatment chamber 6 and heat treatment is performed under conditions such that the silicon substrate 1 is at 350 to 400 degrees Celsius. As a result, the deposited electrode conductor film E1 can be reflowed and the embedding property can be improved. Therefore, the electrode conductor film E1 with fewer voids can be deposited also in the second deposition method in which the deposition temperature is generally lower than that in the first deposition method of the electrode conductor film E1. As a result, the reliability of the semiconductor device having the electrode conductor film can be further improved.

  In the post-heating process, the heating conditions for the silicon substrate 1 are different from those at the time of depositing the first and second conductor films E1a and E1b. However, since the post-heating process is performed in a heat treatment chamber 6 different from the Al sputtering chamber 4 in which the first and second conductor films E1a and E1b are deposited, it does not hinder improvement in throughput.

  A third deposition method of the electrode conductor film E1 will be described as a step subsequent to the steps described with reference to FIGS. In the third deposition method of the electrode conductor film E1, the same processes as those described in FIGS. 16 to 18 are performed except for the following points. In the third deposition method of the electrode conductor film E1, first, the first conductor film E1a is deposited by heating the silicon substrate 1 under conditions such that the actual temperature is 280 to 320 degrees Celsius (FIG. 5). Step s12). Thereafter, the silicon substrate 1 is temporarily held (step s13 in FIG. 5). Subsequently, the second conductor film E1b is deposited by heating the silicon substrate 1 under conditions such that the actual temperature is 400 to 500 degrees Celsius (step s13 in FIG. 5). That is, in the third deposition method of the electrode conductor film E1, the temperature of the silicon substrate 1 is changed between the first conductor film E1a and the second conductor film E1b, and the respective layers are deposited. Different compared to the deposition method.

  In particular, setting the temperature of the silicon substrate 1 when depositing the first conductor film E1a to be low compared to setting the temperature of the silicon substrate 1 when depositing the second conductor film E1b to be high is that It has the following effects. As described above, in the first conductor film E1a filling the contact hole CH, the growth rate is increased to improve the filling property, and the temperature of the silicon substrate 1 during deposition is lowered to improve the flatness. Is preferred. On the other hand, in the second conductor film E1b as the upper layer, it is preferable to improve the reflow property by slowing the growth rate, and improve the embedding property by increasing the temperature of the silicon substrate 1 during deposition.

  From these viewpoints, according to the third deposition method of the electrode conductor film E1, a deposition method satisfying the above-described preferable conditions can be obtained. That is, in the electrode conductor film E1 deposition method, it is possible to further improve the burying property of the contact hole CH and further improve the flatness. As a result, it is possible to form a flatter electrode conductor film E1 with less generation of voids. As a result, the reliability of the semiconductor device having the electrode conductor film can be further improved.

  Further, in the third deposition method of the electrode conductor film E1 in which the heating conditions of the silicon substrate 1 during deposition are changed as described above, the first conductor film E1a and the first conductor film E1a are formed in different sputtering chambers (processing chambers). It is more preferable to deposit the two-conductor film E1b. Thereby, even when the heating conditions of the silicon substrate 1 are changed between the first conductor film E1a and the second conductor film E1b, it is possible to realize a method for manufacturing a semiconductor device that brings about the above-described effect without reducing the throughput. As a result, productivity can be further improved in a method for manufacturing a highly reliable semiconductor device having an electrode conductor film.

  In the method for manufacturing the semiconductor device according to the first embodiment or the second embodiment, the planar shape of the contact hole CH formed in the interlayer insulating film IL is a slit shape (also referred to as a groove shape or a line and space shape). Explained the case. On the other hand, the manufacturing method described above is similarly effective even if the planar shape of the contact hole CH is applied to a hole shape. On the other hand, when the contact hole CH whose planar shape is a slit shape is embedded with the electrode conductor film E1 having a relatively large thickness of 2 to 6 μm as described above, the above problem becomes more conspicuous as the aspect ratio increases with miniaturization. easy. Therefore, the semiconductor device manufacturing method of the first embodiment or the second embodiment is more effective when applied to the step of filling the contact hole CH having a slit shape with the thick electrode conductor film E1. As a result, the reliability of the semiconductor device having the electrode conductor film can be further improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the manufacturing method of the semiconductor device of the first and second embodiments, the manufacturing method of the semiconductor device having the n-type MIS transistor has been described. However, the p-type MIS transistor is obtained by reversing the polarities of all the semiconductor regions. It is applicable to a method for manufacturing a semiconductor device having The semiconductor device manufacturing methods of the first and second embodiments are also effective when applied to a method of manufacturing a semiconductor device having a p-type MIS transistor.

  INDUSTRIAL APPLICABILITY The present invention can be applied to, for example, the semiconductor industry necessary for performing power control and power supply control in various industrial equipment and electrical appliances.

BRIEF DESCRIPTION OF THE DRAWINGS It is explanatory drawing of the structure formed by the manufacturing method of the semiconductor device which is Embodiment 1 of this invention, the upper part is a principal part top view, and the lower part is principal part sectional drawing. It is explanatory drawing of the semiconductor manufacturing apparatus used with the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. It is another explanatory drawing of the semiconductor manufacturing apparatus used with the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. It is another explanatory drawing of the semiconductor manufacturing apparatus used with the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. It is a flowchart which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; FIG. 8 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is an essential part enlarged view of an essential part cross-sectional view during a manufacturing step of the semiconductor device shown in FIG. 12; FIG. 13 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 12; FIG. 15 is an essential part enlarged view of an essential part cross-sectional view during a manufacturing step of the semiconductor device shown in FIG. 14. FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 18 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 17; It is principal part sectional drawing in the manufacturing process of the semiconductor device which the present inventors examined. FIG. 20 is an essential part enlarged view of the essential part cross-sectional view during a manufacturing step of the semiconductor device shown in FIG. 19;

Explanation of symbols

1 Silicon substrate (semiconductor substrate)
DESCRIPTION OF SYMBOLS 2 Semiconductor manufacturing apparatus 3 Mo type sputtering chamber 4 Al type sputtering chamber 5 Ti type sputtering chamber 6 Heat processing chamber 7 Dry etching chamber 8 Wafer cassette 9 Load port 10 Load lock chamber 11 Vacuum transfer chamber 12, 18 Wafer stage 13 Electrostatic chuck 14 Excitation electrode 15 Sputtering target 16 Gas supply system 17 Lower electrode 19 High frequency power supply 20 Upper electrode 21 Photoresist film BE Barrier conductor film CH Contact hole (connection hole)
E1 electrode conductor film E1a first conductor film E1b second conductor film E1w wetting film f1 main surface GE gate electrode GI gate insulating film h1 first hole h2 second hole IL interlayer insulating film ns n-type source region nw n-type Element area pc p-type contact area pw p-type well area Qn n-type MIS transistor (semiconductor element)
tr trench

Claims (25)

(A) forming a semiconductor element on the main surface of the semiconductor substrate;
(B) forming an interlayer insulating film so as to cover the main surface of the semiconductor substrate;
(C) forming a connection hole that penetrates the interlayer insulating film and reaches the main surface of the semiconductor substrate on which the semiconductor element is formed, with respect to the interlayer insulating film;
(D) burying the connection hole with an electrode conductor film,
The step (d)
(D1) depositing a first conductor film so as to fill the connection hole;
(D2) a step of waiting without performing a predetermined step on the semiconductor substrate;
(D3) depositing a second conductor film so as to cover the first conductor film,
During the step (d), each step is performed in a vacuum environment without exposing the semiconductor substrate to the atmosphere.
In the steps (d1) and (d3), the electrode conductor film composed of the first and second conductor films is formed of a conductor film mainly composed of aluminum,
In the step (d1), the first conductor film is deposited at a deposition rate faster than the deposition rate of the second conductor film in the step (d3). In the manufacturing method of the semiconductor device according to claim 1,
In the steps (d1) and (d3), the first and second conductive films are deposited by sputtering,
In the step (d1), the first conductor film having a film thickness of 1 to 3 μm is deposited under conditions where the sputtering rate is 150 to 155 nm / kW and 18 to 22 nm / sec.
In the step (d3), the second conductor film having a thickness of 1 to 3 μm is deposited under the conditions where the sputtering rate is 190 to 200 nm / kW and 15 to 18 nm / sec. Device manufacturing method. The method of manufacturing a semiconductor device according to claim 2.
In the step (c), the connection hole is formed in the interlayer insulating film so as to have a slit shape when the main surface of the semiconductor substrate is viewed in a plan view. . In the manufacturing method of the semiconductor device according to claim 3,
The steps (d1) and (d3) are performed in the same processing chamber,
In the step (d1) and the step (d3), the semiconductor substrate is heated under the same conditions to deposit the first and second conductor films. In the manufacturing method of the semiconductor device according to claim 4,
In the steps (d1) and (d3), the semiconductor device is characterized in that the first and second conductor films are deposited by heating the semiconductor substrate at a temperature of 400 to 500 degrees Celsius. Manufacturing method. In the manufacturing method of the semiconductor device according to claim 5,
In the step (d), before the step (d1),
(D4) including a step of depositing a wetting film with a conductor film mainly composed of aluminum having a thickness smaller than that of the first and second conductor films so as to cover an inner wall of the connection hole;
In the step (d1), the first conductor film is formed through the wetting film,
A method of manufacturing a semiconductor device, wherein the electrode conductor film comprising the wetting film, the first conductor film, and the second conductor film is formed by the steps (d1) to (d4). The method of manufacturing a semiconductor device according to claim 6.
In the step (d4), the wetting film is deposited by sputtering, and the wetting film is deposited under the conditions that the sputtering rate is 150 to 155 nm / kW and 18 to 22 nm / sec.
In the step (d4), the wetting film is deposited without subjecting the semiconductor substrate to predetermined heating. In the manufacturing method of the semiconductor device according to claim 4,
In the steps (d1) and (d3), the semiconductor device is characterized in that the first and second conductor films are deposited by heating the semiconductor substrate at a temperature of 280 to 320 degrees Celsius. Manufacturing method. The method of manufacturing a semiconductor device according to claim 8.
In the step (d), after the step (d3),
(D5) having a step of performing a heat treatment under conditions such that the semiconductor substrate has a temperature of 350 to 400 degrees Celsius;
The method (d5) is performed in a different processing chamber from the steps (d1) to (d3). In the manufacturing method of the semiconductor device according to claim 3,
In the step (d1), the first conductor is heated by heating the semiconductor substrate under a condition that the temperature is lower than the temperature of the semiconductor substrate when the second conductor film is deposited in the step (d3). A method of manufacturing a semiconductor device, comprising depositing a film. The method of manufacturing a semiconductor device according to claim 10.
In the step (d1), the first conductor film is deposited by heating under the condition that the temperature of the semiconductor substrate is 280 to 320 degrees Celsius.
In the step (d3), the semiconductor device is deposited by heating the semiconductor substrate at a temperature of 400 to 500 degrees Celsius to deposit the second conductor film. The method of manufacturing a semiconductor device according to claim 11.
The method of manufacturing a semiconductor device, wherein the steps (d1) to (d3) are performed in different processing chambers. (A) forming a semiconductor element on the main surface of the semiconductor substrate;
(B) forming an interlayer insulating film so as to cover the main surface of the semiconductor substrate;
(C) forming a connection hole that penetrates the interlayer insulating film and reaches the main surface of the semiconductor substrate on which the semiconductor element is formed, with respect to the interlayer insulating film;
(D) depositing a barrier conductor film so as to cover the inner wall of the connection hole;
(E) burying the connection hole with an electrode conductor film,
The step (c)
(C1) forming a first hole in a part of the interlayer insulating film so as to expose a main surface of the semiconductor substrate that is a part of the semiconductor element;
(C2) The main surface of the semiconductor substrate in the portion exposed in the first hole is scraped to be lower than the other portions, so that the planar contour shape overlaps with the first hole. Forming two holes;
(C3) cleaning the semiconductor substrate by performing isotropic etching on the semiconductor substrate;
(C4) processing the end of the second hole of the semiconductor substrate into a tapered shape,
In the step (c2), anisotropic etching using the interlayer insulating film as an etching mask is performed on the main surface of the semiconductor substrate at a portion exposed in the first hole portion, and the second hole is removed. Forming part,
In the step (c3), by the isotropic etching, the planar outline of the first hole portion of the interlayer insulating film is retracted so as to be larger than the planar outline of the second hole portion. ,
In the step (c4), the tapered shape is formed at the end of the second hole by performing sputtering etching on the semiconductor substrate and cutting the second hole of the semiconductor substrate. A method of manufacturing a semiconductor device. 14. The method of manufacturing a semiconductor device according to claim 13,
The step (e)
(E1) depositing a first conductor film so as to fill the connection hole;
(E2) a step of waiting without performing a predetermined step on the semiconductor substrate;
(E3) having a step of depositing a second conductor film so as to cover the first conductor film,
During the step (e), each step is performed in a vacuum environment without exposing the semiconductor substrate to the atmosphere.
In the steps (e1) and (e3), the electrode conductor film composed of the first and second conductor films is formed of a conductor film mainly composed of aluminum,
In the step (e1), the first conductor film is deposited at a deposition rate faster than the deposition rate of the second conductor film in the step (e3). 15. The method of manufacturing a semiconductor device according to claim 14,
In the steps (e1) and (e3), the first and second conductive films are deposited by sputtering,
In the step (e1), the first conductor film having a film thickness of 1 to 3 μm is deposited under conditions where the sputtering rate is 150 to 155 nm / kW and 18 to 22 nm / sec.
In the step (e3), the second conductor film having a film thickness of 1 to 3 μm is deposited under conditions where the sputtering rate is 190 to 200 nm / kW and 15 to 18 nm / sec. Device manufacturing method. 15. The method of manufacturing a semiconductor device according to claim 14,
In the step (c), the connection hole is formed in the interlayer insulating film so as to have a slit shape when the main surface of the semiconductor substrate is viewed in a plan view. . In the manufacturing method of the semiconductor device according to claim 16,
The steps (e1) and (e3) are performed in the same processing chamber,
In the step (e1) and the step (e3), the semiconductor substrate is heated under the same conditions to deposit the first and second conductor films. The method of manufacturing a semiconductor device according to claim 17.
In the steps (e1) and (e3), the semiconductor device is characterized in that the first and second conductive films are deposited by heating the semiconductor substrate at a temperature of 400 to 500 degrees Celsius. Manufacturing method. The method of manufacturing a semiconductor device according to claim 18.
In the step (e), before the step (e1),
(E4) A wetting film is formed by the conductor film mainly composed of aluminum having a smaller film thickness than the first and second conductor films so as to cover the inner wall of the connection hole via the barrier conductor film. Having a process of depositing,
In the step (e1), the first conductor film is formed via the wetting film,
A method of manufacturing a semiconductor device, wherein the electrode conductor film comprising the wetting film, the first conductor film, and the second conductor film is formed by the steps (e1) to (e4). In the manufacturing method of the semiconductor device according to claim 19,
In the step (e4), the wetting film is deposited by sputtering, and the wetting film is deposited under conditions where the sputtering rate is 150 to 155 nm / kW and 18 to 22 nm / sec.
In the step (e4), the wetting film is deposited without subjecting the semiconductor substrate to predetermined heating. The method of manufacturing a semiconductor device according to claim 17.
In the steps (e1) and (e3), the semiconductor device is characterized by depositing the first and second conductive films by heating the semiconductor substrate at a temperature of 280 to 320 degrees Celsius. Manufacturing method. In the manufacturing method of the semiconductor device according to claim 21,
In the step (e), after the step (e3),
(E5) having a step of performing a heat treatment under conditions such that the semiconductor substrate has a temperature of 350 to 400 degrees Celsius;
The method (e5) is performed in a different processing chamber from the steps (e1) to (e3). In the manufacturing method of the semiconductor device according to claim 16,
In the step (e1), the first conductor is heated by heating the semiconductor substrate under a condition that the temperature is lower than the temperature of the semiconductor substrate when the second conductor film is deposited in the step (e3). A method of manufacturing a semiconductor device, comprising depositing a film. 24. The method of manufacturing a semiconductor device according to claim 23.
In the step (e1), the first conductive film is deposited by heating under the condition that the temperature of the semiconductor substrate is 280 to 320 degrees Celsius,
In the step (e3), the semiconductor device is deposited by heating the semiconductor substrate under conditions such that the temperature of the semiconductor substrate is 400 to 500 degrees Celsius. The method of manufacturing a semiconductor device according to claim 24,
The method of manufacturing a semiconductor device, wherein the steps (e1) to (e3) are performed in different processing chambers.

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