JP2010020384A - Simulation system, simulation method, hils device, simulation support device, method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an efficient HILS (Hardware In the Loop Simulation) device and increase the computing accuracy of HILS. <P>SOLUTION: The HILS device for verifying the response of a target system by using a block line drawing model expressing the target system controlled by an electronic control unit includes an FPGA (Field Programmable Gate Array) which includes: a non-real-time processor which constitutes a non-real-time system for executing the input/output of a first subsystem model while communicating with an HILS terminal by executing a simulation program; a user logic unit which constitutes a high-speed computing unit for executing the computation of a second subsystem model while communicating with the electronic control unit by being defined by a net list; and a real-time processor which constitutes a real-time system for executing the computation of the first subsystem model while communicating with the electronic control unit, the non-real-time system, and the high-speed computing unit by executing the simulation program. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to simulation, and more particularly to HILS (Hardware In the Loop Simulation) using an FPGA (Field Programmable Gate Array).

The MATLAB (registered trademark) family, such as Simulink (registered trademark) and Real-Time Workshop (registered trademark), is widely known as a modeling tool that provides a prototyping environment for modeling and testing real-world dynamic systems. In a development environment such as a drive system control system for a hybrid vehicle, speeding up of the simulation calculation is required. For example, in the development environment of an electronic control unit that controls a motor, a HILS test is performed in which a simulation device that simulates the motor response and the electronic control unit are connected. Is required. Therefore, a technique is known in which an FPGA is configured as a high-speed arithmetic processing circuit optimized for simulation calculation using HDL (Hardware Description Language) to shorten the calculation time of the simulation (Patent Documents 1, 2, and 3). In addition, FPGA programming tools have been developed that generate an HDL that uses an FPGA as a high-speed computing unit from a block diagram model. These FPGA-compatible programming tools are linked to modeling tools such as Simulink for general-purpose processors such as System Generator of Xilinx Corporation and Dsp Builder of Altera Corporation. Some have been developed that enable simulation using a single block diagram model integrated with the block diagram model. As a result, an environment in which a parallel arithmetic processing device is configured by a processor that executes source code and an FPGA defined by HDL, and an HILS (Hardware In the Loop Simulation) operation can be executed at high speed is being prepared.
JP 2006-14393 A JP 2007-230105 A JP 2006-318200 A

  However, in parallel processing of HILS using a conventional processor and FPGA, efficient real-time processing is executed, and the results of SILS (Software In the Loop Simulation) and HILS are precisely matched. I can't let you.

  An object of the present invention is to realize an efficient HILS apparatus and to further improve the calculation accuracy of HILS.

  (1) A simulation system for achieving the above object is a simulation system for verifying a response of the target system using a block diagram model representing the target system controlled by an electronic control unit, A simulation support apparatus; an HILS apparatus including an FPGA; and an HILS terminal that operates the HILS apparatus and displays an output of the HILS apparatus. The simulation support apparatus provided in the simulation system of the present invention creates the block diagram model in which a first subsystem model in which processor-compatible blocks are connected and a second subsystem model in which FPGA-compatible blocks are connected are integrated. A model generating unit for generating the program, a program generating unit for generating a simulation program from the first subsystem model, and a net list generating unit for generating a net list from the second subsystem model. The FPGA provided in the simulation system of the present invention includes a non-real-time processor constituting a non-real-time system that executes input / output of the first subsystem model while communicating with the HILS terminal by executing the simulation program, A user logic unit constituting a high-speed calculation unit that executes the calculation of the second subsystem model while communicating with the electronic control unit by being defined by a netlist, and the electronic control by executing the simulation program A real-time processor that constitutes a real-time system that executes computation of the first subsystem model while communicating with a unit, the non-real-time system, and the high-speed computation unit.

  According to the present invention, two processors are incorporated into the FPGA of the HILS apparatus in order to make real-time processing more efficient. That is, according to the present invention, a processor (non-real-time processor) constituting a non-real-time system communicating with an HILS terminal and a processor (real-time processor) constituting a real-time system communicating with a high-speed computing unit constituted by a netlist are provided. The user logic unit, which is defined in the FPGA of the device and is another area of the FPGA, is defined as a high-speed calculation unit. As a result, it is possible to prevent the non-real-time processing by the non-real-time processor communicating with the HILS terminal from competing with the real-time processing by the real-time processor cooperating with the high-speed arithmetic unit, and the two processors and the high-speed arithmetic unit are provided inside the FPGA. Since communication is possible via a high-speed communication line, an efficient HILS apparatus is realized. The processor-corresponding block refers to a block in which processing to be converted into a program executed by the processor is defined, and the FPGA-corresponding block refers to a block in which processing to be converted into a netlist defining FPGA is defined. Shall.

  (2) When data is transferred between the high-speed arithmetic unit customized by the user logic unit and the real-time processor, depending on the configuration of the data transfer unit that controls the data transfer inside the HILS apparatus regardless of the configuration of the target system. Transfer delay occurs, and as a result, the accuracy of the simulation operation by the HILS apparatus decreases.

Therefore, in the simulation system for achieving the above object, the simulation support apparatus includes a data transfer block that simulates an operation of a data transfer unit that transfers data between the real-time processor and the high-speed calculation unit. It is preferable that data transfer block insertion means for insertion into a system model is provided, and the data transfer unit is configured in the user logic unit by being defined by the netlist.
The simulation apparatus includes means (data transfer block insertion means) for inserting a data transfer block that simulates the operation of the data transfer unit that transfers data between the high-speed arithmetic unit and the real-time processor into the block diagram model model. By configuring a part of the user logic unit of the FPGA as a data transfer unit with the data transfer block, it is possible to improve the accuracy of the simulation calculation by the HILS apparatus.

  (3) In the simulation system for achieving the above object, the HILS apparatus includes a buffer storage unit and a buffer interface for transferring data from the real-time processor to the non-real-time processor via the buffer storage unit. Is desirable.

  Thereby, a real-time processor and a non-real-time processor can be used efficiently.

  (4) In the simulation system for achieving the above object, the buffer interface is disposed between the buffer storage unit and the non-real-time processor and used by the non-real-time processor, and the buffer A second dual-port RAM disposed between the storage unit and the real-time processor and used by the real-time processor; and a buffer storage control for controlling the buffer storage unit from the non-real-time processor and the real-time processor And a third dual port RAM disposed between the non-real time processor and the real time processor and used by the non real time processor and the real time processor.

  By separating the data transfer path from the first processor to the second processor and the data transfer path from the second processor to the first processor, the real-time processor and the non-real-time processor can be used more efficiently.

  (5) When a C language source file is generated from a block diagram model created using Simulink using Real-Time Workshop, a portion where FPGA-compatible blocks are connected is temporarily extracted from the entire block diagram model. Must be deleted.

Therefore, in the simulation system for achieving the above object, the simulation support apparatus independently generates a first file in which the first subsystem model is stored and a second file in which the second subsystem model is stored. In addition, it is desirable to provide file management means for storing the information of the first subsystem model necessary for the calculation of the second subsystem model in the second file.
This can reduce the burden on the user who operates the simulation support apparatus.

(6) A simulation method for achieving the above object is a simulation method for verifying the response of the target system using a block diagram model representing the target system controlled by the electronic control unit, The block diagram model in which the first subsystem model in which processor-compatible blocks are connected and the second subsystem model in which FPGA-compatible blocks are connected is integrated, and a simulation program is created from the first subsystem model. Generating a netlist from the second subsystem model, and executing the simulation program by a first processor configured by a part of an FPGA, so that the first subsystem model is communicated with the HILS terminal. Non-realistic that perform I / O A high-speed computing unit configured to execute computation of the second subsystem model while communicating with the electronic control unit by being defined by the netlist, and comprising a part of the FPGA By executing the simulation program by two processors, a real-time system that executes the calculation of the first subsystem model while communicating with the electronic control unit, the non-real-time system, and the high-speed calculation unit is configured, and the HILS terminal And operating the HILS apparatus and displaying the output of the HILS apparatus.
According to the present invention, as described above, an efficient HILS apparatus can be realized.

(7) An HILS apparatus for achieving the above object is a block diagram model representing a target system controlled by an electronic control unit, and a first subsystem model in which processor corresponding blocks are connected and an FPGA corresponding block A HILS apparatus for verifying the response of the target system using the block diagram type model integrated with the second subsystem model connected to each other, the simulation generated from the first subsystem model By executing a program, a non-real-time processor constituting a non-real-time system that executes input / output of the first subsystem model while communicating with the HILS terminal, and a netlist generated from the second subsystem model By defining the electronic control unit A user logic unit that constitutes a high-speed calculation unit that executes the calculation of the second subsystem model while communicating with the computer, and the electronic control unit, the non-real-time system, and the high-speed calculation unit by executing the simulation program And a real-time processor that constitutes a real-time system that executes operations of the first subsystem model while communicating with the first subsystem model.
According to the present invention, as described above, an efficient HILS apparatus can be realized.

(8) A simulation support apparatus for achieving the above object is a block diagram type model representing a target system controlled by an electronic control unit and is compatible with a first subsystem model in which processor-compatible blocks are connected and an FPGA. A model creating means for creating the block diagram model integrated with the second subsystem model in which the blocks are connected, and a simulation program executed by the processor provided in the FPGA are generated from the first subsystem model. And a net list defining a user logic part of the FPGA constituting a high-speed arithmetic unit that executes the calculation of the second subsystem model while communicating with the electronic control unit from the second subsystem model Netlist generation means to generate , And a data transfer block insertion means for inserting the data transfer block to simulate the operation of the data transfer unit for transferring the data to the second sub-system model in between the high-speed arithmetic unit and the real-time processor.
According to the present invention, as described above, the accuracy of the simulation calculation by the HILS apparatus can be increased.

(9) A simulation support method for achieving the above object is a block diagram type model representing a target system controlled by an electronic control unit, which corresponds to an FPGA and a first subsystem model in which processor corresponding blocks are connected. A model creating means for creating the block diagram model integrated with the second subsystem model in which the blocks are connected, and a simulation program executed by the processor provided in the FPGA are generated from the first subsystem model. Generating a net list from the second subsystem model for defining a user logic unit of the FPGA that constitutes a high-speed arithmetic unit that communicates with the electronic control unit and cooperates with the processor Means comprising A simulation support method used in a simulation support apparatus, wherein a data transfer block that simulates an operation of a data transfer unit that transfers data between the real-time processor and the high-speed calculation unit is inserted into the second subsystem model , Including that.
According to the present invention, as described above, the accuracy of the simulation calculation by the HILS apparatus can be increased.

(10) A simulation support program for achieving the above object is a block diagram type model representing a target system controlled by an electronic control unit, and is compatible with a first subsystem model in which processor corresponding blocks are connected and an FPGA. A model creating means for creating the block diagram model integrated with the second subsystem model in which the blocks are connected, and a simulation program executed by the processor provided in the FPGA are generated from the first subsystem model. Generating a net list from the second subsystem model for defining a user logic unit of the FPGA that constitutes a high-speed arithmetic unit that communicates with the electronic control unit and cooperates with the processor Means and A data transfer block inserting means for inserting a data transfer unit for transferring data between the real-time processor and the high-speed arithmetic unit into the second subsystem model, which is a simulation support program executed by a functioning computer To make the computer function.
According to the present invention, as described above, the accuracy of the simulation calculation by the HILS apparatus can be increased.

  The order of the operations described in the claims is not limited to the order of description as long as there is no technical obstruction factor, and may be executed at the same time, may be executed in the reverse order of the description order, or may be continuous. It does not have to be executed in order. The functions of the respective means described in the claims are realized by hardware resources whose functions are specified by the configuration itself, hardware resources whose functions are specified by a program, or a combination thereof. The functions of these means are not limited to those realized by hardware resources that are physically independent of each other. Furthermore, the present invention is also realized as a computer program recording medium. Of course, the recording medium for the computer program may be a magnetic recording medium, a magneto-optical recording medium, or any recording medium that will be developed in the future.

Hereinafter, embodiments of the present invention will be described in the following order with reference to the accompanying drawings. In each figure, corresponding components are denoted by the same reference numerals, and redundant description is omitted.
1. Overview FIG. 1 shows an overall configuration of a simulation system 1 according to an embodiment of the present invention. The simulation system 1 includes a host computer 10 that functions as a simulation support apparatus and a HILS terminal, and a HILS apparatus 20 connected to the electronic control unit 30. In the host computer 10, a program for creating a target model representing a real-world target system composed of a motor, its driver and sensor, SIL (Software In the Loop) test, and customizing the FPGA 29 provided in the HILS apparatus 20 203 and 206 and the net list 207 are generated. In the HILS apparatus 20, a simulation calculation for simulating the operation of the motor controlled by the electronic control unit 30 is performed by the FPGA 29. Operation of the HILS apparatus 20 and display of output are performed by the host computer 10.

2. Configuration of Host Computer As shown in FIG. 2, the host computer 10 includes a processor 11, an I / O 16 that controls communication with the HILS apparatus 20, a memory, a hard disk, and the like (not shown). The host computer 10 includes a display 14 a for displaying a screen constituting a GUI (Graphical User Interface) of the host computer 10 and an output of the HILS apparatus 20, and a keyboard 15 a for operating the host computer 10 and the HILS apparatus 20. A mouse 15b is connected.

  On the Windows (registered trademark), which is a non-real-time operating system, the host computer 10 includes a Simulink 102, a Real-Time Workshop (hereinafter abbreviated as RTW) 103, a System Generator (hereinafter abbreviated as SG) 108, and an ISE. A simulation support program configured by (registered trademark) 107, modeling support program 104, and the like is executed by the processor 11 to function as a simulation support apparatus.

  The Simulink 102 is a module that realizes a function of creating a first subsystem model M1 that is a part calculated by a processor in a block diagram model representing the entire motor as a target system. It functions as a model creation means. The first subsystem model M1 is a model in which processor-compatible blocks to be converted into programs executed by the processor of the HILS apparatus 20 are connected.

  The RTW 103 is a module that generates a communication program 203 and an operation program 206 that can be executed independently from the model created by the Simulink 102, and causes the host computer 10 to function as a program generation unit.

  SG108 is a module that realizes a function of creating a second subsystem model M2 that is a portion calculated by the high-speed calculation unit 26b in the block diagram model representing the entire motor that is the target system. The host computer 10 is caused to function as model creation means. The SG 108 incorporates an SG block, which is an FPGA-compatible block, into the GUI of the Simulink 102. The SG block is a block provided by Xilinx Corporation as a standard block of SG108. The second subsystem model M2 is a model in which FPGA-compatible blocks to be converted into a netlist that defines the FPGA 29 of the HILS apparatus 20 are connected.

  The ISE 107 configures the user logic unit 26 of the FPGA 29 of the HILS apparatus 20 as a high-speed calculation unit 26b that executes calculation of the second subsystem model M2 created by the SG 108 and a netlist 207 for configuring the I / F 26a as a second sub-list. This module is generated from the system model M2, and causes the host computer 10 to function as a net list generating means. The ISE 107 is a single FPGA implementation file (configuration file) expressed in binary notation from the net list 207 defining the user logic unit 26, the net list defining the first processor 21, and the net list defining the second processor 24. Is generated. The net list that defines the first processor 21 and the net list that defines the second processor 24 are incorporated in advance.

  The modeling support program 104 inserts the data transfer block 106 into the second subsystem model M2, and also transmits information on the first subsystem model M1 referenced by the second subsystem model M2 from the first subsystem model M1 to the reference information 105. The host computer 10 functions as data transfer block insertion means and file management means.

3. Configuration of HILS Device As shown in FIG. 2, the HILS device 20 includes an FPGA 29, an I / O 22 that controls communication with the host computer 10, and I / Os 27 and 28 that control communication with the electronic control unit 30. Storage medium that does not. Various functions of the HILS apparatus 20 are realized by loading the FPGA mounting file generated by the host computer 10, the communication program 203, and the arithmetic program 206 into the HILS apparatus 20.

  The FPGA 29 is a PLD (Programmable Logic Device) including a plurality of I / O units (not shown), a plurality of logic cells, internal wiring, a clock network, a plurality of SRAMs, a plurality of dual port block RAMs, and the like. These components of the FPGA 29 constitute a first processor 21, a second processor 24, an I / F 23, a user logic unit 26, a bus and a timer (not shown) of the first processor 21 and the second processor 24, and the like. The first processor 21, the second processor 24, the I / F 23, and the user logic unit 26 implement the functions defined by the netlist by mounting the FPGA mounting file generated by the host computer 10 in the FPGA 29. It is configured as an electronic circuit.

  The first processor 21 that functions as a non-real-time processor executes a down loader (hereinafter abbreviated as DL) 203 on the Linux (registered trademark) 201, which is a non-real-time operating system, to thereby execute a communication program 203 and an operation. The program 206 is stored in a nonvolatile storage medium (not shown) of the HILS apparatus 20. The communication program 203 and the arithmetic program 206 are loaded by the DL 203 and are ready to be executed by the first processor 21 and the second processor 24, respectively.

  The first processor 21 executes a communication program 203 on the Linux 201 to communicate with the host computer 10 and execute a first subsystem model M1 input / output to / from the Micro Blaze (registered trademark) core. It is. The communication program 203 is one of execution type simulation programs generated by the RTW 103 based on the first subsystem model M1, and controls input / output of the first subsystem model M1.

  The second processor 24 that functions as a real-time processor is a Power PC (registered trademark) core that configures the real-time system by executing the Monitor 204 and the arithmetic program 206 on the RTOS 205 compliant with μITRON, which is a real-time operating system. The real-time system configured by the second processor 24 communicates with the non-real-time system configured by the first processor 21, the high-speed calculation unit 26 b of the user logic unit 26, and the electronic control unit 30, and the first subsystem model M 1. Execute the operation. The Monitor 204 mainly controls communication. The calculation program 206 is one of execution-type simulation programs generated by the RTW 103 based on the first subsystem model M1, and controls the calculation of the first subsystem model M1. Communication between the second processor 24 and the first processor 21 is performed via the I / F 23. Communication between the second processor 24 and the high-speed calculation unit 26b is performed via the I / F 26a. Communication between the second processor 24 and the electronic control unit 30 is performed via the I / O 27.

  When the FPGA mounting file generated by the ISE 107 is mounted on the FPGA 29, the user logic unit 26 configures a dedicated processing circuit that executes the operation of the second subsystem model M2 while communicating with the second processor 24 and the electronic control unit 30. To do. That is, the user logic unit 26 is a partial area of the FPGA 29 in which an arbitrary circuit is defined by a block diagram model created by the user using the SG 108. Communication between the user logic unit 26 and the electronic control unit 30 is performed via the I / O 28.

  The user logic unit 26 includes a high-speed calculation unit 26b that performs a calculation of a portion corresponding to the real world target system of the second subsystem model M2, and a portion that does not correspond to the real world target system of the second subsystem model M2. An I / F 26 a corresponding to a certain data transfer block 106 is configured according to the net list 207.

  The I / F 26a of the user logic unit 26 includes a bus and a bus master that transfer data between the second processor 24 and the high-speed arithmetic unit 26b. Since the model of the I / F 26a that functions as the data transfer unit is incorporated in the second subsystem model M2 as the data transfer block 106, even if a transfer delay occurs in the I / F 26a, the first subsystem model M1 and the second subsystem Synchronization with model M2 is guaranteed. Therefore, the accuracy of the simulation operation by the HILS device 20 is improved, and the difference between the result of the SILS operation by the host computer 10 and the result of the HILS operation by the HILS device 20 is reduced.

  FIG. 3 is a block diagram showing a configuration of the I / F 23 for performing data transfer between the first processor 21 and the second processor 24. Each block of the I / F 23 that functions as a buffer interface is configured by an IP core. In FIG. 3, the function of each block is shown by giving the general abbreviation of the IP core to each block constituted by the IP core. The DPRAMs 23b, 23d, and 23h are dual-port block RAMs that can simultaneously read and write. The BRAM-CNTRs 23a, 23e, 23g, and 23j write data to the block RAM and read data from the block RAM. The GPIOs 23f and 23i are used by the first processor 21 and the second processor 24 for writing and reading various control signals and flags for controlling the buffer storage unit 23c.

  Data transfer from the first processor 21 constituting the non-real-time system to the second processor constituting the real-time system includes BRAM-CNTR 23g controlled by the first processor 21 and BRAM-CNTR 23j controlled by the second processor 24. Is performed via the DPRAM 23h in which reading and writing are controlled. That is, data is transferred from the first processor 21 to the second processor 24 by using the DPRAM 23h as a shared memory.

  Data transfer from the second processor 24 configuring the real-time system to the first processor 21 configuring the non-real-time system is performed via the buffer storage unit 23c. The buffer storage unit 23c is a FIFO (First In First Out) storage circuit. The GPIO 23 i functions as a buffer storage control unit for controlling the buffer storage unit 23 c from the second processor 24. The GPIO 23 f functions as a buffer storage control unit for controlling the buffer storage unit 23 c from the first processor 21. The data written to the buffer storage unit 23c is once written to the DPRAM 23d used by the second processor 24 via the BRAM-CNTR 23e. Data read from the buffer storage unit 23c is once written into the DPRAM 23b used by the first processor 21 via the BRAM-CNTR 23a.

  Data is written in the DPRAM 23d used by the second processor 24 constituting the real-time system regardless of the state of the first processor 21, and when a predetermined amount of data written in the DPRAM 23d is accumulated, the data is buffered. It is written in the storage unit 23c. When the first processor 21 constituting the non-real-time system reads out the data stored in the DPRAM 23b, the oldest data among the data stored in the buffer storage unit 23c is written into the DPRAM 23b. Since the buffer storage unit 23c can store data up to its own capacity, the real-time system configured by the second processor 24 is not capable of receiving data by the non-real-time system configured by the first processor 21. Data can be once delivered to the buffer storage unit 23c. For this reason, the first processor 21 and the second processor 24 can be used efficiently.

4). Simulation Method FIG. 4 is a sequence chart showing a simulation method for verifying the response of the target system in the real world using the simulation system 1.
First, the host computer 10 operates the GUI of the Simulink 102 to create a block diagram model integrating the first subsystem model M1 and the second subsystem model M2 (step S10). When the second subsystem model M2 is created using the SG block incorporated in the GUI of the Simulink 102 by the SG 108, the HDL corresponding to the second subsystem model M2 is described. By operating the menu items incorporated in the GUI of the Simulink 102 by the modeling support program 104, the data transfer block 106 is inserted into the second subsystem model M2 as shown in FIG. The HDL corresponding to the data transfer block 106 is described by SG108. At this time, the modeling support program 104 extracts the reference information 105 necessary for the calculation of the second subsystem model M2 from the file in which the first subsystem model M1 is stored by the Simulink 102, and the second subsystem model by the SG 108. The reference information 105 is stored in a file in which M2 is saved.

  Next, the host computer 10 generates a source file of the communication program 203 and a source file of the arithmetic program 206 from the first subsystem model M1 (step S11). These source files are described in C language and are generated by executing the RTW 103. At this time, since the first subsystem model M1 and the second subsystem model M2 are stored in separate files independent from each other, the user can edit the source of the communication program 203 without editing the second subsystem model M2. A file and a source file of the arithmetic program 206 can be generated.

  Next, the host computer 10 compiles the source file of the communication program 203 and the source file of the arithmetic program 206 to generate an executable communication program 203 and the arithmetic program 206 (step S12). This process is performed by executing the RTW 103.

  Next, the host computer 10 generates a netlist 207 for defining the user logic unit 26 of the FPGA 29 from the HDL corresponding to the second subsystem model M2, and the netlist 207 and the netlist defining the first processor 21 One FPGA implementation file of binary representation is generated from the net list defining the two processors 24 (step S13). The FPGA implementation file is generated by executing ISE 107.

  Next, the FPGA mounting file is downloaded from the host computer 10 to the HILS apparatus 20 (step S14). At this time, the function of the FPGA 29 is defined according to the net list.

  Next, the communication program 203 and the arithmetic program 206 are downloaded from the host computer 10 to the HILS apparatus 20 (step S16). At this time, the communication program 203 and the arithmetic program 206 are downloaded to a predetermined area of the nonvolatile storage medium of the HILS apparatus 20 by the DL 202 shown in FIG.

  Next, by operating the GUI of the host computer 10, an operation command for executing, in the HILS apparatus 20, an operation of a block diagram type model in which the first subsystem model M 1 and the second subsystem model M 2 are integrated. The data is transmitted from the host computer 10 to the HILS apparatus 20 (step S18). This operation command is received by the non-real-time system configured by the first processor 21 that executes the communication program 203.

  The HILS apparatus 20 that has received the operation command executes an operation of a block diagram model in which the first subsystem model M1 and the second subsystem model M2 are integrated (step S19). This calculation is executed by the real-time system configured by the second processor 24 that executes the calculation program 206 and the high-speed calculation unit 26 b defined by the netlist 207. At this time, since the high-speed calculation unit 26b defined by the netlist 207 performs calculation by hardware logic, the calculation of the second subsystem model M2 can be performed at high speed. In addition, since the model of the I / F 26a that performs data transfer between the high-speed arithmetic unit 26b and the second processor 24 is preliminarily incorporated in the block diagram model, the high-speed arithmetic unit 26b and the second processor 24 are synchronized. To execute each operation. Therefore, the accuracy of the simulation operation by the HILS apparatus 20 is high, and the result of the HILS operation by the HILS apparatus 20 matches the result of the SILS operation by the host computer 10.

  Next, the calculation result of the block diagram type model in the HILS apparatus 20 is transmitted from the HILS apparatus 20 to the host computer 10 (step S20). This process is executed by a non-real-time system configured by the first processor 21 that executes the communication program 203.

  When the host computer 10 receives the result of the calculation of the block diagram model by the HILS apparatus 20, the host computer 10 displays the result on the display 14a (step S21).

5). Other Embodiments The technical scope of the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, the simulation support apparatus and the HILS terminal may be configured by two independent computers. The present invention can also be applied to modeling tools such as Dsp Builder other than the System Generator. Further, the simulation system according to the present invention is remarkably exhibited in its high calculation accuracy and high-speed performance by being applied to prototyping of various systems in the real world where electric signals are verified as responses.

The schematic diagram concerning embodiment of this invention. The block diagram concerning embodiment of this invention. The block diagram concerning embodiment of this invention. The sequence chart concerning embodiment of this invention.

Explanation of symbols

1: simulation system, 10: host computer, 11: processor, 14a: display, 15a: keyboard, 15b: mouse, 20: HILS device, 21: first processor, 23: I / F, 23b: dual port RAM, 23c : Buffer storage unit, 23d: dual port RAM, 23f: GPIO, 23h: dual port RAM, 23i: GPIO, 24: second processor, 26: user logic unit, 26a: I / F, 26b: high speed calculation unit, 30 : Electronic control unit, 104: modeling support program, 105: reference information, 106: data transfer block, 203: communication program, 206: calculation program, 207: netlist, M1: first subsystem model, M2: second sub System model

Claims (10)

A simulation system for verifying a response of the target system using a block diagram model representing the target system controlled by an electronic control unit,
Model creation means for creating the block diagram model in which the first subsystem model to which the processor corresponding block is connected and the second subsystem model to which the FPGA corresponding block is connected is integrated;
Program generation means for generating a simulation program from the first subsystem model;
Netlist generating means for generating a netlist from the second subsystem model;
A simulation support apparatus comprising:
An HILS device comprising an FPGA;
A HILS terminal for operating the HILS device and displaying the output of the HILS device;
With
The FPGA is
A non-real-time processor constituting a non-real-time system for executing input / output of the first subsystem model while communicating with the HILS terminal by executing the simulation program;
A user logic unit constituting a high-speed calculation unit that executes the calculation of the second subsystem model while communicating with the electronic control unit by being defined by the netlist;
By executing the simulation program, a real-time processor constituting a real-time system that executes computation of the first subsystem model while communicating with the electronic control unit, the non-real-time system, and the high-speed computation unit;
Comprising
Simulation system. The simulation support apparatus includes a data transfer block insertion means for inserting a data transfer block that simulates an operation of a data transfer unit that transfers data between the real-time processor and the high-speed calculation unit into the second subsystem model. With
In the user logic unit, the data transfer unit is configured by being defined by the netlist.
The simulation system according to claim 1. The HILS apparatus includes a buffer storage unit and a buffer interface that transfers data from the real-time processor to the non-real-time processor via the buffer storage unit.
The simulation system according to claim 1. The buffer interface is
A first dual port RAM disposed between the buffer storage unit and the non-real-time processor and used by the non-real-time processor;
A second dual-port RAM that is disposed between the buffer storage unit and the real-time processor and used by the real-time processor;
A buffer storage control unit for controlling the buffer storage unit from the non-real-time processor and the real-time processor;
A third dual-port RAM disposed between the non-real-time processor and the real-time processor and used by the non-real-time processor and the real-time processor;
The simulation system according to claim 3. The simulation support apparatus independently generates a first file in which the first subsystem model is stored and a second file in which the second subsystem model is stored and is necessary for the calculation of the second subsystem model File management means for storing the information of the first subsystem model in the second file,
The simulation system according to any one of claims 1 to 4. A simulation method for verifying a response of the target system using a block diagram model representing the target system controlled by an electronic control unit,
Creating the block diagram model in which the first subsystem model in which processor-compatible blocks are connected and the second subsystem model in which FPGA-compatible blocks are connected are integrated;
Generating a simulation program from the first subsystem model;
Generating a netlist from the second subsystem model;
A non-real-time system that executes input / output of the first subsystem model while communicating with the HILS terminal is configured by executing the simulation program by a first processor configured by a part of an FPGA,
A high-speed calculation unit that executes the calculation of the second subsystem model while communicating with the electronic control unit by being defined by the netlist,
Execution of the first subsystem model while communicating with the electronic control unit, the non-real-time system, and the high-speed arithmetic unit by executing the simulation program by a second processor configured by a part of the FPGA Configure real-time system,
Operating the HILS device at the HILS terminal and displaying the output of the HILS device;
A simulation method including: A block diagram model representing a target system controlled by an electronic control unit, in which a first subsystem model in which processor-compatible blocks are connected and a second subsystem model in which FPGA-compatible blocks are connected are integrated A HILS apparatus for verifying a response of the target system using the block diagram type model,
A non-real-time processor constituting a non-real-time system for executing input / output of the first subsystem model while communicating with the HILS terminal by executing a simulation program generated from the first subsystem model;
A user logic unit that configures a high-speed calculation unit that executes the calculation of the second subsystem model while communicating with the electronic control unit by being defined by a netlist generated from the second subsystem model;
By executing the simulation program, a real-time processor constituting a real-time system that executes the calculation of the first subsystem model while communicating with the electronic control unit, the non-real-time system, and the high-speed calculation unit;
Comprising an FPGA comprising
HILS equipment. A block diagram model representing a target system controlled by an electronic control unit, in which a first subsystem model in which processor-compatible blocks are connected and a second subsystem model in which FPGA-compatible blocks are connected are integrated Model creation means for creating the block diagram type model;
Program generation means for generating a simulation program to be executed by a processor included in the FPGA from the first subsystem model;
Netlist generating means for generating a netlist defining a user logic unit of the FPGA constituting a high-speed calculation unit that executes the calculation of the second subsystem model while communicating with the electronic control unit from the second subsystem model When,
A data transfer block inserting means for inserting a data transfer block for simulating an operation of a data transfer unit for transferring data between the real-time processor and the high-speed arithmetic unit into the second subsystem model;
A simulation support apparatus comprising: A block diagram model representing a target system controlled by an electronic control unit, in which a first subsystem model in which processor-compatible blocks are connected and a second subsystem model in which FPGA-compatible blocks are connected are integrated A model creating means for creating the block diagram type model, a program generating means for generating a simulation program executed by a processor included in the FPGA from the first subsystem model, and the electronic control unit And a netlist generating means for generating a netlist defining the user logic part of the FPGA constituting the high-speed arithmetic unit cooperating with the processor from the second subsystem model. There is provided a method,
Inserting a data transfer block that simulates an operation of a data transfer unit that transfers data between the real-time processor and the high-speed calculation unit into the second subsystem model;
A simulation support method including the above. A block diagram model representing a target system controlled by an electronic control unit, in which a first subsystem model in which processor-compatible blocks are connected and a second subsystem model in which FPGA-compatible blocks are connected are integrated A model creating means for creating the block diagram type model, a program generating means for generating a simulation program executed by a processor included in the FPGA from the first subsystem model, and the electronic control unit A simulation support program executed by a computer functioning as netlist generating means for generating a netlist defining the user logic part of the FPGA constituting the high-speed arithmetic unit cooperating with the processor from the second subsystem model A-time,
Causing the computer to function as data transfer block insertion means for inserting a data transfer unit for transferring data between the real-time processor and the high-speed calculation unit into the second subsystem model;
Simulation support program.

Images