JP2010016937A - Power conversion device and dead time compensation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power conversion device and a dead time compensation method wherein dead time is compensated by a simple, low-cost, and small circuit without adding any high breakdown voltage circuit or an insulating device. <P>SOLUTION: The power conversion device includes: a gate signal generation unit 26 that provides an on-delay time in a PWM signal for alternately driving a first switching element and a second switching element and generates a first gate signal and a second gate signal; a first gate drive 23 that drives the first switching element; and a second gate drive 24 that drives the second switching element. It includes a dead time generation unit 25 that generates the following dead time based on the gate voltage of the second switching element: first dead time from when the second switching element is turned off to when the first switching element is turned on; and second dead time from when the first switching element is turned off to when the second switching element is turned on. The gate signal generation unit varies the on-delay time of the first switching element and the on-delay time of the second switching element based on the first dead time and the second dead time. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a power conversion device and a dead time compensation method.

  Conventionally, an output circuit such as an inverter device, a servo amplifier device, or a switching power supply device employs an arm circuit in which two switching elements are connected in series and the connection point is an output terminal. In order to measure the dead time, it is necessary to detect the source-gate voltage, the emitter-gate voltage, the source-drain voltage, the emitter-collector voltage, or the like of each element. Since the source or emitter of the two switching elements have different potentials, an insulation circuit, a high withstand voltage circuit (level shift circuit), a high power resistor, etc. are used to detect the detected voltage value of the other switching element. It is necessary to convert to a signal having the same potential as the reference potential of the value.

FIG. 9 shows a 1-arm circuit of the inverter circuit in the first prior art, and a gate drive circuit that logically calculates the switching state of the switching element and the drive command signal of the switching device, and drives the gate of the switching element based on the result. It is a block diagram.
9, Q1 of 41 is a switching element connected to the positive electrode (P) of the DC power supply, Q2 of 42 is a switching element connected to the negative electrode (N) of the DC power supply, and 47 and 53 are the respective switching elements. The comparators 44, 45, 50, 51 for comparing the gate voltage VG of 48 and the reference voltage VE of 48, 54 and inferring whether each switching element is in the ON state or the OFF state The gate resistance of the element, T1, T2, T3, and T4 of 43, 46, 49, and 52 are switches for turning on and off the voltage to the gate of each switching element through the gate resistance, and 60 is a command to switch the switching element 59 is an inverter control circuit, and 59 is a gate drive command signal for the positive side switching element output from the inverter control circuit. Is a high withstand voltage circuit for level-shifting and transmitting the output to the potential of the switching element on the positive side, 58 is a high withstand voltage circuit for level-shifting the output of the 53 comparator to the potential of the switching element on the positive side, and 57 is the output of the 47 comparator High voltage circuit 55, 56 that inputs the gate drive command signal and the output signal of each comparator, and inputs the drive commands of switches T1, T2, T3, T4 to the potential of the switching element on the negative electrode side. This is a logic circuit to output. (For example, see Patent Document 1)

Next, the operation will be described. When the switching element of Q1 in FIG. 9 is turned on, the turn-off of the switching element of Q2 is detected, for example, by comparing the gate voltage VE with the reference voltage VE by the comparator 53, and becomes below a predetermined value. In this case, it is determined that Q2 is turned off, the output signal of the comparator 53 is guided to the logic circuit 55 through the high voltage circuit 58, and the gate drive command signal UA of Q1 is also transmitted through the high voltage circuit 59. This is a conventional technique that leads to the logic circuit 55 and turns on the switch T1 from the output of the logic circuit to turn on Q1, thereby substantially eliminating the need for setting the dead time.
JP 2002-272131 A (page 4, Fig. 1)

  Since the emitters of the switching elements of Q1 and Q2 shown in the first prior art have different potentials, the output resulting from comparing the gate voltage of Q1 by the comparator 47 is the emitter potential of Q2 via the high withstand voltage circuit 57, or It must be transmitted to a potential close to the emitter potential. Also, the output resulting from comparing the gate voltage of Q2 with the comparator must be transmitted to the emitter potential of Q1 or a potential close to the emitter potential via the high voltage circuit 58. As described above, in the conventional technology, a high voltage circuit is indispensable for signal transmission. The high voltage circuit is complicated and requires an expensive high voltage device, and the components constituting the circuit Also, an insulation distance that can withstand a high voltage is required between components, and this circuit is not suitable for miniaturization. An insulating circuit using an insulating device such as a transformer or a photocoupler instead of a high voltage circuit is also expensive and has a circuit configuration that is not suitable for downsizing. Furthermore, the gate voltages of Q1 and Q2 have no means for preventing false detection against the occurrence of voltage fluctuations due to the effects of switching of Q2 and Q1, respectively. Q1 and Q2 may cause switching malfunction.

  The present invention has been made in view of such problems, and a power conversion apparatus and dead time compensation that compensate for dead time with a simple, low-cost and small circuit without adding a high voltage circuit and an insulating device. It aims to provide a method.

In order to solve the above problem, the present invention is as follows.
According to the first aspect of the present invention, one end of the first switching element and one end of the second switching element are connected in series at a phase output terminal, the other end of the first switching element is connected to a positive electrode of a DC power source, and the first A power conversion device in which the other end of the two switching elements and the negative electrode of the DC power supply are connected, wherein an on-delay time is provided in a PWM signal that alternately drives the first switching element and the second switching element. A gate signal generator for generating a gate signal and a second gate signal; a first gate drive for amplifying the first gate signal to drive the first switching element; and amplifying the second gate signal for the second And a second gate drive for driving the switching element, wherein the second switch is based on a gate voltage of the second switching element. A first dead time from turning off the first switching element to turning on the first switching element and a second dead time from turning off the first switching element to turning on the second switching element. A dead time generating unit, wherein the gate signal generating unit varies an on delay time of the first switching element and an on delay time of the second switching element based on the first dead time and the second dead time. The power converter characterized by the above-mentioned.

According to a second aspect of the present invention, in the power conversion device according to the first aspect, the first switching element and the second switching element are a set of diodes connected in reverse parallel to the IGBT. is there.
According to a third aspect of the present invention, in the power conversion device according to the first aspect, the first switching element and the second switching element are a set of diodes connected in antiparallel with a power MOSFET. It is.
According to a fourth aspect of the present invention, in the power conversion device according to the first aspect, the dead time generating unit is generated when the first switching element is turned on from the time when the gate voltage is lowered from the on-gate voltage to the off-gate voltage. The time until the time when the gate floating voltage starts to appear is defined as the first dead time.

According to a fifth aspect of the present invention, in the power conversion device according to the first aspect, the dead time generation unit shifts to the on-gate voltage from the time when the gate voltage becomes the reflux mode gate voltage when the first switching element is turned off. The time until this is set as the second dead time.
The invention described in claim 6
2. The power conversion device according to claim 1, wherein the dead time generation unit changes the threshold voltage in conjunction with a change in the output of the first comparator that compares the gate voltage with the threshold voltage. A first variable threshold value unit, a first count enable unit for generating a first count enable signal based on the output of the first comparator, the first gate signal, and the second gate signal, and counting a clock according to the count enable And a first dead time is set as the count value of the first time counter.

According to a seventh aspect of the present invention, in the power conversion device according to the first aspect, the dead time generation unit is configured to change a second comparator that compares the gate voltage with a threshold voltage, and a change in the output of the second comparator. A second variable threshold unit that changes the threshold voltage in conjunction with the second count enable unit that generates a second count enable signal based on the output of the second comparator, the first gate signal, and the second gate signal. And a second time counter that counts clocks in accordance with the count enable, and the count value of the second time counter is set to a second dead time.
According to an eighth aspect of the present invention, in the power conversion device according to the first aspect, the gate signal generation unit generates a first excessive on-delay time by subtracting a first dead time from an initial dead time value, and A first on-delay time is generated by subtracting the first excessive on-delay time from a delay time, and a first gate signal is generated based on the PWM signal and the first on-delay time. is there.

According to a ninth aspect of the present invention, in the power conversion device according to the first aspect, the gate signal generation unit generates a second excessive on-delay time by subtracting a second dead time from an initial dead time value, and A second on-delay time is generated by subtracting the second excessive on-delay time from a delay time, and a second gate signal is generated based on the PWM signal and the second on-delay time. is there.
Invention of Claim 10 WHEREIN: In the power converter device of Claim 1, the said gate signal production | generation part selects the longer dead time among the said 1st dead time and the said 2nd dead time, Subtracting the selected dead time from an initial dead time value to generate an excessive on delay time, subtracting the excessive on delay time from the on delay time to generate a new on delay time, and generating the PWM signal and the The first gate signal and the second gate signal are generated based on a new on-delay time.

  According to an eleventh aspect of the present invention, one end of the first switching element and one end of the second switching element are connected in series at a phase output terminal, the other end of the first switching element is connected to a positive electrode of a DC power source, and the first A power conversion device in which the other end of the two switching elements and the negative electrode of the DC power supply are connected, wherein an on-delay time is provided in a PWM signal that alternately drives the first switching element and the second switching element. A gate signal generator for generating a gate signal and a second gate signal; a first gate drive for amplifying the first gate signal to drive the first switching element; and amplifying the second gate signal for the second Based on a second gate drive for driving the switching element and a gate voltage of the second switching element, the second switching element is turned off and then the second switching element is turned off. A power comprising: a first dead time until a switching element is turned on; and a dead time generation unit that generates a second dead time from when the first switching element is turned off until the second switching element is turned on In the dead time compensation method of the converter, the step of enabling the time counter when it is confirmed that the second switching element is turned off, and the time when the gate floating voltage generated when the first switching element is turned on starts to appear. Invalidating the counter, setting the count value of the time counter as a first dead time, subtracting the first dead time from the initial dead time value, and generating a first excessive on-delay time; Subtracting the first excess on-delay time from the on-delay time results in a first Generating a delay time; generating a first gate signal based on the PWM signal and the first on-delay time; and when the gate voltage is off for both the first switching element and the second switching element. A time counter is activated when a recirculation mode gate voltage appears, a step of disabling the time counter when the gate voltage starts to rise above the recirculation mode gate voltage, and a count value of the time counter A second dead time, subtracting the second dead time from the initial dead time value to generate a second excessive on-delay time, and subtracting the second excessive on-delay time from the on-delay time Generating a second on-delay time, and the PWM signal And a step of generating a second gate signal based on the second on-delay time.

  The invention according to claim 12 is the dead time compensation method of the power conversion device according to claim 11, wherein a step of selecting a longer dead time out of the first dead time and the second dead time; Subtracting the selected dead time from an initial dead time value to generate an excessive on delay time; subtracting the excessive on delay time from the on delay time to generate a new on delay time; and Generating a first gate signal and a second gate signal based on the PWM signal and the new on-delay time.

According to the first to tenth aspects of the present invention, a dead time period in which both the switching elements of the arm are turned off with a simple, small and low cost circuit without adding a high voltage circuit and an insulating device. As a result, it is possible to provide a power device that can be controlled with an optimum dead time.
According to the invention described in claims 11 to 12, a dead time period in which both the switching elements of the arm are turned off with a simple, small and low cost circuit without adding a high voltage circuit and an insulating device. As a result, it is possible to provide a dead time compensation method for a power device that performs control with an optimum dead time.

    The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of dead time compensation of the power conversion device of the present invention, and is a diagram in which one arm of the inverter circuit of FIG. 2 is described in detail. In FIG. 1, 1 is a first switching element, 2 is a second switching element, 21 is a first gate resistance, 22 is a second gate resistance, 23 is a first gate drive, and 24 is a second gate drive. Reference numeral 25 denotes a dead time generator, and 26 denotes a gate signal generator. The first and second switching elements are composed of a set of diodes connected in reverse parallel to the IGBT or power MOSFET, or a single power MOSFET.
The gate signal generation unit generates the first gate signal G1 and the second gate signal G2 by providing an on-delay time for the PWM signal. The first gate drive amplifies the first gate signal G 1 and drives the switching element 1 through the first gate resistor 21. The second gate drive amplifies the second gate signal G 2 and drives the switching element 2 through the gate resistor 22. The dead time generator 25 includes a first dead time from when the second switching element is turned off to when the first switching element is turned on, and a second time from when the first switching element is turned off to when the second switching element is turned on. A dead time is generated from a change in the gate voltage of the second switching element.

FIG. 3 is a block diagram for explaining the block diagram of FIG. 1 in more detail. When the output current is flowing from the phase output terminal, when the switching element 2 is turned off and the first switching element 1 is turned on, the transistor mode current is passed through the first switching element 1 from the positive electrode of the DC power supply. Therefore, the output terminal voltage is close to the power supply positive electrode potential. At this time, a current flows into the gate-source capacitance Cgs of the second switching element 2 via the gate-drain capacitance Cgd and the Cgs is charged, so that a phenomenon in which the gate voltage rises appears. When the first switching element 1 is turned off, the return mode current flows from the negative electrode of the DC power source through the antiparallel diode of the second switching element 2 from the phase output terminal, so that the phase output terminal voltage is the source of the switching element. −Drain voltage Vsd lower than N potential. At this time, a charging current flows from N to the gate-source capacitance Cgs of the switching element 2 and is charged via the gate-drain capacitance Cgd, so that a phenomenon in which the gate voltage drops from the negative power supply potential appears. Assuming that the gate-source voltage of the second switching element 2 is Vgs and the drain-source voltage is Vds, the change in Vgs relative to the change in Vds can be expressed by equation (1).
ΔVgs = Cgd / (Cgs + Cgd) × ΔVds (1)
A change in the level of the first gate signal G1 and the second gate signal G2 and a change in the gate voltage of the switching element 2 corresponding thereto will be described with reference to the timing chart of FIG.

  The first gate signal G1 and the second gate signal G2 in FIG. 4 are commands to turn on the switching element when the signal level is “L”, and are commands to turn off when the signal level is “H”. First, when the second gate signal G2 is turned off on the time axis t0, the gate voltage NG of the second switching element 2 passes through the internal delay of the second gate drive 24 of FIG. 3 and the charging period of Cgs and Cgd of the second switching element. Descends to t2. When the first gate signal G1 is turned on between t1 and t3, the Cgs of the second switching element 2 is charged, so that the gate voltage NG once rises like t4. However, since the potential of the output GD2 of the second gate drive is “L”, Cgs is discharged through the second gate resistor 22 and reaches t5. Next, when the first gate signal G1 is turned off at t6, the phase output terminal becomes lower than the N potential by Vsd. At this time, Cgs of the second switching element 2 is charged through the power supply negative electrode and charged via Cgd, so that the phenomenon that the second gate voltage NG falls from the power supply negative electrode potential appears and reaches t8. When the second gate signal G2 is turned on between t7 and t9, the second gate voltage NG starts to increase from t10. Here, the period from t2 to t4 is the time from when the second switching element 2 is turned off until the first switching element 1 is turned on, and the period from t8 to t10 is the first period after the first switching element 1 is turned off. 2 is a time until the switching element 2 is turned on. If these times are measured and the measurement results can be reflected in the first gate signal G1 and the second gate signal G2, optimum dead time control can be performed. Means for measuring the time in the section from t2 to t4 and the section from t8 to t10 will be described with reference to FIG.

  FIG. 5 is a block diagram of a dead time generation unit that generates the first dead time and the second dead time from the waveform change of the gate voltage of the second switching element. In FIG. 5, 31 is a first comparator, 32 is a second comparator, 33 is a first variable threshold unit, 34 is a second variable threshold unit, 35 is a first time counter, 36 is a second time counter, and 37 is A clock generation unit 38 is a first count enable unit, and 39 is a second count enable unit. The first comparator 31 detects a section from t2 to t4, and the second comparator 32 detects a section from t8 to t10. In the first comparator 31, the threshold value at which the output becomes “L” is set high, and the threshold value at which “H” is set low. The first threshold value indicated in the gate voltage NG in FIG. 4 is a threshold value that is “L”, and the second threshold value is a threshold value that is “H”. In order to detect only the timing of t2 and t4, the fall of the gate voltage NG at t2 and the rise of the gate voltage NG at t4 are detected, but not at the time of the voltage drop at t5. In the second comparator 32, the threshold value at which the output becomes “H” is set low, and the threshold value at which “L” is set high. The third threshold value indicated by NG in FIG. 4 is a threshold value that is “H”, and the fourth threshold value is a threshold value that is “L”. The third threshold value is set to detect a gate voltage that appears only at t8, and the third and fourth threshold values are set so that only the timings t8 and t10 can be detected. The timings t2 and t4 are input to the count enable 38 and the count enable 39 as the output NGOFF of the first comparator 31 and the timings t8 and t10 are output NGON of the second comparator 34, respectively. The first count enable 38 monitors the levels of NGOFF, G1, and G2, and starts counting by the first time counter 35 when a certain condition is satisfied, and counts the first time counter 35 when a certain condition is satisfied. Stop. The second count enable 39 monitors the levels of NGON, G1, and G2, starts counting by the second time counter 36 when a certain condition is satisfied, and counts the second time counter 36 when a certain condition is satisfied. Stop. The time counters 35 and 36 count according to the clock 37, and the count values represent the first dead time and the second dead time, respectively.

The gate signal generation unit generates a first excessive on-delay time by subtracting the first dead time from the initial dead time, and generates a first on-delay time by subtracting the first excessive on-delay time from the on-delay time. To do. Next, a first gate signal is generated based on the PWM signal and the first on-delay time, and a second excess on-delay time is generated by subtracting the second dead time from the dead time initial value. Next, a second excessive on delay time is subtracted from the on delay time to generate a second on delay time, and a second gate signal is generated based on the PWM signal and the second on delay time.
The gate signal generation unit can also be configured as follows. The longer dead time is selected from the first dead time and the second dead time, and the selected dead time is subtracted from the initial dead time value to generate the excessive on-delay time. Next, a new on-delay time is generated by subtracting the excessive on-delay time from the on-delay time, and a first gate signal and a second gate signal are generated based on the PWM signal and the new on-delay time.

  FIG. 6 is a flowchart illustrating a first dead time compensation method according to the present invention. The first dead time from the time when the second switching element 2 is turned on to the time when the second switching element 2 is turned on is shown in FIG. Generate dead time. In step SA1, it is determined whether or not the second switching element is turned off. If turned off, the process proceeds to step SA2. Counting is started in step SA2, and in step SA3, it is checked whether the command of the first gate signal G1 is turned on. In step SA4, the counter is compared with the default value. If the default value is exceeded, the process proceeds to step 9, and if smaller than the default value, the process proceeds to step 5. In step SA5, it is determined whether or not a gate floating voltage appears in which the gate voltage NG has risen above the off voltage. If it appears, the process proceeds to step SA6. In step SA6, the count is stopped and the process proceeds to step SA7. In step SA7, the counter value is read, and in step SA8, FLG1 = 0 is set. In step SA9, the counter is cleared and the process proceeds to step SA8. As described above, the timings t2 and t4 in FIG. 4 are determined based on the level of the output NGOFF of the first comparator 31. However, since the determination is performed while also viewing the levels of the first gate signal G1 and the second gate signal G2, it is ensured. The on / off timing of the switching element can be determined. By counting the time from t2 to t4 with the first time counter 35, a dead time from when the second switching element 2 is turned off to when the first switching element 1 is turned on can be generated. If this dead time is reflected in the timings of the first gate signal G1 and the second gate signal G2, the time during which both switching elements are simultaneously turned off can be shortened as much as possible, and the optimum dead time can be controlled. In addition, in the control of the switching element, there is a case where the switching element is always turned on or off for a time longer than the carrier cycle. During this control period, a change such as the gate voltage at t4 does not appear for each carrier cycle, so a certain constant. If the default value is exceeded, the count value is cleared and the dead time time calculation process is terminated.

FIG. 7 is a flowchart showing the second dead time compensation method according to the present invention. The second dead time from the time when the first switching element 1 is turned on to the time when the second switching element 2 is turned on is shown in FIG. Generate dead time. In step SB1, it is determined whether or not the first switching element is turned off. If turned off, the process proceeds to step SB2. In step SB2, the counter is started, and in step SB3, it is checked whether the command of the second gate signal G2 is turned on.
In step SB4, it is determined whether the counter value is smaller than the default value. If it is smaller, the process proceeds to step SB5, and if larger, the process proceeds to step SB9. In step SB5, it is determined whether or not the gate voltage NG has started to increase from what has been reduced to the reflux mode voltage, and if it has started to increase, the process proceeds to step SB6. In step SB6, the count ends. In step SB7, the contents of the counter are read. In step SB7, the flag FLG2 is set to 0, and the process ends. In step SB9, the counter is cleared and the process proceeds to step SB8. As described above, the timing of t8 and t10 in FIG. 4 is determined from the level of the output NGON of the second comparator 32. However, since the determination is also made while observing the levels of the first gate signal G1 and the second gate signal G2, switching is surely performed. The on / off timing of the element can be determined. By counting the time from t8 to t10 by the second time counter 36, a dead time from when the first switching element 1 is turned off to when the second switching element 2 is turned on can be generated. If this dead time is reflected in the timings of the first gate signal G1 and the second gate signal G2, the time during which both switching elements are simultaneously turned off can be shortened as much as possible, and the optimum dead time can be controlled. Further, in the control of the switching element, there is a case where the switching element is always turned on or off for a time longer than the carrier cycle, and a change such as the gate voltage from t8 to t10 does not appear every carrier cycle in this control period. When a certain default value is exceeded, the count value is cleared and the calculation process of the dead time is terminated.

FIG. 8 is a logic circuit that implements the count enable unit of FIG. When the second switching element 2 is off, the NGOFF signal is “L”, and the first count enable signal CE1 generated by the first count enable unit is “H”. When the first switching element 1 is turned on, the NGOFF signal is “H”, and the first enable signal CE1 generated by the first count enable unit is “L”. If the CE1 signal is taken into the operator and the time from “H” to “L” is counted, the count value is the first dead time from when the second switching element 2 is turned off to when the first switching element 1 is turned on. Become.
When the first switching element 1 is off, the NGON signal is “H”, and the second count enable signal CE2 generated by the second count enable unit is “H”. When the second switching element 2 is on, the NGON signal is “L”, and the second count enable signal CE2 generated by the second count enable unit is “L”. If the CE2 signal is taken into the operator and the time from “H” to “L” is counted, the count value is calculated as the second dead time from the first switching element 1 to the second switching element 2 being turned on. Become. If the clock is counted when the count enable is valid, the time counter becomes dead time.

  As described above, according to the present invention, the dead time can be compensated with a simple, low-cost and small circuit, and it is not necessary to add a high voltage circuit and an insulating device, so that the apparatus can be miniaturized.

  The present invention can be applied to a servo drive device, an inverter device, or a general switching power source used for a machine tool, a robot, a general industrial machine, or the like.

Block diagram of dead time compensation showing an embodiment of the present invention Inverter circuit block diagram incorporating dead time compensation according to an embodiment of the present invention Explanation of the principle that the gate voltage of the switching element 2 changes Timing chart showing change of gate voltage of switching element 2 The block diagram which showed the gate voltage detection circuit of the Example of this invention in detail Operator dead time calculation flowchart 1 Operator dead time calculation flowchart 2 Logic circuit block diagram with part of the operator's dead time calculation replaced with hardware Block diagram of dead timeless in the first conventional technology

Explanation of symbols

1-6 First to sixth switching elements 7-9 Arm 10 First to sixth gate drives 11 Dead time generator 12 Gate signal generators 21, 22 First and second gate resistors 23, 24 First, second Gate drive 25 Dead time generation unit 26 Gate signal generation unit 31, 32 First and second comparators 33 and 34 First and second variable threshold units 35 and 36 First and second time counters 37 Clock 38 and 39 Count enable Part

Claims (12)

One end of the first switching element and one end of the second switching element are connected in series at a phase output terminal, the other end of the first switching element and a positive electrode of a DC power source are connected, and the other end of the second switching element and the A power conversion apparatus in which a negative electrode of a direct current power source is connected, wherein an on-delay time is provided in a PWM signal that alternately drives the first switching element and the second switching element, and the first gate signal and the second gate signal are provided. A gate signal generator for generating, a first gate drive for amplifying the first gate signal to drive the first switching element, and a second gate for amplifying the second gate signal to drive the second switching element. A power conversion device including a drive,
Based on the gate voltage of the second switching element, a first dead time from when the second switching element is turned off to when the first switching element is turned on, and after the first switching element is turned off, A dead time generating unit that generates a second dead time until the two switching elements are turned on;
The gate signal generation unit varies an on-delay time of the first switching element and an on-delay time of the second switching element based on the first dead time and the second dead time. apparatus.   The power converter according to claim 1, wherein the first switching element and the second switching element are a set of diodes connected in antiparallel to the IGBT.   The power converter according to claim 1, wherein the first switching element and the second switching element are a set of diodes connected in antiparallel with a power MOSFET.   The dead time generation unit is defined as a time from the time when the gate voltage is lowered from the on-gate voltage to the off-gate voltage until the time when the gate floating voltage generated when the first switching element is turned on starts to appear as the first dead time. The power conversion device according to claim 1, wherein:   The dead time generating unit sets the second dead time as a time from when the gate voltage is turned to a reflux mode gate voltage when the first switching element is turned off to when the gate voltage is changed to an on-gate voltage. Item 4. The power conversion device according to Item 1. The dead time generation unit includes a first comparator that compares the gate voltage with a threshold voltage, a first variable threshold unit that changes the threshold voltage in conjunction with a change in the output of the first comparator, A first count enable unit that generates a first count enable signal based on an output of one comparator, the first gate signal, and the second gate signal, and a first time counter that counts a clock according to the count enable,
The power conversion device according to claim 1, wherein a count value of the first time counter is a first dead time. The dead time generation unit includes a second comparator that compares the gate voltage with a threshold voltage, a second variable threshold unit that changes the threshold voltage in conjunction with a change in the output of the second comparator, A second count enable unit that generates a second count enable signal based on the output of the two comparators, the first gate signal, and the second gate signal, and a second time counter that counts a clock according to the count enable,
The power conversion device according to claim 1, wherein a count value of the second time counter is set as a second dead time.   The gate signal generation unit generates a first excess on-delay time by subtracting a first dead time from a dead time initial value, and subtracts the first excess on-delay time from the on-delay time. The power converter according to claim 1, wherein time is generated, and a first gate signal is generated based on the PWM signal and the first on-delay time.   The gate signal generation unit generates a second excessive on-delay time by subtracting a second dead time from an initial dead time value, and subtracts the second excessive on-delay time from the on-delay time. The power converter according to claim 1, wherein time is generated, and a second gate signal is generated based on the PWM signal and the second on-delay time.   The gate signal generation unit selects a longer dead time of the first dead time and the second dead time, and subtracts the selected dead time from an initial dead time value to obtain an excessive on-delay time. And generating a new on-delay time by subtracting the excess on-delay time from the on-delay time, and generating the first gate signal and the second gate signal based on the PWM signal and the new on-delay time. The power converter according to claim 1, wherein the power converter is generated. One end of the first switching element and one end of the second switching element are connected in series at a phase output terminal, the other end of the first switching element and a positive electrode of a DC power source are connected, and the other end of the second switching element and the A power conversion apparatus in which a negative electrode of a direct current power source is connected, wherein an on-delay time is provided in a PWM signal that alternately drives the first switching element and the second switching element, and the first gate signal and the second gate signal are provided. A gate signal generator for generating, a first gate drive for amplifying the first gate signal to drive the first switching element, and a second gate for amplifying the second gate signal to drive the second switching element. Based on the drive and the gate voltage of the second switching element, the first switching element is turned on after the second switching element is turned off. And a dead time generation unit that generates a second dead time from when the first switching element is turned off to when the second switching element is turned on. In the time compensation method,
Enabling the time counter upon confirming that the second switching element is turned off;
Disabling the time counter when a gate floating voltage generated when the first switching element is turned on begins to appear;
Setting the count value of the time counter as a first dead time;
Subtracting a first dead time from the initial dead time value to generate a first excess on-delay time;
Subtracting the first excess on-delay time from the on-delay time to generate a first on-delay time;
Generating a first gate signal based on the PWM signal and the first on-delay time;
Enabling a time counter when a reflux mode gate voltage appears when the gate voltage appears when both the first switching element and the second switching element are off;
Disabling the time counter when the gate voltage begins to rise above the reflux mode gate voltage;
Setting the count value of the time counter as a second dead time;
Subtracting a second dead time from the initial dead time value to generate a second excess on-delay time;
Subtracting the second excessive on-delay time from the on-delay time to generate a second on-delay time;
Generating a second gate signal based on the PWM signal and the second on-delay time;
A dead time compensation method for a power conversion device, comprising: Selecting the longer dead time of the first dead time and the second dead time;
Subtracting the selected dead time from an initial dead time value to generate an excessive on-delay time;
Subtracting the excess on-delay time from the on-delay time to generate a new on-delay time;
Generating a first gate signal and a second gate signal based on the PWM signal and the new on-delay time;
The dead time compensation method for a power converter according to claim 11, comprising:

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