JP2010016423A - Distortion compensation circuit - Google Patents

Abstract

Disclosed is a distortion compensation circuit in which the mutual timing of an input signal and an output signal can be matched with a configuration as simple as possible.
A model estimation unit 2 for estimating a model representing input / output characteristics of an amplifier 10 and distortion compensation for performing distortion compensation for canceling distortion of the input / output characteristics of the amplifier 10 by adding an inverse model to the input signal to the input signal. In the distortion compensation circuit 1 including the unit 4, the peak comparison unit 9 that detects the occurrence of a peak value for each of the input signal and the output signal of the amplifier 10 and detects the time difference in which they appear, and the amount corresponding to the time difference A delay adjustment unit 5 is provided for providing the delayed input signal to the model estimation unit 2.
[Selection] Figure 1

Description

  The present invention relates to a distortion compensation circuit having a function of compensating for nonlinear characteristics of a high-power amplifier used in, for example, a radio transceiver.

In general, a high power amplifier (HPA) has low linearity of input / output characteristics. Therefore, when power is amplified using such an amplifier, a desired output may not be obtained due to distortion of input / output characteristics. Therefore, as a distortion compensation method for compensating such distortion, a reverse distortion characteristic opposite to the distortion characteristic of the amplifier is generated by digital signal processing for the input signal of the amplifier and added to the input of the amplifier. A technique for obtaining a desired amplifier output by performing DPD (Digital Pre-Distortion) processing has been proposed (for example, see Non-Patent Document 1).
In addition, it has been proposed to perform distortion compensation represented by a polynomial in order to perform highly accurate DPD processing on a high-power amplifier that amplifies a broadband signal (see, for example, Patent Document 1).

  On the other hand, there are an AM-AM characteristic related to amplitude and an AM-PM characteristic related to phase as indices indicating nonlinearity in the input / output characteristics of the amplifier. In order to accurately grasp these characteristics, the timings of the input signal and the output signal to be compared with each other must match on the time axis.

FIG. 4 is an example of a waveform diagram showing a timing shift between an input signal to an amplifier and an output signal in a conventional distortion compensation circuit. (A), (b) is the waveform (same) of an input signal, (c) is a waveform of an output signal. In the input signal shown in (a), for example, a peak value appears at time τ ₁ . The peak value of the output signal (c) corresponding to this appears at time τ ₂ later than τ ₁ . When the input signal shown in (b) and the output signal shown in (c) are received at the timing of τ ₂ , as shown in (d), the input signal and the output signal Will receive. Such a timing shift is caused by a difference in the signal path, and the output signal becomes slower. Therefore, a means for adjusting the delay amount of the input signal is required.

Thesis by Lei Ding, "Digital predistortion of power amplifiers for wireless application", Georgia institute of Technology, March 2004 JP 2007-282066 A Japanese Patent No. 4014343

  In order to adjust the delay amount as described above, for example, a digital delay circuit may be provided on the signal path and the delay time may be manually adjusted. However, such adjustment is very complicated, and adjustment with high accuracy is difficult. On the other hand, in order to obtain high accuracy, it is preferable from the viewpoint of shortening the adjustment time and reducing the manufacturing cost to provide a large adjustment device using a complex arithmetic processing such as a correlation function (see, for example, Patent Document 2). Absent. In addition, the correlation function method has a problem that the correlation result cannot be set to a constant value depending on how to take in data sampled for digital circuit processing due to white noise remaining after distortion convergence. That is, the amount of delay deviation is not fixed.

  In view of such a conventional problem, an object of the present invention is to provide a distortion compensation circuit in which the mutual timing of an input signal and an output signal can be matched with a configuration as simple as possible.

  A distortion compensation circuit according to the present invention includes a model estimation unit that estimates a model representing input / output characteristics of an amplifier, and distortion compensation that cancels distortion of the input / output characteristics of the amplifier by adding an inverse model to the input signal to the input signal. A distortion compensator for detecting the occurrence of a peak value for each of the input signal and output signal of the amplifier, and a peak comparator for detecting a time difference in which they appear, and the input signal delayed by the time difference And a delay adjustment unit that provides the model estimation unit.

  In the distortion compensation circuit configured as described above, the input signal is delayed by the time difference at which the peak value appears in the input signal and the output signal, respectively, so that the mutual timing of the input signal and the output signal can be matched. it can. Further, since it is easy to detect the appearance of the peak value and it is easy to delay by the time difference, a simple configuration is sufficient for the peak comparison unit and the delay adjustment unit.

In the distortion compensation circuit, the input signal and the output signal are preferably digital communication signals.
In a signal for digital communication, a peak appears almost certainly within a predetermined period, and this can be used to match the timings of the input signal and the output signal.

  According to the distortion compensation circuit of the present invention, a distortion compensation circuit capable of matching the timings of the input signal and the output signal can be provided with a simple configuration.

  FIG. 1 is a block diagram showing a main part of a distortion compensation circuit 1 according to an embodiment of the present invention. The distortion compensation circuit 1 is a model representing the input / output characteristics of a high-power amplifier (HPA, hereinafter simply referred to as an amplifier) 10 (specifically, the output signal Y is expressed in the form of a polynomial of the nth power series of the input signal X). The model estimation unit 2 for estimating the model), the coefficient table 3 for temporarily storing the model coefficients, and the inverse model (inverse function of the model) for the model are added to the input signal X so that the amplifier 10 is turned on. And a distortion compensation unit 4 that performs distortion compensation that cancels out distortion of the output characteristics.

  The distortion compensation circuit 1 detects the appearance of a peak value for each of the input signal and the output signal of the amplifier 10 and detects the time difference in which they appear, and the input delayed by the time difference. And a delay adjustment unit 5 that provides a signal to the model estimation unit 2. The peak comparison unit 9 includes a peak detection unit 6 that detects the peak value of the input signal X and the current output time point, a peak value detection unit 8 that detects the peak value of the output signal Y and the current output time point, and two peak detection units 6. , 8 and a time difference detection unit 7 for detecting a time difference at the present time of peak value output. The model estimation unit 2, the coefficient table 3, the distortion compensation unit 4, the delay adjustment unit 5, and the peak comparison unit 9 are configured by, for example, a DSP (Digital Signal Processor).

The nonlinear characteristic of the amplifier 10 is expressed by a power series polynomial of the input signal X. That is, when the output signal is Y, it can be expressed as follows. Note that a _i is a coefficient of each order.

  FIG. 2 is a flowchart showing processing in the distortion compensation circuit 1. This process is executed periodically. After the start of processing, the peak detectors 6 and 8 both determine whether or not a peak value has been detected (step S1), and if “No”, wait for the peak value to appear. Since the peak value is known in advance, the appearance of the peak value can be easily detected by comparing with the threshold value. For example, if threshold value = peak value is set, the time when the threshold value is reached is the time when the peak value appears. Further, if a value slightly smaller than the peak value is set as the threshold value, an intermediate point between the time point when the value becomes equal to or higher than the threshold value and the time point after that becomes the threshold value or less can be set as the time point when the peak value appears. If this method is used, even if data values sampled for digital circuit processing vary due to white noise remaining after distortion convergence, the peak value does not deviate greatly.

  The signal peak is always included in a signal for digital communication such as W-CDMA and OFDM, and appears with a substantially constant probability. Therefore, the peak value can be detected if the signal is acquired by sampling a predetermined number of times.

When the time points τ _X and τ _{Y at} which the peak values appear for the input signal X and the output signal Y are obtained, the time difference is obtained by the time difference detection unit 7 as τ _Y −τ _X. In accordance with this time difference, the delay adjustment unit 5 adjusts the delay of the input signal X (step S2). The delay adjustment is performed so that the time difference becomes 0 (or within a predetermined value close to 0). When the time difference becomes 0 (“Yes” in step S3), the input signal X thus adjusted for delay and the output are output. Model estimation by the model estimation unit 2 is performed with the signal Y (step S4). After model estimation, the coefficients are temporarily stored in the coefficient table 3. The distortion compensation unit 4 estimates an inverse model using these coefficients and performs distortion compensation (step S5).

  In addition to the above, the model estimation unit 2 may obtain the inverse model and store the coefficients in the coefficient table 3, and the distortion compensation unit 4 may perform distortion compensation while referring to the coefficient table 3. Good.

FIG. 3 is a graph showing an example of input / output signal waveforms. (A) is the waveform of the input signal X, and (b) is the waveform of the output signal Y. In the waveform of the input signal X, for example, a peak value appears at time τ ₁ . The peak value of the output signal Y corresponding to this appears at time τ ₂ . When the time difference (τ ₂ −τ ₁ ) is adjusted by the delay adjustment unit 5, the input signal X is shifted in the delay direction by the time difference and provided to the model estimation unit 2. Therefore, in the model estimation unit 2, the timings of the input signal X and the output signal Y coincide with each other as shown in (c).

  As described above, in the distortion compensation circuit 1 according to the present embodiment, the input signal is delayed by the time difference at which the peak values appear in the input signal and the output signal, respectively. Therefore, the mutual timing between the input signal and the output signal Can be combined. Further, since it is easy to detect the appearance of the peak value and it is easy to delay by the time difference, the peak comparison unit 9 and the delay adjustment unit 5 need only have a simple configuration. That is, the distortion compensation circuit 1 capable of matching the timings of the input signal and the output signal can be provided with a simple configuration.

  In the distortion compensation circuit, since the input signal and the output signal are signals for digital communication, a peak appears almost certainly within a predetermined period. It is convenient in that the timing of each other can be matched.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined not by the above-mentioned meaning but by the scope of claims for patent, and is intended to include all modifications within the scope and meaning equivalent to the scope of claims for patent.

It is a block diagram which shows the principal part of the distortion compensation circuit which concerns on one Embodiment of this invention. It is a flowchart which shows the process in the distortion compensation circuit of FIG. It is a wave form diagram which shows the shift | offset | difference and adjustment of the timing of an input signal and an output signal. It is a wave form diagram which shows the shift | offset | difference of the timing of the input signal and output signal to an amplifier in the conventional distortion compensation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Distortion compensation circuit 2 Model estimation part 3 Coefficient table 4 Distortion compensation part 5 Delay adjustment part 6 Peak detection part 7 Time difference detection part 8 Peak detection part 9 Peak comparison part 10 Amplifier

Claims (2)

A model estimation unit for estimating a model representing the input / output characteristics of the amplifier;
A distortion compensation unit that performs distortion compensation to cancel distortion of input and output characteristics of the amplifier by adding an inverse model to the input signal to the input signal;
Detecting the appearance of peak values for each of the input signal and output signal of the amplifier, and detecting a time difference in which they appear;
A distortion compensation circuit comprising: a delay adjustment unit that provides the input signal delayed by the time difference to the model estimation unit.   The distortion compensation circuit according to claim 1, wherein the input signal and the output signal are signals for digital communication.

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