JP2010010382A - Semiconductor device and its method for manufacturing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with strained silicon technology exhibiting effects applied even in a microfabricated structure, and its method for manufacturing. <P>SOLUTION: The semiconductor device includes a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate insulation film, a channel region formed under the gate insulation film in the semiconductor substrate, a strain applying layer containing a first layer formed on both sides of the channel region and a second layer located in a lower layer of the first layer and having an edge toward the center of the gate electrode closer to the center of the gate electrode than the first layer for causing strain in the channel region, and a source-drain region formed on both sides of the channel region so that at least part of it overlaps the strain applying layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  As a conventional semiconductor device, a semiconductor device in which strain is generated by applying tensile stress to the channel region by epitaxially growing a Si: C crystal having a lattice constant smaller than that of the Si crystal at a position sandwiching the channel region of the n-type transistor. (For example, refer to Patent Document 1). According to the semiconductor device described in Patent Document 1, tensile strain is generated in the Si crystal constituting the channel region, thereby improving the mobility of electrons in the channel region and improving the operation speed of the n-type transistor. be able to. Such a technique for generating strain in the channel region to improve the charge mobility in the channel region is called a strained silicon technology.

However, according to the semiconductor device described in Patent Document 1 and the like, when the semiconductor device is miniaturized, the volume of the Si: C crystal is also reduced, and there is a possibility that the distortion generated in the channel region becomes insufficient.
US Pat. No. 6,621,131

  An object of the present invention is to provide a semiconductor device to which a strained silicon technique that exhibits an effect even in a miniaturized structure is applied, and a manufacturing method thereof.

  One embodiment of the present invention includes a semiconductor substrate, a gate electrode formed over the semiconductor substrate with a gate insulating film interposed therebetween, a channel region formed under the gate insulating film in the semiconductor substrate, and the channel region A first layer formed on both sides of the first layer, and a second layer positioned below the first layer, the end of the gate electrode being closer to the center of the gate electrode than the first layer And a strain applying layer for generating strain in the channel region, and a source / drain region formed on both sides of the channel region so as to at least partially overlap the strain applying layer.

  According to another aspect of the present invention, a step of forming a gate electrode on a semiconductor substrate through a gate insulating film and anisotropic etching are performed in regions separated from the gate electrode on both sides of the gate electrode of the semiconductor substrate. Forming a first trench, and covering the inner surface of the first trench with a sidewall mask, and then performing isotropic etching to form a gate electrode in a region under the first trench of the semiconductor substrate. A step of forming a second trench in which the position of the end portion on the center side is closer to the center of the gate electrode than the first trench, and after removing the side wall mask, the first and first And a step of growing a crystal having a lattice constant different from that of the crystal constituting the semiconductor substrate in a trench of 2.

  According to the present invention, it is possible to provide a semiconductor device to which a strained silicon technique that exhibits an effect even in a miniaturized structure is applied, and a manufacturing method thereof.

[First Embodiment]
(Configuration of semiconductor device)
FIG. 1A is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention. The semiconductor device includes a semiconductor substrate 1, a gate electrode 6 formed on the semiconductor substrate 1 via a gate insulating film 6, a channel region 4 formed below the gate insulating film 6 in the semiconductor substrate 1, and a channel region. 4, a strain applying layer 2 that generates strain in the channel region 4, a source / drain region 3 that is formed on both sides of the channel region 4 so as to at least partially overlap the strain applying layer 2, Have

  An offset spacer 6 is formed on the side surface of the gate electrode 6, and a gate sidewall 8 is formed on the side surface of the offset spacer 6. A silicide layer 9 and a silicide layer 10 are formed on the upper surfaces of the strain imparting layer 2 and the gate electrode 6, respectively.

  As the semiconductor substrate 1, for example, a Si substrate whose principal surface has a {100} or {110} plane orientation can be used. Note that {100} represents a plane orientation equivalent to (100) and (100). The same applies to {110}.

The gate insulating film 5 is made of, for example, SiO ₂ , SiON, or a high dielectric material (for example, Hf-based materials such as HfSiON, HfSiO, and HfO, Zr-based materials such as ZrSiON, ZrSiO, and ZrO, and Y-based materials such as Y ₂ O _3. ).

The gate electrode 6 is made of, for example, Si-based polycrystal such as polycrystal Si or polycrystal SiGe containing a conductive impurity. B, BF ₂ or the like is used as the p-type conductivity type impurity, and As, P or the like is used as the n-type conductivity type impurity. Further, the gate electrode 6 may be a metal gate electrode made of W, Ta, Ti, Hf, Zr, Ru, Pt, Ir, Mo, Al, or the like, or a compound thereof. Layer 10 is not formed. Moreover, the structure which laminated | stacked the metal gate electrode and the polycrystal Si-type electrode may be sufficient.

  For example, when the surface orientation of the main surface of the semiconductor substrate 1 is {100}, the channel region 4 is formed so that the channel direction is <100> or <110>. When the surface orientation of the main surface of the semiconductor substrate 1 is {110}, the channel direction is <110> or <111 ′>. Note that <111 '> indicates a direction in which <110> is rotated by 45 ° in the {110} plane. In such a case, when an extension strain occurs in the channel direction, the mobility of electrons in the channel region 4 is improved, and when a compressive strain occurs in the channel direction, the mobility of holes in the channel region 4 is improved. Note that <100> represents a direction equivalent to [100] and [100]. The same applies to <110> and <111 '>.

  The strain imparting layer 2 is positioned below the first layer 2a and the first layer 2a, and the position of the end portion on the gate electrode center (center position in the gate length direction of the gate electrode) side is the first layer 2a. A second layer 2b closer to the center of the gate electrode.

  The first and second layers 2a and 2b are made of crystals having a lattice constant different from that of the crystals constituting the semiconductor substrate. For example, when the semiconductor substrate 1 is made of Si crystal, SiGe crystal, Si: C crystal, or the like can be used as the material of the first and second layers 2a and 2b. When the SiGe crystal is used, since the lattice constant of the SiGe crystal is larger than that of the Si crystal, compressive strain is generated in the channel region 4 made of the Si crystal, and the mobility of holes in the channel region 4 can be improved. . Further, when a Si: C crystal is used, the Si: C crystal has a lattice constant smaller than that of the Si crystal. Therefore, an elongation strain is generated in the channel region 4 made of the Si crystal, and the mobility of electrons in the channel region 4 is increased. Can be improved.

  When SiGe crystal or Si: C crystal is used as the first and second layers 2a and 2b, the Ge concentration of the SiGe crystal is 10 to 30 atomic%, and the C concentration of the Si: C crystal is 1 to 3 atomic%. Preferably there is. When the Ge concentration of the SiGe crystal is less than 10 atomic%, the strain applied to the channel region is insufficient, and when it exceeds 30 atomic%, a crystal defect may be caused in the substrate or the like, leading to leakage current. Further, when the C concentration of the Si: C crystal is less than 1 atomic%, the strain applied to the channel region is insufficient, and when it exceeds 3 atomic%, a crystal defect is caused in the substrate and the like, causing a leakage current. There is a fear.

The source / drain region 3 is formed, for example, by implanting conductive impurities into the surface of the semiconductor substrate 1 using an ion implantation method. B, BF ₂ or the like is used as the p-type conductivity type impurity, and As, P or the like is used as the n-type conductivity type impurity.

The offset spacer 7 is made of an insulating material such as SiO ₂ or SiN, for example. The gate sidewall 8 is made of an insulating material such as SiN. Further, it may be a two-layer structure made of a plurality of types of insulating materials such as SiN, SiO ₂ , TEOS (Tetraethoxysilane), or a structure having three or more layers.

  The silicide layers 9 and 10 are made of, for example, a compound of metal such as Ni, Pt, Co, Er, Y, Yb, Ti, Pd, NiPt, and CoNi and Si.

FIG. 1B is a cross-sectional view showing the dimensions of each part of the strain imparting layer 2. As shown in FIG. 1B, the thicknesses of the first and second layers 2a and 2b of the strain imparting layer 2 are Y ₁ and Y ₂ , respectively. Further, the positions of the end portions of the first and second layers 2a and 2b on the center side of the gate electrode are E ₁ and E ₂ , respectively, and the distance in the gate length direction of E ₁ and E ₂ is X. Also, the gate length direction of the position of the gate electrode center and E _0. In FIG. 1B, illustration of the source / drain region 3 and the silicide layer 9 is omitted.

2 (a) and 2 (b) show the relationship between the compressive stress in the channel direction generated in the channel region 4 and the thicknesses of the first and second layers 2a and 2b of the strain imparting layer 2 obtained by simulation, and 6 is a graph showing the relationship between the compressive stress in the channel direction generated in the channel region 4 and the difference in the position of the end of the first and second layers 2a, 2b on the gate electrode center side. As the stress generated in the channel region 4 increases, the strain increases and the charge mobility increases. Here, as simulation conditions, the gate length is 28 nm, the distance between E ₀ and E ₁ is 39 nm, the sum of Y ₁ and Y ₂ is 100 nm, the width in the gate length direction of the first layer 2a is 42 nm, the second The width of the layer 2b in the gate length direction was set to 42 + 2X nm, and the magnitude of the compressive stress at a position at a depth of 2 nm from the boundary between the semiconductor substrate 1 and the gate insulating film 5 in the center of the gate electrode was calculated. The semiconductor substrate 1 was made of Si crystal, and the first and second layers 2a and 2b were made of SiGe crystal having a Ge concentration of about 20 atomic%.

In the graph of FIG. 2A, the horizontal axis represents the thickness Y ₁ of the first layer 2 a of the strain imparting layer 2, and the vertical axis represents the magnitude of the compressive stress in the channel direction generated in the channel region 4. Here, X was fixed at 30 nm. 2 (a) is, but almost no change in the magnitude of the compressive stress in the range greater than Y ₁ is about 20nm, the range Y ₁ is about 20nm or less, abruptly size of a compressive stress approaching 10nm It shows that it increases. Note that it is difficult in the manufacturing process to make Y ₁ smaller than 10 nm.

From this result, Y ₁ is preferably in the range of 10 nm ≦ Y ₁ ≦ 20 nm. That is, Y ₁ is preferably 10% or more and 20% or less of the total of Y ₁ and Y ₂ .

In the graph of FIG. 2B, the horizontal axis represents the distance X between E ₁ and E ₂ , and the vertical axis represents the magnitude of the compressive stress in the channel direction generated in the channel region 4. Here, _{Y 1} was fixed at 10 nm. FIG. 2B shows that the maximum value of X is about 20 nm, and the range in which a larger compressive stress is generated than when X is 0 is approximately 0 <X <33 nm. Note that the case where X is 0 is a case where E ₀ and E ₁ are equal, and corresponds to a structure of a semiconductor device in which charge mobility is improved by generating distortion in a conventional channel region.

From this result, X is preferably in the range of 0 <X <33 nm. That, X is greater than the ratio (X / _{Y 1)} are 0 and _{Y 1,} preferably in the range smaller than 3.3.

Further, as a result of calculating the tensile stress generated in the channel region 4 under the same conditions by replacing the SiGe crystal with a Si: C crystal having a C concentration of about 2 atomic%, as in the case of the SiGe crystal, Y _{1, Y 1} and _{Y 2} in total more than 10%, preferably at most 20%, X is greater than the ratio (X / _{Y 1)} are 0 and _{Y 1,} range smaller than 3.3 It was found to be preferable.

(Manufacture of semiconductor devices)
3A (a) to 3 (d) and FIGS. 3B (e) to (h) are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the present invention.

  First, as shown in FIG. 3A, a gate insulating film 5, a gate electrode 6, a cap layer 11, an offset spacer 7, and dummy sidewalls 12 are formed on a semiconductor substrate 1, and source / drain regions are formed in the semiconductor substrate 1. The extension region 3a of the region 4 is formed.

  Here, each of these members is formed by the following method, for example. First, after each material film of the gate insulating film 5, the gate electrode 6, and the cap layer 11 is laminated on the semiconductor substrate 1 by a CVD method or the like, these material films are formed by a lithography method, an RIE (Reactive Ion Etching) method, or the like. Then, the gate insulating film 5, the gate electrode 6, and the cap layer 11 are formed.

  Next, after forming a material film of the offset spacer 7 on the entire surface of the semiconductor substrate 1 by using the CVD method or the like, etching is performed by the RIE method or the like to thereby form the gate insulating film 5, the gate electrode 6, and An offset spacer 7 covering the side surface of the cap layer 11 is formed.

  Next, using the cap layer 11 and the offset spacer 7 as a mask, a conductive impurity is implanted into the surface of the semiconductor substrate 1 by an ion implantation method or the like to form an extension region 3a.

  Next, a material film for the dummy side wall 12 is formed on the entire surface of the semiconductor substrate 1 by using the CVD method or the like, and then etched by the RIE method or the like to thereby form the dummy side wall 12 that covers the side surface of the offset spacer 7. Form. Here, as the material of the dummy sidewall 12, the same material as that of the gate sidewall 8 can be used.

  Next, as shown in FIG. 3A (b), the trench 13a is formed by etching the semiconductor substrate 1 by the RIE method or the like using the cap layer 11, the offset spacer 7 and the dummy sidewall 12 as a mask. In a later step, the first layer 2a of the strain imparting layer 2 is formed in the trench 13a.

Next, as shown in FIG. 3A (c), a film made of SiO ₂ or the like is formed on the entire surface of the semiconductor substrate 1 and then etched by the RIE method or the like to cover the inner side surface of the trench 13. Sidewall mask 14 is formed.

  Next, as shown in FIG. 3A (d), isotropic etching such as RIE is performed on the semiconductor substrate 1 using the cap layer 11, the offset spacer 7, the dummy sidewall 12, and the sidewall mask 14 as a mask. A trench 13b is formed under the trench 13a, the end of the gate electrode at the center side being closer to the center of the gate electrode than the trench 13a. In the later step, the second layer 2b of the strain imparting layer 2 is formed in the trench 13b.

  Next, as shown in FIG. 3B (e), the natural oxide film (not shown) and the sidewall mask 14 on the inner surfaces of the trenches 13a and 13b of the semiconductor substrate 1 are removed by wet etching, respectively, and then epitaxial growth is performed. Then, using the inner surfaces of the trenches 13a and 13b as a base, a crystal such as a SiGe crystal is grown, and the strain imparting layer 2 is formed. At this time, the first and second layers 2a and 2b of the strain imparting layer 2 are formed in the trenches 13a and 13b, respectively.

  Next, as shown in FIG. 3B (f), conductive impurities are implanted into the surface of the semiconductor substrate 1 and the strain imparting layer 2 by ion implantation or the like using the cap layer 11, the offset spacer 7 and the dummy sidewall 12 as a mask. Then, the deep region 3b of the source / drain region 3 is formed.

  Next, as shown in FIG. 3B (g), the cap layer 11 and the dummy sidewall 12 are removed by wet etching.

  Next, as shown in FIG. 3B (h), gate sidewalls 8 and silicide layers 9 and 10 are formed. Here, the gate side wall 8 is formed on the side surface of the offset spacer 7 by forming a material film of the gate side wall 8 on the entire surface of the semiconductor substrate 1 and then etching it by RIE or the like. In the silicide layers 9 and 10, after forming the gate sidewall 8, a metal film made of Ni or the like is formed on the entire surface of the semiconductor substrate 1, and heat treatment is performed to form the metal film, the strain imparting layer 2, and the gate electrode 6. It is formed by generating a silicide reaction with the upper surface of the substrate.

  It should be noted that the gate side wall 8 is formed so that the bottom surface thereof is in contact with not only the semiconductor substrate 1 but also the strain imparting layer 2 so that the silicide layer 9 is not formed on the semiconductor substrate 1. When the silicide layer 9 is formed in a region including the semiconductor substrate 1, when the semiconductor substrate is made of Si crystal, the silicide reaction tends to abnormally grow in the Si crystal, and thus there is a risk of causing leakage.

  Thereafter, although not shown, an etching stopper film is formed as a stopper when a contact hole is formed on the entire surface of the semiconductor substrate 1, an interlayer insulating film is formed thereon, and silicide layers 9, 10 are formed in the interlayer insulating film. The contact plug connected to the contact plug and the wiring connected to the contact plug are formed.

(Effects of the first embodiment)
According to the first embodiment of the present invention, by forming the strain imparting layer 2 having the first and second layers 2a and 2b, the channel region 4 is effectively strained even in a miniaturized structure. Can be effectively generated and the charge mobility can be improved.

  4A to 4D show the effects of forming the trench 13a and the trench 13b by anisotropic etching and isotropic etching, respectively. FIGS. 4A to 4D are diagrams corresponding to FIGS. 3A to 3D and 3B (e), respectively, including the side surface on the transistor side of the element isolation region 15 around the transistor. It is.

  First, as shown in FIG. 4A, when the trench 13a is formed by anisotropic etching, a part of the semiconductor substrate 1 remains on the inclined side surface of the element isolation region 15 without being removed.

  Next, as shown in FIG. 4B, when the sidewall mask 14 is formed on the inner side surface of the trench 13 a, the sidewall mask 14 is also formed on a part of the side surface of the semiconductor substrate 1 remaining on the side surface of the element isolation region 15. Is done.

  Next, as shown in FIG. 4C, when the trench 13b is formed by isotropic etching, the semiconductor substrate 1 is formed on the inclined side surface of the element isolation region 15 for the sidewall mask 14 on the element isolation region 15 side. A part remains without being removed.

  Next, as shown in FIG. 4D, when the strain imparting layer 2 is formed by epitaxially growing the crystal, the crystal grows also from a part of the semiconductor substrate 1 remaining on the side surface of the element isolation region 15. The strain imparting layer 2 can be filled with almost no gap on the side surface of the separation region 15.

  On the other hand, when the trench 16 for forming the strain imparting layer 2 is formed at a time using only isotropic etching, a semiconductor is interposed between the element isolation region 15 and the trench 16 as shown in FIG. Substrate 1 hardly remains. For this reason, the side surface of the element isolation region 15 is exposed on the inner side surface of the trench 16, and the crystal does not grow epitaxially from the side surface of the element isolation region 15. Therefore, as shown in FIG. A large gap is formed between the separation regions.

  Further, when the trench 16 for forming the strain imparting layer 2 is formed at a time using only isotropic etching, the depth of the trench 16 at the time when the amount of etching in the horizontal direction by the isotropic etching reaches the limit. Therefore, as compared with the semiconductor device 1 according to the present embodiment, the depth of the strain imparting layer 2 becomes shallower and the strain generated in the channel region 4 becomes smaller.

[Second Embodiment]
The second embodiment differs from the first embodiment in the height of the upper surface of the strain imparting layer 2. Note that description of the same parts as those in the first embodiment is omitted or simplified.

(Configuration of semiconductor device)
6A and 6B are cross-sectional views of a semiconductor device according to the second embodiment of the present invention.

  The semiconductor device shown in FIG. 6A has a raised source / drain structure in which the height of the upper surface of the strain imparting layer 2 is higher than the height of the interface between the gate insulating film 5 and the semiconductor substrate 1.

  In order to form a raised source / drain structure, crystals are formed between the gate insulating film 5 and the semiconductor substrate 1 in the step of forming the strain imparting layer 2 shown in FIG. 3B (e) of the first embodiment. Grow to a position higher than the height of the interface. Subsequent steps are the same as those in the first embodiment.

  The semiconductor device shown in FIG. 6B has a structure in which the height of the upper surface of the strain imparting layer 2 is lower than the height of the interface between the gate insulating film 5 and the semiconductor substrate 1.

  In order to form such a structure, in the step of forming the strain imparting layer 2 shown in FIG. 3B (e) of the first embodiment, the crystal is formed at the interface between the gate insulating film 5 and the semiconductor substrate 1. Grow to a position lower than the height. The subsequent steps are the same as those in the first embodiment.

(Effect of the second embodiment)
According to the second embodiment of the present invention, when the semiconductor device has a raised source / drain structure, since the volume of the strain applying layer 2 becomes larger, the strain applying layer 2 is generated in the channel region 4. The strain to be increased increases, and the charge mobility in the channel region 4 increases. Further, since the distance between the silicide layer 9 and the semiconductor substrate 1 is increased, the occurrence of leakage due to the silicide layer 9 can be effectively suppressed.

  Further, when the semiconductor device has a structure in which the height of the upper surface of the strain imparting layer 2 is lower than the height of the interface between the gate insulating film 5 and the semiconductor substrate 1, the following effects are produced. When a stress liner film made of SiN or the like having a function of generating strain in the channel region 4 is formed on the entire surface of the semiconductor substrate 1 including the upper surface of the strain imparting layer 2, the semiconductor device 1 according to the first embodiment. Compared with this structure, the distance between the stress liner film and the channel region 4 becomes short, so that the distortion generated in the channel region 4 increases, and the charge mobility in the channel region 4 increases.

[Other Embodiments]
The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. For example, the first layer 2a and the second layer 2b of the strain imparting layer 2 may be formed by growing different crystals such as SiGe crystal and Si: C crystal.

  In addition, the constituent elements of the above embodiments can be arbitrarily combined without departing from the spirit of the invention.

(A) is sectional drawing of the semiconductor device which concerns on the 1st Embodiment of this invention, (b) is a schematic diagram which shows the dimension of each part of the strain imparting layer 2. FIG. (A), (b) is a graph showing the relationship between the compressive stress which generate | occur | produces in the channel region 4 calculated | required by simulation, and the shape of the strain imparting layer 2. FIG. (A)-(d) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (E)-(h) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(d) is sectional drawing which shows the effect by forming the trench 13a and the trench 13b of the semiconductor device which concerns on the 1st Embodiment of this invention by anisotropic etching and isotropic etching, respectively. (A), (b) is sectional drawing of the semiconductor device which concerns on a comparative example. (A), (b) is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

  1 Semiconductor substrate. 2 Strain imparting layer. 2a First layer. 2b Second layer. 3 Source / drain region. 4 Channel region. 5 Gate insulating film. 6 Gate electrode. 13a, 13b Trench. 14 Sidewall mask.

Claims (5)

A semiconductor substrate;
A gate electrode formed on the semiconductor substrate via a gate insulating film;
A channel region formed under the gate insulating film in the semiconductor substrate;
The first layer formed on both sides of the channel region and the lower layer of the first layer, the end of the gate electrode at the center side is closer to the gate electrode center than the first layer A strain-imparting layer that includes two layers and generates strain in the channel region;
Source / drain regions formed on both sides of the channel region so as to at least partially overlap the strain applying layer;
A semiconductor device.   2. The semiconductor device according to claim 1, wherein a thickness of the first layer is not less than 10% and not more than 20% of a total thickness of the first layer and the second layer.   The ratio of the distance in the gate length direction between the position of the end of the first layer on the gate electrode center side and the position of the end of the second layer on the center side of the gate electrode, and the thickness of the first layer is: The semiconductor device according to claim 1, wherein the semiconductor device is larger than 0 and smaller than 3.3.   4. The semiconductor device according to claim 1, wherein the strain imparting layer includes a SiGe crystal or a Si: C crystal. 5. Forming a gate electrode on a semiconductor substrate via a gate insulating film;
Forming a first trench in a region spaced from the gate electrode on both sides of the gate electrode of the semiconductor substrate by anisotropic etching;
After the inner surface of the first trench is covered with a side wall mask, the position of the end portion on the gate electrode central side is located in the region below the first trench of the semiconductor substrate by isotropic etching. Forming a second trench closer to the center of the gate electrode than the other trench;
After removing the sidewall mask, growing a crystal having a lattice constant different from that of the crystal constituting the semiconductor substrate in the first and second trenches by an epitaxial crystal growth method;
A method of manufacturing a semiconductor device including:

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