JP2010006304A - Communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication device capable of more quickly exchanging information between a high-order control device and low-order control devices by constituting the low-order control devices to communicate with the high-order control device on the most upstream side and the most downstream side, even if there are many low-order control devices. <P>SOLUTION: A CPU 5 is provided with an overcharge state detection command 204 and an overdischarge state detection command 205, etc. to transmit addresses of the control devices IC 1 to IC 24 on the most downstream side of the control devices IC 1 to IC 24 detected with abnormalities, and a through-setting 203 for detecting abnormalities in which the control devices IC 1 to IC 24 located on a downstream side from array positions of the designated addresses only transmit data to an upstream side, and are prevented from performing command operations of the overcharge state detection command 204 and the overdischarge state detection command 205, etc. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention belongs to the technical field of communication devices that perform communication between a plurality of communication devices.

Conventionally, a low-order control device is provided for each predetermined number of cells in which a predetermined number is connected in series, and the plurality of low-order control devices and the high-order control device communicate with each other by a photocoupler. To control a secondary battery device used for an electric vehicle or a hybrid vehicle. The lower level control devices communicate with each other, and the uppermost and lowermost lower level control devices communicate with the higher level control device (see, for example, Patent Document 1).
JP 2003-70179 A (page 2-14, full view)

  However, conventionally, when there are many lower-level control devices, in the configuration in which communication is performed with the upper-level control device at the uppermost stream and the lowermost-stream, the exchange of information between the upper level and the lower level is a problem.

  The present invention has been made paying attention to the above-mentioned problems, and the object of the present invention is to communicate with the upper control device at the most upstream and the most downstream, even when there are many lower control devices. It is an object of the present invention to provide a communication device that can exchange information with a lower level more quickly.

  In order to achieve the above object, in the present invention, a plurality or a plurality of units are arranged in series in the vertical direction, and a subordinate control device that performs communication for receiving from one downstream side and transmitting to one upstream side, and a subordinate located at the most downstream side. A main control device that communicates with a plurality or a plurality of subordinate control devices by transmitting to the subordinate control device and receiving from the subordinate control device located at the most upstream, and for communication control of the main control device The main control is provided with identification data set in association with the upper and lower arrays so as to identify which subordinate control device in the communication device constituting the communication network when the subordinate control device responds or operates accordingly. The apparatus includes a predetermined condition detection command for transmitting the identification data of the subordinate control apparatus, which is the most downstream among the subordinate control apparatuses corresponding to the predetermined condition, and a downstream position from the arrangement position of the specified identification data. It said dependent side control device that is only send data upstream, characterized in that and a through-setting instruction to not perform the command operation of the predetermined condition detection command.

  Therefore, in the present invention, even when there are a large number of lower-level control devices, it is possible to exchange information between the higher-order and the lower-order faster with a configuration in which communication is performed with the upper-level control device at the most upstream and the most downstream. .

  Hereinafter, the embodiment for realizing the communication device of the present invention corresponds to the first embodiment corresponding to the invention according to claims 1, 2, 3 and 6, and the invention according to claims 1, 2, 3 and 4. A description will be given based on Example 2 and Example 3 corresponding to the invention according to claim 5.

First, the configuration will be described.
FIG. 1 is a schematic diagram of a battery system using the communication device of the first embodiment.
In the first embodiment, the communication device is provided inside the battery controller 1 and performs communication related to control such as charging and discharging of the battery 2 that is a secondary battery.
The battery controller 1 and the battery 2 according to the first embodiment are used for driving a vehicle like an electric vehicle or a hybrid vehicle. Therefore, the load 6 is, for example, a drive motor and a motor drive inverter.

FIG. 2 is a diagram illustrating a schematic configuration of a battery controller using the communication device according to the first embodiment.
The battery controller 1 is configured by series connection of the single cells VB1 to VB96, and controls the battery 2 that supplies a high voltage of about 400V as a whole.
First, the configuration of the control device IC1 portion of the battery 2 will be described. In the first embodiment, each of the control devices IC1 to IC24 configured by, for example, an ASIC is configured to handle four unit cells.

  For example, the control device IC1 controls the four most upstream cells of the battery 2, the single cells VB1 to VB4. Hereinafter, for the convenience of explanation, the entire positive terminal side, that is, the single cell VB1 side is the upstream side and the opposite side is the downstream side with respect to the single cells VB1 to VB96 of the battery 2 in series.

The upstream sides of the single cells VB1 to VB4 are connected to the terminals VC1 to VC4 of the control device IC1, respectively. Moreover, after adjusting an electric current through resistance R13-R16, it connects also to terminal CB1D-CB4D of control apparatus IC1, respectively.
Further, the downstream side of the unit cell VB4 is connected to the ground terminals AGND and DGND and the terminals AD1 to AD4 of the control device IC1.

Next, the control device IC1 is connected to the terminal RX via the resistor R12 so as to receive the transmission line from the control device IC2 on one downstream side. Further, it is also connected to terminals CDVDD and AD0 through a resistor R11.
Terminals AD0 to AD4 are terminals for setting addresses of the control devices IC1 to IC24.
Next, the terminal TX for transmitting the control device IC1 is connected to the base of the transistor TR1 via the resistor R1. The transistor TR1 connects the emitter and the base via a resistor R2 for biasing, and the emitter is connected to the terminal CDVDD. The collector is connected to the light emitting side of the photocoupler 3, that is, the anode of the diode via the resistor R3. The cathode of the diode is connected to the terminal DGND. The light receiving side of the photocoupler 3 is configured such that when the light is received, the switch element is turned on and the voltage value stepped down by the resistor R4 is input to the receiving terminal RXD of the CPU 5. When no light is received, a voltage value obtained by pulling up the resistor R4 to a predetermined voltage is input to the reception terminal RXD of the CPU 5.

Similarly, the control device on the downstream side of the control device IC1 connects the upstream and downstream of the four unit cells to the terminals. Then, one transmission line from the downstream side is connected to the reception terminal RX, and the transmission line from the transmission terminal TX is connected to the reception terminal RX of the one upstream control device. Therefore, the control devices IC <b> 2 to IC <b> 23 only communicate with the control device one upstream and downstream, and do not communicate with the CPU 5.
A description of circuit components similar to those of the control device IC1 will be omitted.

The most downstream control device IC <b> 24 connects the terminals VC <b> 1 to VC <b> 4 to the upstream side of the most downstream single cells VB <b> 93 to VB <b> 96 of the battery 2. Further, after adjusting the current through the resistors R243 to R246, the current is also connected to the terminals CB1D to CB4D of the control device IC24.
Further, the downstream side of the unit cell VB96 is connected to the ground terminals AGND and DGND and the terminals AD0 to AD2 of the control device IC24.

The terminals CDVDD, AD3, and AD4 of the control device IC24 are connected to the upstream side (collector side) of the light receiving side switch element of the photocoupler 4 through the resistor 5. The downstream (emitter side) of the switch element is connected to the terminal DGND.
The light-emitting diode of the photocoupler 4 has a cathode connected to the ground and an anode connected to the collector side of the transistor TR2 via a resistor R6. The base of the transistor TR2 is connected to the transmission terminal TXD of the CPU 5 through the resistor R8. The emitter of the transistor TR2 is connected to a predetermined voltage line, and the emitter and base are connected for biasing via a resistor R7.

  As described above, the transmission from the CPU 5 is performed to the control device IC 24 at the most downstream side, is transmitted from the control device IC 24 to the control device at one upstream side in sequence, and is transmitted from the control device IC 1 at the most upstream side to the CPU 5. Communication configuration. This communication form is also called a daisy chain.

FIG. 3 is a diagram illustrating a block configuration related to transmission / reception of the control device of the battery controller in which the communication device of the first embodiment is used.
As illustrated in FIG. 3, the control devices IC <b> 1 to IC <b> 24 include a communication control unit 71, a reception circuit 72, a transmission circuit 73, and a switching unit 74.
The control devices IC1 to IC24 receive communication signals from the terminal RX.

The communication control unit 71 transmits necessary control operations from the received data to other circuit parts, determines necessary transmission control and transmission data from the received data, and outputs to the transmission circuit 73 if there is transmission data. When transmission control is necessary, a control command is output to the switching unit 74.
The receiving circuit 72 receives a communication signal from the terminal RX, converts it into received data, and outputs it to the communication control unit 71.
The transmission circuit 73 converts transmission data from the communication control unit 71 into a communication signal and outputs the communication signal to the C terminal of the switching unit 74.

The switching unit 74 includes an A terminal 741, a B terminal 742, and a C terminal 743 on the input side, and switches which input side terminal is connected to the output terminal. The switching is performed according to a control command from the communication control unit 71.
The A terminal 741 outputs a state without a dominant signal to the terminal TX.
The B terminal 742 outputs the communication signal input to the terminal RX as it is to the terminal TX.
The C terminal 743 outputs the communication signal output from the transmission circuit 73 to the terminal TX.
As described above, the control devices IC1 to IC24 according to the first embodiment each receive one communication signal from the downstream side and receive nothing, transmit itself and transmit itself, The case of receiving and passing the communication signal as it is is provided as communication control, and one upstream transmission is performed.

FIG. 4 is an explanatory diagram of communication data (communication signals) performed by the control devices IC1 to IC24 and the CPU 5 according to the first embodiment.
In the battery controller 1 of the first embodiment, communication in the master-slave system based on the LIN protocol is performed between the control devices IC1 to IC24 and the CPU 5.
The communication frame 100 includes a wakeup signal 101, a header part 102, a response part 103, and an interframe area 104.

The wake-up signal 101 is added before the subsequent data transmission when starting from the sleep mode. It is not added to the continuous communication frame 100 after activation.
The header unit 102 includes a synchronization start unit 102a, a synchronization signal unit 102b, and a control command unit 102c, and is transmitted only from the CPU 5 on the master side.
The synchronization start unit 102a is a data signal portion that causes the reception side to recognize the header unit 102, and the reception side (control devices IC1 to IC24) thereby recognizes the start of the communication frame 100.

The synchronization signal portion 102b is a predetermined synchronization signal portion, and is a portion that causes the receiving side to perform baud rate adjustment and the like for reliably receiving subsequent data.
The control command unit 102c is a part indicating a control command identified by a predetermined number of bytes. The control command to be identified is determined in advance and is stored in the communication control unit 71 and the CPU 5 of the control devices IC1 to IC24.

The response unit 103 includes a data unit 103a and a checksum 103b, and is a data part that is transmitted from the CPU 5 together with the header unit 102 or transmitted as a response to the header unit 102 by the control devices IC1 to IC24.
The data portion 103a is a data portion having a variable data length.
The checksum 103b is an error detection code (addition data) for detecting a data error in the communication frame 100.

  The inter-frame area 104 is an area for partitioning with the next communication frame 100, and is a part without data. After the inter-frame area 104, continuous data transmission is performed such that the synchronization start unit 102a of the next communication frame 100 is sent.

FIG. 5 is an explanatory diagram showing control commands and response data set in advance in the control devices IC1 to IC24 and the CPU 5 of the first embodiment.
In the communication data, unique addresses that can be identified are set in the control devices IC1 to IC24 and the single cells VB1 to VB96, respectively.
In the first embodiment, at least all data detection command 201, total voltage detection command 202, abnormality detection through setting 203, overcharge state detection command 204, overdischarge state detection command 205, built-in data 1 abnormality detection command 206, built-in A data 2 abnormality detection command 207, a state value 1 abnormality detection command 208, and a state value 2 abnormality detection command 209 are provided as the control command unit 102c.

Data that the control devices IC1 to IC24 respond in response to the control command of the control command unit 102c is provided as data units 301 to 309.
Of the data parts 301 to 309, the data part 303 is transmission data from the CPU 5, and the other data is transmission data to which the control devices IC1 to IC24 respond.

The all data detection command 201 is a command indicating a request to transmit the voltages, data, state values, and the like of the four unit cells monitored by the control devices IC1 to IC24.
The address assigned to each of the control devices IC1 to IC24 is specified as which control device is to respond. That is, the control command unit 102c in the case of this command is configured by data and an address indicating the identified command.
The data section 301 that responds includes an address indicating a control device, an address indicating a single cell, a voltage value, an overcharge state, an overdischarge state, built-in data 1 and 2, and state values 1 and 2.

The total voltage detection command 202 is a command indicating a request for transmitting the total voltage of the four unit cells monitored by each of the control devices IC1 to IC24.
The address assigned to each of the control devices IC1 to IC24 is specified as which control device is to respond. That is, the control command unit 102c in the case of this command is configured by data and an address indicating the identified command.
The responding data unit 302 is an address indicating the control device and a total voltage.

The abnormality detection through setting 203 is a command for recognizing the address setting of the control device that passes without detection when an abnormality is detected (through).
That is, when there is an address in the data part 303 transmitted together with the command, it passes through the control device at that address and the control device downstream from it without detection. When there is no address in the data unit 303 (for example, address = 0), all control devices are detected.

The overcharge state detection command 204 is a command for detecting whether an overcharge state has occurred in the single cells monitored by all the control devices IC1 to IC24 using the through setting. On the control device side, if any of the four unit cells is abnormal, it is determined that there is an abnormality.
Addresses indicating the control devices IC <b> 1 to IC <b> 24 are written in the data portion 304 that responds to this command.

  The address is the address of the control device where the abnormality was first detected by detection from the downstream side to the upstream side. Alternatively, if there is a through setting, the address of the control device in which an abnormality is first detected by detection upstream of the control device of the through setting. Or, there is no abnormality without the address to write.

The overdischarge state detection command 205 is a command for detecting whether an overdischarge state has occurred in the single cells monitored by all the control devices IC1 to IC24 using the through setting. On the control device side, if any of the four unit cells is abnormal, it is determined that there is an abnormality.
Since the data part 305 responding to this command is the same as that of the data part 304, the description is omitted.

The built-in data 1 abnormality detection command 206 is set for each single cell monitored by all the control devices IC1 to IC24 using the through setting, and whether or not there is an abnormality in the first data built in the control device. This is a command to be detected. On the control device side, if any of the first data of the four unit cells is abnormal, it is determined that there is an abnormality.
Since the data part 306 responding to this command is the same as that of the data part 304, description thereof is omitted.

The built-in data 2 abnormality detection command 207 is set for each single cell monitored by all the control devices IC1 to IC24 using the through setting, and whether or not there is an abnormality in the second data built in the control device. This is a command to be detected. On the control device side, if any of the second data of the four unit cells is abnormal, it is determined that there is an abnormality.
Since the data part 307 responding to this command is the same as that of the data part 304, the description is omitted.

The state value 1 abnormality detection command 208 is a command for detecting whether or not an abnormality has occurred in the state value 1 of the single cells monitored by all the control devices IC1 to IC24 using the through setting. On the control device side, if any of the four unit cells is abnormal, it is determined that there is an abnormality.
Since the data part 308 responding to this command is the same as the case of the data part 304, description thereof is omitted.

The state value 2 abnormality detection command 209 is a command for detecting whether or not an abnormality has occurred in the state value 1 of the single cells monitored by all the control devices IC1 to IC24 using the through setting. On the control device side, if any of the four unit cells is abnormal, it is determined that there is an abnormality.
Since the data part 309 responding to this command is the same as that of the data part 304, the description is omitted.

The operation will be described.
[Communication state transition on the controller side]
FIG. 6 is a state transition diagram showing the transition of the communication state on the control device side.
Hereinafter, each state will be described.

  The synchronization start part detection state S1 is a state in which the synchronization start part detection signal is received, and when the synchronization start detection signal is normally received, the state shifts to the baud rate processing state S2. When the synchronization signal is insufficient, the process shifts to the idle state S8.

  The baud rate processing state S2 is a state in which the synchronization signal is processed, and the synchronization timing and the baud rate for reception are adjusted from the synchronization signal. When the baud rate adjustment ends normally, the control command reception state S3 is entered. In the case of an error other than normal termination, the process shifts to the idle state S8.

The control command reception state S3 is a state in which the control command unit 102c is received. The processing of the control command unit 102c includes processing for writing data from the CPU 5 into the control devices IC1 to IC24 and processing for reading data from the control devices IC1 to IC24. In the case of the writing process, the process proceeds to the data reception state S4, and in the case of the reading process, the process proceeds to the data transmission state S6.
In the case of an error in which the control command unit 102c cannot be normally received, the process proceeds to the idle state S8.

  The data reception state S4 is a state in which the data portion 103a and the checksum 103b are received. When the reception of the checksum 103b is completed, the data reception state S4 shifts to the data check state S5. If the data part 103a and the checksum 103b are in an error that cannot be normally received, the process proceeds to the idle state S8.

  The data check state S5 is a state in which received data is confirmed by the checksum 103b. If the data confirmation by the checksum 103b is OK, the process is shifted to the idle state S8 as normal termination. If the data check by the checksum 103b is NG, the process shifts to an idle state S8 as an error.

  The data transmission state S6 is a state in which the data part 103a is transmitted. When the transmission of the data part 103a is completed, the data transmission state S6 shifts to the data check state S7. For example, in the case of an error such as interruption of transmission due to receiving a synchronization start signal during transmission, the process shifts to the idle state S8.

  The data check state S7 is a state in which the checksum 103 is generated and transmitted for transmission. When the transmission of the checksum 103b is completed, the process ends as a normal end and shifts to the idle state S8. In the case of an error that the transmission of the checksum 103b is not completed, the process proceeds to the idle state S8.

  The idle state S8 is a state where there is no process waiting for the start of the process. From this state, when the synchronization start signal is detected, the state shifts to the synchronization start part detection state S1.

[Abnormality detection processing]
FIG. 7 is a flowchart showing a flow of abnormality detection processing executed by the CPU 5, and each step will be described below.
In the following description of steps, the addresses of the control devices IC1 to IC24 are 1 to 24, and the addresses where abnormality is detected are X and Y.

  In step S11, the CPU 5 sets the abnormality detection through setting 203 in the control command unit 102c, sets the address = 0 in the data unit 103a, and transmits it to each control device.

  In step S12, the CPU 5 sets an overcharge state detection command 204 in the control command unit 102c and transmits it to each control device.

  In step S13, the CPU 5 determines whether or not the data portion 103a of the response on the control device side with respect to the overcharge state detection command 204 is address = 0, and if the address = 0, the next abnormality detection after step S21 is detected. If the address is not 0, the process proceeds to step S14.

  In step S14, the CPU 5 sets the abnormality detection through setting 203 in the control command unit 102c, sets the response data address X in step S13 in the data unit 103a, and transmits it to each control device.

  In step S15, the CPU 5 sets an overcharge state detection command 204 in the control command unit 102c and transmits it to each control device.

  In step S16, the CPU 5 determines whether or not the data portion 103a of the response on the control device side with respect to the overcharge state detection command 204 is address = 0, and if the address = 0, the next abnormality detection after step S21 is detected. If the address is not 0, the process proceeds to step S17.

  In step S17, the CPU 5 sets the abnormality detection through setting 203 in the control command unit 102c, sets the response data address = Y in step S16 in the data unit 103a, and transmits it to each control device.

  In step S18, the CPU 5 sets an overcharge state detection command 204 in the control command unit 102c and transmits it to each control device.

  In step S19, the CPU 5 determines whether or not the data portion 103a of the response on the control device side with respect to the overcharge state detection command 204 is address = 0, and if the address = 0, the next abnormality detection after step S21 is detected. If the address is not 0, the processing is repeated until the address of the data portion 103a of the response portion 103 becomes 0 as described above.

  In this way, if the address for the overcharge state detection command 204 becomes 0, the next abnormality is detected.

  In step S21, the CPU 5 sets an abnormality detection through setting 203 in the control command unit 102c, sets address = 0 in the data unit 103a, and transmits the data to each control device.

  In step S22, the CPU 5 sets an overdischarge state detection command 205 in the control command unit 102c and transmits it to each control device.

  In step S23, the CPU 5 determines whether or not the data section 103a of the response on the control device side with respect to the overdischarge state detection command 205 is address = 0. If the address = 0, the CPU 5 proceeds to the next abnormality detection, and the address If not = 0, the process proceeds to step S24.

  In step S24, the CPU 5 sets the abnormality detection through setting 203 in the control command unit 102c, sets the response data address = X in step S23 in the data unit 103a, and transmits it to each control device.

  In step S25, the CPU 5 sets an overdischarge state detection command 205 in the control command unit 102c and transmits it to each control device.

  In step S26, the CPU 5 determines whether or not the data section 103a of the response on the control device side with respect to the overdischarge state detection command 205 is address = 0. If the address = 0, the CPU 5 proceeds to the next abnormality detection, and the address If not = 0, the process proceeds to step S27.

  In step S27, the CPU 5 sets the abnormality detection through setting 203 in the control command unit 102c, sets the response data address = Y in step S26 in the data unit 103a, and transmits it to each control device.

  In step S28, the CPU 5 sets an overdischarge state detection command 205 in the control command unit 102c and transmits it to each control device.

  In step S29, the CPU 5 determines whether or not the data section 103a of the response on the control device side with respect to the overdischarge state detection command 205 is address = 0. If the address = 0, the CPU 5 proceeds to the next abnormality detection, and the address If not = 0, as described above, the process is repeated until the address of the data part 103a of the response part 103 becomes 0.

  If the address for the overdischarge state detection command 205 is 0, the built-in data 1 and 2 are detected as abnormal and the state values 1 and 2 are detected as abnormal.

[Function to perform communication for abnormality detection faster]
FIG. 8 is an explanatory diagram illustrating a state in which through setting is performed for abnormality detection in the first embodiment. FIG. 9 is an explanatory diagram illustrating a state in which an overcharge state is detected in the abnormality detection in the first embodiment. FIG. 10 is an explanatory diagram illustrating a state in which the second through setting is performed in the abnormality detection in the first embodiment. FIG. 11 is an explanatory diagram illustrating a state in which the second overcharge state is detected in the abnormality detection in the first embodiment. FIG. 12 is an explanatory diagram illustrating a state in which the third through setting is performed in the abnormality detection in the first embodiment. FIG. 13 is an explanatory diagram illustrating a state in which the third overcharge state in the abnormality detection in the first embodiment is detected.

In the first embodiment, an all data detection command 201 is set in advance in the control command unit 102c. Therefore, if the CPU 5 transmits 24 times to each of the control devices IC1 to IC24, all detectable data can be obtained as a response, and abnormality detection can be performed.
However, if the number of the single cells VB1 to VB96 is large and normal data is collected, the amount of data becomes very large, and as a result, the abnormality detection process is delayed.

Therefore, in the first embodiment, after identifying a control device in which an abnormality has occurred, data of the control device is obtained.
First, as initialization processing for abnormality detection processing, transmission with a through setting of address = 0 is performed from the CPU 5. Then, the through setting is written in the storage units (not shown) of the control devices IC1 to IC24 (see FIG. 8). This writing is performed in step S11 on the CPU 5 side and in the data reception state S4 on the control device side.

Once initialized, the overcharge state detection command 204 is transmitted from the CPU 5 to the control device IC 24 via the photocoupler 4.
In the control device IC24, since the through setting address = 0, abnormality is detected in the unit cells VB93 to VB96 that the control device IC24 is responsible for, and if there is no abnormality, the abnormality detection address = 0 is set as one upstream control device without abnormality detection. Send to IC23.
In this case, in the communication block, the switching unit 74 is switched to the C terminal, and the output from the transmission circuit 73 is transmitted from the terminal TX to the terminal RX of the control device IC23.

In this manner, the abnormality detection result response unit 103 is sequentially transmitted to the upstream one upstream control device.
For example, if an overcharge state is detected in one of the cells monitored by the control device IC5, the control device IC5 sets its own address as an abnormality detection address (abnormality detection address = 5), and one upstream The response part 103 of the abnormality detection result is transmitted to the control device.

In the control devices IC1 to IC4 upstream of the control device IC5 that detects the abnormality, when there is a write in the abnormality detection address, the abnormality detection is not performed and the response unit 103 from the control device IC5 is transmitted to the upstream as it is.
In this case, in the communication block, the switching unit 74 is switched to the B terminal, and the input from the terminal RX is directly transmitted from the terminal TX to the upstream.

Then, the response unit 103 is transmitted from the control device IC1 to the CPU 5 via the photocoupler 3. As a result, the CPU 5 obtains the address of the control device in which the abnormality is detected most downstream (see FIG. 9).
Then, the CPU 5 performs transmission from the CPU 5 with the through setting set to address = 5. Then, the through setting is written in the storage units (not shown) of the control devices IC1 to IC24 (see FIG. 10). This writing is performed, for example, in step S14 on the CPU 5 side, and in the data reception state S4 on the control device side.

Then, an overcharge state detection command 204 is transmitted from the CPU 5 to the control device IC 24 via the photocoupler 4.
Here, since the control device IC24 is in sequence downstream from the through-set address up to the upstream control device IC5, the transmission is simply passed (through) without detecting abnormality.
In this case, in the communication block, the switching unit 74 is switched to the B terminal, and the input from the terminal RX is directly transmitted upstream from the terminal TX.

Then, the control device IC4 of the address one upstream from the through-set address detects an abnormality. In this case, since there is no abnormality, the abnormality detection address = 0 is transmitted to the control device IC3 upstream.
Since there is no abnormality in the control device IC3, the abnormality detection address = 0 is transmitted one upstream.

  For example, if an overcharge state is detected in one of the cells monitored by the control device IC2, the control device IC2 sets its own address as an abnormality detection address (abnormality detection address = 2), and controls one upstream. The response part 103 of the abnormality detection result is transmitted to the device IC1.

In the control device IC1 upstream of the control device IC2 that has detected the abnormality, if there is a write in the abnormality detection address, the abnormality detection is not performed, and the response unit 103 from the control device IC2 is directly passed through the photocoupler 3 to the CPU 5 Send to.
In this case, in the communication block, the switching unit 74 is switched to the B terminal, and the input from the terminal RX is directly transmitted from the terminal TX to the upstream.

In this way, the CPU 5 obtains the address of the control device in which the abnormality is detected most downstream (see FIG. 11).
In this case, since the remaining control device is only the control device IC1, in addition to the control devices IC2 and IC5 that detect the abnormality, all data may be obtained for the control device IC1 by the all data detection command 201. . However, in order to clarify the operation of the first embodiment, the process will be further described.

  Next, the CPU 5 performs transmission from the CPU 5 with the through setting set to address = 2. Then, the through setting is written in the storage units (not shown) of the control devices IC1 to IC24 (see FIG. 12). This writing is performed, for example, in step S17 on the CPU 5 side, and in the data reception state S4 on the control device side.

Then, an overcharge state detection command 204 is transmitted from the CPU 5 to the control device IC 24 via the photocoupler 4.
Here, since the control device IC24 to the upstream control device IC2 are downstream from the through-set address, transmission is simply passed (through) without detecting abnormality.
In this case, in the communication block, the switching unit 74 is switched to the B terminal, and the input from the terminal RX is directly transmitted upstream from the terminal TX.

Then, the control device IC1 of the address one upstream from the through-set address detects an abnormality, and in this case, since there is no abnormality, an abnormality detection address = 0 is transmitted to the CPU 5 via the photocoupler 3.
In this way, the CPU 5 ends the overcharge state detection process upon detecting the abnormality detection address = 0, and proceeds to the next overdischarge state detection process (see FIG. 13).

Then, in each abnormality detection process, after identifying the abnormal control device, send all data detection commands only to the abnormal control device, obtain detailed data, What is necessary is just to identify and to grasp the abnormal state.
In this abnormality detection process, only the address of the most downstream control device in the abnormality detection range is written in the data part 103a of the response unit 103, and the amount of data is very small.
In the first embodiment, since the CPU 5 obtains more detailed data after identifying a control device having an abnormality through communication that requires a small amount of data, the processing is very fast.

In order to clarify the operation of the first embodiment, further explanation will be added below.
In order to achieve the abnormality detection process, a configuration described below can be considered.
FIG. 14 is an explanatory diagram showing control commands set in advance in the devised control devices IC1 to IC24 and the CPU 5 and their response data.
In the example shown in FIG. 14, all data detection command 201, total voltage detection command 202, overcharge state detection command 210, overdischarge state detection command 211, internal data 1 abnormality detection command 212, internal data 2 abnormality detection command 213, state A value 1 abnormality detection command 214 and a state value 2 abnormality detection command 215 are provided as the control command unit 102c.
The all data detection command 201, the total voltage detection command 202, and the corresponding data parts 301 and 302 are the same as those in the first embodiment, and the description thereof is omitted.

14 differs from the first embodiment in the overcharge state detection command 210 to the state value 2 abnormality detection command 215 in the addresses indicating the control devices IC1 to IC24 written in the data portions 310 to 315 corresponding thereto.
In the data parts 310 to 315, the address of the control device in which the abnormality is first detected by the detection from the downstream side to the upstream side is written.

The flow of abnormality detection processing performed using this communication data configuration will be described using a flowchart.
FIG. 15 is a flowchart showing the flow of abnormality detection processing executed by the CPU 5, and each step will be described below.

In step S41, the CPU 5 sets an overcharge state detection command 210 in the control command unit 102c and transmits it to each control device.
Each of the control devices IC1 to IC24 transmits the response unit 103 to the CPU 5 in response to this command in order to send it upstream.

  In step S42, the CPU 5 determines whether or not the data section 103a of the response on the control device side with respect to the overcharge state detection command 210 has an address = 0. If the address = 0, the process proceeds to step S44, and the address = 0 If not, the process proceeds to step S43.

  In step S43, it is determined that there is an abnormality, and the control device identifying process in which the abnormality has occurred in steps S47 to S50 is performed later.

  In step S44, the CPU 5 sets an overdischarge state detection command 211 in the control command unit 102c and transmits it to each control device.

  In step S45, the CPU 5 determines whether the data portion 103a of the response on the control device side with respect to the overdischarge state detection command 211 has an address = 0, and if the address = 0, performs other abnormality detection processing thereafter. Similarly, if the address is not 0, the process proceeds to step S46.

  In step S46, it is determined that there is an abnormality, and the control device identifying process in which the abnormality has occurred in steps S47 to S50 is performed later.

  The processing of steps S47 to S50 described below is processing performed when an abnormality is detected in the processing of steps S41 to S46 (including abnormality detection processing after S46).

In step S47, the CPU 5 transmits an all data detection command 201 to the control device at address = X where the abnormality is detected.
On the other hand, the control device corresponding to the address = X transmits the response unit 103 to the CPU 5.

  In step S47, the CPU 5 transmits an all data detection command 201 to the control device at address = X−1 where the abnormality is detected.

  In step S47, the CPU 5 transmits an all data detection command 201 to the control device at the address = X-2 where the abnormality is detected.

  Thus, the address is changed, and all data of all the control devices upstream from the control device of the address = X where the abnormality is detected is transmitted to the CPU 5. The last is the control device with address = 1.

In step S50, the CPU 5 transmits an all data detection command 201 to the control device at address = 1 where the abnormality is detected.
Then, the CPU 5 checks the state of the control device at address = X and whether there is any abnormality in other control devices from all data upstream from address = X.

  In this way, when an abnormal address is detected without providing a through setting for abnormality detection, all data is transmitted to all the control devices upstream from that address, and the CPU 5 makes a decision. It is done.

However, when the communication data configuration of FIG. 14 is performed by the processing of FIG. 15, the load on the CPU 5 is high and it takes time to specify the second and subsequent abnormal control devices. As a result, the response to the abnormality is delayed, which is not preferable. In the first embodiment, it is advantageous that the control device having an abnormality is identified in a short time. This is remarkable in a battery system that monitors nearly 100 single cells.
In particular, when the control device that has detected an abnormality is close to the most downstream side, the processing time is further increased if the communication data configuration of FIG. 14 is performed by the processing of FIG. In this case, the first embodiment is advantageous in that the processing time does not change between the upstream and downstream positions.

Moreover, as an abnormality occurrence mode, an abnormality may occur in a plurality of unit cells, and a time difference may occur. In the case where the communication data configuration of FIG. 14 is performed by the processing of FIG. 15, it takes time to transmit / receive all data detection commands and abnormality detection processing, so there may be an increase in the number of cells in which abnormality occurs. A difference is likely to occur between the abnormal cell specified at the end and the actual abnormal state, which is not preferable.
In the first embodiment, since the processing time is short, it is difficult to cause a difference between the abnormal cell specified at the end of the processing and the actual abnormal state, which is also advantageous.

  Further, as a countermeasure for the abnormality on the CPU 5 side, different processing may be performed when the number of detected abnormalities is large. Even in that case, the first embodiment is advantageous because the control device that detects the occurrence of abnormality is identified very quickly.

Next, the effect will be described.
In the communication apparatus according to the first embodiment, the effects listed below can be obtained.
(1) A plurality or a large number are arranged in series in the vertical direction, and are received from one downstream side and transmitted to one upstream side, and transmitted to the control devices IC1 to IC24 and the control device IC24 located on the most downstream side. By receiving from the control device IC1 located upstream, the CPU 5 communicates with a plurality or a plurality of control devices IC1 to IC24, and the control devices IC1 to IC24 respond or operate according to the communication control of the CPU5. In the battery controller 1 constituting the communication network, an address set in association with the upper and lower arrays is provided so that it can be identified which control device IC1 to IC24, and the CPU 5 Overcharge state detection command 204 and overdischarge state detection command 205 for transmitting the addresses of the most downstream control devices IC1 to IC24. Then, the control devices IC1 to IC24 located downstream from the arrangement position of the designated address only send data upstream, and the abnormality is such that the command operations such as the overcharge state detection command 204 and the overdischarge state detection command 205 are not performed. Since the detection through setting 203 is provided, even when there are many lower-level control devices (control devices IC1 to IC24), it is configured to communicate with the upper-level control device (CPU 5) at the most upstream and the most downstream, Information can be exchanged faster.

  (2) In the above (1), the abnormality detection through setting 203 is that the control devices IC1 to IC24 located downstream from the arrangement position of the most upstream address among a plurality of designated addresses send data upstream. Only the overcharge state detection command 204, the overdischarge state detection command 205, and the like are configured so as not to perform the command operation. When commands such as the charge state detection command 204 and the overdischarge state detection command 205 are performed, an abnormality detection process is performed only upstream from the designated address without detecting an abnormality from the plurality of designated addresses. This makes it possible to identify the abnormal control device earlier.

(3) In the above (1) and (2), each of the control devices IC1 to IC24 is a unit cell for every four of the batteries 2 for driving the vehicle, in which a plurality or a plurality of unit cells VB1 to VB96 are configured in series. The overcharge state detection command 204, the overdischarge state detection command 205, etc. are controlled when any one of the four cells has an abnormality. Since the devices IC1 to IC24 transmit when there is an abnormality, it is possible to identify very quickly whether the single cell monitored by the control devices IC1 to IC24 is abnormal. As a result, it can be identified very quickly which unit cell is abnormal.
Therefore, it is possible to make the battery controller 1 capable of detecting an abnormality earlier and responding earlier.

  Capture and explain. In the battery controller 1, the battery 2 that monitors the state of charge / discharge control, charge / discharge, etc. has a high voltage of several hundred volts as a whole. Since this battery 2 is composed of a series of nearly one hundred cells, as shown in FIG. 2 of the first embodiment, if several of them are controlled and monitored by one control device, one battery is The voltage is allowed within the operating voltage range of the existing high breakdown voltage CMOS. Therefore, in the first embodiment, one control device is provided for every four unit cells, and transmission is performed only to one upstream control device so as not to process a high voltage difference, etc. Costs and performance are secured.

However, the voltage handled by the entire control devices IC1 to IC24 is a high voltage (strong electric power). On the other hand, the CPU 5 is a weak electric power having an operating voltage of about several volts. Therefore, communication is established by reception from the control device IC1 and transmission to the control device IC24 using the photocouplers 3 and 4 so that the weak power side is not affected by the high power side. It is difficult to provide a large number of photocouplers because of cost.
When such a communication network is configured, Example 1 provides an advantageous communication device as to how to quickly detect an abnormality of nearly one hundred cells.

(6) A plurality or many are arranged in series in the vertical direction, receiving from one downstream side and transmitting to one upstream side, and transmitting to one upstream side control device IC1 to IC24 and the most downstream control device IC24, By receiving from the control device IC1 located upstream, the CPU 5 communicates with a plurality or a plurality of control devices IC1 to IC24, and the control devices IC1 to IC24 respond or operate according to the communication control of the CPU5. In the battery controller 1 constituting the communication network, an address set in association with the upper and lower arrangements is provided so that which control device IC1 to IC24 can be identified,
Through the overcharge state detection command 204, overdischarge state detection command 205 and the like from the CPU 5, the address of the control device IC1 to IC24 at the most downstream of the control devices IC1 to IC24 in which the abnormality has been detected is transmitted. With the setting 203, the control devices IC1 to IC24 do not perform command operations such as the overcharge state detection command 204 and the overdischarge state detection command 205 only by sending data upstream from the arrangement position of the designated address. Therefore, even when there are many lower-level control devices (control devices IC1 to IC24), information is exchanged between the higher-order and the lower-order more quickly by the configuration that communicates with the higher-order control device (CPU 5) in the most upstream and the most downstream. be able to.

  The second embodiment is an example in which a plurality of abnormality detections are performed at a time, and in the through setting for abnormality detection, which abnormality detection is set to be processed to pass downstream from a specified address. .

The configuration will be described.
FIG. 16 is an explanatory diagram showing control commands and response data preset in the control devices IC1 to IC24 and the CPU 5 of the second embodiment.
In the second embodiment, at least the all data detection command 201, the total voltage detection command 202, the abnormality detection through setting 216, and the abnormality detection command 217 are provided as the control command unit 102c.
Then, data that the control devices IC1 to IC24 respond in response to the control command of the control command unit 102c is provided as the data units 301, 302, 316, and 317.

Of the data parts 301, 302, 316, and 317, the data part 316 is transmission data from the CPU 5, and the other data is transmission data to which the control devices IC1 to IC24 respond.
Further, the all data detection command 201, the total voltage detection command 202, and the data portions 301 and 302 corresponding thereto are the same as those in the first embodiment, and thus description thereof is omitted.

The abnormality detection through setting 216 is a command for recognizing the address setting of the control device that passes without detection when an abnormality is detected (through). In the second embodiment, an error type setting flag is provided in the data section 316 in addition to the address setting.
In the handling of the address setting, when there is an address in the data part 316 transmitted together with the command, it passes through the control device of that address and the control device downstream thereof without detection. When there is no address in the data part 316, all the control devices are detected.

Here, a more specific example of the abnormality type setting flag will be described.
For example, 1 bit is assigned to each of overcharge state detection, overdischarge state detection, internal data 1 error detection, internal data 2 error detection, status value 1 error detection, and status value 2 error detection after the address data of the data part 316 The setting flag “000000” is provided. That is, if “100000” in which the first bit is “1”, it indicates that an abnormality has been detected in overcharge state detection.

The abnormality detection command 217 is a command for detecting whether an abnormality has occurred in all the control devices IC1 to IC24 and the cell to be monitored using the through setting. The abnormality includes overcharge state detection, overdischarge state detection, internal data 1 abnormality detection, internal data 2 abnormality detection, state value 1 abnormality detection, and state value 2 abnormality detection.
The data section 317 responding to this command is provided with an address indicating the control devices IC1 to IC24 and a setting flag indicating the abnormality type.

The address is the address of the control device where the abnormality was first detected in the detection from the downstream side to the upstream side. Alternatively, when there is a through setting, the address of the control device in which an abnormality is first detected by the detection upstream of the control device of the through setting is used.
Or, there is no abnormality when there is no address to write (for example, address = 0).
Then, an abnormality type setting flag is set together with the through setting control device address.
Since other configurations are the same as those of the first embodiment, description thereof is omitted.

The operation will be described.
[Abnormality detection processing]
FIG. 17 is a flowchart showing the flow of abnormality detection processing executed by the CPU 5, and each step will be described below.
In the following description of steps, the addresses of the control devices IC1 to IC24 are 1 to 24, and the addresses where abnormality is detected are X, Y, and Z.

  In step S51, the CPU 5 sets the abnormality detection through setting 216 in the control command unit 102c, sets the address = 0 and the setting flag = 000000 in the data unit 103a (reference numeral 316), and transmits it to each control device.

  In step S52, the CPU 5 sets an abnormality detection command 217 in the control command unit 102c and transmits it to each control device.

  In step S53, the CPU 5 determines whether or not the data section 103a of the response on the control device side with respect to the abnormality detection command 217 is address = 0. If address = 0, the process proceeds to step S54, and if address = 0 is not satisfied. If so, the process proceeds to step S55.

  In step S54, the CPU 5 determines that there is no abnormality and ends the abnormality detection process.

  In step S55, the CPU 5 sets the abnormality detection through setting 216 in the control command unit 102c, and in the data unit 103a (reference numeral 316), the address of the response data in step S52 = X and the setting flag = 010000 (for example, the overdischarge state is set). (When detected) is set and transmitted to each control device.

  In step S56, the CPU 5 sets an abnormality detection command 217 in the control command unit 102c and transmits it to each control device.

  In step S57, the CPU 5 determines whether or not the data section 103a of the response on the control device side with respect to the abnormality detection command 217 has an address = 0. If the address = 0, the process proceeds to step S58. If so, the process proceeds to step S59.

  In step S58, the CPU 5 determines that there is no abnormality except for the control device with the address = X, and ends the abnormality detection process. Then, as the next processing, all the data of the single cell monitored by the control device of address = X may be acquired by the all data detection command 201.

  In step S59, the CPU 5 sets the abnormality detection through setting 216 in the control command unit 102c, and in the data unit 103a (reference numeral 316), the address of the response data in step S56 = Y and the setting flag = 000100 (for example, the built-in data 2). Is set) and sent to each control device.

  In step S60, the CPU 5 sets an abnormality detection command 217 in the control command unit 102c and transmits it to each control device.

  In step S61, the CPU 5 determines whether or not the data section 103a of the response on the control device side with respect to the abnormality detection command 217 is address = 0. If address = 0, the process proceeds to step S62, and if address = 0 is not satisfied. If so, the process proceeds to step S63.

  In step S62, the abnormality detection process is terminated by assuming that there is no abnormality in the control devices other than the addresses X and Y. Then, as the next processing, all the data of the single cell monitored by the control device of the address = X, Y may be acquired by the all data detection command 201.

  In step S63, the CPU 5 sets the abnormality detection through setting 216 in the control command unit 102c, and in the data unit 103a (reference numeral 316), the address of the response data in step S60 = Z and the setting flag = 000010 (for example, state value 1) Is set) and sent to each control device.

  In step S64, the process is repeated until the address of the response unit 103 = 0 as described below.

[Function to perform communication for abnormality detection faster]
FIG. 18 is an explanatory diagram illustrating a state in which initial through setting has been performed in abnormality detection in the second embodiment. FIG. 19 is an explanatory diagram illustrating an abnormality detection state in the second embodiment.
FIG. 20 is an explanatory diagram illustrating a state in which the second through setting is performed in the abnormality detection in the second embodiment. FIG. 21 is an explanatory diagram illustrating a second abnormality detection state according to the second embodiment. FIG. 22 is an explanatory diagram illustrating a state in which the third through setting is performed in the abnormality detection in the second embodiment. FIG. 23 is an explanatory diagram illustrating a third abnormality detection state according to the second embodiment.

In the second embodiment, after specifying the control device in which an abnormality has occurred and the type of the abnormality, data of the control device is obtained.
First, as initialization processing for abnormality detection processing, transmission with a through setting of address = 0 and an abnormality type setting flag of 000000 is performed from the CPU 5. Then, the through setting is written in the storage units (not shown) of the control devices IC1 to IC24 (see FIG. 18). This writing is performed in step S51 on the CPU 5 side and in the data reception state S4 on the control device side.

When the initialization is performed, the abnormality detection command 217 is transmitted from the CPU 5 to the control device IC 24 through the photocoupler 4.
In the control device IC24, since the through setting address = 0, abnormality is detected in the unit cells VB93 to VB96 that the control device IC24 is responsible for, and if there is no abnormality, the abnormality detection address = 0 is set as one upstream control device without abnormality detection. Send to IC23.

In this manner, the abnormality detection result response unit 103 is sequentially transmitted to the upstream one upstream control device.
For example, if an abnormal state is detected in any of the single cells monitored by the control device IC5, the control device IC5 sets its own address as an abnormality detection address (abnormality detection address = 5), and the type of abnormality. Is set (for example, 010000 as an overcharge abnormality), and the response part 103 of the abnormality detection result is transmitted to the control device one upstream.

In the control devices IC1 to IC4 upstream of the control device IC5 that detects the abnormality, when there is a write in the abnormality detection address, the abnormality detection is not performed and the response unit 103 from the control device IC5 is transmitted to the upstream as it is.
Then, the response unit 103 is transmitted from the control device IC1 to the CPU 5 via the photocoupler 3. As a result, the CPU 5 obtains a setting flag for specifying the address of the control device in which the abnormality is detected most downstream and its abnormality type (see FIG. 19).

  Then, the CPU 5 performs transmission with the through setting as address = 5 and the setting flag as “010000” from the CPU 5. Then, the through setting is written in the storage units (not shown) of the control devices IC1 to IC24 (see FIG. 20). This writing is performed, for example, in step S55 on the CPU 5 side, and in the data reception state S4 on the control device side.

Then, an abnormality detection command 217 is transmitted from the CPU 5 to the control device IC 24 via the photocoupler 4.
Here, since the control device IC24 to the upstream control device IC5 are downstream from the through-set address, transmission is simply passed (through) without detecting abnormality.

Then, the control device IC4 of the address one upstream from the through-set address detects an abnormality. In this case, since there is no abnormality, the abnormality detection address = 0 is transmitted to the control device IC3 upstream.
Since there is no abnormality in the control device IC3, the abnormality detection address = 0 is transmitted one upstream.

  For example, if an abnormality is detected in one of the cells monitored by the control device IC2, the control device IC2 sets its own address as an abnormality detection address (abnormality detection address = 2), and sets the abnormality type as a setting flag. It is set (for example, “000100” when the built-in data 2 is abnormal), and the abnormality detection result response unit 103 is transmitted to the control device IC1 one upstream.

In the control device IC1 upstream of the control device IC2 that has detected the abnormality, if there is a write in the abnormality detection address, the abnormality detection is not performed, and the response unit 103 from the control device IC2 is directly passed through the photocoupler 3 to the CPU 5 Send to.
In this way, the CPU 5 obtains the address of the control device in which the abnormality is detected most downstream (see FIG. 21).
In this case, since the remaining control device is only the control device IC1, in addition to the control devices IC2 and IC5 that detect the abnormality, all data may be obtained for the control device IC1 by the all data detection command 201. . However, in order to clarify the operation of the second embodiment, the process will be further described.

  Next, the CPU 5 performs transmission from the CPU 5 with the through setting set to address = 2 and the setting flag set to “000100”. Then, the through setting is written in the storage units (not shown) of the control devices IC1 to IC24 (see FIG. 22). This writing is performed, for example, in step S59 on the CPU 5 side, and in the data reception state S4 on the control device side.

Then, an abnormality detection command 217 is transmitted from the CPU 5 to the control device IC 24 via the photocoupler 4.
Here, since the control device IC24 to the upstream control device IC2 are downstream from the through-set address, transmission is simply passed (through) without detecting abnormality.

Then, the control device IC1 of the address one upstream from the through-set address detects an abnormality. In this case, since there is no abnormality, the abnormality detection address = 0 and the setting flag “000000” are set via the photocoupler 3. , To CPU5.
In this manner, the CPU 5 ends the abnormality detection process when the abnormality detection address = 0 is detected (see FIG. 23).

Then, in each abnormality detection process, after specifying the abnormal control device and the type of abnormality, all data detection commands are transmitted only to the abnormal control device to obtain detailed data, What is necessary is just to identify a certain cell and to grasp the abnormal state.
At this time, since it is not possible to obtain only the data because the type of abnormality is specified, it is only necessary to perform processing while paying attention to selecting only the specified abnormality. Will be very fast.
In this abnormality detection process, only the address and setting flag of the control device that is most downstream in the abnormality detection range are written in the data part 103a of the response unit 103, and the amount of data is very small.
In the second embodiment, the CPU 5 obtains more detailed data after identifying the abnormal control device and the type of abnormality through communication that requires only a small amount of data, so that the processing is very fast.

  In the second embodiment, the operation that does not detect the abnormality by the through setting is performed for each control device. Therefore, for this operation, a setting flag is not necessary as a through setting. In the second embodiment, for example, when the type of abnormality of the unit cell monitored by the control device increases, by setting a matching flag match error, the abnormality spreads to other unit cells at an early stage, It is possible to detect that the degree of progress is advanced. Further, the accuracy of abnormality detection and related processing is improved by checking the coincidence of the setting flags.

Explain the effect. The communication device according to the second embodiment has the following effects in addition to the above (1) to (3).
(4) In (1) to (3) above, the abnormality detection command 217 is set in advance as an overcharge state, overdischarge state, internal data 1 abnormality, internal data 2 abnormality, state value 1 abnormality, state value 2 abnormality. In any of the control devices IC1 to IC24, in order to cause the control devices IC1 to IC24 to transmit the address indicating the vertical arrangement position of the control device and the setting flag indicating the abnormality type. It is possible to very quickly identify whether or not a cell being monitored is abnormal, and what type of abnormality is occurring, and as a result, identify which single cell is abnormal. can do.
Therefore, it is possible to make the battery controller 1 capable of detecting an abnormality earlier and responding earlier.

The third embodiment is an example in which communication data is used as the response to the address and setting flag of the control device that first detects an abnormality in the abnormality detection from the downstream side to the upstream side.
The configuration will be described.
FIG. 24 is an explanatory diagram showing control commands and response data set in advance in the control devices IC1 to IC24 and the CPU 5 in the third embodiment.
In FIG. 24, an all data detection command 201, a total voltage detection command 202, and an abnormality detection command 218 are provided as a control command unit 102c.
The all data detection command 201, the total voltage detection command 202, and the corresponding data parts 301 and 302 are the same as those in the first embodiment, and the description thereof is omitted.

The abnormality detection command 218 is a command for detecting whether or not an abnormality has occurred in all the control devices IC1 to IC24 and the cell to be monitored.
The data section 318 responding to this command is provided with an address indicating the control devices IC1 to IC24 and a setting flag indicating the abnormality type.
Since the contents of the abnormality and the setting flag are the same as those in the second embodiment, description thereof is omitted.

The operation will be described.
[Abnormality detection processing]
FIG. 25 is a flowchart showing the flow of abnormality detection processing executed by the CPU 5, and each step will be described below.

In step S71, the CPU 5 sets an abnormality detection command 218 in the control command unit 102c and transmits it to each control device.
Each of the control devices IC1 to IC24 transmits the response unit 103 to the CPU 5 in response to this command in order to send it upstream.

  In step S72, the CPU 5 determines whether or not the data section 103a of the response on the control device side with respect to the abnormality detection command 218 has an address = 0. If the address = 0, the process is terminated, and the address is not 0. If so, the process proceeds to step S73.

  In step S73, it is determined that there is an abnormality, and the control device identifying process in which the abnormality has occurred in steps S74 to S77 is performed later.

  The processes in steps S74 to S77 described below are processes performed when an abnormality is detected in the processes in steps S71 to S73.

In step S <b> 74, the CPU 5 transmits an all data detection command 201 to the control device at the address = X where the abnormality is detected.
On the other hand, the control device corresponding to the address = X transmits the response unit 103 to the CPU 5.

  In step S <b> 73, the CPU 5 transmits an all data detection command 201 to the control device at address = X−1 where the abnormality is detected.

  In step S72, the CPU 5 transmits an all data detection command 201 to the control device at address = X-2 where the abnormality is detected.

  Thus, the address is changed, and all data of all the control devices upstream from the control device of the address = X where the abnormality is detected is transmitted to the CPU 5. The last is the control device with address = 1.

In step S <b> 71, the CPU 5 transmits an all data detection command 201 to the control device with the address = 1 where the abnormality is detected.
Then, the CPU 5 checks the state of the control device at address = X and whether there is any abnormality in other control devices from all data upstream from address = X.
At this time, in the third embodiment, since the type of abnormality of the address = X where the abnormality is detected is obtained, the data of the other control device and the unit cell monitored by the control device of the address = X Thus, a detailed abnormality determination is performed with priority given to the abnormality obtained by the setting flag. [Function to perform communication for abnormality detection faster]
In the third embodiment, it is not possible to obtain the communication processing speed for detecting an abnormality as high as the through setting. However, the abnormality detection command 218 obtains the address of the control device that detected the abnormality most downstream and its abnormality type. Then, abnormality detection is performed with priority on the obtained abnormality type with respect to all data upstream of the control apparatus that detected the abnormality acquired in steps S74 to S77. For this reason, when the ambient condition or the like affects the entire battery 2, the abnormality of another unit cell is detected quickly. In addition, since the abnormality type is specified in the process of searching for an abnormal cell from the four cells monitored by the abnormal control device, the CPU 5 only has to look at the data, and the specification is fast. It becomes processing.

Explain the effect.
The communication device according to the third embodiment has the following effects.
(5) A plurality or many are arranged in series in the vertical direction, receive from one downstream side and transmit to one upstream side, and transmit to one upstream side control device IC1 to IC24 and the most downstream control device IC24. By receiving from the control device IC1 located upstream, the CPU 5 communicates with a plurality or a plurality of control devices IC1 to IC24, and the control devices IC1 to IC24 respond or operate according to the communication control of the CPU5. In the battery controller 1 constituting the communication network, an address set in association with the upper and lower arrays is provided so that the control devices IC1 to IC24 can be identified, and the CPU 5 corresponds to one of the preset abnormalities. The control device IC1 to IC24 of the most downstream control device IC1 to IC24 among the control devices IC1 to IC24 that detected the abnormality And an abnormality detection command 218 for transmitting a setting flag indicating the type of abnormality, so that when detecting abnormality after the CPU 5 acquires data of all control devices upstream from the address where the abnormality is detected. By giving priority to the obtained abnormality type, the abnormality detection process can be performed efficiently and quickly.

  As mentioned above, although the communication apparatus of this invention has been demonstrated based on Example 1-Example 3, it is not restricted to these Examples about a concrete structure, It concerns on each claim of a claim Design changes and additions are allowed without departing from the scope of the invention.

For example, in the first embodiment, the abnormality detection of the unit cell and the control device has been described, but other predetermined conditions may be used.
In the first and second embodiments, when an abnormality is detected in the second abnormality detection, the address of the control device that detected the abnormality in the most upstream position is set in the through setting before the third abnormality detection. Although set, the address of the control device that detected the abnormality in the first abnormality detection may be included in the through setting.

It is the schematic of the battery system using the communication apparatus of Example 1. FIG. It is a figure which shows schematic structure of the battery controller using the communication apparatus of Example 1. FIG. It is a figure which shows the block structure regarding transmission / reception of the control apparatus of the battery controller in which the communication apparatus of Example 1 was used. It is explanatory drawing of the data (communication signal) of communication performed by control apparatus IC1-IC24 and CPU5 of Example 1. FIG. It is explanatory drawing which shows the control command preset to control apparatus IC1-IC24 and CPU5 of Example 1, and its response data. It is a state transition diagram which shows the transition of the communication state by the side of a control apparatus. It is a flowchart which shows the flow of the abnormality detection process performed by CPU5. It is explanatory drawing which shows the state which performed through setting by the abnormality detection in Example 1. FIG. It is explanatory drawing which shows the state which detects the overcharge state in the abnormality detection in Example 1. FIG. It is explanatory drawing which shows the state which performed the 2nd through setting by the abnormality detection in Example 1. FIG. It is explanatory drawing which shows the state which detects the 2nd overcharge state in the abnormality detection in Example 1. FIG. It is explanatory drawing which shows the state which performed the 3rd through setting by the abnormality detection in Example 1. FIG. It is explanatory drawing which shows the state which detects the 3rd overcharge state by the abnormality detection in Example 1. FIG. It is explanatory drawing which shows the control command preset to control apparatus IC1-IC24 and CPU5 which were devised, and its response data. It is a flowchart which shows the flow of the abnormality detection process performed by CPU5. It is explanatory drawing which shows the control instruction | command preset to the control apparatuses IC1-IC24 of Example 2, and CPU5, and its response data. It is a flowchart which shows the flow of the abnormality detection process performed by CPU5. It is explanatory drawing which shows the state which performed the initial through setting by the abnormality detection in Example 2. FIG. It is explanatory drawing which shows the abnormality detection state in Example 2. FIG. It is explanatory drawing which shows the state which performed the 2nd through setting by the abnormality detection in Example 2. FIG. FIG. 10 is an explanatory diagram showing a second abnormality detection state in the second embodiment. FIG. 10 is an explanatory diagram illustrating a state in which a third through setting is performed in abnormality detection in the second embodiment. FIG. 10 is an explanatory diagram illustrating a third abnormality detection state in the second embodiment. It is explanatory drawing which shows the control command preset to control apparatus IC1-IC24 and CPU5 in Example 3, and its response data. It is a flowchart which shows the flow of the abnormality detection process performed by CPU5.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Battery controller 2 Battery VB1-VB96 Single cell 3 Photocoupler 4 Photocoupler 5 CPU
6 load 71 communication control unit 72 reception circuit 73 transmission circuit 74 switching unit 741 A terminal 742 B terminal 743 C terminal 100 communication frame 101 wakeup signal 102 header unit 102a synchronization start unit 102b synchronization signal unit 102c control command unit 103 response unit 103a data Section 103b Checksum 104 Inter-frame region 201 Total data detection command 202 Total voltage detection command 203 Through detection detection 204 setting Overcharge state detection command 205 Overdischarge state detection command 206 Built-in data 1 abnormality detection command 207 Built-in data 2 abnormality detection command 208 Status value 1 error detection command 209 Status value 2 error detection command 210 Overcharge status detection command 211 Overdischarge status detection command 212 Built-in data 1 error detection command 213 Built-in data 2 error detection command 214 Status value 1 error detection command 215 Through setting the status value 2 abnormality detection command 216 abnormality detection 217 abnormality detection command 218 abnormality detection command 301 to 318 data unit IC1~IC24 controller R1~R8 resistance R11~R16 resistance R231~R236 resistance R243~R246 resistance

Claims (6)

A subordinate control device that is arranged in a plurality of numbers in the vertical series and that performs communication for receiving from one downstream side and transmitting to one upstream side,
It has a main control device that communicates with a plurality or a plurality of subordinate control devices by transmitting to the subordinate control device located on the most downstream side and receiving from the subordinate control device located on the most upstream side. In the communication device constituting the communication network, the subordinate control device responds or operates according to the communication control of the device.
In order to identify which subordinate control device, identification data set in association with the upper and lower arrays is provided,
The main controller is
A predetermined condition detection command for transmitting the identification data of the subordinate control apparatus that is the most downstream among the subordinate control apparatuses that satisfy a predetermined condition;
The subordinate control device located downstream from the arrangement position of the specified identification data only sends data upstream, and a through setting command for not performing the command operation of the predetermined condition detection command;
A communication apparatus comprising: The communication device according to claim 1,
In the through setting command, the subordinate control device located downstream from the arrangement position of the most upstream identification data among the plurality of designated identification data only sends the data upstream, and the predetermined condition detection command The command configuration is such that command operation is not performed.
A communication device. The communication device according to claim 1 or 2,
The subordinate control device includes:
Monitoring a single cell for each predetermined number of secondary batteries for driving a vehicle constituted by a plurality of or a plurality of single cells connected in series;
The predetermined condition detection command has a predetermined condition that an abnormality has occurred in any of a predetermined number of single cells,
A communication device. In the communication apparatus according to claim 1 to claim 3,
The predetermined condition of the predetermined condition detection command is a case where any of a plurality of preset conditions is satisfied,
The predetermined condition detection command causes the identification data and type data to specify which condition is transmitted,
A communication device. A plurality or a plurality of cells are arranged in series in the vertical direction so as to monitor a predetermined number of secondary batteries for driving a vehicle constituted by a plurality or a plurality of cells arranged in series, and received from one downstream side, A subordinate control device that performs communication to be transmitted to one upstream side;
It has a main control device that communicates with a plurality or a plurality of subordinate control devices by transmitting to the subordinate control device located on the most downstream side and receiving from the subordinate control device located on the most upstream side. In the communication device constituting the communication network, the subordinate control device responds or operates according to the communication control of the device.
In order to identify which subordinate control device, identification data set in association with the upper and lower arrays is provided,
The main controller is
A case where any one of a plurality of conditions set in advance is set as a predetermined condition, and the identification data of the subordinate control device at the most downstream among the subordinate control devices corresponding to the predetermined condition;
Type data that identifies which conditions, and
With a predetermined condition detection command to transmit
A communication device. A subordinate control device that is arranged in a plurality of numbers in the vertical series and that performs communication for receiving from one downstream side and transmitting to one upstream side,
It has a main control device that communicates with a plurality or a plurality of subordinate control devices by transmitting to the subordinate control device located on the most downstream side and receiving from the subordinate control device located on the most upstream side. In the communication device constituting the communication network, the subordinate control device responds or operates according to the communication control of the device.
It is possible to identify which subordinate control device by the identification data set in association with the upper and lower arrays,
In response to a command from the main control device, the control device on the subordinate side transmits the identification data of the subordinate control device on the most downstream side among the subordinate control devices corresponding to a predetermined condition as a response to the command,
In response to a command from the main control device, when the subordinate control device is located downstream from the specified identification data arrangement position, the command operation of the predetermined condition detection command is performed only by sending data upstream. Lost
A communication method characterized by the above.

Images