JP2009302631A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device provided with a reception terminal resistor set with high precision. <P>SOLUTION: A first terminal of a first circuit connects a resistance element having a desired resistance value, a voltage comparison part forms a comparison output signal between voltage of the first terminal and a first intermediate voltage, a control logic part controls a switch part to supply a second intermediate voltage to a gate of MOSFET of a second resistor circuit, changes a composite resistance value from one to another by on/off control of a plurality of MOSFETs of the first resistor circuit, detects on/off control when voltage comparison output is reversed, and stores it. The switch part is controlled to supply a gate of MOSFET of the second resistor circuit with the voltage comparison output. In a third resistor circuit of the second circuit, a plurality of MOSFETs similar to those of the first resistor circuit are on/off controlled and a gate of MOSFET of a fourth resistor circuit is supplied with the same voltage comparison output as the gate of the MOSFET of the second resistor circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and relates to a technique effective when used in a semiconductor integrated circuit device having a built-in termination resistor.

The receiving end resistor matched with the characteristic impedance of the transmission line is composed of a MOSFET, and the resistance value is digitally controlled by an N-bit signal (N is an integer). Can be realized. In the investigation of known examples after the present invention was made, it was reported by JP-A-11-145814 that a programmable impedance output circuit exists. In this publication, the gate voltages of a plurality of output MOSFETs constituting a first output buffer and a plurality of output MOSFETs constituting a second output buffer are changed in parallel and selectively driven by a digital control signal. And an analog control unit for finely adjusting the output impedance steplessly.
JP-A-11-145814

  In a semiconductor integrated circuit device incorporating a receiving end resistor, it is necessary to keep the resistance value of the receiving end resistor within a standard range in order to match the characteristic impedance of the transmission line. However, when the receiving end resistor is configured using a MOSFET, the resistance value may change due to process variations or external changes (temperature, voltage) during actual use, and the standard may not be satisfied. When the resistance value of the receiving end resistor is out of the standard, the quality of the received signal is deteriorated and a failure such as malfunction occurs. Alternatively, it is necessary to perform signal transmission at a low transmission rate in consideration of fluctuations in the resistance value of the receiving end resistor. Therefore, it is necessary to provide a circuit that can keep the resistance value within the standard range without being affected by variations in the MOSFET process and changes in the external environment (temperature, voltage). The technology of the reported publication controls the output impedance of the output circuit, and the circuit function itself is different from the receiving end resistor.

  One object of the present invention is to provide a semiconductor integrated circuit device having a receiving end resistor set with high accuracy. Another object of the present invention is to provide a semiconductor integrated circuit device with a built-in receiving resistor that is not affected by process variations and external changes during actual use with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  One embodiment disclosed in the present application is as follows. The semiconductor integrated circuit device has a first circuit, a second circuit, and a third circuit. The first circuit includes a first terminal, a first resistance circuit, a second resistance circuit, a voltage comparison unit, a switch unit, and a control logic unit. A resistance element having a desired resistance value is connected between the first terminal and an external first voltage. In the first resistance circuit, a plurality of first MOSFETs are provided in parallel between the first terminal and the second voltage. In the second resistance circuit, a second MOSFET is provided between the first terminal and the second voltage. The voltage comparison unit forms a comparison output signal between the voltage at the first terminal and the first intermediate voltage. The control logic unit controls the switch unit to supply a second intermediate voltage to the gate of the second MOSFET, and the combined resistance value is changed from the maximum value to the minimum value by the on / off control of the plurality of first MOSFETs. A first operation for detecting and storing a combination of the ON states of the plurality of first MOSFETs when the comparison output signal of the voltage comparison unit is inverted from one to the other, and changing from the value toward the maximum value; Based on the information, the first MOSFET is turned on / off, and the switch section is controlled to perform the second operation of supplying the comparison output signal of the voltage comparison section to the gate of the second MOSFET. The second circuit includes a second terminal, a third resistor circuit including a plurality of third MOSFETs having a circuit configuration similar to that of the first resistor circuit, and a fourth MOSFET having a circuit configuration similar to that of the second resistor circuit. It has a 4 resistance circuit. The plurality of third MOSFETs are similarly turned on / off by the stored information for controlling on / off of the plurality of first MOSFETs, and the gate of the fourth MOSFET is compared with the voltage supplied to the gate of the second MOSFET. The comparison output signal of the unit is supplied. The third circuit includes an input circuit that receives an input signal supplied from the second terminal.

  The resistance value of the receiving end resistor can be adjusted with high accuracy. Since it is not necessary to adjust the receiving resistance during actual use of the LSI and no readjustment is required, the system can be operated stably.

  FIG. 1 is a circuit diagram showing an embodiment of a receiving resistor circuit mounted on a semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device shown in FIG. 1 is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique. In the drawing, a circuit corresponding to one terminal is exemplarily shown as a representative among receiving end resistors provided corresponding to a plurality of receiving terminals formed in the semiconductor integrated circuit device.

  The receiving end resistance circuit of this embodiment is composed of an adjustment cell and a normal cell. The normal cell constitutes a pull-down receiving resistor connected between the terminal PD2 and the circuit ground potential. The adjustment cell is a circuit that controls the receiving end resistance value of the normal cell. When there are a plurality of terminals PD2 to which a received signal is input, the normal cell is provided with a circuit exemplarily shown in the figure corresponding to each terminal. On the other hand, the adjustment cell is provided in common for the plurality of normal cells.

  The adjustment cell includes a first resistance circuit DC1 and a second resistance circuit AC1. The first resistor circuit DC1 is a digital resistor circuit, and a plurality of N-channel MOSFETs Q11 to Q15 are provided in parallel between the terminal PD1 and the circuit ground potential VSS. The second resistor circuit AC1 is a so-called analog resistor circuit, and is composed of one N-channel MOSFET Q16 provided between the terminal PD1 and the ground potential VSS of the circuit. Although the first resistance circuit DC1 is not particularly limited, it is composed of five MOSFETs, of which two MOSFETs Q11 and Q15 are representatively shown. The remaining MOSFETs Q12 to Q14 are omitted as shown in parentheses.

  The MOSFETs Q11 to Q15 of the first resistor circuit DC1 have the same channel length, and the channel width is set corresponding to the power of 2 such as 1: 2: 4: 8: 16. As a result, when the on-resistance value of the MOSFET Q15 having a channel width of 16 is defined as one unit resistance value, a variable resistance that varies in 32 steps such as 1-32 unit resistance values depending on the combination of the on-states of the five MOSFETs Q15 to Q11. It can be operated as an element, ie a digital resistance element. The MOSFET Q16 of the second resistance circuit AC1 operates as a variable resistance element whose on-resistance value is analog-controlled by a control voltage supplied to the gate itself.

  When resistance value control of the pull-down receiving resistor is performed, a resistor R is connected between the terminal PD1 of the adjustment cell and the external power supply voltage VDD. The resistance value of the resistor R is determined corresponding to the voltage value of the reference voltage VREF. For example, when the reference voltage VREF is a midpoint voltage that is ½ of the power supply voltage VDD, it is set equal to the resistance value of the receiving end resistor connected to the terminal PD2. That is, when the characteristic impedance of the transmission line connected to the terminal PD2 is 50Ω, the resistor R having a resistance of 50Ω is connected to set the resistance value of the receiving end resistor to 50Ω.

  The voltage comparison circuit AMP compares the voltage at the terminal PD1 with the reference voltage VREF to form a comparison output signal VC. The switch SW has contacts a and b. When the switch SW is connected to the contact a side, the switch SW supplies the reference voltage VREF to the gate of the MOSFET Q16. When the switch SW is connected to the contact b, the comparison output signal VC is supplied to the gate of the MOSFET Q16. To supply. In order to perform stable resistance control operation of the MOSFET Q16, a capacitor C is provided at the output terminal. The capacitance value of the capacitor C is set to about 1 f to 100 f, for example.

  The logic control circuit LOGC is a sequence control circuit, and performs the following first operation immediately after power-on, and then performs the second operation. The register REG is a memory circuit, and holds and outputs control signals d1 to d5 and D1 to D5 by an input signal from the logic control circuit LOGC. CLK is a clock signal and is used for the operation of the register REG.

  In the first operation, the logic control circuit LOGC connects the switch SW to the contact a side and supplies the reference voltage VREF to the gate of the MOSFET Q16 of the second resistance circuit AC1. Although not particularly limited, the signal d1 is set to high level (logic 1) and the other signals d2 to d5 are set to low level (logic 0) via the register REG so as to turn on the MOSFET Q11 having the largest on-resistance value. As a result, the MOSFET Q11 is turned on so that the first resistance circuit DC1 has the largest resistance value. The first resistance circuit DC1 has the largest resistance value theoretically when all the MOSFETs Q11 to Q15 are in the OFF state, but is excluded because it is not the resistance value as the termination resistor.

  The voltage VPD1 at the terminal PD1 is a divided voltage corresponding to the resistance ratio of the resistor R, the combined resistance of the MOSFET Q11 of the first resistor circuit DC1 and the MOSFET Q16 of the second resistor circuit AC1. The voltage comparison circuit AMP compares the voltage VPD1 with the reference voltage VREF to form a comparison output signal VC. For example, when the reference voltage VREF is the midpoint voltage (VDD / 2) of the power supply voltage VDD and VPD1> VREF, the comparison output signal VC is at a high level.

  The logic control circuit LOGC receives the first comparison output signal VC and changes the signals d1, d2, d3, d4, and d5 to 01000 so that the MOSFET Q12 is turned on instead of the MOSFET Q11 through the register REG. . Here, 0 represents a low level and 1 represents a high level. As a result, the resistance value of the first resistance circuit DC1 is reduced by the one unit resistance value, and the voltage VPD1 at the terminal PD1 is lowered. The voltage comparison circuit AMP compares the lowered voltage VPD1 with the reference voltage VREF to form a comparison output signal VC. If VPD1> VREF, the comparison output signal VC remains at the high level.

  The logic control circuit LOGC receives the second comparison output signal VC and changes the signals d1, d2, d3, d4, and d5 to 11000 so as to turn on the MOSFET Q11 and the MOSFET Q12 through the register REG. Although not particularly limited, the control logic circuit LOGC has an adder circuit, and performs an operation of adding +1 to the previous signals d1, d2, d3, d4, and d5 according to the high level of the comparison output signal VC. Since the register REG captures the addition result in synchronization with the clock CLK, the signals d1, d2, d3, d4, and d5 are binary counts such as 10,000, 01000, 11000,... In synchronization with the clock CLK. Perform the action. Here, d1 is the least significant bit and d5 is the most significant bit.

  The binary counting operation is sequentially performed until VPD1 <VREF corresponding to the clock CLK, and the resistance value of the first resistance circuit DC1 is decreased by one unit resistance value in synchronization with the clock CLK. The When the comparison output signal VC changes to the high level / low level, that is, when the VPD1 <VREF is first satisfied, the first operation is entered into the second operation, and the signals d1, d2, d3, d4, The level of d5 is fixed, and signals of the same level are supplied to the normal cell as signals D1 to D5. The control logic circuit LOGC switches the switch SW to the contact b in the second operation. As a result, the voltage VPD1 is supplied to the gate of the MOSFET Q16 of the second resistor circuit AC1.

  The normal cell has a third resistance circuit DC2 and a fourth resistance circuit AC2. The third resistor circuit DC2 includes MOSFETs Q21 to Q25 having the same configuration as the first resistor circuit DC1 of the adjustment cell, and the signals D1 to D5 are supplied to the respective gates. The fourth resistance circuit AC2 is configured by a MOSFET Q26 having the same configuration as that of the second resistance circuit AC1 of the adjustment cell, and the gate is commonly connected to the MOSFET Q16.

  FIG. 2 is a characteristic diagram for explaining the operation of the receiving resistor circuit according to the present invention. The figure shows the relationship between the combined resistance value (Ω) of the first resistor circuit DC1 and the second resistor circuit AC1 and the control value in which the binary signals d1, d2, d3, d4, and d5 are expressed in decimal. It is a resistance characteristic diagram. The control value is a decimal value of 0, that is, the binary signals d1, d2, d3, d4, and d5 are 00000, and the MOSFETs Q11 to Q15 (Q21 to Q25) of the first resistor circuit DC1 (third resistor circuit DC2) are off. Thus, the combined resistance value of the MOSFET Q16 (Q26) of the second resistor circuit AC1 (fourth resistor circuit AC2) is about 73Ω.

  The control value is a decimal value of 1, that is, the binary signals d1, d2, d3, d4, and d5 are 10,000, and only the MOSFET Q11 (Q21) of the first resistor circuit DC1 (third resistor circuit DC2) is turned on. The resistance value drops to about 70Ω. Thereafter, the resistance value is sequentially decreased by the combination of the on / off states of the MOSFETs Q11 to Q15 (Q21 to Q25), and all of the MOSFETs Q11 to Q15 (Q21 to Q25) of the first resistor circuit DC1 (third resistor circuit DC2). Is about 39Ω, which is the lowest resistance value for turning on.

  As described above, when the characteristic impedance of the transmission line is 50Ω, the resistance R is set to 50Ω. At this time, for example, when the control value expressed in decimal is 12 (the binary signals d1, d2, d3, d4, and d5 are 00110), VPD1 <VREF, and the first resistor circuit DC1 (third resistor circuit DC2). ) MOSFETs Q13 and Q14 (Q23 and Q24) are turned on, and the others are kept fixed in the off state. In this state, as shown in the enlarged view, an error occurs with respect to the resistance target value of 50Ω. The error in the resistance value of the receiving end resistor is eliminated by the second operation. That is, since the switch SW is switched to the contact b side by the second operation, the voltage comparison circuit AMP eliminates the error by generating the gate voltage VC of the MOSFET Q16 (Q26) so that VPD1 = VREF. .

  In the above state, the first resistance circuit DC1 (third resistance circuit DC2) and the second resistance due to temperature change and voltage change are operated in addition to operating to eliminate errors due to process variations of the MOSFETs Q11 to Q16 (Q21 to Q26). It also functions to compensate for the variation in the combined resistance value with the circuit AC1 (fourth resistor circuit AC2).

  FIG. 3 shows a characteristic diagram for explaining the amount of change in the receiving end resistance due to temperature change. The first operation and the second operation are performed at the temperature t1, and the resistance value of the receiving end resistor is set to 50Ω. If the set values of the first operation and the second operation remain as they are, the resistance value of the receiving resistances of the MOSFETs Q11 to Q16 (Q21 to Q26) increases as the temperature rises. For example, when the temperature becomes high as t2, the resistance value increases as 55Ω, so that the voltage VPD1 is increased. When the receiving end resistance value is increased in this way, VPD1> VREF, and the voltage comparison output VC increases to the high level side. As a result, the gate voltage of the MOSFET Q16 (Q26) becomes higher than that at the time of VREF, and the on-resistance value of the MOSFET Q16 (Q26) is lowered to automatically adjust the combined resistance value to 50Ω.

  FIG. 4 shows a characteristic diagram for explaining the amount of change in the receiving end resistance due to voltage change. When the power supply voltage VDD is the voltage v1, the first operation and the second operation are performed, and the resistance value of the receiving end resistor is set to 50Ω. If the set values of the first operation and the second operation remain as they are, the resistance value of the receiving end resistors by the MOSFETs Q11 to Q16 (Q21 to Q26) decreases as the voltage increases. For example, when the voltage increases as v2, the resistance value decreases as 48Ω, so that the voltage VPD1 is decreased. When the receiving end resistance value is reduced in this way, VPD1 <VREF, and the voltage comparison output VC decreases to the low level side. As a result, the gate voltage of the MOSFET Q16 (Q26) becomes lower than that at the time of VREF, and the on-resistance value of the MOSFET Q16 (Q26) is increased to automatically adjust the combined resistance value to 50Ω.

  FIG. 5 is an operation explanatory diagram of the receiving end resistor circuit according to the present invention. FIG. 5A shows an example of a combination of temperature and voltage. The temperature is the minimum value (MIN) t1, the representative value t2, and the maximum value (MAX) t3, and the voltage is the minimum value (MIN) v1, the representative value v2, and the maximum value (MAX) v3. FIG. 5B shows examples of resistance values corresponding to the temperatures t1 to t3 in FIG. If the resistance value of the receiving end resistor is set only by the first operation at the temperature t1, the maximum change amount is 10Ω, which is a significant change of 20% with respect to the target value. When the resistance value of the receiving end resistor is set only at the first operation at the temperature t2, the maximum change amount is 5Ω, which is a significant change of 10% with respect to the target value. FIG. 5C shows examples of resistance values corresponding to the voltages v1 to v3 in FIG. If the resistance value of the receiving end resistor is set only by the first operation when the voltage is v1, the maximum change amount is 5Ω, which is a significant change of 10% with respect to the target value. When the resistance value of the receiving end resistor is set only by the first operation when the voltage is v2, the maximum change amount is 3Ω, which is a change of 6% with respect to the target value.

  In the present invention, by the first operation and the second operation, in addition to the variation in the programming of the MOSFET, the variation in the resistance value of the receiving resistor as shown in FIG. Therefore, the signal transmission operation can be performed stably and at high speed without setting a margin in consideration of the variation in the receiving end resistance value as described above.

  FIG. 6 shows an equivalent circuit diagram of the adjustment cell according to the present invention. This figure is an equivalent circuit corresponding to the second operation. In the second operation, the comparison output signal VC of the voltage comparison circuit AMP is supplied to the gate of the MOSFET Q16 of the second resistance circuit AC1.

  FIG. 7 shows an input / output characteristic diagram of the voltage comparison circuit AMP of FIG. When the input signal (PD1 side) is VREF, the output side (VC) is also made equal to VREF.

  FIG. 8 shows a characteristic diagram of the gate-source voltage Vgs and the drain-source current Ids of the N-channel MOSFET Q16. A variable resistance region in which the current Ids changes linearly before and after Vgs is VREF is used.

  FIG. 9 shows a resistance characteristic diagram of the receiving end resistance circuit (the combined resistance of the first resistance circuit and the second resistance circuit) in the second operation. Corresponding to the increase of the comparison output signal VC of the voltage comparison circuit AMP, the resistance value viewed from the terminal PD1 side linearly decreases. Thereby, for example, the resistance value of the receiving resistor circuit (the combined resistor of the first resistor circuit and the second resistor circuit) can be controlled to 50Ω. That is, when VPD1> VREF, the resistance value of the receiving end resistance circuit increases, and the voltage comparison circuit AMP detects this and raises the comparison output signal VC. Control to reduce the resistance value of the end resistor circuit. On the contrary, when VPD1 <VREF, the resistance value of the receiving end resistance circuit becomes small, and the voltage comparison circuit AMP detects this and lowers the comparison output signal VC. Therefore, the on-resistance value of the MOSFET Q16 becomes large, and Control to increase the resistance value of the receiving resistor circuit.

  FIG. 10 is a circuit diagram showing another embodiment of the receiving end resistor circuit mounted on the semiconductor integrated circuit device according to the present invention. The normal cell of this embodiment constitutes a pull-up receiving resistor connected between the terminal PD2 and the power supply voltage VDD. Correspondingly, the adjustment cell is also configured to control the pull-up receiving end resistance. The difference from FIG. 1 is that the MOSFETs Q11 to Q16 and Q21 to Q26 are P-channel MOSFETs connected to the power supply voltage VDD side. Further, a resistor R is provided between the terminal PD1 and the circuit ground potential VSS. Other configurations are the same as those in FIG. In this embodiment, although not particularly limited, a voltage comparison circuit is provided in the control logic unit LOGC. In order to simplify the circuit, it is advantageous to use a voltage comparison circuit AMP that performs analog control of the resistance value of the receiving end resistor as in the embodiment of FIG. The clock CLK is not input from the outside as shown in FIG. 1, but an appropriate clock inside the LSI is used.

  FIG. 11 is a circuit diagram showing still another embodiment of a receiving end resistor circuit mounted on a semiconductor integrated circuit device according to the present invention. This embodiment is a modification of the embodiment of FIG. 1, and the register REG is replaced with a nonvolatile memory EPROM. In this embodiment, adjustment of the receiving end resistance that is digitally controlled using the first resistance circuit DC1 is performed in the adjustment cell during the LSI pre-shipment test. The adjustment is performed by connecting the same resistance R as the target value to PAD1. When the bit of the receiving end resistance (d1 to d5 = D1 to D5) to be digitally controlled is changed and the potential of PAD1 becomes VREF, the receiving end resistance of the first resistance circuit DC1 (third resistance circuit DC2) becomes the target value. Become. The voltage and temperature at the time of adjustment are set to typical values as shown in FIG. By setting with the representative value, the difference in the external environment between setting and actual use can be reduced.

  The adjusted bit is stored in the nonvolatile memory EPROM. The bit of the receiving resistor to be digitally controlled is a value stored in the nonvolatile memory EPROM. During actual use of the LSI, the switch SW is fixedly connected to the contact b side, and the control of the receiving end resistance when the error or the external environment (temperature, voltage) changes occurs is controlled by the analog control unit (AC1). , AC2). That is, when the power is turned on, a digital resistance adjustment operation is performed by the first resistance circuit DC1 (third resistance circuit DC2) according to the contents of the nonvolatile memory EPROM, and the second resistance circuit AC1 (fourth resistance circuit). Analog control by AC2) is performed, and the resistance value of the receiving end resistor is set.

  The voltage VPD1 of the adjustment cell and the reference voltage VREF are compared by the voltage comparison circuit AMP, and a comparison output signal VC is output. A capacitor C as a stabilization capacitor is connected to the output terminal of the voltage comparison circuit. The voltage comparison circuit AMP outputs a comparison output signal VC larger than VREF if (1) VPD1> VREF (the receiving end resistance is large). Since the gate potential of the analog-controlled N-channel MOSFET Q16 (Q26) becomes larger than VREF fixed at the time of adjusting the receiving end resistance of digital control, the resistance value of the receiving end resistor becomes small. If (2) VPD1 <VREF (the receiving end resistance is small), a comparison output signal VC smaller than VREF is output. Since the gate potential of the analog-controlled N-channel MOSFET Q16 (Q26) is smaller than VREF, the resistance value of the receiving end resistor is increased.

  In the embodiment shown in FIGS. 1 and 10, since the register REG and the flip-flop circuit FF are used for the memory circuit, the first resistor circuit DC1 (the first resistor circuit DC1 ( After setting the receiving resistance by digital control using the second resistor circuit DC2), analog control using the second resistor circuit AC1 (fourth resistor circuit AC2) by the second operation is performed.

  FIG. 12 is a circuit diagram showing still another embodiment of a receiving end resistor circuit mounted on a semiconductor integrated circuit device according to the present invention. This embodiment is a modification of the embodiment of FIG. 1, and an analog control function is also added to the first resistor circuit DC1 (fourth resistor circuit DC2). That is, the gates of the MOSFETs Q11 to Q15 that operate as the resistance elements of the first resistance circuit DC1 are connected to the gate of the MOSFET Q16 of the second resistance circuit AC1 via the switch MOSFETs Q110 to Q150. The digital signals d1 to d5 are supplied to the gates of the switch MOSFETs Q110 to Q150.

  Similarly to the first resistor circuit DC1, in the third resistor circuit DC2, the gates of the MOSFETs Q21 to Q25 operating as resistor elements are connected to the gate of the MOSFET Q26 of the fourth resistor circuit AC2 via the switch MOSFETs Q210 to Q250. The digital signals D1 to D5 are supplied to the gates of the switch MOSFETs Q110 to Q150.

  In this configuration, the MOSFETs Q11 to Q15 of the first resistance circuit DC1 do not have a fixed resistance value corresponding to the power supply voltage VDD as shown in FIG. 1, but a resistance corresponding to the reference voltage VREF in the first operation. Works with values. In the second operation, since the switch SW is switched to the contact b side, the switch SW operates as a variable resistance element whose resistance value changes according to the comparison output signal VC of the voltage comparison circuit AMP. As a result, the first resistance circuit DC1 (fourth resistance circuit DC2) is digitally controlled in the first operation and analog control is performed in the second operation. With this configuration, the controllable resistance value range of the receiving end resistor can be widened.

  FIG. 13 is a circuit diagram showing still another embodiment of a receiving end resistor circuit mounted on a semiconductor integrated circuit device according to the present invention. This embodiment is a modification of the embodiment of FIG. 12, and the second resistor circuit AC1 (third resistor circuit AC2) is omitted. That is, since the MOSFETs Q11 to Q15 (Q21 to Q25) perform both digital control and analog control, they can be represented as resistor circuits DAC1 and DAC2, and the second resistor of FIG. The circuit AC1 and the fourth resistance circuit AC2 are omitted.

  11 to 13, the clock used for digital control of the first resistor circuit DC1 is an appropriate internal clock as in FIG. The logic control circuit LOGC and the register REG can be replaced with a binary counter circuit. For example, when the comparison output signal VC of the voltage comparison circuit AMP is at a high level (VPD1> VREF), the signals d1 to d5 (D1 to D5) are formed by performing a +1 counting operation in synchronization with the clock CLK. be able to.

  FIG. 14 is a block diagram showing one embodiment of the input / output unit of the semiconductor integrated circuit device according to the present invention. The terminal PD13 of the first semiconductor integrated circuit device LSI1 and the terminal PD22 of the second semiconductor integrated circuit device LSI2 are connected by a transmission line L1. The terminal PD13 is connected to the output terminal of the output circuit (driver) TX1, and the terminal PD22 is connected to the input terminal of the input circuit (receiver) RX2. Thereby, signal transmission is performed from the first semiconductor integrated circuit device LSI1 to the second semiconductor integrated circuit device LSI2. Conversely, in order to transmit a signal from the second semiconductor integrated circuit device LSI2 to the first semiconductor integrated circuit device LSI1, the terminal PD23 and the terminal PD12 are connected by a transmission line L2, and the second semiconductor integrated circuit is connected to the terminal PD23. It is connected to the output terminal of the output circuit (driver) TX2 of the device LSI2, and is connected to the input terminal of the input circuit (receiver) RX1 to the terminal PD12 of the first semiconductor integrated circuit device LSI1.

  In the first semiconductor integrated circuit device LSI1, a signal to be transmitted, which is formed by an internal circuit, is transmitted to the output circuit TX1. The received signal of the input circuit RX1 is transmitted to the internal circuit. Similarly, in the first semiconductor integrated circuit device LSI2, a signal to be transmitted, which is formed by an internal circuit, is transmitted to the output circuit TX2. The received signal of the input circuit RX2 is transmitted to the internal circuit.

  In this embodiment, in order to perform stable signal transmission at high speed between the two first and second semiconductor integrated circuit devices LSI1 and LSI2, the second semiconductor integrated circuit device LSI2 has an input terminal PD22. A normal cell is provided correspondingly. This normal cell is shown as a pull-down variable resistance element, and is configured as shown in FIG. 1 and FIGS. The resistance value of the normal cell is controlled by the adjustment cell as in the above embodiment. The terminal PD21 connected to the adjustment cell is provided with a resistor R corresponding to the characteristic impedance of the transmission line L1. Thereby, the resistance value (receiving end resistance value) of the normal cell is controlled to be equal to the resistance R, and as a result, it is matched with the characteristic impedance of the transmission line L1, and the problem of reflection due to impedance mismatching is solved. High-speed signal transmission becomes possible.

  The second semiconductor integrated circuit device LSI1 is also provided with a normal cell corresponding to the input terminal PD12. This normal cell is also shown as a pull-down variable resistance element in the same manner as described above, and is configured as shown in FIGS. 1 and 11 to 13. The resistance value of the normal cell is controlled by the adjustment cell as in the above embodiment. The terminal PD11 connected to the adjustment cell is provided with a resistor R corresponding to the characteristic impedance of the transmission line L2. Thereby, the resistance value (receiving end resistance value) of the normal cell is controlled to be equal to the resistance R, and as a result, it is matched with the characteristic impedance of the transmission line L2, and problems such as reflection due to impedance mismatching are solved. High-speed signal transmission becomes possible.

  FIG. 15 is a block diagram showing another embodiment of the input / output unit of the semiconductor integrated circuit device according to the present invention. Unlike the FIG. 14, the normal cell of this embodiment is shown as a pull-up variable resistance element, and is configured as shown in FIG. Other configurations are the same as those in FIG.

  FIG. 16 is a block diagram showing still another embodiment of the input / output unit of the semiconductor integrated circuit device according to the present invention. The normal cell of this embodiment is provided with both a pull-down variable resistance element and a pull-up variable resistance element. That is, the normal cell includes, for example, the receiving resistor circuit shown in FIG. 1 and the receiving resistor circuit shown in FIG. 10 for each of the terminals PD12 and PD22 of the first and second semiconductor integrated circuit devices LSI1 and LSI2. Both are provided. There are provided two adjustment cells corresponding to these two receiving resistance circuits, one corresponding to the pull-down receiving resistance circuit and one corresponding to the pull-up receiving resistance circuit. Accordingly, the resistors R used for setting the resistance value of the receiving end resistor circuit are also provided at the two terminals PD11N and PD11P and PD21N and PD21P for pull-up and pull-down, respectively.

  In the present invention described above, the resistance value of the receiving end resistor can be set to a desired resistance value with high accuracy regardless of the process variation of the MOSFET. If the external environment (temperature, voltage) changes during actual use of the LSI, the adjustment is dynamically performed using the receiving resistance in analog control, so that readjustment is unnecessary. Since it is not necessary to adjust the receiving resistance during actual use of the LSI and readjustment is unnecessary, the system can be operated stably.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, when the signal terminals of the semiconductor integrated circuit device LSI are divided and arranged in the peripheral part of the square chip, and the respective temperatures may be different, corresponding to the respective predicted temperature distributions, Alternatively, the signal terminal may be divided into a plurality corresponding to the voltage fluctuation, and the adjustment cell may be provided for each to control the resistance value of the normal cell corresponding to the temperature distribution or the voltage fluctuation portion. The MOSFETs constituting the resistance circuits DC1, DC2, etc. that perform the digital control have a variable resistance characteristic that is more linear than that of FIG. Various embodiments such as those for setting the respective channel widths and those for increasing or decreasing the number of MOSFETs to be used can be adopted.

  The reference voltage supplied through the contact a of the switch SW does not need to be equal to the reference voltage supplied to the voltage comparison circuit AMP, and may be appropriately set according to the variable resistance characteristic of the MOSFET Q16. Good. The reference voltage VREF supplied to the voltage comparison circuit AMP need not be the midpoint voltage (VDD / 2) of the power supply voltage VDD. For example, when the reference voltage VREF is set to VDD / 3, the resistance value ratio between the resistor R and the receiving end resistor is set to 2: 1. That is, the resistance value of the receiving resistor circuit is set to a resistance value that is ½ of the resistance R. The nonvolatile memory of the embodiment of FIG. 11 may use a fuse means that is electrically cut or a fuse means that is cut by a laser beam.

  The present invention can be widely used for a semiconductor integrated circuit device including an interface circuit that incorporates a receiving end resistor and needs to keep the resistance value constant.

1 is a circuit diagram of one embodiment of a receiving end resistance circuit mounted on a semiconductor integrated circuit device according to the present invention; FIG. It is a characteristic view for demonstrating operation | movement of a receiving end resistor circuit based on this invention. It is a characteristic view for demonstrating the receiving end resistance change amount by a temperature change. It is a characteristic view for demonstrating the receiving end resistance change amount by a voltage change. It is operation | movement explanatory drawing of the receiving end resistor circuit based on this invention. It is an equivalent circuit diagram of the adjustment cell which concerns on this invention. FIG. 7 is an input / output characteristic diagram of the voltage comparison circuit AMP in FIG. 6. It is a characteristic view of gate-source voltage Vgs and drain-source current Ids of MOSFET. It is a resistance characteristic figure of a receiving end resistance circuit in the 2nd operation in one example of this invention. FIG. 6 is a circuit diagram of another embodiment of a receiving resistor circuit mounted on a semiconductor integrated circuit device according to the present invention. FIG. 10 is a circuit diagram of still another embodiment of a receiving end resistor circuit mounted on a semiconductor integrated circuit device according to the present invention. FIG. 10 is a circuit diagram of still another embodiment of a receiving end resistor circuit mounted on a semiconductor integrated circuit device according to the present invention. FIG. 10 is a circuit diagram of still another embodiment of a receiving end resistor circuit mounted on a semiconductor integrated circuit device according to the present invention. 1 is a block diagram of an embodiment of an input / output unit of a semiconductor integrated circuit device according to the present invention. It is a block diagram of another embodiment of the input / output unit of the semiconductor integrated circuit device according to the present invention. It is a block diagram of another embodiment of the input / output unit of the semiconductor integrated circuit device according to the present invention.

Explanation of symbols

AMP ... Voltage comparison circuit, DC1 ... first resistance circuit, AC1 ... second resistance circuit, DC2 ... third resistance circuit, AC2 ... fourth resistance circuit, LOGC ... logic control circuit, REG ... register, R ... resistance, C ... Capacitor, SW ... switch, EPROM ... nonvolatile memory,
Q11 to Q26 ... MOSFET, Q110 to Q250 ... switch MOSFET,
TX1,2 ... Output circuit (driver), RX1,2 ... Input circuit (receiver)
LS11: first semiconductor integrated circuit device, LSI2: second semiconductor integrated circuit device.

Claims (9)

A first circuit, a second circuit, and a third circuit;
The first circuit includes
A first terminal;
A first resistance circuit;
A second resistance circuit;
A voltage comparison unit;
A switch part;
A control logic unit,
The first terminal is for connecting a resistance element having a desired resistance value to an external first voltage corresponding to the operating voltage,
The first resistance circuit has a plurality of first MOSFETs provided in parallel between the first terminal and a second voltage corresponding to the operating voltage,
The second resistance circuit includes a second MOSFET provided between the first terminal and the second voltage,
The voltage comparison unit forms a comparison output signal of the voltage of the first terminal and a first intermediate voltage between the first voltage and the second voltage;
The control logic part is
The switch section is controlled to supply a second intermediate voltage between the first voltage and the second voltage to the gate of the second MOSFET, and the combined resistance value is maximized by on / off control of the plurality of first MOSFETs. The first change is made from the minimum value to the minimum value or from the minimum value to the maximum value, and the combination of the ON states of the plurality of first MOSFETs at the time when the comparison output signal of the voltage comparison unit is inverted from one to the other is detected and stored. One action,
A second operation of turning on / off the first MOSFET according to the stored information and controlling the switch unit to supply a comparison output signal of the voltage comparison unit to the gate of the second MOSFET;
The second circuit is
A second terminal;
A third resistance circuit comprising a plurality of third MOSFETs having a circuit configuration similar to that of the first resistance circuit;
A fourth resistance circuit comprising a fourth MOSFET having a circuit configuration similar to that of the second resistance circuit;
The plurality of third MOSFETs are similarly on / off controlled by the stored information for controlling on / off of the plurality of first MOSFETs,
The gate of the fourth MOSFET is supplied with the comparison output signal of the voltage comparator supplied to the gate of the second MOSFET,
The semiconductor integrated circuit device, wherein the third circuit has an input circuit that receives an input signal supplied from the second terminal. In claim 1,
The control logic unit is a semiconductor integrated circuit device that performs the first operation immediately after power-on and then performs the second operation. In claim 1,
The semiconductor integrated circuit device, wherein the first intermediate voltage and the second intermediate voltage are respectively set to a midpoint voltage between the first voltage and the second voltage. In claim 1,
The control logic unit is a semiconductor integrated circuit device that performs the first operation before shipment, stores the stored information in a nonvolatile storage means, and performs only the second operation after shipment. In claim 1,
The first voltage is a positive power supply voltage, the second voltage is a ground potential of the circuit,
The first to fourth resistance circuits are semiconductor integrated circuit devices configured by N-channel MOSFETs. In claim 1,
The first voltage is a ground potential of the circuit, the second voltage is a power supply voltage,
The first to fourth resistance circuits are semiconductor integrated circuit devices configured by P-channel MOSFETs. A first circuit, a second circuit, and a third circuit;
The first circuit includes:
A first terminal;
A first resistance circuit;
A voltage comparison unit;
A switch part;
A control logic unit,
The first terminal is for connecting a resistance element having a desired resistance value to an external first voltage corresponding to the operating voltage,
The first resistor circuit includes a plurality of first MOSFETs provided in parallel between the first terminal and a second voltage corresponding to an operating voltage, and a gate and a circuit node of each of the plurality of first MOSFETs. A plurality of second switch MOSFETs provided in
The voltage comparison unit forms a comparison output signal of a voltage at the first terminal and a midpoint voltage between the first voltage and the second voltage,
The control logic part is
The midpoint voltage is supplied to the circuit node by controlling the switch unit, and the combined resistance value of the plurality of first MOSFETs is changed from the maximum value to the minimum value or from the minimum value by the on / off control of the plurality of second MOSFETs. A first operation for detecting and storing a combination of the ON states of the plurality of second MOSFETs at the time when the comparison output signal of the voltage comparison unit is inverted from one to the other;
A second operation of turning on / off the second MOSFET according to the stored information and controlling the switch unit to supply a comparison output signal of the voltage comparison unit to a circuit node;
The second circuit is
A second terminal;
A second resistance circuit including a plurality of third MOSFETs and a plurality of fourth switch MOSFETs having a circuit configuration similar to that of the first resistance circuit;
The plurality of fourth switch MOSFETs are similarly turned on / off by the stored information for controlling on / off of the plurality of second switch MOSFETs,
The semiconductor integrated circuit device, wherein the third circuit has an input circuit that receives an input signal supplied from the second terminal. The semiconductor integrated circuit device according to claim 1, wherein the output terminal of the voltage comparison unit has a capacitance means. 9. The semiconductor integrated circuit device according to claim 1, wherein a plurality of the second circuits and the third circuits are provided as a pair by sharing the first circuit. 10.

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