JP2009302579A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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Abstract
【解決手段】半導体チップ11の表面電極25とリードフレーム43を同一材料にして、リードフレーム43の先端部44を凸状に加工し、半導体チップの表面膜25とリードフレーム43を互いに向き合せて、加圧しながら超音波振動させることで、最表面(界面)に形成された同一金属が互いに拡散し、半田レスで直接金属接合できる。
【選択図】 図3
Description
図7は、半導体チップの要部断面図である。この図は1/2セルを示している。半導体チップ11の表面電極20側は、半導体基板21(例えばシリコン)上に、ゲート酸化膜22、ポリシリコンで形成されたゲート電極23、層間絶縁膜24、表面電極膜25、さらにその上に図示しない保護膜が形成され構成され、この段差形状(セル)が複数回に渡って繰返され半導体チップが構成された段差形状となっている。一方、裏面電極30側は半田接合を確保するため、Al層31、Ti層32、Ni層33およびAu層34がベタ膜状態で積層されている。尚、Au層34が最表面膜となる。また、図の点線は、IGBTセルの場合の半導体基板21内に形成されるエミッタ領域、ウエル領域、ドリフト領域およびコレクタ領域を示している。
最近、半導体チップ11は大型化されてきており、熱応力による半田接合部への歪みは、さらに大きくなってきている。このような状況で接合方法として、半田接合を用いることは、信頼性の低いパワーモジュールの提供につながる可能性がある。また、半導体チップ11の表面電極と接続するワイヤ13は、配線抵抗やインダクタンスが大きく、半導体装置の特性が十分に発揮できない場合もある。
また、半導体チップは大型化され、ワイヤボンディングによる配線方法では半導体装置の性能を十分に生かすことが困難となってきている。
従って、半導体チップの裏面電極を絶縁基板に構成された回路パターンに如何に半田を用いない方法で接合できるか、また、表面電極への安定した電気的接続が如何に確保できるかが課題となる。
この発明の目的は、前記の課題を解決して、半導体チップの裏面と絶縁基板との接合、半導体チップの表面と外部導出導体との接合および絶縁基板と冷却体(ヒートシンク)との接合において、半田を用いない接合とすることで、高性能で高信頼性の半導体装置を提供することにある。
前記の目的を達成するために、半導体チップの表面に形成した表面電極と、導体とを接続した半導体装置において、前記表面電極と前記導体の各表面を同一材料とし、互いの表面を直に接触させて直接金属接合する。
また、回路パターン導板を形成した絶縁基板の裏面に形成した導板と、放熱体を接続した半導体装置において、前記導板と前記放熱体の各表面を同一材料とし、互いの表面を直に接触させて直接金属接合する構成とする。
また、前記の半導体装置の製造方法において、互いの前記表面を加圧し、超音波振動もしくは加熱の少なくとも一方を実施することで直接金属接合するとよい。
前記したように、互いに接合する部材表面の材質を同一にし、加圧しながら、超音波振動を与えることで、直接金属接合ができる。加熱するとさらに直接金属接合がし易くなる。
また、半導体チップの表面電極膜への電気的配線をリードフレームとし、その接合方法を直接金属接合とすることで、大容量クラスまで電気的接続が安定した半導体装置の供給が可能となる。
また、絶縁基板とヒートシンクとの接合方法を直接金属接合とすることで、半田層の熱抵抗が削除でき、機械的負荷に対して安定した半導体装置の供給が可能となる。
半導体チップ11の裏面電極30(図7参照)の最表面膜41aは、Ni層、Cu層、Al層あるいは貴金属層(Au層)を、蒸着またはスパッタあるいはメッキにより成膜して形成する。一方、半導体チップ11を接合する絶縁基板15上の回路パターン15aの最表面膜41bも、半導体チップ11の裏面電極30の最表面膜41aと同一材料であるNi層、Cu層、Al層あるいは貴金属層(Au層など)を蒸着またはスパッタあるいはメッキによって成膜する。そして、最表面膜41a、41bで被覆された半導体チップの裏面電極30および絶縁基板15上に構成された回路パターン15aを互いに向き合せに配置し、加圧しながら超音波振動をさせ、場合によっては加熱することで、最表面(界面)に形成された同一金属が互いに拡散し、半田レスで直接金属接合する。超音波振動で直接金属接合させる条件は、例えば、半導体チップの大きさが5mm□〜10mm□の場合、超音波振動周波数は20kHz〜40kHz程度、加圧力は10kg(9.8×10N)〜40kg(9.8×40N)程度、時間は0.3sec〜0.6sec程度である。半導体チップ11の面積が大きくなった場合には、チップサイズに合わせて前記加圧力を増大する。また、加熱する場合の温度は150℃程度以下でよい。また、最表面41a、41bの粗さは小さい程好ましいが、μmオーダー以下であれば構わない。
また、前記の直接金属接合とは、接合する金属間に何も介在させず、接合する金属同志を直接接触させて接合することをいう。
図2は、この発明の第2参考例の半導体装置の要部断面図である。半導体チップ11の裏面電極30はSi地またはTi膜、Cr膜を成膜する。次に、半導体チップ11の裏面電極30と絶縁基板15の表面に構成された回路パターン15aをCMP(化学的機械的研磨)装置などによって表面粗さをそれぞれ100nm以下に平坦加工する。さらに、ドライエッチング装置を用いて、加工したそれぞれの平坦面を酸化しないように不活性雰囲気(N2 減圧雰囲気や真空雰囲気)内でArなどをスパッタして活性化し、清浄化して、面粗さを10nm以下の平坦面とし、半導体チップ11の裏面電極30と絶縁基板上15の回路パターン15aとを重ね合せて加圧し直接金属接合する。平坦面の状態によっては、熱加圧するか、あるいは加圧しながら超音波振動させることで、原子(分子)間力によって半田レスで直接金属接合が行われる。尚、半導体チップ11と回路パターン15aとの線膨張係数の差による熱応力を緩和するために、回路パターン15aには、焼き鈍しあるいは半導体チップ11を囲むように回路パターン15aに溝42を設ける。また、裏面電極30と回路パターン15aの最表面は同一金属であると好ましい。
図5は、この発明の第2実施例の半導体装置の要部断面図である。絶縁基板の裏面導電膜15cの面とヒートシンク16の表面とを直接重ね合せ、直接金属接合させる。尚、ヒートシンク16の表面には絶縁基板の裏面導電膜15cより外側に絶縁基板の裏面導電膜15cを囲むように溝42を設ける。尚、直接金属接合の方法は前記した第1、第2参考例の方法と同じである。
尚、これらの実施例は半導体チップを回路パターンに接合して使用するパワー半導体装置(IGBT、ダイオード、サイリスタ、トランジスタ、MOSFETなど)に共通したものである。
12 半田
13 ワイヤ
14 端子
15 絶縁基板
15a 回路パターン
15b 絶縁板
15c 裏面導電膜
16 ヒートシンク
20 表面電極
21 半導体基板
22 ゲート酸化膜
23 ゲート電極
24 層間絶縁膜
25 表面電極膜
30 裏面電極
31 Al膜
32 Ti膜
33 Ni膜
34 Au膜
41a 最表面膜(半導体チップ側)
41b 最表面膜(回路パターン側)
43 リードフレーム
44 先端部
45 ガードリング
Claims (4)
- 半導体チップの表面に形成した表面電極と、リードフレーム状の導体とを接続し、前記半導体チップを搭載する回路パターン導板を形成した絶縁基板の裏面に形成した導板と、放熱体を接続した半導体装置において、
前記表面電極と前記リードフレーム状の導体との接続と、前記導板と前記放熱体との接続のうち少なくとも一方について、互いに接合する部材表面の材質をニッケル層,銅層,アルミニウム層,貴金属層のいずれかの同一材料とし、互いの表面を接触させて直接金属接合することを特徴とする半導体装置。 - 請求項1に記載の半導体装置の製造方法において、互いの前記表面を加圧し、超音波振動もしくは加熱の少なくとも一方を実施することで前記接合が行われることを特徴とする半導体装置の製造方法。
- 請求項1に記載の半導体装置において、
前記表面電極と前記リードフレーム状の導体との接続と、前記導板と前記放熱体との接続のうち、前記表面電極と前記リードフレーム状の導体との接続を、互いに接合する部材表面の材質をニッケル層,銅層,アルミニウム層,貴金属層のいずれかの同一材料とし、互いの表面を接触させて直接金属接合する場合は、
前記表面電極と直接金属接合させる前記リードフレーム状の導体の先端部の接合面を凸状としたことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記表面電極と前記リードフレーム状の導体との接続と、前記導板と前記放熱体との接続のうち、前記表面電極と前記リードフレーム状の導体との接続を、互いに接合する部材表面の材質をニッケル層,銅層,アルミニウム層,貴金属層のいずれかの同一材料とし、互いの表面を接触させて直接金属接合する場合は、
前記導体と直接金属接合させる前記表面電極を、前記半導体チップが備えるガードリング部より高く堆積させたことを特徴とする半導体装置。
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JPH06268027A (ja) * | 1993-03-11 | 1994-09-22 | Hitachi Ltd | 半導体装置 |
JPH0964258A (ja) * | 1995-08-25 | 1997-03-07 | Hitachi Ltd | 大電力半導体デバイス |
JP2001110823A (ja) * | 1999-10-13 | 2001-04-20 | Hitachi Ltd | 半導体装置の製造方法 |
JP2001156219A (ja) * | 1999-11-24 | 2001-06-08 | Denso Corp | 半導体装置 |
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JPH06268027A (ja) * | 1993-03-11 | 1994-09-22 | Hitachi Ltd | 半導体装置 |
JPH0964258A (ja) * | 1995-08-25 | 1997-03-07 | Hitachi Ltd | 大電力半導体デバイス |
JP2001110823A (ja) * | 1999-10-13 | 2001-04-20 | Hitachi Ltd | 半導体装置の製造方法 |
JP2001156219A (ja) * | 1999-11-24 | 2001-06-08 | Denso Corp | 半導体装置 |
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WO2021014007A1 (en) | 2019-07-25 | 2021-01-28 | Abb Power Grids Switzerland Ag | Power semiconductor module |
DE112020003541T5 (de) | 2019-07-25 | 2022-06-09 | Hitachi Energy Switzerland Ag | Leistungshalbleitermodul |
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