JP2009296392A - Power source selecting apparatus - Google Patents

Abstract

Provided is a power supply selection device in which an operation of a supplied circuit connected to an output terminal does not become unstable and a through current does not occur.
The power source selection device includes a PMOS transistor 11a and a PMOS transistor 11b connected in series between a voltage source input terminal 1 and a voltage source output terminal 3, and the voltage source input terminal 2 and the voltage source output terminal are connected. The PMOS transistor 11c and the PMOS transistor 11d connected in series between the voltage source input terminal 2 and the PMOS transistor 11a are cut off and the PMOS transistor 11d is turned on when the power supply voltage is switched. Is supplied to the voltage source output terminal 3 via the parasitic diode of the PMOS transistor 11c.
[Selection] Figure 1

Description

  The present invention relates to a power supply selection device that supplies, as a power supply voltage, a voltage based on one of voltages applied to two voltage source input terminals to a supplied circuit connected to the voltage source output terminal.

  In recent years, electronic devices such as portable devices are supplied with the minimum power supply voltage required for the normal operation mode in the normal operation mode, and in the standby mode, in order to reduce power consumption. Thus, the minimum necessary power supply voltage is supplied to the internal circuit.

  As described above, there is a power supply selection device disclosed in Patent Document 1 as a conventional technique for supplying one of two types of power supply voltages to a supplied circuit. This power supply selection device includes two input terminals to which two kinds of voltages having different sizes are applied, and one of them is connected to the output terminal. Hereinafter, a conventional power supply selection device will be described with reference to FIG.

As shown in FIG. 5, the conventional power supply selection device includes input terminals 101 and 102 to which two types of voltages V _DD1 and V _DD2 having different sizes are applied, an input terminal 103 to which a SEL signal is input, Between the output terminal 104, the PMOS transistor Tr11 connecting the input terminal 101 and the output terminal 104, the PMOS transistor Tr12 connecting the input terminal 102 and the output terminal 104, and between the input terminal 101 and the back gate of the PMOS transistor Tr11. And the diode D2 connected between the input terminal 102 and the back gate of the PMOS transistor Tr12, and the SEL signal (logic signal) input to the input terminal 103 is inverted to invert the PMOS transistor Tr11. Inverter In11 applied to the gate and Inverter In An inverter In12 to be applied to the gate of the PMOS transistor Tr12 and further inverts the signal from the 1, composed.

With the configuration described above, when the SEL signal is at the H level, the PMOS transistor Tr11 is turned on and the PMOS transistor Tr12 is turned off, so that the voltage V _DD1 is applied to the output terminal 104. On the other hand, when the SEL signal is at the L level, the PMOS transistor Tr11 is turned off and the PMOS transistor Tr12 is turned on, so that the voltage V _DD2 is applied to the output terminal 104.

The diodes D1 and D2 are connected in parallel to parasitic PN diodes that are parasitic between the source and back gate of the PMOS transistors Tr11 and Tr12, respectively, thereby preventing an excessive current from flowing into these parasitic PN diodes.
JP 2000-124780 A

As described above, the conventional power supply selection device controls the switching operation of the PMOS transistors Tr11 and Tr12 in accordance with the level of the SEL signal, thereby supplying the power supply voltage supplied to the supplied circuit connected to the output terminal 104. The voltage V _DD1 and the voltage V _DD2 were selected from two different sizes.

However, the above conventional power source selection unit inverts the level of the SEL signal, the voltage _{V DD2} power supply voltage from the voltage _{V DD1,} or when the voltage _{V DD2} switched to the voltage _{V DD1,} albeit in minutes There is a period in which both the PMOS transistors Tr11 and Tr12 are in an ON state. During this period, the input terminal 101 and the input terminal 102 are short-circuited, causing a problem that a through current flows. In particular, when the SEL signal is inverted from the L level to the H level, the PMOS transistor Tr11 is turned on longer than the PMOS transistor Tr12 is turned off due to the delay time of the inverter In12.

  Therefore, in general, in order to prevent the occurrence of a through current, it is conceivable to provide a dead time period in which the PMOS transistors Tr11 and Tr12 are both turned off when the power supply voltage is switched. However, in the case where the dead time is provided, if the output terminal 104 does not have a large capacity, the potential of the output terminal 104 becomes unstable, and a problem occurs in that a supplied circuit to which the power supply voltage is supplied from the output terminal 104 malfunctions.

  In view of the above-described conventional problems, an object of the present invention is to provide a power supply selection device in which the operation of a supplied circuit connected to an output terminal does not become unstable and no through current is generated.

  The power source selection device according to claim 1 of the present invention is connected in series between first and second input terminals to which a voltage is applied, an output terminal, and the first input terminal and the output terminal. The first and second transistors, the third and fourth transistors connected in series between the second input terminal and the output terminal, and the first transistor connected in parallel to the first transistor. A first rectifying element that allows current to flow from one input terminal side to the second transistor side, and a second rectifier that is connected in parallel to the second transistor and causes current to flow from the output terminal side to the first transistor side. A rectifying element connected in parallel to the third transistor, a third rectifying element that conducts current from the second input terminal side to the fourth transistor side, and a parallel connection to the fourth transistor. The third transistor from the output terminal side A first rectifying element that causes a current to flow to the data side, a first state in which the first and third transistors are cut off, and a state in which the second and fourth transistors are in a conductive state; A second state in which the second transistor is turned off and the third and fourth transistors are turned on, and during the transition from the first or second state to the second or first state. And a control circuit having a third state in which the first to third transistors are turned off and the fourth transistor is turned on.

  The power selection device according to claim 2 of the present invention is the power selection device according to claim 1, wherein the control circuit sets the first and second transistors in a conductive state, and the third and A fourth state in which the fourth transistor is turned off, and a state in which the first to fourth transistors are turned off during the transition from the fourth or second state to the second or fourth state. And a fifth state.

  The power selection device according to claim 3 of the present invention is the power selection device according to claim 2, wherein the control circuit makes a transition from the first or fourth state to the second state. A first delay circuit for transitioning the third transistor or the third and fourth transistors from a cut-off state to a conductive state after a preset delay time; and from the second state to the first or A second delay circuit for transitioning the second transistor or the first and second transistors from a cut-off state to a conductive state after a preset delay time when transitioning to a fourth state; It is characterized by that.

  A power selection device according to a fourth aspect of the present invention is the power selection device according to any one of the first to third aspects, wherein the control circuit is applied to the first and second input terminals. And a state transition is made according to the detected voltage.

  A power selection device according to claim 5 of the present invention is the power selection device according to any one of claims 1 to 4, wherein the first transistor, the first rectifying element, and the second The transistor and the second rectifier element, the third transistor and the third rectifier element, and the fourth transistor and the fourth rectifier element each comprise a PMOS transistor and its parasitic diode. .

  According to the preferred embodiment of the present invention, the power supply voltage can be constantly supplied to the supplied circuit connected to the output terminal, so that the operation of the supplied circuit can be prevented from becoming unstable. Further, since it is possible to prevent a through current from flowing between the first input terminal and the second input terminal, a safe power supply voltage switching operation can be realized.

(Embodiment 1)
Hereinafter, Embodiment 1 of the power supply selection apparatus of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an example of a circuit configuration of a power supply selection device according to Embodiment 1 of the present invention.

  This power supply selection device uses a voltage source input terminal 1 to which a voltage V1 is applied as a first input terminal to which a voltage is applied, and a voltage to which a voltage V2 is applied as a second input terminal to which a voltage is applied. The source input terminal 2 is used as an output terminal, and a voltage source output terminal 3 to which a supplied circuit (not shown) is connected is provided. This power supply selection device supplies a voltage based on one of the voltages V1 and V2 applied to the voltage source input terminals 1 and 2 to the supplied circuit as a power supply voltage.

  In addition, the power source selection device includes PMOS transistors as first and second transistors connected in series between a first input terminal (voltage source input terminal 1) and an output terminal (voltage source output terminal 3). 11a and a PMOS transistor 11b.

  In addition, the power source selection device includes PMOS transistors as third and fourth transistors connected in series between the second input terminal (voltage source input terminal 2) and the output terminal (voltage source output terminal 3). 11c and a PMOS transistor 11d.

  Although not shown, this power source selection device is connected in parallel to the first transistor (PMOS transistor 11a) and from the first input terminal (voltage source input terminal 1) side to the second transistor (PMOS transistor 11b) side. As a first rectifying element that causes a current to flow through, a parasitic diode that is parasitic between the source and back gate of the PMOS transistor 11a is provided.

  In addition, although not shown, this power supply selection device is connected in parallel to the second transistor (PMOS transistor 11b) to supply current from the output terminal (voltage source output terminal 3) side to the first transistor (PMOS transistor 11a) side. As a second rectifying element to be flown, a parasitic diode parasitic between the source and back gate of the PMOS transistor 11b is provided.

  Although not shown, this power source selection device is connected in parallel to the third transistor (PMOS transistor 11c) and is connected from the second input terminal (voltage source input terminal 2) side to the fourth transistor (PMOS transistor 11d) side. As a third rectifying element that causes a current to flow through, a parasitic diode that is parasitic between the source and back gate of the PMOS transistor 11c is provided.

  In addition, although not shown, this power source selection device is connected in parallel to the fourth transistor (PMOS transistor 11d) and supplies current from the output terminal (voltage source output terminal 3) side to the third transistor (PMOS transistor 11c) side. As a fourth rectifying element to be flown, a parasitic diode parasitic between the source and back gate of the PMOS transistor 11d is provided.

  In addition, the power source selection device turns off the first and third transistors (PMOS transistors 11a and 11c) and turns on the second and fourth transistors (PMOS transistors 11b and 11d). The first state to be turned on), the first and second transistors (PMOS transistors 11a and 11b) are turned off, and the third and fourth transistors (PMOS transistors 11c and 11d) are turned on. 2 and the first to third transistors (PMOS transistors 11a to 11c) are turned off during the transition from the first state or the second state to the second or first state, and the fourth state. As a control circuit having a third state in which the transistor (PMOS transistor 11d) is turned on, It comprises Toggles control circuit 6 and the PMOS transistor control circuit 7.

  When the control circuit including the switching control circuit 6 and the PMOS transistor control circuit 7 is in the first state, the first and third transistors (PMOS transistors 11a and 11c) are turned off, and the second and fourth transistors Since the transistors (PMOS transistors 11b and 11d) are turned on, the voltage value of the voltages (voltages V1 and V2) applied to the first and second input terminals (voltage source input terminals 1 and 2) is high. The other voltage is supplied to the output terminal (voltage source output terminal 3) via the first or third rectifier element (PMOS transistor 11a or PMOS transistor 11c parasitic diode).

  When the control circuit including the switching control circuit 6 and the PMOS transistor control circuit 7 is in the second state, the first and second transistors (PMOS transistors 11a and 11b) are turned off, and the third and third transistors Since the fourth transistor (PMOS transistors 11c and 11d) is turned on, the voltage (voltage V2) applied to the second input terminal (voltage source input terminal 2) is supplied to the output terminal (voltage source output terminal 3). Is done.

  When the control circuit including the switching control circuit 6 and the PMOS transistor control circuit 7 is in the third state, the first to third transistors (PMOS transistors 11a to 11c) are turned off, and the fourth transistor Since the (PMOS transistor 11d) is turned on, the voltage (voltage V2) applied to the second input terminal (voltage source input terminal 2) passes through the third rectifier element (parasitic diode of the PMOS transistor 11c). It is supplied to the output terminal (voltage source output terminal 3).

  In this way, the power source selection device switches the power source voltage supplied to the supplied circuit connected to the voltage source output terminal 3, that is, from the first or second state to the second or first state. During the state transition of the control circuit to the state, the voltage V2 applied to the voltage source input terminal 2 can be supplied to the voltage source output terminal 3 via the parasitic diode of the PMOS transistor 11c (third state). Therefore, it is possible to avoid an unstable operation of the supplied circuit.

  The control circuit including the switching control circuit 6 and the PMOS transistor control circuit 7 further brings the first and second transistors (PMOS transistors 11a and 11b) into a conductive state and the third and fourth transistors (PMOS transistors). 11c and 11d), and the first to fourth transistors (PMOS transistors 11a to 11d) during the transition from the fourth state or the second state to the second or fourth state. 11d) has a fifth state for shutting off.

  When the control circuit including the switching control circuit 6 and the PMOS transistor control circuit 7 is in the fourth state, the first and second transistors (PMOS transistors 11a and 11b) are turned on, and the third and fourth transistors Since the transistors (PMOS transistors 11c and 11d) are turned off, the voltage (voltage V1) applied to the first input terminal (voltage source input terminal 1) is supplied to the output terminal (voltage source output terminal 3). .

  The switching control circuit 6 constituting the control circuit also includes a third transistor (PMOS transistor) after a preset delay time when the control circuit transitions from the first or fourth state to the second state. 11c) or a rising delay circuit 15 as a first delay circuit for causing the third and fourth transistors (PMOS transistors 11c and 11d) to transition from the cutoff state to the conductive state.

  Further, the switching control circuit 6 constituting the control circuit has a second transistor (PMOS transistor) after a preset delay time when the control circuit transitions from the second state to the first or fourth state. 11b) or a rising delay circuit 14 as a second delay circuit for transitioning the first and second transistors (PMOS transistors 11a and 11b) from the cutoff state to the conductive state.

  As described above, the power supply selection device includes the rise delay circuits 14 and 15, so that the time required for switching the power supply voltage can be set in the rise delay circuits 14 and 15.

Hereinafter, the power supply selection apparatus according to the first embodiment will be described in detail.
In FIG. 1, the drain of the PMOS transistor 11 a is connected to the voltage source input terminal 1, and the drain of the PMOS transistor 11 b is connected to the voltage source output terminal 3. The sources of the PMOS transistors 11a and 11b are connected to each other, and the back gates of the PMOS transistors 11a and 11b are connected to the respective sources.

  Similarly, the drain of the PMOS transistor 11 c is connected to the voltage source input terminal 2, and the drain of the PMOS transistor 11 d is connected to the voltage source output terminal 3. The sources of the PMOS transistors 11c and 11d are connected to each other, and the back gates of the PMOS transistors 11c and 11d are connected to the respective sources.

  The output terminal of the OR circuit 18 is connected to the gate of the PMOS transistor 11a, and the voltage source output terminal 3 is connected to one input terminal of the OR circuit 18 through the resistor 12a. Further, the drain of the NMOS transistor 13a whose source is grounded is connected to the connection point between the OR circuit 18 and the resistor 12a. The other input terminal of the OR circuit 18 is connected to the PMOS transistor control terminal 5.

  Therefore, when an L level signal is input to the PMOS transistor control terminal 5, the PMOS transistor 11a is turned off and turned on in response to the turn-off and turn-on of the NMOS transistor 13a. That is, when the NMOS transistor 13a is in the OFF state, the voltage from the voltage source output terminal 3 is applied to one input terminal of the OR circuit 18 via the resistor 12a, and the gate voltage Va of the PMOS transistor 11a becomes H level. Therefore, the PMOS transistor 11a is turned off. When the NMOS transistor 13a is in the on state, the gate voltage Va of the PMOS transistor 11a is at the L level, so that the PMOS transistor 11a is in the on state.

  On the other hand, when an H level signal is input to the PMOS transistor control terminal 5, the gate voltage Va of the PMOS transistor 11a is always at the H level regardless of whether the NMOS transistor 13a is on or off. The PMOS transistor 11a is always off.

  The voltage source output terminal 3 is connected to the gate of the PMOS transistor 11c via the resistor 12c. The drain of the NMOS transistor 13c whose source is grounded is connected to the connection point between the gate of the PMOS transistor 11c and the resistor 12c. Is connected.

  Therefore, the PMOS transistor 11c is turned off and turned on in response to the turn-off and turn-on of the NMOS transistor 13c. That is, when the NMOS transistor 13c is off, the voltage from the voltage source output terminal 3 is applied to the gate of the PMOS transistor 11c via the resistor 12c, and the gate voltage Vc of the PMOS transistor 11c becomes H level. The transistor 11c is turned off. When the NMOS transistor 13c is in the on state, the gate voltage Vc of the PMOS transistor 11c is at the L level, so that the PMOS transistor 11c is in the on state.

  The connection point between the PMOS transistor 11a and the PMOS transistor 11b is connected to the gate of the PMOS transistor 11b via the resistor 12b, and the source is grounded at the connection point between the gate of the PMOS transistor 11b and the resistor 12b. The drain of the NMOS transistor 13b is connected.

  Therefore, the PMOS transistor 11b is turned off and turned on in response to the turn-off and turn-on of the NMOS transistor 13b. That is, when the PMOS transistor 11a is on and the NMOS transistor 13b is off, the voltage from the voltage source input terminal 1 is applied to the gate of the PMOS transistor 11b via the resistor 12b, and the PMOS transistor 11b Since the gate voltage Vb becomes H level, the PMOS transistor 11b is turned off. When both the PMOS transistor 11a and the NMOS transistor 13b are in the off state, the voltage from the higher potential of the voltage source input terminal 1 and the voltage source output terminal 3 is changed between the PMOS transistor 11a and the parasitic diode of the PMOS transistor 11b. Since it is applied to the gate of the PMOS transistor 11b via the resistor 12b and the gate voltage Vb of the PMOS transistor 11b becomes H level, the PMOS transistor 11b is turned off. When the NMOS transistor 13b is in the on state, the gate voltage Vb of the PMOS transistor 11b is at the L level, so that the PMOS transistor 11b is in the on state.

  The output terminal of the AND circuit 19 is connected to the gate of the PMOS transistor 11d, and the connection point between the PMOS transistor 11c and the PMOS transistor 11d is connected to one input terminal of the AND circuit 19 through the resistor 12d. Is connected. The drain of the NMOS transistor 13d whose source is grounded is connected to the connection point between the AND circuit 19 and the resistor 12d. The other input terminal of the AND circuit 19 is connected to the PMOS transistor control terminal 5 via the logic inverter 17.

  Therefore, when an L level signal is input to the PMOS transistor control terminal 5, the PMOS transistor 11d is turned off and turned on in response to the turn-off and turn-on of the NMOS transistor 13d.

  That is, when the PMOS transistor 11c is on and the NMOS transistor 13d is off, the voltage from the voltage source input terminal 2 is applied to one input terminal of the AND circuit 19 via the resistor 12d. Since the gate voltage Vd of the PMOS transistor 11d becomes H level, the PMOS transistor 11d is turned off. When both the PMOS transistor 11c and the NMOS transistor 13d are in the off state, the voltage from the higher potential of the voltage source input terminal 2 and the voltage source output terminal 3 is the PMOS transistor 11c or the parasitic diode of the PMOS transistor 11d. Since it is applied to one input terminal of the AND circuit 19 via the resistor 12d and the gate voltage Vd of the PMOS transistor 11d becomes H level, the PMOS transistor 11d is turned off. When the NMOS transistor 13d is in the on state, the gate voltage Vd of the PMOS transistor 11d is at the L level, so that the PMOS transistor 11d is in the on state.

  On the other hand, when an H level signal is input to the PMOS transistor control terminal 5, the gate voltage Vd of the PMOS transistor 11d is always at the L level regardless of whether the NMOS transistor 13d is on or off. The PMOS transistor 11d is always on.

  The switching control circuit 6 controls the switching operation of the NMOS transistors 13a to 13d according to the selection signal Vddcnt (logic signal) input to the switching control input terminal 4. Specifically, the switching control circuit 6 includes rise delay circuits 14 and 15 and a logic inverter 16, and applies the input selection signal Vddcnt to the gates of the NMOS transistors 13 a and 13 b via the rise delay circuit 14. Then, a signal obtained by inverting the selection signal Vddcnt by the logic inverter 16 is applied to the gates of the NMOS transistors 13c and 13d via the rising delay circuit 15.

  Therefore, when the selection signal Vddcnt is at the H level, the signal V14 applied from the rising delay circuit 14 to the gates of the NMOS transistors 13a and 13b becomes the H level, and is applied from the rising delay circuit 15 to the gates of the NMOS transistors 13c and 13d. Since the signal V15 is L level, the NMOS transistors 13a and 13b are turned on, and the NMOS transistors 13c and 13d are turned off. On the other hand, when the selection signal Vddcnt is at L level, the signal V14 is at L level and the signal V15 is at H level, so that the NMOS transistors 13a and 13b are turned off and the NMOS transistors 13c and 13d are turned on.

  Further, when the selection signal Vddcnt is inverted from the L level to the H level, the signal V14 is inverted from the L level to the H level with a delay of a predetermined delay time, and the signal V15 is instantaneously inverted from the H level to the L level. Further, when the selection signal Vddcnt is inverted from the H level to the L level, the signal V14 is instantaneously inverted from the H level to the L level, and the signal V15 is inverted from the L level to the H level after a predetermined delay time.

  The PMOS transistor control circuit 7 includes the logical inverter 17, the logical sum circuit 18, and the logical product circuit 19 described above. The PMOS transistor control circuit 7 is configured to determine whether the control circuit including the switching control circuit 6 and the PMOS transistor control circuit 7 transits between the first, second, and third states. It is determined according to the control signal Vswcnt (logic signal) input to the PMOS transistor control terminal 5 whether the transition is made between these states.

  That is, when the control signal Vswcnt is at the H level, the H level signal is applied from the OR circuit 18 to the gate of the PMOS transistor 11a regardless of whether the NMOS transistor 13a is on or off. The transistor 11a is turned off. Further, when the control signal Vswcnt is at the H level, an L level signal is applied from the AND circuit 19 to the gate of the PMOS transistor 11d regardless of whether the NMOS transistor 13d is in the on state or the off state. The transistor 11d is turned on.

  Therefore, when the control signal Vswcnt is at the H level, if the selection signal Vddcnt input to the switching control input terminal 4 is at the H level, the PMOS transistors 11a and 11c are turned off and the PMOS transistors 11b and 11d are turned on. Therefore, the higher voltage of the voltages V1 and V2 applied to the voltage source input terminals 1 and 2 is supplied to the voltage source output terminal 3 via the PMOS transistor 11a or the parasitic diode of the PMOS transistor 11c ( In the first state), if the selection signal Vddcnt is at L level, the PMOS transistors 11a and 11b are turned off and the PMOS transistors 11c and 11d are turned on, so that the voltage V2 applied to the voltage source input terminal 2 is The voltage is supplied to the voltage source output terminal 3 (second state).

  Further, when the selection signal Vddcnt is inverted from the H level to the L level, the signal V14 is instantaneously inverted from the H level to the L level as described above, and the signal V15 is inverted from the L level to the H level after a predetermined delay time. Therefore, the PMOS transistor 11b is instantaneously turned off, and the PMOS transistor 11c is turned on with a predetermined delay time after the selection signal Vddcnt is inverted from the H level to the L level. Further, when the selection signal Vddcnt is inverted from the L level to the H level, the signal V14 is inverted from the L level to the H level with a predetermined delay time as described above, and the signal V15 is instantaneously inverted from the H level to the L level. Therefore, the PMOS transistor 11b is turned on with a predetermined delay time after the selection signal Vddcnt is inverted from the L level to the H level, and the PMOS transistor 11c is instantaneously turned off.

  Accordingly, the PMOS transistors 11a to 11c are turned off during the transition of the control circuit from the first state to the second state and during the transition of the control circuit from the second state to the first state. Since the PMOS transistor 11d is turned on, the voltage V2 applied to the voltage source input terminal 2 is supplied to the voltage source output terminal 3 via the parasitic diode of the PMOS transistor 11c (third state).

  On the other hand, when the control signal Vswcnt is at the L level, the PMOS transistors 11a and 11d are turned on and turned off according to the turn-on and turn-off of the NMOS transistors 13a and 13d.

  Therefore, when the control signal Vswcnt is at the L level, if the selection signal Vddcnt input to the switching control input terminal 4 is at the H level, the PMOS transistors 11a and 11b are turned on and the PMOS transistors 11c and 11d are turned off. Therefore, if the voltage V1 applied to the voltage source input terminal 1 is supplied to the voltage source output terminal 3 (fourth state) and the selection signal Vddcnt is at L level, the PMOS transistors 11a and 11b are turned off, and the PMOS transistor Since the transistors 11c and 11d are turned on, the voltage V2 applied to the voltage source input terminal 2 is supplied to the voltage source output terminal 3 (second state).

  When the selection signal Vddcnt is inverted from the H level to the L level, the signal V14 is instantaneously inverted from the H level to the L level, and the signal V15 is inverted from the L level to the H level after a predetermined delay time. The transistors 11a and 11b are instantaneously turned off, and the PMOS transistors 11c and 11d are turned on with a predetermined delay time after the selection signal Vddcnt is inverted from the H level to the L level. Further, when the selection signal Vddcnt is inverted from the L level to the H level, the signal V14 is inverted from the L level to the H level with a delay of a predetermined delay time, and the signal V15 is instantaneously inverted from the H level to the L level. The transistors 11a and 11b are turned on with a predetermined delay time after the selection signal Vddcnt is inverted from the L level to the H level, and the PMOS transistors 11c and 11d are instantaneously turned off.

  Therefore, during the transition of the control circuit from the fourth state to the second state and during the transition of the control circuit from the second state to the fourth state, the PMOS transistors 11a to 11d are in the off state. (Fifth state)

  In this way, the PMOS transistor control circuit 7 is used when the selection signal Vddcnt input to the switching control input terminal 4 is inverted from the H level to the L level, or from the L level to the H level, that is, when the power supply voltage is switched. A dead time period in which all of the PMOS transistors 11a to 11d are cut off is provided, or the PMOS transistors 11a to 11c are cut off and the PMOS diode 11 is turned on, so that the voltage source output is switched even when the power supply voltage is switched. By supplying the power supply voltage to the supplied circuit connected to the end 3, it is determined whether or not to provide a dead time period.

  Therefore, when the control signal Vswcnt input to the PMOS transistor control terminal 5 is at the L level, a dead time period in which all of the PMOS transistors 11a to 11d are cut off when the power supply voltage is switched is provided. It is possible to prevent a through current from occurring between 1 and 2. Even when the control signal Vswcnt is at the H level, the PMOS transistors 11a and 11c are cut off when the power supply voltage is switched, so that a through current can be prevented from being generated between the voltage source input terminals 1 and 2. .

  In addition, when a dead time period is provided, if the voltage source output terminal 3 does not have a large capacity, a constant voltage cannot be supplied to the supplied circuit connected to the voltage source output terminal 3, and the supplied circuit Operation may become unstable. On the other hand, when the dead time period is not provided, when the power supply voltage is switched, a forward voltage drop due to the parasitic diode of the PMOS transistor 11c occurs in the voltage supplied to the supplied circuit connected to the voltage source output terminal 3. Therefore, a voltage lower than the voltage V2 supplied to the voltage source input terminal 2 is supplied to the supplied circuit. Therefore, when it is not necessary to always supply the power supply voltage to the supplied circuit, a dead time period is provided to prevent the forward voltage drop, and the power supply voltage supplied to the supplied circuit decreases due to the forward voltage drop. Even when the power supply voltage needs to be constantly supplied to the supplied circuit, the dead time period is not provided.

  Subsequently, the operation of the power supply selection apparatus according to the first embodiment will be described. 2 shows a control signal Vswcnt input to the PMOS transistor control terminal 5, a selection signal Vddcnt input to the switching control input terminal 4, gate voltages Va, Vb, Vc, Vd of the PMOS transistors 11a, 11b, 11c, and 11d. FIG. 2A is a timing chart of an output voltage Vout generated at a voltage source output terminal 3. FIG. 2A shows a case where the control signal Vswcnt is at L level, and FIG. 2B shows a case where the control signal Vswcnt is H. The case of level is shown.

  First, the operation of the power supply selection device when the control signal Vswcnt is at the L level will be described. As shown in FIG. 2A, when the selection signal Vddcnt is at the H level, the gate voltages Va and Vb of the PMOS transistors 11a and 11b are at the L level, and the gate voltages Vc and Vd of the PMOS transistors 11c and 11d are at the H level. Therefore, the PMOS transistors 11a and 11b are turned on, and the PMOS transistors 11c and 11d are turned off. Therefore, at this time, the output voltage Vout supplied from the voltage source output terminal 3 to the supplied circuit becomes the voltage V1 applied to the voltage source input terminal 1 (fourth state).

  Next, when the selection signal Vddcnt is inverted from the H level to the L level, the gate voltages Va and Vb of the PMOS transistors 11a and 11b are instantaneously inverted from the L level to the H level, and the gate voltages Vc and Vd of the PMOS transistors 11c and 11d. Is delayed from the H level to the L level by a delay time t1 by the rising delay circuit 15, so that the PMOS transistors 11a and 11b instantaneously change from the conductive state to the cut-off state, and the PMOS transistors 11c and 11d become after the delay time t1. Transition from the interrupted state to the conductive state. That is, when the selection signal Vddcnt is inverted from the H level to the L level, the PMOS transistors 11a to 11d are cut off during the delay time t1 (fifth state), and the output voltage Vout is input to the voltage source after the delay time t1. The voltage V2 is applied to the terminal 2 (second state). The period of the delay time t1 is a dead time period.

  Next, when the selection signal Vddcnt is inverted from the L level to the H level, the gate voltages Va and Vb of the PMOS transistors 11a and 11b are inverted from the H level to the L level after a delay time t2 by the rising delay circuit 14, and the PMOS transistor Since the gate voltages Vc and Vd of 11c and 11d are instantaneously inverted from the L level to the H level, the PMOS transistors 11a and 11b transition from the cutoff state to the conductive state after the delay time t2, and the PMOS transistors 11c and 11d instantaneously Transition from the conduction state to the cutoff state. That is, when the selection signal Vddcnt is inverted from the L level to the H level, the PMOS transistors 11a to 11d are cut off (fifth state) during the delay time t2, and the output voltage Vout becomes the voltage V1 after the delay time t2. (Fourth state). The period of the delay time t2 becomes a dead time period.

  Next, the operation of the power supply selection apparatus when the control signal Vswcnt is at the H level will be described. As shown in FIG. 2B, when the control signal Vswcnt is at the H level, the gate voltage Va of the PMOS transistor 11a is always at the H level, and the gate voltage Vd of the PMOS transistor 11d is always at the L level. Is always cut off, and the PMOS transistor 11d is always on.

  When the selection signal Vddcnt is at the H level, the gate voltage Vb of the PMOS transistor 11b is at the L level, and the gate voltage Vc of the PMOS transistor 11c is at the H level, so that the PMOS transistor 11b is in the conductive state and the PMOS transistor 11c is in the cutoff state. Become. Accordingly, at this time, the higher voltage of the voltage V1 applied to the voltage source input terminal 1 and the voltage V2 applied to the voltage source input terminal 2 is applied to the parasitic diode of the PMOS transistor 11a or PMOS transistor 11c. The output voltage Vout applied to the voltage source output terminal 3 and supplied from the voltage source output terminal 3 to the supplied circuit becomes the voltage (V1-Vf) or the voltage (V2-Vf) (first state) ). Here, “Vf” is the forward voltage of the parasitic diode.

  Next, when the selection signal Vddcnt is inverted from the H level to the L level, the gate voltage Vb of the PMOS transistor 11 b is instantaneously inverted from the L level to the H level, and the gate voltage Vc of the PMOS transistor 11 c is delayed by the delay circuit 15. Since the inversion from the H level to the L level is delayed by t1, the PMOS transistor 11b instantaneously changes from the conductive state to the cut-off state, and the PMOS transistor 11c changes from the cut-off state to the conductive state after the delay time t1. Therefore, during this delay time t1, the voltage V2 applied to the voltage source input terminal 2 is applied to the voltage source output terminal 3 via the parasitic diode of the PMOS transistor 11c, and the output voltage Vout is the voltage (V2-Vf). (Third state), and after the delay time t1, the output voltage Vout becomes the voltage V2 (second state).

  Next, when the selection signal Vddcnt is inverted from the L level to the H level, the gate voltage Vb of the PMOS transistor 11b is inverted from the H level to the L level after a delay time t2 by the rising delay circuit 14, and the gate voltage of the PMOS transistor 11c is inverted. Since Vc is instantaneously inverted from the L level to the H level, the PMOS transistor 11b changes from the cutoff state to the conduction state after the delay time t2, and the PMOS transistor 11c instantaneously changes from the conduction state to the cutoff state. Therefore, during this delay time t2, the voltage V2 applied to the voltage source input terminal 2 is applied to the voltage source output terminal 3 via the parasitic diode of the PMOS transistor 11c, and the output voltage Vout is the voltage (V2-Vf). (The third state), and after the delay time t2, the output voltage Vout becomes the voltage (V1-Vf) or the voltage (V2-Vf) (first state).

  As described above, according to the first embodiment, a through current generated between the voltage source input terminals can be prevented. In addition, when the dead time is provided, a voltage without a forward voltage drop can be supplied to the supplied circuit, so that it is possible to widen the operating range of the supplied circuit, and to the supplied circuit when the dead time is not provided. The power supply voltage can always be supplied, and the operation of the supplied circuit can be prevented from becoming unstable.

(Embodiment 2)
Hereinafter, a second embodiment of the power source selection apparatus of the present invention will be described with reference to the drawings. FIG. 3 is a diagram illustrating an example of a circuit configuration of the power supply selection device according to the second embodiment of the present invention. However, the same members as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In this power source selection device, a voltage applied to the voltage source input terminals 1 and 2 is detected by the switching control circuit 6a, and a control circuit comprising the switching control circuit 6a and the PMOS transistor control circuit 7 is detected according to the detected voltage. This is different from the power source selection apparatus in the first embodiment described above in that it transits between the first, second, and third states or between the second, fourth, and fifth states.

  Specifically, this power supply selection device has a specification in which a voltage V1 having a voltage value higher than the voltage V2 applied to the voltage source input terminal 2 is applied to the voltage source input terminal 1, and the switching control circuit 6a is When the voltages V1 and V2 are applied to the voltage source input terminals 1 and 2, the voltage based on the voltage V1 applied to the voltage source input terminal 1 is supplied to the supplied circuit as a power supply voltage. When the signals V14 and V15 for controlling the switching operation of the NMOS transistors 13a to 13d are generated and the voltage source input terminal 1 is not input and the voltage V2 is applied to the voltage source input terminal 2, the voltage source input terminal 2 The signals V14 and V15 for controlling the switching operation of the NMOS transistors 13a to 13d are generated so that a voltage based on the voltage V2 applied to is supplied to the supplied circuit as a power supply voltage. When the voltage V1 is applied to the voltage source input terminal 1 and the voltage source input terminal 2 is not input, a voltage based on the voltage V1 applied to the voltage source input terminal 1 is supplied to the supplied circuit as a power supply voltage. As described above, the signals V14 and V15 for controlling the switching operation of the NMOS transistors 13a to 13d are generated. The specification that the voltage V1 having a voltage value higher than the voltage V2 applied to the voltage source input terminal 2 is applied to the voltage source input terminal 1 is, for example, the voltage from the AC adapter applied to the voltage source input terminal 1 There is a specification in which a voltage is applied to the voltage source input terminal 2 via the USB.

Hereinafter, the power supply selection apparatus according to the second embodiment will be described in detail.
In FIG. 3, a reference voltage generation circuit 22 generates a reference voltage using a high potential side of voltages input from voltage source input terminals 1 and 2 via diodes 21a and 22b as a power source.

  In the comparator 24, a voltage obtained by dividing the voltage V1 from the voltage source input terminal 1 by the detection resistors 23a and 23b is input to the non-inverting input terminal, and the reference voltage from the reference voltage generating circuit 22 is input to the inverting input terminal. When the voltage obtained by dividing the voltage V1 by the detection resistors 23a and 23b is higher than the reference voltage, an H level signal is generated. When the voltage obtained by dividing the voltage V1 by the detection resistors 23a and 23b is lower than the reference voltage, L is generated. Generate level signal.

  The output terminal of the comparator 24 is connected to the gates of the NMOS transistors 13a and 13b via the rise delay circuit 14. The output terminal of the comparator 24 is also connected to the gate of the NMOS transistor 28a whose source is grounded. When the voltage obtained by dividing the voltage V1 by the detection resistors 23a and 23b is higher than the reference voltage, the NMOS transistor 28a When the voltage obtained by dividing the voltage V1 by the detection resistors 23a and 23b is lower than the reference voltage, the NMOS transistor 28a is turned off.

  In the comparator 26, a voltage obtained by dividing the voltage V2 from the voltage source input terminal 2 by the detection resistors 25a and 25b is input to the inverting input terminal, and the reference voltage from the reference voltage generating circuit 22 is input to the non-inverting input terminal. When the voltage obtained by dividing the voltage V2 by the detection resistors 25a and 25b is lower than the reference voltage, an H level signal is generated. When the voltage obtained by dividing the voltage V2 by the detection resistors 25a and 25b is higher than the reference voltage, L is generated. Generate level signal.

  The output terminal of the comparator 26 is connected to the gate of the NMOS transistor 28b whose source is grounded. When the voltage divided by the detection resistors 25a and 25b is lower than the reference voltage, the NMOS transistor 28b is turned on. When the voltage obtained by dividing the voltage V2 by the detection resistors 25a and 25b is higher than the reference voltage, the NMOS transistor 28b is turned off.

  The load resistor 27 has one end connected to the voltage source input terminal 2 and the other end connected to the rising delay circuit 15. The drains of the NMOS transistors 28a and 28b are connected to the connection point between the load resistor 27 and the rising delay circuit 15.

  Next, the operation of the power supply selection device according to the second embodiment will be described. 4 shows a control signal Vswcnt input to the PMOS transistor control terminal 5, a voltage V1 applied to the voltage source input terminal 1, a voltage V2 applied to the voltage source input terminal 2, the rise delay circuit 14 to the NMOS transistor 13a, 13B is a timing chart of the signal V14 applied to the gate of 13b, the signal V15 applied from the rising delay circuit 15 to the gates of the NMOS transistors 13c and 13d, and the output voltage Vout generated at the voltage source output terminal 3. 4 (a) shows the case where the control signal Vswcnt is at L level, and FIG. 4 (b) shows the case where the control signal Vswcnt is at H level.

  When voltages V1 and V2 (V1> V2) are applied to the voltage source input terminals 1 and 2, an H level signal is generated from the comparator 24, an L level signal is generated from the comparator 26, and an NMOS Since the transistor 28a is turned on and the NMOS transistor 28b is turned off, the signal V14 becomes H level and the signal V15 becomes L level.

  Therefore, when the control signal Vswcnt is at the L level, the PMOS transistors 11a and 11b are turned on, and the PMOS transistors 11c and 11d are turned off. As shown in FIG. The output voltage Vout supplied to the supply circuit becomes the voltage V1 applied to the voltage source input terminal 1 (fourth state).

  On the other hand, when the control signal Vswcnt is at the H level, the PMOS transistors 11a and 11c are cut off and the PMOS transistors 11b and 11d are turned on. Here, since voltage V1> voltage V2, the voltage V1 applied to the voltage source input terminal 1 is applied to the voltage source output terminal 3 via the parasitic diode of the PMOS transistor 11a, and is shown in FIG. As described above, the output voltage Vout supplied from the voltage source output terminal 3 to the supplied circuit becomes the voltage (V1−Vf) (first state).

  When the voltage source input terminal 1 is not input from this state, the signal from the comparator 24 is instantaneously inverted from the H level to the L level, and the NMOS transistor 28a instantaneously changes from the on state to the off state. V14 is instantaneously inverted from the H level to the L level, and the signal V15 is inverted by the rising delay circuit 15 from the L level to the H level after a delay time t1.

  Therefore, when the control signal Vswcnt is at the L level, the PMOS transistors 11a and 11b instantaneously change from the conductive state to the cut-off state, and the PMOS transistors 11c and 11d change from the cut-off state to the conductive state after the delay time t1. Therefore, as shown in FIG. 4A, during the delay time t1, the PMOS transistors 11a to 11d are cut off (fifth state), and the output voltage Vout is applied to the voltage source input terminal 2 after the delay time t1. The applied voltage becomes V2 (second state).

  On the other hand, when the control signal Vswcnt is at the H level, the PMOS transistor 11b instantaneously changes from the conductive state to the cut-off state, and the PMOS transistor 11c changes from the cut-off state to the conductive state after the delay time t1. As shown in (b), during the delay time t1, the voltage V2 applied to the voltage source input terminal 2 is applied to the voltage source output terminal 3 via the parasitic diode of the PMOS transistor 11c, and the output voltage Vout is the voltage. (V2−Vf) (third state), and after the delay time t1, the output voltage Vout becomes the voltage V2 (second state).

  Next, when the voltage V1 is applied to the voltage source input terminal 1 again from this state, the signal from the comparator 24 is instantaneously inverted from the L level to the H level, and the NMOS transistor 28a is instantaneously turned off. Since the transition is made to the ON state, the signal V14 is inverted from the L level to the H level after a delay time t1 by the rising delay circuit 14, and the signal V15 is instantaneously inverted from the H level to the L level.

  Therefore, when the control signal Vswcnt is at the L level, the PMOS transistors 11c and 11d instantaneously change from the conductive state to the cut-off state, and the PMOS transistors 11a and 11b change from the cut-off state to the conductive state after the delay time t2. Therefore, as shown in FIG. 4A, during the delay time t2, the PMOS transistors 11a to 11d are cut off (fifth state), and after the delay time t2, the output voltage Vout becomes the voltage V1 (fourth state). Status).

  On the other hand, when the control signal Vswcnt is at the H level, the PMOS transistor 11c instantaneously changes from the conductive state to the cut-off state, and the PMOS transistor 11b changes from the cut-off state to the conductive state after the delay time t2. As shown in (b), during the delay time t2, the voltage V2 applied to the voltage source input terminal 2 is applied to the voltage source output terminal 3 via the parasitic diode of the PMOS transistor 11c, and the output voltage Vout is the voltage. (V2−Vf) (third state), and after the delay time t2, the output voltage Vout becomes the voltage (V1−Vf) (first state).

  Although not shown, when the voltage V1 is applied to the voltage source input terminal 1 and the voltage source input terminal 2 is not input, an H level signal is generated from the comparators 24 and 26, and the NMOS transistor 28a. 28b are turned on, the signal V14 becomes H level and the signal V15 becomes L level. Therefore, when the control signal Vswcnt is at the L level, the PMOS transistors 11a and 11b are turned on, the PMOS transistors 11c and 11d are turned off, and the output voltage Vout becomes the voltage V1 (fourth state). When the signal Vswcnt is at the H level, the PMOS transistors 11a and 11c are cut off, the PMOS transistors 11b and 11d are turned on, and the output voltage Vout becomes the voltage (V1-Vf) (first state). .

  In the power supply selection device according to the present invention, the operation of the supplied circuit connected to the output terminal does not become unstable, and no through current is generated. For example, the power supply selection device supplies the internal circuit according to a plurality of types of operation modes This is useful for an electronic device or the like configured to switch the power supply voltage.

The figure which shows an example of the circuit structure of the power supply selection apparatus in Embodiment 1 of this invention. The figure which shows the timing chart for demonstrating operation | movement of the power supply selection apparatus in Embodiment 1 of this invention. The figure which shows an example of the circuit structure of the power supply selection apparatus in Embodiment 2 of this invention. The figure which shows the timing chart for demonstrating operation | movement of the power supply selection apparatus in Embodiment 2 of this invention. The figure which shows the circuit structure of the conventional power supply selection apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Voltage source input terminal 3 Voltage source output terminal 4 Switching control input terminal 5 PMOS transistor control terminal 6, 6a Switching control circuit 7 PMOS transistor control circuit 11a-11d PMOS transistor 12a-12d Resistance 13a-13d NMOS transistor 14, 15 Rise delay circuit 16, 17 Logical inverter 18 OR circuit 19 AND circuit 21a, 21b Diode 22 Reference voltage generation circuit 23a, 23b, 25a, 25b Detection resistor 24, 26 Comparator 27 Load resistor 28a, 28b NMOS transistor 101-103 Input terminal 104 Output terminal Tr11, Tr12 PMOS transistor D1, D2 Diode In11, In12 Inverter

Claims (5)

First and second input terminals to which a voltage is applied;
An output terminal;
First and second transistors connected in series between the first input terminal and the output terminal;
Third and fourth transistors connected in series between the second input terminal and the output terminal;
A first rectifier element connected in parallel to the first transistor and configured to flow current from the first input terminal side to the second transistor side;
A second rectifier element connected in parallel to the second transistor and configured to flow current from the output terminal side to the first transistor side;
A third rectifier element connected in parallel to the third transistor and configured to flow current from the second input terminal side to the fourth transistor side;
A fourth rectifying element connected in parallel to the fourth transistor and configured to flow current from the output terminal side to the third transistor side;
A first state in which the first and third transistors are turned off and a state in which the second and fourth transistors are turned on; a state in which the first and second transistors are turned off; and the third and During the transition from the first state or the second state to the second state or the first state, the first to third transistors are turned off while the fourth transistor is turned on. And a control circuit having a third state for bringing the fourth transistor into a conductive state;
A power supply selection device comprising:   The control circuit includes a fourth state in which the first and second transistors are turned on and a state in which the third and fourth transistors are cut off, and the second state from the fourth or second state. The power supply selection device according to claim 1, further comprising: a fifth state in which the first to fourth transistors are turned off during the transition to the fourth state.   When the control circuit transits from the first or fourth state to the second state, the control circuit conducts the third transistor or the third and fourth transistors from the cut-off state after a preset delay time. A first delay circuit for transitioning to a state, and the second transistor or the first and second after a predetermined delay time when transitioning from the second state to the first or fourth state 3. A power selection device according to claim 2, further comprising: a second delay circuit configured to cause the two transistors to transition from the cutoff state to the conduction state.   4. The power supply according to claim 1, wherein the control circuit detects a voltage applied to the first and second input terminals and makes a state transition according to the detected voltage. 5. Selection device.   The first transistor and the first rectifier element, the second transistor and the second rectifier element, the third transistor and the third rectifier element, and the fourth transistor and the fourth transistor 5. The power supply selecting device according to claim 1, wherein each of the rectifying elements is a PMOS transistor and a parasitic diode thereof.

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