JP2009290950A - Power system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply system capable of improving the power factor and power loss as compared with the conventional one and reducing the size of the transformer.
A power supply system 100 includes a power transformer 110 that converts AC 100V into AC 24V, and a plurality of power units 200-1 to 200-n connected to the power transformer 110. The power supply unit 200-1 includes a rectifier circuit 210 that rectifies AC 24V by a synchronous rectifier bridge, a power factor improvement circuit 220 that improves the power factor of the rectified voltage, and an output circuit 230 that outputs a DC voltage. The power factor correction circuit 220 includes an inductor L, FET1, FET2, and a control circuit 222 that controls switching of the FET1 and FET2. The control circuit 222 adjusts the duty ratio of the FET1 and FET2 to obtain a desired direct current. The voltage is output from the output circuit 230.
[Selection] Figure 4

Description

  The present invention relates to a power supply system that supplies AC power from a single AC power supply to a plurality of power supply units, and more particularly to improvement of power loss and power factor in the power supply unit.

  As semiconductor devices and electronic devices are miniaturized and combined, driving voltages of internal power supplies used in those devices and devices are diversified. For example, in a semiconductor device such as a CPU or a memory, the circuit line width is reduced in order to achieve high density integration, and accordingly, the drive voltage is decreased from 5V to 3.3V and 1.8V. In addition, driving voltages for driving liquid crystal displays, audio devices, recording media, semiconductor devices, and the like may be different in electronic devices such as mobile phones, computers, OA equipment, in-vehicle electronic devices, and gaming machines. For example, drive voltages of 24V, 12V, 5V, 3.3V, and 1.8V are required.

  Against this background, the power supply device is required to supply various drive voltages. When a desired DC voltage is generated from a commercial AC voltage or a DC voltage, a switching power supply is widely used. The switching power supply generates a DC voltage obtained by converting the input DC voltage by adjusting the duty ratio of the on / off switching of the transistor.

  FIG. 1 is a circuit diagram showing an example of a conventional step-down switching power supply device. The transistor Tr is connected to the primary side of the transformer T, and the drive signal S from the PWM drive circuit is connected to the gate of the transistor Tr. On the secondary side of the transformer T, rectifying and circulating diodes D1 and D2, an inductor L, and a capacitor C are connected. The input DC voltage Vin is converted into a desired DC voltage Vout by adjusting the ON / OFF duty ratio of the transistor Tr.

  In the switching power supply device shown in FIG. 1, a synchronous rectification type power supply in which the diodes D1 and D2 are replaced with switching elements is proposed in Patent Document 1 in order to suppress power loss due to a forward voltage drop of the diodes D1 and D2. ing. According to this, as shown in FIG. 2, the auxiliary winding 4 provided on the secondary side of the conversion transformer T1 and the output of the auxiliary winding 4 are received and arranged between the conversion transformer secondary windings. A forward type DC / DC converter including an FET gate voltage holding circuit 3 for generating a signal for turning on / off the gates of the rectifying FET 2 and the commutating FET 3 is disclosed. Further, Patent Document 2 discloses a technique for obtaining different voltages, for example, 3.3 V and 1.8 V outputs from one input in a synchronous rectification DC-DC converter power supply device.

JP 2004-180386 A JP 2004-208490 A

  As described above, the conventional switching power supply device, as shown in Patent Document 1 and Patent Document 2, reduces power loss by a synchronous rectifier circuit, but improves power factor correction (PFC). It wasn't enough. The reason why synchronous rectification was not used for power factor improvement is that when AC100V (domestic) or AC220V (Europe) is input, the input voltage is boosted to a peak value (approximately 1.4 times the input voltage). This is because the current was not a problem.

  However, the power supply unit connected to the power supply obtained by stepping down the AC power supply becomes a power supply device or power supply system with a large input current (secondary side of the transformer T), and apparent power due to a decrease in power factor cannot be ignored. . For example, as shown in FIG. 3, a power supply system including a transformer 10 that converts an AC power supply of AC 100 V into an AC power supply of AC 24 volts, and a plurality of power supply units 20 to 26 that input the AC 24 V AC power supply generated by the transformer 10. Then, the current Ib supplied to each of the power supply units 20 to 26 is approximately four times (Ib = 4 × Ia) as compared to the current Ia flowing when the AC power supply is 100 V, and if the power factor is low, it is not used effectively. The ratio of apparent power increases.

  The power factor in the rectifier circuit is expressed by the ratio of the active power W and the apparent power VA, that is, W / VA. If the power factor is low, the apparent power VA includes a lot of reactive power that is not effectively used. In normal capacitor input type rectification, the power factor is about 0.6. For this reason, for example, in the power supply system as shown in FIG. 3, assuming that the efficiency is 0.85, the power factor is 0.6, and the power consumption of the load on the output side is 12 V × 5 A, the apparent power VA of the transformer 10 is As shown in Formula (1), it is about 117 VA.

  As a result, the input current of the transformer 10 is 4.875 A as shown in Equation (2). As is clear from the equation (2), the higher the power factor, the smaller the input current from the transformer 10 (current on the secondary side of the transformer 10).

  In the power supply system as shown in FIG. 3, since a plurality of power supply units are connected to the transformer 10, the input current of the transformer 10 is increased by the number of power supply units. As a result, the transformer 10 can be reduced in size. Becomes difficult and the cost becomes high.

  On the other hand, the diode D used for rectification of the power supply units 20 to 26 causes a voltage drop in the forward direction. If the voltage drop is about 0.9V, 0.9V × 4Ia of power is lost. As described above, if the power factor is not improved, the power of 4.875A × 0.9V≈4.4W will be lost in one power supply unit, and the power loss of the entire power supply unit is also considerably large. turn into. In particular, if the voltage or current of the input AC power supply increases, a large amount of power is lost accordingly, which cannot be ignored at all.

The present invention has been made to solve the above-described conventional problems, and provides a power supply system capable of improving the power factor as compared with the conventional technique and reducing the size and cost of the power transformer. Objective.
Furthermore, an object of this invention is to provide the power supply system which can reduce a power loss conventionally.

  A power supply system according to the present invention is connected to a transformer for converting a first AC power supply having a first voltage into a second AC power supply having a second voltage lower than the first voltage, And a plurality of power supply units for inputting a second AC power supply of the transformer. Each power supply unit rectifies the second AC voltage of the second AC power source supplied from the transformer and outputs the rectified voltage, and the power factor of the rectified power connected to the rectifier circuit A power factor correction circuit for improving and an output circuit connected to the power factor correction circuit and outputting a DC voltage, the power factor correction circuit being an inductor connected in series to the first voltage line of the rectifier circuit A first transistor connected in series with the inductor, a second transistor connected between a node connecting the inductor and the first transistor, and a second voltage line of the rectifier circuit; And a control circuit that controls switching of the second transistor, and when the second transistor is turned on, the control circuit turns off the first transistor and turns off the second transistor. When the first transistor is turned on, the rectifying circuit comprises a bridge of a plurality of MOS transistors operating in response to the current.

  Preferably, the first and second transistors are MOSFETs, the drain of the first transistor is connected to the inductor, the source of the first transistor is connected to the output circuit, and the drain of the second transistor is the first transistor. The drain of the second transistor, the source of the second transistor is connected to the second voltage line, the gates of the first and second transistors are connected to the control circuit, and from the output circuit, the second voltage A boosted DC voltage is output.

Preferably, the rectifier circuit includes first and second MOS transistors connected in series between a direct current output of a first potential and a direct current output of a second potential, and the first and second potentials. Third and fourth MOS transistors connected in series with the DC output, and gates of the first, second, third, and fourth MOS transistors in response to the current flowing through the DC output Driving means for outputting a gate signal;
One input of the AC voltage is connected to a first connection node that connects the first and second MOS transistors, and the other input of the AC voltage is a second that connects the third and fourth MOS transistors. In response to the input AC voltage connected to the connection node, current flows through the first and fourth MOS transistors during the first half-wave period, and during the second half-wave period, the second, A current flows through the third MOS transistor.

  Preferably, the first transistor, the second transistor, the control circuit, and the rectifier circuit are housed in one package. In this case, the package includes six external lead terminals, the first and second external terminals receive AC power, the third and fourth external terminals are connected to the inductor, and the fifth external terminal. Are connected to the ground potential, and the sixth external terminal is connected to the output.

  More preferably, the first voltage of the first AC power supply is 100 volts, the second AC voltage of the second AC power supply is 24 volts, and the output circuit outputs the DC voltage stepped down by the switching circuit. A DC-DC converter can be included.

  According to the present invention, in the power factor correction circuit, the first and second transistors capable of switching control are used to convert the second AC power source to the DC power source, so that the power factor can be improved. it can. For this reason, the input current of the transformer can be reduced as compared with the conventional one. As a result, the transformer can be reduced in size and cost. Furthermore, the overall power loss of the power system can be reduced by reducing the power consumption of the transistor in the power supply unit compared to that of the diode. Furthermore, by using a device in which the first and second transistors of the power factor correction circuit and the control circuit are packaged, the device can be easily adapted to various power supply units.

  Furthermore, according to the present invention, the AC voltage is converted into the DC voltage using the first to fourth transistors (MOSFETs), so that the power loss is greatly reduced compared with the rectification by the conventional diode bridge. can do. In particular, when the load current increases, the effect of reducing power loss is great.

  The best mode for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 4 is a diagram showing the configuration of the power supply system according to the embodiment of the present invention. The power supply system 100 includes an insulating power transformer 110 and a plurality of power supply units 200-1 to 200-n (n is a natural number) connected to the power transformer 110. The insulated power transformer 110 preferably inputs commercial AC 100V AC power to the primary side and outputs AC 24V AC power to the secondary side. On the secondary side of the power transformer 110, n power units 200-1 to 200-n are connected, and AC power of 24V AC is supplied to each of the power units 200-1 to 200-n. Such a power supply system is used, for example, in a pachinko game hall, and each play stand has one power supply unit.

  Since the internal configurations of the plurality of power supply units 200-1 to 200-n are substantially the same, the power supply unit 200-1 will be described here. The power supply unit 200-1 includes a rectifier circuit 210 that rectifies the AC 24 V power supply, a power factor correction circuit 220 connected to the rectifier circuit 210, and an output circuit 230 connected to the power factor improvement circuit 220. The

  The rectification circuit 210 includes a synchronous rectification type bridge 212 and rectifies an AC voltage of 24 V AC. The power factor correction circuit 220 includes an inductor L, FET1, FET2, and a control circuit 222. The inductor L is connected in series to the positive power supply line of the synchronous rectification bridge 212. The drain of FET1 is connected to inductor L at node N1, and the source of FET1 is connected to output circuit 230 at node N3. The drain of the FET2 is connected to the node N1, and the source of the FET2 is connected to the node N2 of the ground line. Control signals S1 and S2 output from the control circuit 222 are connected to the gates of the FET1 and FET2. The control circuit 222 preferably controls the switching of FET1 and FET2 at an appropriate frequency and duty ratio to bring the power factor close to 1.0.

  The output circuit 230 includes an electric field capacitor C connected between the node N3 and the ground line, and an output terminal Vout that outputs a DC voltage. By the switching control of the control circuit 222, a DC voltage boosted to about 34V is output from the output terminal Vout. If necessary, the output circuit 230 can include DC / DC converters 232 and 234 that step down the DC voltage of Vout. The converters 232 and 234 convert the output voltage into, for example, a DC voltage of 12V and 5V. The

  FIG. 5 is a diagram showing a preferred configuration of the synchronous rectification bridge shown in FIG. The synchronous rectification type bridge 212 includes an AC input ACIN for inputting an AC voltage, a DC output + DC for outputting a positive DC voltage, a DC output -DC for outputting a negative DC voltage, and an N-channel FET Q1 as a rectifying element. , FETQ2, FETQ3, FETQ4, FETQ1, Q2, a first driving circuit 250 for driving FETQ3, Q4, a second driving circuit 260 for driving FETQ3, Q4, and a comparison circuit (comparator for detecting current in synchronization with a half wave of AC voltage) ) 270. In the figure, R1 to R4, R14 and R15 are resistors, C1 to C3 are capacitors, D1 to D4 are diodes, and D1p to D4p are parasitic diodes of FETs Q1, Q2, Q3 and Q4. The first and second drive circuits 250 and 260 are preferably constituted by semiconductor integrated circuits.

  The DC output + DC of the synchronous rectifier converter 212 is connected to one end of the inductor L, and -DC is connected to the node N2. An FET Q1 and an FET Q2, and an FET Q3 and an FET Q4 are connected in series between the direct current output + DC and the direct current output -DC. One AC input ACIN of the AC voltage is connected to the connection node N10 where the FET Q1 is connected to the FET Q2. A drive signal G1 output from the first drive circuit 250 is connected to the gate of the FET Q1, and a resistor R1 is connected between the gate and source of the FET Q1. A parasitic diode D1p is connected in parallel with the FET Q1 between the DC output DC + and the connection node N10.

  A drive signal G2 output from the first drive circuit 250 is connected to the gate of the FET Q2, and a resistor R2 is connected between the gate and source of the FET Q2. A parasitic diode D2p is connected in parallel with the FET Q2 between the DC output DC− and the connection node N10.

  The other AC input ACIN of the AC voltage is connected to the connection node N20 where the FET Q3 is connected to the FET Q4. A drive signal G3 output from the second drive circuit 260 is connected to the gate of the FET Q3, and a resistor R3 is connected between the gate and source of the FET Q3. Between the DC output DC + and the node N20, a parasitic diode D3p is connected in parallel with the FET Q3.

  A drive signal G4 output from the second drive circuit 260 is connected to the gate of the FET Q4, and a resistor R4 is connected between the gate and source of the FET Q4. A parasitic diode D4p is connected between the DC output DC− and the node N20 in parallel with the FET Q4.

  Resistors R 14 and R 15 are connected to the DC output DC−, and the resistor R 15 is connected to one input of the comparison circuit 270. The resistor R14 is connected to the node N30, and a capacitor C3 is connected between the node N30 and the resistor R15. The node N30 is connected to the other input of the comparison circuit 270.

  The comparison circuit 270 is synchronized with an input AC voltage, that is, a high level (positive voltage) or a low level (negative voltage) in response to a current flowing when the smoothing capacitor is charged or discharged. Outputs a voltage signal. This output is connected to the cathode of the diode D3, and the anode of the diode D3 is connected to the node N40. The node N40 is connected to the first input of the first drive circuit 250 and the second input of the second drive circuit 260, respectively.

  The output of comparison circuit 270 is further connected to the cathode of diode D4, and the anode of diode D4 is connected to node N50. The node N50 is connected to the second input of the first drive circuit 250 and the first IN of the second drive circuit 260, respectively.

  Next, the operation of the power supply system will be described. The 24V AC power converted by the power transformer 110 is supplied to each of the power supply units 200-1 to 200-n. The 24V AC voltage is rectified by the rectifier circuit 210, and the rectified power is input to the power factor correction circuit 220.

  In the synchronous rectification type bridge 212, the comparison circuit 270 detects a current flowing when the smoothing capacitor C is charged or discharged, and outputs a high level voltage when the current is detected. When the output of the comparison circuit 270 is at a high level, the diodes D3 and D4 are disabled, and a constant high voltage is held at the nodes N40 and N50. On the other hand, when no current is detected by the comparison circuit 270, the output of the comparison circuit 270 is a low level voltage, and the diodes D3 and D4 are turned on, so that the nodes N40 and N50 are at a low voltage.

  When the nodes N40 and N50 are at a high voltage, high voltage signals are input to the first and second inputs of the first and second drive circuits 250 and 260, and the corresponding drive signals G1, G2, and G3. , G4 becomes high level, and FETs Q1, Q2, Q3, Q4 are turned on. In other words, a high-level gate signal is supplied to the FET Q1, FET Q2, FET Q3, and FET Q4 while the constant current is detected by the comparison circuit 270, and the FET Q1, FET Q2, FET Q3, and FET Q4 are in an operable on state. Placed.

  On the other hand, when the nodes N40 and N50 are at a low voltage, the first and second inputs of the first and second drive circuits 250 and 260 are at low level, and the corresponding drive signals G1, G2, G3, and G4 are at low level. The FETs Q1, Q2, Q3, and Q4 are turned off. That is, FETQ1, FETQ2, FETQ3, and FETQ4 are placed in an off state during a period when no current is detected by the comparison circuit 270.

  When a positive AC voltage is applied to the AC input ACIN while the output of the comparison circuit 270 is at a high level, the AC current is applied from the node N10 to the diode-connected FET Q1, DC output + DC, smoothing capacitor , DC output-DC, diode-connected FET Q4, and the path of node N20. When a negative AC voltage is applied, the AC current flows through the path of node N20, diode-connected FET Q3, DC output + DC, smoothing capacitor, DC output -DC, diode-connected FET Q2, and node N10. . Thus, the AC voltage is rectified every half wave.

  In this synchronous rectification type bridge, the FETs Q1 to Q4 are kept in an operating state during a current flow, so that the AC voltage can be rectified safely and efficiently.

  The control circuit 222 adjusts the duty ratio of the FET1 and FET2 by the control signals S1 and S2, accumulates electric energy in the inductor L, and supplies the accumulated energy to the capacitor C. That is, when the control circuit 222 turns on the FET 2, the control circuit 222 turns off the FET 1 and accumulates energy in the inductor L. Next, when the FET 2 is turned off, the FET 1 is turned on, and the energy accumulated in the inductor L is output to the capacitor C. As a result, a DC voltage of about 32 V is output from the output terminal Vout.

  In this embodiment, the power factor improvement circuit 220 is provided in the power supply unit, and the power factor is brought close to 1.0, so that the apparent power of this embodiment is compared with the apparent power VA shown in the conventional formula (1). VA is 70.5 VA as shown in Equation (3). The input current (secondary side current) from the transformer 110 is 2.937 A, as shown in Expression (4).

  As described above, although the efficiency is somewhat reduced by inserting the power factor correction circuit 220, on the other hand, the input current of the transformer 110 can be reduced to about half, and the transformer 110 can be reduced in size and cost. be able to.

  Further, by using a rectifying transistor instead of a conventional rectifying diode, power loss due to the diode (power loss = 0.9V × 5A = 4.5 W when the voltage drop is 0.9 V and the current is 5 A) On the other hand, the power loss due to the transistor (power loss = 0.005Ω × 5A × 5A = 1.25 W when the on-resistance is 0.005Ω and the current is 5 A) can be reduced. Since the on-resistance tends to be smaller as the source-drain breakdown voltage of the FET is smaller, if the breakdown voltage is about 34 volts as in this embodiment, an FET with a lower on-resistance should be used. Can do.

  The control circuit 222 included in the power factor correction circuit 220 can use a known PWM control circuit. For example, by monitoring the switching current, output voltage, output current, etc. of the FET, the frequency of the FET1, FET2 is monitored. And the duty ratio can be adjusted.

  Next, an actual measurement waveform of the power factor correction circuit of the power supply system of the present embodiment is shown in FIG. 6A shows a waveform when the power factor correction circuit is turned off, and FIG. 6B shows a waveform when the power factor correction circuit is operated. The vertical axis is 10 A / Div, and the horizontal axis is 5 mS / Div (one division). 6A, the input current when the power factor correction circuit is off is 15.43 A, whereas in FIG. 6B, the input current when the power factor correction circuit is on is 11.5 A. The input current can be reduced by about 4A.

  FIG. 7A shows a rectifier circuit using a conventional diode bridge, and FIG. 7B shows a synchronous rectifier bridge according to this embodiment. Here, it is assumed that the AC voltage input to the diode bridge in FIG. 7A is 24 V and the output is 300 W. Since the input current is 300/24 = 12.5 A and the forward voltage drop of the Schottky diode is about 0.6 V, the loss due to the diode bridge is 0.6 × 2 × 12.5 = 15 W.

On the other hand, it is assumed that the AC voltage input to the synchronous rectification bridge in FIG. 7B is 24 V and the output is 300 W. The input current is 300/24 = 12.5 A, and the on-resistance of the MOSFET is 3 mΩ × 2 (for series connection). Therefore, loss due to the synchronous rectification bridge becomes 12.5 ² × 0.006 = 0.9375W. As described above, the synchronous rectification type bridge according to this embodiment can significantly reduce the power loss as compared with the conventional rectifier circuit using the diode bridge. These comparisons are examples, but it goes without saying that even if the input AC voltage is 100 V, the power loss can be similarly reduced. Further, since the MOSFET itself used for the synchronous rectification type bridge can be made to have a very small on-resistance (about 1/10) as compared with the conventional MOEFET, the synchronous rectification as in this embodiment is performed. The effectiveness of the type bridge is significantly improved.

  Next, a second embodiment of the present invention will be described. In the second embodiment, the synchronous rectification bridge 212 and the power factor correction circuit 220 shown in FIG. 4 are packaged or modularized. 8A shows a semiconductor device with an inductor externally attached, FIG. 8B shows a perspective view of the semiconductor device incorporating the inductor, and FIG. 8C shows a plan view thereof.

  A semiconductor device 300 shown in FIG. 8A includes a rectangular parallelepiped package body 310 in which the synchronous rectification bridge 212 and the power factor correction circuit 220 are sealed with resin, and six externals protruding from the bottom surface of the package body 310. Lead terminals 320, 322, 324, 326, 328, 330 are provided. The external lead terminals 320 to 330 are electrically connected to a circuit in the package main body 310. For example, ACIN of an AC power supply is connected to the external terminals 320 and 322, one terminal of the inductor L is connected to the external lead terminal 324, and GND (node N2) is connected to the external lead terminal 326. The other terminal of the inductor L is connected to the external lead terminal 328, and the output Vout (node N3) is connected to the external lead terminal 330 and the external lead terminal 330.

  When the inductor L is built-in, as shown in FIG. 8B, the semiconductor device 300A is attached to a rectangular parallelepiped package body 310, a heat sink 340 attached to the package body 310, and one surface of the package body 310. And four external lead terminals 350, 352, 354, and 356. An inductor (coil) L is attached to the central portion of the heat sink. The heat sink 340 may be configured to be connected to a lead frame in the package main body 310. Further, for example, ACIN of an AC power source is connected to the external lead terminals 350 and 352, GND (node N2) is connected to the external lead terminal 354, and output Vout (node N3) is connected to the external lead terminal 356. Is connected.

  Next, a third embodiment of the present invention will be described. The power supply unit shown in FIG. 4 shows a preferable example of AC24V, but the third embodiment shows an example of a preferable synchronous rectification bridge used in a power supply unit of AC100V in FIG. 9 (a). The same components as those in FIG. 4 are denoted by the same reference numerals, and redundant description is omitted. The synchronous rectifier bridge 102 according to the third embodiment uses a rectifier circuit 212a using a diode bridge. The inductor L is provided with a magnetically coupled inductor L1. One end of the inductor L1 is connected to GND, and the other end is connected to the power supply of the control circuit 222 via the diode D1. By appropriately selecting the number of turns of the inductor L1 relative to the number of turns of the inductor L, the power supply voltage supplied to the control circuit 222 can be set to a desired value. Thereby, even when the AC voltage is 100 V or higher, the power supply voltage to the control circuit 222 can be easily obtained. Further, as shown in FIG. 9B, the synchronous rectification bridge 102 may be configured by replacing the FET 1 of the transistor to be switched with a diode D2.

  FIG. 10 shows an example of a PFC integrated module (semiconductor device) in which the synchronous rectification bridge according to the third embodiment is integrated. FIG. 10A shows a module with an external inductor, FIG. b) is a perspective view of a module incorporating the inductor, and FIG. 10C is a perspective view thereof.

  A PFC integrated module 400 shown in FIG. 10A includes a package main body 410, and the package main body 410 is provided with six external lead terminals 420, 422, 424, 426, 428 and 430. A power input is connected to the external lead terminals 420 and 422, one terminal of the inductor L is connected to the external lead terminal 424, GND is connected to the external lead terminal 426, and the external lead terminal 428 is connected to the external lead terminal 428. The other terminal of the inductor (coil) L is connected, and one terminal of the inductor (coil) L1 is connected to the external lead terminal 430. The other terminal of the inductor L2 is commonly connected to the GND of the external lead end 426.

  When the inductors L and L1 are built in, as shown in FIG. 10B, the PFC integrated module 400A includes a rectangular parallelepiped package body 410, a heat sink 440 attached to the package body 410, and a package body 410. And four external lead terminals attached to one surface. Inductors (coils) L and L1 are attached to the central portion of the heat sink. The heat sink 440 may be configured to be connected to a lead frame in the package main body 310.

  The ACIN of the AC power source is connected to the two external lead terminals, the GND (ground) is connected to one external lead terminal, and the output is connected to one external lead terminal. And as shown in FIG.10 (c), the internal electrode 450 in the package main body 310 connects the output of the rectifier circuit 212a to the end of the inductor (coil) L. As shown in FIG. The internal electrodes 452 and 454 are connected to an external lead terminal connected to GND, the internal electrode 452 is connected to the inductor L2, and the internal electrode 454 connects the output of the rectifier circuit 212a to GND. The internal electrode 456 connects the output Vout to the external lead terminal.

  The power supply system according to the present invention can be used in a synchronous rectification type power supply device with improved power factor.

It is a figure which shows the structure of the conventional switching power supply device. It is a figure which shows the structure of the conventional synchronous rectification type switching power supply device. It is a figure explaining the subject of the conventional switching power supply device. It is a figure which shows schematic structure of the synchronous rectification type | mold power supply system which concerns on the Example of this invention. It is a figure which shows the preferable structural example of the synchronous rectification type bridge | bridging shown in FIG. It is a figure which shows the measured waveform when a power factor improvement circuit is OFF. It is a figure which shows the measured waveform when a power factor improvement circuit is turned ON. It is a figure explaining the loss comparison of a diode bridge and a synchronous rectification type bridge. FIG. 8A is a diagram illustrating a configuration example of a semiconductor device in which a power supply unit according to a second embodiment of the present invention is packaged. FIG. 8A illustrates a semiconductor device with an inductor externally attached, and FIG. FIG. 8C is a perspective view of a semiconductor device incorporating an inductor, and FIG. It is a figure which shows the structure of the synchronous rectification type bridge | bridging concerning the 3rd Example of this invention. It is a figure which shows the module which integrated the synchronous rectification type bridge | bridging shown in FIG.

Explanation of symbols

100: power supply system 110: power supply transformer 200-1 to 200-n: power supply unit 210: rectifier circuit 212: synchronous rectifier bridge 220: power factor correction circuit 222: control circuit 230: output circuit 300, 300A: semiconductor device 310: Package body 320, 322, 324, 326, 328, 330: External lead terminal 340: Heat sink 350, 352, 354, 356: External lead terminal 400, 400A: PFC integrated module 420, 422, 424, 426, 428, 430 : External lead terminal 440: Heat sink 450, 452, 454, 456: Internal electrode

Claims (6)

A transformer for converting a first AC power source having a first voltage into a second AC power source having a second voltage lower than the first voltage, and a second AC power source connected to the transformer, Including a plurality of power supply units to input,
Each power supply unit rectifies the second AC voltage of the second AC power supplied from the transformer, and outputs a rectified voltage;
A power factor correction circuit connected to the rectifier circuit to improve the power factor of the rectified power;
An output circuit connected to the power factor correction circuit and outputting a DC voltage;
The power factor correction circuit includes an inductor connected in series to the first voltage line of the rectifier circuit, a first transistor connected in series to the inductor, a node connecting the inductor and the first transistor, and rectification A second transistor connected between a second voltage line of the circuit and a control circuit for controlling switching of the first and second transistors, the control circuit turning on the second transistor; When turning off the first transistor and turning off the second transistor, turn on the first transistor,
The rectifier circuit is composed of a bridge of a plurality of MOS transistors that operate in response to a current.
Power system. The first and second transistors are MOSFETs, the drain of the first transistor is connected to the inductor, the source of the first transistor is connected to the output circuit, and the drain of the second transistor is the drain of the first transistor. , The source of the second transistor is connected to the second voltage line, the gates of the first and second transistors are connected to the control circuit, and the output circuit boosts the voltage from the second voltage. The power supply system according to claim 1, wherein a direct current voltage is output. The rectifier circuit includes first and second MOS transistors connected in series between a direct current output having a first potential and a direct current output having a second potential.
Third and fourth MOS transistors connected in series between the first and second potential DC outputs;
Driving means for outputting a gate signal to each gate of the first, second, third, and fourth MOS transistors in response to a current flowing through the DC output;
One input of the AC voltage is connected to a first connection node that connects the first and second MOS transistors, and the other input of the AC voltage is a second that connects the third and fourth MOS transistors. Connected to the connection node,
In response to the input AC voltage, current flows in the first and fourth MOS transistors during the first half-wave period, and in the second and third MOS transistors during the second half-wave period. The power supply system according to claim 1, wherein a current flows. 4. The power supply system according to claim 1, wherein the first transistor, the second transistor, the control circuit, and the rectifier circuit are accommodated in one package. 5. The package includes six external lead terminals, the first and second external terminals input AC power, the third and fourth external terminals are connected to the inductor, and the fifth external terminal is grounded. The power supply system according to any one of claims 1 to 4, wherein the power supply system is connected to a potential and the sixth external terminal is connected to an output. The power supply system according to claim 1, wherein the output circuit includes a DC-DC converter that generates a direct-current voltage stepped down by a switching circuit.