JP2009284065A - Transmitting circuit of radio transmitter - Google Patents

Abstract

A control range of 80 dB or more required for a UMTS terminal and a control step of 0.2 dB or less are enabled, and miniaturization is possible by sharing both GSM / UMTS transmission circuits.
A transmission circuit of a wireless transmitter includes a baseband signal processing circuit, a local signal generation circuit, a mixer circuit, and a control circuit. The baseband signal processing circuit performs baseband signal processing of the first baseband signal and generates a second baseband signal. The local signal generation circuit generates a local signal. The mixer circuit frequency-converts the second baseband signal based on the local signal to generate a frequency conversion signal. The control circuit generates a first control signal for discretely controlling the gain of the baseband signal processing circuit and a second control signal for discretely controlling the gain of the mixer circuit.
[Selection] Figure 1

Description

  The present invention relates to a transmission circuit of a wireless transmitter, and more particularly to a gain control circuit of a wireless transmitter.

  In recent years, mobile communication devices are compatible with various communication methods, and multiband systems having a plurality of frequency bands are increasing. A radio device compatible with such a system has a very complicated configuration and an increased circuit scale. However, there is a strong demand for downsizing, cost reduction, and consumption reduction, and further rationalization is required.

  As an example of the above, a conventional example of a gain control circuit of a transmitter will be described with reference to the drawings. FIG. 12 is a block diagram of a transmitter of GSM (Global System for Mobile Communications). The output signal of the baseband circuit 701 and the output signal of the local amplifier 702 are multiplied by a mixer 703, and the gain is adjusted by a GCA (Gain Control Amplifier) 704 and a power amplifier 705, and then output. Here, the gain of the GCA 704 is adjusted by the gain control circuit 706. GSM is divided into a GMSK (Gaussian filtered Minimum Shift Keying) modulation mode and an 8PSK (8-Phase Shift Keying) modulation mode. In the GMSK modulation mode, since the modulation wave has a constant amplitude, the power amplifier 705 is used in the saturation region, and the gain control of 40 dB is performed by the power amplifier 705. For this reason, gain control is not performed in the wireless transmitter 707.

  On the other hand, in the 8PSK modulation mode, the amplitude of the modulated wave does not become constant, so that gain control is performed by the GCA 704 in the wireless transmitter 707 instead of the power amplifier 705. The gain control range is 40 dB as in the GMSK modulation mode.

  FIG. 13 is a block diagram of a UMTS (Universal Mobile Telecommunications System) transmitter. Since UMTS is a Code Division Multiple Access (CDMA) system, the same channel is shared with other terminals, and strict level management is required in order to increase frequency utilization efficiency. Therefore, the gain control range needs to be 80 dB or more and the gain step needs to be 0.2 dB or less. The difference from the GSM transmission block configuration is that the driver 808 performs gain control together with the GCA 804 in order to realize a wide control range of 80 dB. Both the GCA 804 and the driver 808 are controlled by a gain control circuit 806.

  Next, a specific circuit configuration example of the GCAs 704 and 804 will be described with reference to FIG. The gain is changed by changing the proportion of the mixer output currents I1 and I2 flowing through the load resistors R1 and R2, respectively, by the gain control voltage V1. Since the constant mixer output currents I1 and I2 flow regardless of the output level, so-called discard current that does not flow to the load resistors R1 and R2 when the output level is small increases and efficiency decreases. Further, since the gain control characteristic is generated in an analog manner as a problem of the GCA 704 and 804, the curve 1001 deviates from the theoretical value 1002 due to manufacturing variation as shown in FIG. There was a point that the adjustment in was complicated. Furthermore, in order to achieve miniaturization, it is desirable to share the GSM and UMTS transmission blocks as much as possible.

  As a technique for increasing the efficiency when the output level is small, there is a configuration of Patent Document 1 devised for a transmission apparatus of a CDMA base station.

In Patent Document 1, D / A converters 1101 to 1108, quadrature modulators 1109 to 1112, and amplifiers 1113 to 1116 are connected in parallel as shown in FIG. 16, and according to the output level of a CDM (Code Division Multiplex) modulator 1117. Therefore, the operation control circuit 1118 drives only the necessary number of stages to reduce the consumption. If the point where the output level is changed by driving only the required number of stages is applied to a radio transmitter for a terminal, the transmission output level can be discretely controlled by changing the number of driven quadrature modulators. By controlling discretely, it is not necessary to pass a current through an unnecessary block, so that low consumption can be realized. At the same time, it is possible to suppress the shift of the gain control curve due to the manufacturing variation, which is a problem in the analog gain control, and to facilitate the adjustment in the mobile terminal manufacturing process.
JP 2002-135137 A

  However, Patent Document 1 is described with the adjustment of the transmission output level according to the CDM modulator output level of the base station in mind, and one set of D / A converter, quadrature modulator, and amplifier are connected to the same control line ( G1, G2, G3, G4). Therefore, even if the gain control of 40 dB and 1 dB steps necessary for the GSM terminal can be realized, in order to enable adjustment of the 80 dB and 0.2 dB steps necessary for the UMTS terminal, a very large number of D / There was a problem that a combination of an A converter, a quadrature modulator, and an amplifier was required, which was not practical.

  An object of the present invention is to enable a control range of 80 dB or more required for a UMTS terminal and a control step of 0.2 dB or less, and to enable miniaturization by sharing both transmission circuits of GSM / UMTS.

  To achieve the above-described object, a transmission circuit of a wireless transmitter according to the present invention includes a baseband signal processing circuit that performs baseband signal processing of a first baseband signal and generates a second baseband signal, and a local baseband signal processing circuit. A local signal generating circuit for generating a signal, a mixer circuit for generating a frequency converted signal by frequency-converting the second baseband signal based on the local signal, and a gain for discretely controlling the gain of the baseband signal processing circuit. And a control circuit for generating a second control signal for discretely controlling the gain of the mixer circuit.

  The mixer circuit includes N pieces composed of a first group,..., A Kth group,..., And an Nth group (N is an integer of 2 or more and K is an integer of 1 to N). The control circuit controls the K-th group to either the operating state or the non-operating state based on the second control signal.

  The Kth group includes a maximum of 2 (K−1) power element block groups having substantially the same configuration, and the control circuit is configured to generate the maximum 2 (K−) based on a second control signal. 1) Control all of the raised element block groups to either the operating state or the non-operating state.

  According to the transmission circuit of the wireless transmitter of the present invention, a gain of 80 dB or more necessary for a UMTS terminal is obtained by using a mixer circuit and a baseband signal processing circuit having a gain adjustment function and a control circuit for assigning gains. A gain control characteristic of a control range and a gain step of 0.2 dB or less can be realized. Furthermore, by providing the mixer circuit itself with a gain adjustment function and securing a wide adjustment range, a new circuit for gain adjustment becomes unnecessary, and the circuit scale as a transmission circuit can be reduced. Accordingly, since the configuration is the same as that of the GSM transmission circuit, it is easy to share the transmission circuit between the UMTS and GSM, and the UMTS / GSM multiband transmission radio can be reduced in size and cost. Further, by eliminating so-called discard current in the mixer circuit and setting only the group contributing to the gain to the operating state, the mixer circuit can be operated with the minimum power consumption. In addition, the gain adjustment function in the mixer circuit and the baseband signal processing circuit is realized by a digital configuration corresponding to the binary first control signal and the second control signal, respectively, thus simplifying the adjustment in the manufacturing process. , Enabling cost reduction.

  Several examples relating to the best mode for carrying out the present invention will be described below with reference to the drawings. In the drawings, elements that represent substantially the same configuration, operation, and effect are denoted by the same reference numerals. In addition, all the numbers described below are exemplified for specifically explaining the present invention, and the present invention is not limited to the illustrated numbers. In addition, logic levels represented by high / low or switching states represented by on / off are illustrative for the purpose of illustrating the invention, and different combinations of illustrated logic levels or switching states. Therefore, it is possible to obtain an equivalent result. In addition, the connection relationship between the components is exemplified for specifically explaining the present invention, and the connection relationship for realizing the function of the present invention is not limited to this. Furthermore, although the following embodiments are configured using hardware and / or software, the configuration using hardware can also be configured using software, and the configuration using software uses hardware. Can be configured.

(First embodiment)
First, the basic configuration of the first embodiment will be described with reference to FIG. The transmission circuit of the wireless transmitter in the first embodiment includes a baseband signal processing circuit 11, a mixer circuit 10, a local signal generation circuit 15, and a gain control circuit 112. The baseband signal processing circuit 11 performs baseband signal processing of the baseband signal IN and generates a baseband signal BB. The local signal generation circuit 15 generates a local signal DIV. The mixer circuit 10 frequency-converts the baseband signal BB based on the local signal DIV to generate a frequency conversion signal OUT. A gain control circuit 112 (also simply referred to as a control circuit) generates a control signal 111 and a control signal 110. The baseband signal processing circuit 11 has discrete gain control based on the control signal 111, and the mixer circuit 10 has discrete gain control based on the control signal 110. The mixer circuit 10 is configured such that a plurality of substantially identical element blocks having a mixer function are connected in parallel.

  Next, a more specific configuration of the first embodiment will be described with reference to FIG. The baseband signal processing circuit 11 includes a digital baseband signal processing circuit 14 and an analog baseband signal processing circuit 13. The digital baseband signal processing circuit 14 includes a digital modulation circuit 100 and a D / A converter 101. The analog baseband signal processing circuit 13 includes an MDAC (Multiple Digital to Analog Converter) electronic circuit 102 and a filter circuit 103. The mixer circuit 10 includes a mixer input circuit 104, a mixer 105, an output selection circuit 106, and a local buffer circuit 107. The local signal generation circuit 15 includes an oscillator 109 and a frequency divider 108.

  The digital modulation circuit 100 digitally modulates the baseband signal IN, and performs an I-phase digital modulation signal MOD-I representing an I-axis (horizontal axis) component and a Q-phase digital modulation signal MOD-Q representing a Q-axis (vertical axis) component. Is generated. The D / A converter 101 performs digital / analog conversion on the I-phase digital modulation signal MOD-I and the Q-phase digital modulation signal MOD-Q, and converts the I-phase baseband signal DAC-I and the Q-phase baseband signal DAC-Q into Generate each. The MDAC electronic circuit 102 generates an I-phase baseband signal MDAC-I that is proportional to the I-phase baseband signal DAC-I and that is proportional to a control signal 111 (described later) that represents a digital setting code. Similarly, the MDAC electronic circuit 102 generates a Q-phase baseband signal MDAC-Q that is proportional to the Q-phase baseband signal DAC-Q and proportional to the control signal 111. The MDAC electronic circuit 102 is also referred to as a multiplying digital / analog conversion circuit, and discretely attenuates the baseband signals DAC-I and DAC-Q based on the control signal 111.

  The filter circuit 103 limits the band of the I-phase baseband signal MDAC-I, and generates the baseband signal BB-I and the baseband signal BB-IX having a phase difference of 180 degrees. Similarly, the filter circuit 103 generates a baseband signal BB-Q and a baseband signal BB-QX that limit the band of the Q-phase baseband signal MDAC-Q and have a phase difference of 180 degrees. The mixer input circuit 104 amplifies the baseband signals BB-I, BB-IX, BB-Q, and BB-QX and generates baseband signals MIX-I, MIX-IX, MIX-Q, and MIX-QX, respectively. .

  Here, for example, the baseband signal BB-I and the baseband signal BB-IX represent differential output signals in the differential circuit configuration. For example, the baseband signal DAC-I described above represents a single-ended output signal. The configuration for inputting or outputting a differential signal may be a configuration for inputting or outputting a single-ended signal. The configuration for inputting or outputting a single-ended signal may be configured to input or output a differential signal. It may be.

  The oscillator 109 generates an oscillation signal, and the frequency divider 108, based on the oscillation signal, has a four-phase local signal DIV-I, a local signal DIV-Q, and a local signal DIV-IX whose phases are sequentially delayed by 90 degrees. The local signal DIV-QX is generated. Further, the local buffer circuit 107 generates local signals LO-I, LO-IX, LO-Q, and LO-QX that are waveform-shaped based on the local signals DIV-I, DIV-IX, DIV-Q, and DIV-QX. Are generated respectively. The local signals LO-I and LO-IX and the local signals LO-Q and LO-QX are orthogonal to each other.

  The mixer 105 mixes (specifically, multiplies) the baseband signals MIX-I, MIX-IX, MIX-Q, MIX-QX and the local signals LO-I, LO-IX, LO-Q, LO-QX. The frequency conversion signals OUT and OUTX are generated. The mixer 105 generates baseband signals MIX-I, MIX-IX, and baseband signals MIX-Q, MIX for local signals LO-I, LO-IX and local signals LO-Q, LO-QX that are orthogonal to each other. In order to mix QX, the first embodiment operates as a quadrature modulator. The output selection circuit 106 selects one of the two paths corresponding to the dual band, and based on the frequency conversion signals OUT and OUTX, the low band frequency conversion signal OUT-L and OUT-LX or the high band frequency conversion signal OUT. -H and OUT-HX are generated. In the first embodiment, a dual-band configuration is shown, but a configuration of three or more bands can be described in the same manner, and thus the details are omitted.

  The gain control circuit 112 generates a control signal 110 and a control signal 111 representing a gain setting code. The gain control circuit 112 simultaneously controls the mixer input circuit 104, the local buffer circuit 107, the mixer 105, and the output selection circuit 106 based on an N-bit (N is a positive integer) control signal 110. Controls the MDAC electronic circuit based on a control signal 111 of another M bit (M is a positive integer). When 11 is used as N and 8 is used as M, it is possible to obtain a control step of 0.2 dB or less and a gain control range of 82 dB or more. Details will be described later.

  Next, the gain control method will be described with reference to FIG. The mixer input circuit 104 includes N mixer input circuit groups represented by a Kth mixer input circuit group 104K (K = 1, 2,..., N). The local buffer circuit 107 includes N local buffer circuit groups represented by a Kth local buffer circuit group 107K (K = 1, 2,..., N). The mixer 105 includes N mixer groups represented by the Kth mixer group 105K (K = 1, 2,..., N). The output selection circuit 106 includes N output selector groups represented by a Kth output selector group 106K and an adder 106AD (K = 1, 2,..., N).

  The K-th mixer input circuit group 104K includes 2 (K−1) power elements (K = 1, 2,..., N) that are referred to as mixer input circuit element blocks having substantially the same configuration. . The K-th local buffer circuit group 107K includes 2 (K-1) power blocks (K = 1, 2,..., N), which are referred to as local buffer circuit element blocks having substantially the same configuration. . The K-th mixer group 105K includes 2 (K−1) power elements (K = 1, 2,..., N), which are element blocks called mixer element blocks having substantially the same configuration. The K-th output selector group 106K includes 2 (K−1) power elements (K = 1, 2,..., N), which are called output selector element blocks having substantially the same configuration. .

  The mixer input circuit element block generates baseband signals MIX-I, MIX-IX, MIX-Q, and MIX-QX based on baseband signals BB-I, BB-IX, BB-Q, and BB-QX, respectively. To do. The local buffer circuit element block generates local signals LO-I, LO-IX, LO-Q, and LO-QX based on the local signals DIV-I, DIV-Q, DIV-IX, and DIV-QX, respectively. The mixer element block mixes the baseband signals MIX-I, MIX-IX, MIX-Q, MIX-QX and the local signals LO-I, LO-IX, LO-Q, LO-QX, and the frequency conversion signal OUT, OUTX is generated. The output selector element block generates the low-band frequency conversion signals OUT-L1 and OUT-LX1 or the high-band frequency conversion signals OUT-H1 and OUT-HX1 based on the frequency conversion signals OUT and OUTX.

The mixer input circuit element block, local buffer circuit element block, mixer element block, and output selector element block constitute an element block group. The Kth mixer input circuit group 104K, the Kth local buffer circuit group 107K, the Kth mixer group 105K, and the Kth output selector group 106K constitute a Kth group 10K (K = 1, 2,..., N). The K-th group 10K is composed of 2 (K−1) power element block groups having substantially the same configuration (K = 1, 2,..., N). The mixer circuit 10 includes N groups consisting of a first group, a second group,..., A Kth group,..., An Nth group (K = 1, 2,..., N) and an addition. And 106AD. Therefore, the mixer circuit 10 includes (2 ^N −1) element block groups as shown in Equation 1. Similarly, the mixer input circuit 104 includes (2 ^N −1) mixer input circuit element blocks, the local buffer circuit 107 includes (2 ^N −1) local buffer circuit element blocks, and the mixer 105 , (2 ^N −1) mixer element blocks, and the output selection circuit 106 includes (2 ^N −1) output selector element blocks.
2 ⁰ +2 ¹ +... +2 ^N−1 = 2 ^N −1 (1)

The mixer input circuit 104 is based on one baseband signal BB-I, BB-IX, BB-Q, BB-QX, and (2 ^N -1) baseband signals MIX-I, MIX-IX, MIX-Q and MIX-QX are generated respectively. Based on one system of local signals DIV-I, DIV-Q, DIV-IX, and DIV-QX, the local buffer circuit 107 (2 ^N -1) systems of local signals LO-I, LO-IX, LO- Q and LO-QX are respectively generated. The mixer 105 includes (2 ^N -1) systems of baseband signals MIX-I, MIX-IX, MIX-Q, MIX-QX, and (2 ^N -1) systems of local signals LO-I, LO-IX, LO-Q and LO-QX are mixed to generate (2 ^N -1) frequency conversion signals OUT and OUTX. Based on the (2 ^N −1) system frequency conversion signals OUT and OUTX, the output selection circuit 106 selects the (2 ^N −1) system frequency conversion signals OUT-L1, OUT-LX1, OUT-H1, and OUT-HX1. Is generated.

Further, in the adder 106AD, the output selection circuit 106 generates the frequency conversion signal OUT-L by adding the frequency conversion signals OUT-L1 of (2 ^N −1) systems to each other, and generates (2 ^N −1) systems of frequency conversion signals OUT-L. The frequency conversion signal OUT-LX1 is added to each other to generate the frequency conversion signal OUT-LX, and the frequency conversion signals OUT-H1 of (2 ^N -1) systems are added to each other to generate the frequency conversion signal OUT-H. Then, the frequency conversion signal OUT-HX is generated by adding the frequency conversion signals OUT-HX1 of (2 ^N −1) systems.

In FIG. 3, for example, the baseband signals MIX-I, MIX-IX, MIX-Q, and MIX-QX are only drawn for 4 × N systems. However, as understood from the above description, the baseband signals MIX-I, MIX-IX, MIX-Q, and MIX-QX are actually 4 × 2 ^K-1 systems for each Kth group. Then, it becomes 4 × (2 ^N −1) systems. Similarly, local signals LO-I, LO-IX, LO-Q, LO-QX, frequency conversion signals OUT, OUTX, and frequency conversion signals OUT-L1, OUT-LX1, OUT-H1, OUT-HX1 are respectively For each Kth group, there are 4 × 2 ^K−1 systems, and the total is 4 × (2 ^N− 1) systems. The local signals DIV-I, DIV-Q, DIV-IX, DIV-QX and the frequency conversion signals OUT-L, OUT-LX, OUT-H, OUT-HX are each four systems as shown in the figure. .

The N groups in each of the mixer input circuit 104, the local buffer circuit 107, the mixer 105, and the output selection circuit 106 are either in an operating state or a non-operating state for each group by an N-bit control signal 110. Is controlled. Thus, by simultaneously controlling the mixer input circuit 104, the local buffer circuit 107, the mixer 105, and the output selection circuit 106, the frequency conversion signals OUT-L, OUT-LX, OUT-H, OUT-HX can be accurately performed. Output level can be controlled. If the control signal 110 is, for example, 11 bits, a gain control range of 66 dB can be secured according to Equation 2.
20 × log (2 ¹¹ ) = 66 dB (2)

FIG. 4 shows an MDAC electronic circuit 102 represented by an R-2R ladder type D / A converter. Specifically, the MDAC electronic circuit 102 corresponds to 2 ⁰ , 2 ¹ ,..., 2 ^M− corresponding to the least significant bit (LSB) to the most significant bit (MSB) of the control signal 111 composed of M bits. ¹ is multiplied by the I-phase baseband signal DAC-I. Further, the MDAC electronic circuit 102 collects and sums only the multiplied I-phase baseband signal DAC-I when the bit of the control signal 111 is at a high level to generate the I-phase baseband signal MDAC-I. Thereby, the magnitude of the I-phase baseband signal MDAC-I is approximately proportional to the I-phase baseband signal DAC-I and approximately proportional to the control signal 111. Similarly, the MDAC electronic circuit 102 generates a Q-phase baseband signal MDAC-Q that is approximately proportional to the Q-phase baseband signal DAC-Q and approximately proportional to the control signal 111. As described above, the gain control circuit 112 can control the gain of the MDAC electronic circuit 102 based on the control signal 111.

The gain of the MDAC electronic circuit 102 is basically 0 dB or less. If the number of bits of the control signal 111 and 8-bit, 8 when bits all at a high level, if ^{20 × log (2 8/2} 8) = 0dB, 8 bits all at the low level, 20 × log ⁽² 0 / 2 ⁸ ) = − 48 dB, and according to Equation 3, the gain control range can be 48 dB.
^{20 × log (2 8/2} 8) -20 × log (2 0/2 8) = 48dB (3)

  However, 16 dB out of the 48 dB control range is used to ensure the gain accuracy of 0.2 dB required for the UMTS terminal. A control range of 82 dB in total is secured by combining the upper 16 dB of 8 bits by the control signal 111 and 66 dB by the control signal 110. Details will be described later.

  FIG. 5 is a circuit diagram showing one of 2 (K−1) th element block groups 10KK constituting the K-th group 10K of FIG. In FIG. 5, the mixer input circuit element block 402 inputs the baseband signal BB-I output from the filter circuit 103 to the gate of the transistor M1, and the current corresponding to the baseband signal BB-I from the drain of the transistor M1. Is output as a baseband signal MIX-I. The transistors M2, M3, and M4 output baseband signals MIX-IX, MIX-Q, and MIX-QX according to the baseband signals BB-IX, BB-Q, and BB-QX, respectively, by the same operation. Further, the mixer input circuit element block 402 is provided with switches for turning on / off the inputs of the baseband signals BB-I, BB-IX, BB-Q, and BB-QX at the gates of the transistors M1, M2, M3, and M4, respectively. . The mixer input circuit element block 402 has baseband signals BB-I, BB-IX, BB-Q, BB-QX when the wired 1-bit control signal 110K of the N-bit control signal 110 is at a high level. When the control signal 110K is at a low level, the transistors M1, M2, M3, and M4 are turned off by grounding the gate. As described above, the mixer input circuit element block 402 is in an operating state when the control signal 110K is at a high level, and is in a non-operating state when the control signal 110K is at a low level.

  The local buffer circuit element block 403 inputs local signals DIV-I, DIV-Q, DIV-IX, DIV-QX, and passes through the switches and buffer circuits to local signals LO-I, LO-IX, LO-Q, LO. -Outputs each QX. The local buffer circuit element block 403 receives local signals DIV-I, DIV-Q, DIV-IX, and DIV-QX when the wired 1-bit control signal 110K of the N-bit control signal 110 is high. Conversely, when the control signal 110K is at a low level, the local signals DIV-I, DIV-Q, DIV-IX, and DIV-QX are blocked. As described above, the local buffer circuit element block 403 is in an operating state when the control signal 110K is at a high level, and is in a non-operating state when the control signal 110K is at a low level.

  The mixer element block 401 inputs the local signal LO-I to the gates of the transistors M5 and M8, similarly inputs the local signal LO-IX to the gates of the transistors M6 and M7, and inputs the gates of the transistors M9 and M12. The local signal LO-Q is input, and the local signal LO-QX is input to the gates of the transistors M10 and M11. In the mixer element block 401, the baseband signal MIX-I is input to the sources of the transistors M5 and M6, the baseband signal MIX-IX is input to the sources of the transistors M7 and M8, and the sources of the transistors M9 and M10 are input. The baseband signal MIX-Q is input, and the baseband signal MIX-QX is input to the sources of the transistors M11 and M12. The mixer element block 401 multiplies the baseband signals MIX-I and MIX-IX by the local signals LO-I and LO-IX. Similarly, the mixer element block 401 multiplies the baseband signals MIX-Q and MIX-QX by the local signals LO-Q and LO-QX. The mixer element block 401 adds both multiplication results on the current to generate the frequency conversion signals OUT and OUTX. Thus, the mixer element block 401 multiplies the baseband signals MIX-I, MIX-IX, MIX-Q, MIX-QX and the local signals LO-I, LO-IX, LO-Q, LO-QX, Frequency conversion signals OUT and OUTX are generated.

  The output selector element block 400 selects the output path of the frequency conversion signals OUT and OUTX based on the band selection signals BS and BSX generated by the band selection signal generation circuit (not shown), and outputs the low band frequency conversion signal. OUT-L1, OUT-LX1, or high-band frequency conversion signals OUT-H1, OUT-HX1 are output. The output selector element block 400 outputs the low-band frequency conversion signals OUT-L1 and OUT-LX1 when the band selection signal BS is high level and the band selection signal BSX is low level, and the band selection signal BS is low level. When the selection signal BSX is at a high level, high band frequency conversion signals OUT-H1 and OUT-HX1 are output.

Thus, the element block group 10KK uses the baseband signals BB-I, BB-IX, BB-Q, and BB-QX as frequencies based on the local signals DIV-I, DIV-IX, DIV-Q, and DIV-QX. The low-band frequency conversion signals OUT-L1 and OUT-LX1 or the high-band frequency conversion signals OUT-H1 and OUT-HX1 are generated. The magnitudes of the frequency conversion signals OUT-L1, OUT-LX1, OUT-H1, and OUT-HX1 generated by the element block group 10KK are referred to as element block levels. The mixer circuit 10 includes (2 ^N −1) element block groups 10KK having substantially the same configuration, but all operate in the same manner, and the frequency conversion signals OUT-L1 and OUT-LX1 having the size of the element block level. , OUT-H1, OUT-HX1 are output. The adder 106AD adds (2 ^N −1) frequency conversion signals OUT-L1, OUT-LX1, OUT-H1, and OUT-HX1 having the size of the element block level to each other, and each frequency conversion signal OUT-L , OUT-LX, OUT-H, and OUT-HX are generated. Therefore, if all (2 ^N −1) element block groups 10KK included in the mixer circuit 10 are in an operating state, the magnitudes of the frequency conversion signals OUT-L, OUT-LX, OUT-H, and OUT-HX. Is (2 ^N −1) times the element block level.

  When the control signal 110K is at a high level, the gain control circuit 112 sets the mixer input circuit element block 402 and the local buffer circuit element block 403 in an operating state, thereby causing the entire element block group 10KK including these two element blocks to be in an operating state. Put into operation. Conversely, when the control signal 110K is at a low level, the gain control circuit 112 makes the mixer input circuit element block 402 and the local buffer circuit element block 403 non-operating so as to include an element block group including these two element blocks. The entire 10KK is made inactive. Based on the control signal 110K, the gain control circuit 112 converts the entire (K−1) th element block groups constituting the K-th group 10K including the element block group 10KK into an active state or a non-operating state. Either one. Further, the gain control circuit 112 sets each of the N groups included in the mixer circuit 10 to either the operating state or the non-operating state for each group based on the N-bit control signal 110.

The adder 106AD adds 2 ^K-1 times the element block level when the ^K- th group 10K is in an operating state, and adds zero when the K-th group 10K is in a non-operating state. OUT-L, OUT-LX, OUT-H, and OUT-HX are generated. Therefore, the magnitudes of the frequency conversion signals OUT-L, OUT-LX, OUT-H, and OUT-HX are approximately proportional to the magnitude of the N-bit control signal 110. In this way, the mixer circuit 10 can give a gain from 0 db to 66 dB based on the 11-bit control signal 110.

  In FIG. 2, the gain control circuit 112 controls the gain of the MDAC electronic circuit 102 through an 8-bit control signal 111 and controls the gain of the mixer circuit 10 through an 11-bit control signal 110. Furthermore, the gain control circuit 112 has an input terminal (not shown) that receives a target signal (not shown) that represents the target value of the sum of the gain of the MDAC electronic circuit 102 and the gain of the mixer circuit 10, Based on the target signal, the control signals 111 and 110 are generated. The number of bits of the target signal must be greater than or equal to the number of bits of each control signal 111, 110. Here, the number of bits of the target signal is 11 bits, similar to the control signal 110.

  Specific gain assignment characteristics of the control signals 111 and 110 with respect to the target signal will be described with reference to FIGS. 6A, 6B, 6C, 6D, and 6E. Here, the gain code CDAC represents the decoded value of the control signal 111, the gain code CMIX represents the decoded value of the control signal 110, and the gain code CTTL represents the decoded value of the target signal. The gain GDAC represents the gain of the MDAC electronic circuit 102, the gain GMIX represents the gain of the mixer circuit 10, and the total gain GTTL represents the sum of the gain GDAC and the gain GMIX in decibel (dB) display or logarithmic display. . The change width in which each of the gain codes CTTL, CDAC, CMIX changes is called a code step, and the change width (decibel display) of each gain GTL, GDAC, GMIX corresponding to the code step is called a gain step.

  The gain control circuit 112 assigns the gain code CTTL to the gain code CDAC and the gain code CMIX. The MDAC electronic circuit 102 provides a gain GDAC corresponding to the gain code CDAC. The mixer circuit 10 provides a gain GMIX corresponding to the gain code CMIX. As a result, the transmission circuit of the wireless transmitter according to the first embodiment provides the total gain GTTL corresponding to the gain code CTTL.

  As described above, on the linear display, the MDAC electronic circuit 102 provides the gain GDAC having a magnitude proportional to the gain code CDAC, and the mixer circuit 10 provides the gain GMIX having a magnitude proportional to the gain code CMIX. On the decibel display, the gain GDAC is a logarithmic curve with respect to the gain code CDAC, and the gain GMIX is a logarithmic curve with respect to the gain code CMIX. That is, the gain step of the gain GDAC increases as the gain code CDAC decreases, and the gain step of the gain GMIX increases as the gain code CMIX decreases. Therefore, the total gain GTTL becomes a logarithmic curve with respect to the gain code CDAC and the gain code CMIX. Since all gains GTTL are desirably linearized with respect to the gain code CTTL on the decibel display, the gain control circuit 112 adjusts the allocation of the gain code CDAC and the gain code CMIX corresponding to the gain code CTTL. Thus, linearization is achieved as follows.

  FIG. 6A is a table showing the distribution of gain GMIX and gain GDAC for all gains GTTL. As illustrated in FIG. 6A, the description will be divided into a gain section GRG1, a gain section GRG2, and a gain section GRG3.

  First, in the gain section GRG1, as is understood from FIG. 6A and FIG. 6B illustrating the characteristics in the gain section GRG1, the MDAC electronic circuit 102 is fixed at the maximum gain, and gain control is performed only by the mixer circuit 10. Is called. The gain control in the mixer circuit 10 is controlled by the gain control circuit 112 so that the gain step is within 0.2 dB. That is, as the gain code CTTL decreases from 2048 by one code step, the gain code CMIX decreases from 2048, and the gain code CDAC is held at 256. Therefore, as the gain code CTTL decreases from 2048 by one code step, the gain GMIX decreases from 66 dB, and the gain GDAC is held at 0 dB. As a result, the total gain GTTL decreases from 66 dB, and the gain step of the gain GMIX increases. The gain section GRG1 is set so that the gain GMIX gain step does not exceed 0.2 dB.

  Next, in the gain section GRG2, as can be understood from FIG. 6A and FIG. 6C illustrating the characteristics in the gain section GRG2, the gain step of the gain GMIX in the mixer circuit 10 is 0.2 dB or more, so that the total gain GTL Is adjusted to be within 0.2 dB, both gains of the mixer circuit 10 and the MDAC electronic circuit 102 are adjusted. That is, the gain code CMIX is decreased by one code step CMIXD (shown in FIG. 6C) corresponding to a plurality of code steps of the gain code CTTL. The gain code CDAC decreases from 256 in the code step CMIXD, and repeats the decreasing characteristic from 256 for each code step CMIXD. Therefore, as the gain code CTTL decreases, the gain GMIX decreases at a gain step exceeding 0.2 dB for each code step CMIXD, and the gain GDAC decreases so as not to exceed 0.2 dB within the code step CMIXD. As the gain code CTTL decreases, the width of the code step CMIXD increases. As described above, the gain code CDAC is repeatedly assigned to different values of the gain code CTTL, and as a result, the gain GDAC is repeatedly reduced for different values of the gain code CTTL. That is, the gain control circuit 112 repeatedly generates the control signal 111 corresponding to different target signals in the gain section GRG2.

  In the gain section GRG3, as can be understood from FIG. 6A and FIG. 6D illustrating the characteristics in the gain section GRG3, the mixer circuit 10 is fixed at the minimum gain, and gain control is performed only by the MDAC electronic circuit 102. Is called. The gain control in the MDAC electronic circuit 102 is used only until the gain step is within 0.2 dB. That is, as the gain code CTTL decreases by one code step, the gain code CDAC decreases from 256, and the gain code CMIX is held at 1. Therefore, as the gain code CTTL decreases by one code step, the gain GDAC decreases from 0 dB, and the gain GMIX is held at 0 dB. As a result, the total gain GTTL decreases from 0 dB, and the gain step of the gain GDAC increases. The gain section GRG3 is set to a range where the gain step of the gain GDAC does not exceed 0.2 dB.

  FIG. 6E is a characteristic diagram showing gain control characteristics obtained by the above-described assignment. As described above, as the gain code CTTL is decreased by one code step from 2048, first, gain control is performed only by the mixer circuit 10 until the gain step does not exceed 0.2 dB (gain section GRG1). By adding the function of the circuit 102, the gain step is maintained at 0.2 dB or less (gain interval GRG2), and when the gain step exceeds 0.2 dB, the gain control is performed only by the MDAC electronic circuit 102 (gain interval GRG3). The gain code CTTL is used until the interval in which the gain step does not exceed 0.2 dB. Thereby, a gain control range of approximately 80 dB from approximately 66 dB to −15 dB can be achieved while maintaining a gain step of 0.2 dB or less.

  As described above, according to the transmission circuit of the wireless transmitter according to the first embodiment, the mixer circuit 10 and the MDAC electronic circuit 102 having the gain adjustment function and the gain control circuit 112 that performs gain allocation are used. Thus, a gain control characteristic of a gain control range of 80 dB or more and a gain step of 0.2 dB or less necessary for the UMTS terminal can be realized. Furthermore, by providing the mixer circuit 10 itself with a gain adjustment function and ensuring a wide adjustment range, a new circuit for gain adjustment is not required, and the circuit scale as a transmission circuit can be reduced. Accordingly, since the configuration is the same as that of the GSM transmission circuit, it is easy to share the transmission circuit between the UMTS and GSM, and the UMTS / GSM multiband transmission radio can be reduced in size and cost. Furthermore, the so-called discard current is eliminated in the mixer circuit 10 and only the group that contributes to the gain is in the operating state, so that the mixer circuit 10 can be operated with the minimum power consumption. In addition, the gain adjustment function in the mixer circuit 10 and the MDAC electronic circuit 102 is realized by a digital configuration corresponding to the binary control signals 110 and 111, respectively, thus simplifying adjustment in the manufacturing process and reducing costs. enable.

  The control signal 110 and the control signal 111 are 11 bits and 8 bits, but this is an example, and it is clear that the same effect can be obtained even if other numbers of bits are used.

  Further, the mixer 105 has been described as operating as a quadrature modulator, but this is an example, and the same effect can be obtained even when used in a system using an intermediate frequency.

(Second Embodiment)
The second embodiment will be described with a focus on differences from the first embodiment. Other configurations, operations, and effects are the same as those of the first embodiment, and thus description thereof is omitted.

  FIG. 7 is a block diagram illustrating an example of a transmission circuit of a wireless transmitter according to the second embodiment. The configuration of the second embodiment shown in FIG. 7 is different from the configuration of the first embodiment shown in FIG. 2 in that the mixer circuit 10 and the local buffer circuit 107 included in the mixer circuit 10 have the mixer circuit 10A and the mixer circuit. The local buffer circuit 107A included in 10A is changed.

  The local buffer circuit 107A does not receive the control signal 110, and the gain control circuit 112 does not control the local buffer circuit 107A. For this reason, the local buffer circuit 107A is composed of only one local buffer circuit group including one local buffer circuit element block. The local buffer circuit 107A is based on one system of local signals DIV-I, DIV-Q, DIV-IX, DIV-QX, and one system of local signals LO-I, LO-IX, LO-Q, LO-QX. Are generated respectively. The local signals LO-I, LO-IX, LO-Q, and LO-QX are four systems as illustrated.

  As described above, according to the transmission circuit of the wireless transmitter according to the second embodiment, the configuration of the local buffer circuit 107A is simplified, and the circuit scale can be reduced.

(Third embodiment)
In the third embodiment, a description will be given focusing on differences from the first embodiment. Other configurations, operations, and effects are the same as those of the first embodiment, and thus description thereof is omitted.

  FIG. 8 is a block diagram illustrating an example of a transmission circuit of a wireless transmitter according to the third embodiment. The configuration of the third embodiment shown in FIG. 8 is different from the configuration of the first embodiment shown in FIG. 2 in that the mixer circuit 10 and the mixer 105 and the output selection circuit 106 included in the mixer circuit 10 are 10B and the mixer 105B included in the mixer circuit 10B, and the mixer circuit 10B does not include an output selection circuit. The output selection circuit 106 of the first embodiment includes an adder 106AD. In the third embodiment, the mixer 105B includes an adder (not shown).

The mixer 105B includes N mixer groups represented by the Kth mixer group 105K and an adder (K = 1, 2,..., N). The mixer 105B includes (2 ^N −1) systems of baseband signals MIX-I, MIX-IX, MIX-Q, MIX-QX, and (2 ^N −1) systems of local signals LO-I, LO-IX, LO-Q and LO-QX are mixed to generate ( ^2N- 1) frequency conversion signals. Further, the mixer 105B adds (2 ^N −1) frequency conversion signals of the element block level in the adder to each other to add two frequency conversion signals OUT and OUT as shown in FIG. -X is generated. In FIG. 5 showing the element block group 10KK of the first embodiment, the output selector element block 400 is replaced with a resistor or a transistor representing each load of the two frequency conversion signals OUT and OUT-X. The mixer element block 401 also includes loads for the frequency conversion signals OUT and OUT-X.

  Thus, according to the transmission circuit of the wireless transmitter according to the third embodiment, the configuration of the mixer circuit 10 is simplified, and the circuit scale can be reduced.

(Fourth embodiment)
In the fourth embodiment, a description will be given focusing on differences from the first embodiment. Other configurations, operations, and effects are the same as those of the first embodiment, and thus description thereof is omitted.

  FIG. 9 is a block diagram illustrating an example of a transmission circuit of a wireless transmitter according to the fourth embodiment. The configuration of the fourth embodiment shown in FIG. 9 is different from the configuration of the first embodiment shown in FIG. 2 in that the baseband signal processing circuit 11, the analog baseband signal processing circuit 13, and the analog baseband signal processing circuit. 13 is changed to a baseband signal processing circuit 11A, an analog baseband signal processing circuit 13A, and a filter circuit 103A and an MDAC electronic circuit 102A included in the analog baseband signal processing circuit 13A. It is a point that has been.

  The baseband signal processing circuit 11A includes a digital baseband signal processing circuit 14 and an analog baseband signal processing circuit 13A. The analog baseband signal processing circuit 13A includes a filter circuit 103A and an MDAC electronic circuit 102A. The filter circuit 103A limits the band of the I-phase baseband signal DAC-I, and generates the baseband signal FIL-I and the baseband signal FIL-IX having a phase difference of 180 degrees. Similarly, the filter circuit 103 generates a baseband signal FIL-Q and a baseband signal FIL-QX that limit the band of the Q-phase baseband signal DAC-Q and have a phase difference of 180 degrees. The MDAC electronic circuit 102A generates I-phase baseband signals BB-I and BB-IX that are proportional to the I-phase baseband signals FIL-I and FIL-IX and proportional to the control signal 111, respectively. Similarly, the MDAC electronic circuit 102A generates Q-phase baseband signals BB-Q and BB-QX that are proportional to the Q-phase baseband signals FIL-Q and FIL-QX and proportional to the control signal 111, respectively.

  As described above, according to the transmission circuit of the wireless transmitter according to the fourth embodiment, even if the MDAC electronic circuit 102A is arranged at the subsequent stage of the filter circuit 103A, the same effect as that of the first embodiment can be obtained. it can.

(Fifth embodiment)
In the fifth embodiment, a description will be given focusing on differences from the first embodiment. Other configurations, operations, and effects are the same as those of the first embodiment, and thus description thereof is omitted.

  FIG. 10 is a block diagram illustrating an example of a transmission circuit of a wireless transmitter according to the fifth embodiment. The configuration of the fifth embodiment shown in FIG. 10 is different from the configuration of the first embodiment shown in FIG. 2 in that the baseband signal processing circuit 11, the analog baseband signal processing circuit 13, and the analog baseband signal processing circuit. 13 is changed to a filter circuit 103B included in the baseband signal processing circuit 11B, the analog baseband signal processing circuit 13B, and the analog baseband signal processing circuit 13B. is there.

  The baseband signal processing circuit 11B includes a digital baseband signal processing circuit 14 and an analog baseband signal processing circuit 13B. The analog baseband signal processing circuit 13B includes a filter circuit 103B. The filter circuit 103B limits the band of the I-phase baseband signal DAC-I, and generates the baseband signal BB-I and the baseband signal BB-IX having a phase difference of 180 degrees. Similarly, the filter circuit 103B limits the band of the Q-phase baseband signal DAC-Q, and generates the baseband signal BB-Q and the baseband signal BB-QX having a phase difference of 180 degrees. Each baseband signal BB-I, BB-IX is proportional to the I-phase baseband signal DAC-I and proportional to the control signal 111. Each baseband signal BB-Q, BB-QX is proportional to the Q-phase baseband signal DAC-Q and proportional to the control signal 111. In this manner, the gain control circuit 112 can control the gain of the filter circuit 103B based on the control signal 111.

  FIG. 11 is a circuit diagram showing an example of the filter circuit 103B designed so that the gain can be varied. Specifically, the filter circuit 103B is configured to weight the differentially configured baseband signals DAC-I and DAC-IX with the control signal 111 to generate the baseband signals BB-I and BB-IX. .

  Thus, according to the transmission circuit of the wireless transmitter according to the fifth embodiment, the MDAC electronic circuit 102 can be reduced, the configuration of the analog baseband signal processing circuit 13B is simplified, and the circuit scale is reduced. It becomes possible to do.

  Since the transmission circuit of the wireless transmitter according to the present invention can secure a wide control range in fine steps, it is useful for a transmission circuit of a wireless transmitter that requires high-precision and wide-range switching control.

  The above description of the embodiments is merely an example embodying the present invention. The present invention is not limited to these examples and can be easily configured by those skilled in the art using the technology of the present invention. It can be expanded to various examples.

  The present invention can be used for a transmission circuit of a wireless transmitter.

It is a block diagram which shows the basic composition of the transmission circuit of the wireless transmitter in the 1st Embodiment of this invention. It is a block diagram which shows the specific structure of the transmission circuit of the radio | wireless transmitter in the 1st Embodiment of this invention. It is a block diagram which shows an example of the mixer circuit in the 1st Embodiment of this invention. It is a circuit diagram showing an example of an MDAC electronic circuit in a 1st embodiment of the present invention. It is a circuit diagram which shows an example of the element block group in the 1st Embodiment of this invention. It is a table | surface which shows the gain control characteristic in the 1st Embodiment of this invention. It is a characteristic view which shows the gain control characteristic in the 1st Embodiment of this invention. It is a characteristic view which shows the gain control characteristic in the 1st Embodiment of this invention. It is a characteristic view which shows the gain control characteristic in the 1st Embodiment of this invention. It is a characteristic view which shows the gain control characteristic in the 1st Embodiment of this invention. It is a block diagram which shows an example of the transmission circuit of the radio | wireless transmitter in the 2nd Embodiment of this invention. It is a block diagram which shows an example of the transmission circuit of the wireless transmitter in the 3rd Embodiment of this invention. It is a block diagram which shows an example of the transmission circuit of the wireless transmitter in the 4th Embodiment of this invention. It is a block diagram which shows an example of the transmission circuit of the wireless transmitter in the 5th Embodiment of this invention. It is a circuit diagram which shows an example of the filter circuit in the 5th Embodiment of this invention. It is a block diagram of the transmission apparatus of GSM in a prior art example. It is a block diagram of the transmission apparatus of UMTS in a prior art example. It is a circuit diagram of GCA in a prior art example. It is a characteristic view which shows the gain control characteristic in a prior art example. It is a block diagram of the transmitter of the CDMA base station in a prior art example.

Explanation of symbols

10, 10A, 10B Mixer circuit 10K Group K 10KK Element block group 11, 11A, 11B Baseband signal processing circuit 13, 13A, 13B Analog baseband signal processing circuit 14 Digital baseband signal processing circuit 15 Local signal generation circuit 100 Digital Modulation circuit 101 D / A converter 102, 102A MDAC electronic circuit 103, 103A, 103B Filter circuit 104 Mixer input circuit 104K Mixer input circuit group 105, 105B Mixer 105K Mixer group 106 Output selection circuit 106K Output selector group 106AD Adder 107, 107A Local buffer circuit 107K Local buffer circuit group 108 Frequency divider 109 Oscillator 110 Control signal 111 Control signal 112 Gay Control circuit 400 output selector element block 401 mixer element block 402 mixer input circuit element block 403 local buffer circuit element block

Claims (21)

A baseband signal processing circuit that performs baseband signal processing of the first baseband signal and generates a second baseband signal;
A local signal generation circuit for generating a local signal;
A mixer circuit that frequency-converts the second baseband signal based on the local signal and generates a frequency-converted signal;
Transmission of a radio transmitter comprising: a first control signal for discretely controlling the gain of the baseband signal processing circuit; and a control circuit for generating a second control signal for discretely controlling the gain of the mixer circuit circuit. The mixer circuit includes N pieces composed of a first group,..., A Kth group,..., And an Nth group (N is an integer of 2 or more and K is an integer of 1 to N). Including groups of
2. The transmission circuit of the radio transmitter according to claim 1, wherein the control circuit controls the K-th group to be either in an operating state or a non-operating state based on a second control signal. The Kth group includes up to 2 (K−1) power element block groups having substantially the same configuration,
3. The control circuit according to claim 2, wherein the control circuit controls all of the maximum 2 (K−1) power element block groups based on a second control signal to be in an operating state or a non-operating state. A transmitter circuit of a wireless transmitter. The Kth group includes a mixer input circuit group that receives a second baseband signal;
The transmission circuit of the radio transmitter according to claim 2, wherein the control circuit controls the mixer input circuit group to either one of an operating state and a non-operating state based on a second control signal. The mixer input circuit group includes up to 2 (K−1) power elements blocks having substantially the same configuration,
5. The radio according to claim 4, wherein the control circuit controls all of the maximum 2 (K−1) power element blocks to either an operating state or a non-operating state based on a second control signal. 6. Transmitter transmission circuit. The Kth group includes a local buffer circuit group that receives a local signal,
The transmission circuit of the radio transmitter according to claim 2, wherein the control circuit controls the local buffer circuit group to either one of an operating state and a non-operating state based on a second control signal. The local buffer circuit group includes up to 2 (K−1) power elements blocks having substantially the same configuration,
7. The radio according to claim 6, wherein the control circuit controls all of the maximum 2 (K−1) power element blocks to one of an operating state and a non-operating state based on a second control signal. Transmitter transmission circuit. The Kth group includes a mixer group that mixes the second baseband signal and the local signal,
The transmission circuit of the wireless transmitter according to claim 2, wherein the control circuit controls the mixer group to either one of an operating state and a non-operating state based on a second control signal. The mixer group includes up to 2 (K−1) power elements blocks having substantially the same configuration,
9. The radio according to claim 8, wherein the control circuit controls all of the maximum 2 (K−1) power element blocks to either an operating state or a non-operating state based on a second control signal. Transmitter transmission circuit. The Kth group includes an output selector group that selects any one of a plurality of paths for outputting the frequency conversion signal;
The transmission circuit of the radio transmitter according to claim 2, wherein the control circuit controls the output selector group to one of an operating state and a non-operating state based on a second control signal. The output selector group includes up to 2 (K−1) power elements blocks having substantially the same configuration,
11. The radio according to claim 10, wherein the control circuit controls all of the maximum 2 (K−1) power element blocks to either an operating state or a non-operating state based on a second control signal. Transmitter transmission circuit. The baseband signal processing circuit includes a digital baseband signal processing circuit and an analog baseband signal processing circuit,
The digital baseband signal processing circuit performs digital baseband signal processing of the first baseband signal and performs digital / analog conversion to generate a third baseband signal,
The analog baseband signal processing circuit performs analog baseband signal processing of the third baseband signal to generate a second baseband signal,
The transmission circuit of the wireless transmitter according to claim 1, wherein the control circuit discretely controls a gain of the analog baseband signal processing circuit based on a first control signal. The analog baseband signal processing circuit includes a multiplying digital / analog conversion circuit that discretely attenuates an analog signal,
The transmission circuit of the radio transmitter according to claim 12, wherein the control circuit discretely controls a gain of the multiplying digital / analog conversion circuit based on a first control signal.   The transmission circuit of the wireless transmitter according to claim 12, wherein the analog baseband signal processing circuit includes a filter circuit that limits a band of a third baseband signal.   The transmission circuit of the radio transmitter according to claim 14, wherein the control circuit discretely controls the gain of the filter circuit based on a first control signal. The baseband signal processing circuit generates an I-phase baseband signal representing a horizontal axis component of the second baseband signal and a Q-phase baseband signal representing a vertical axis component of the second baseband signal,
The local signal generation circuit generates an I-phase local signal and a Q-phase local signal that are orthogonal to each other,
2. The radio transmitter according to claim 1, wherein the mixer circuit frequency-converts the I-phase baseband signal based on the I-phase local signal and frequency-converts the Q-phase baseband signal based on the Q-phase local signal. Transmitter circuit.   2. The transmission circuit of the radio transmitter according to claim 1, wherein the control circuit controls a gain of the baseband signal processing circuit to 1 time or less and controls a gain of the mixer circuit to 1 time or more. The control circuit includes:
An input terminal for receiving a target signal representing a target value of the sum of the gain of the baseband signal processing circuit and the gain of the mixer circuit;
The transmission circuit of the wireless transmitter according to claim 1, wherein the first control signal and the second control signal are generated based on the target signal.   The transmission circuit of the radio transmitter according to claim 18, wherein the control circuit sets the magnitude of the first control signal to a predetermined value in the vicinity of the maximum value of the target signal.   The transmission circuit of the radio transmitter according to claim 18, wherein the control circuit sets the magnitude of the second control signal to a predetermined value in the vicinity of the minimum value of the target signal.   The control circuit outputs the first control signal corresponding to a different target signal in a range where the gain change width of the mixer circuit with respect to the minimum change width of the second control signal is not less than the first predetermined value and not more than the second predetermined value. The transmission circuit of the radio transmitter according to claim 18, wherein the transmission circuit is repeatedly generated.

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