JP2009282109A - Display element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal panel adaptive to grayscale characteristic which is different for each color without lowering yield. <P>SOLUTION: An auxiliary capacitance line 24 is formed between each scan lines 22 on an array substrate 12. Voltage of each auxiliary capacitance line 24 is adjusted for each color of a coloring section, whereby auxiliary capacitance line voltage circuits 32r, 32g and 32b for adjusting a voltage difference between each pixel electrode 26 and an opposing electrode are formed. Since the grayscale characteristic can be individually adjusted for each color without adjusting the grayscale characteristic of the coloring section for each color in manufacturing process, the liquid crystal panel is adaptive to grayscale characteristic which is different for each color without lowering yield. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display element having auxiliary capacitance lines formed between scanning lines.

  2. Description of the Related Art Conventionally, a liquid crystal display element that is a display element of this type, that is, a liquid crystal panel, is configured such that a liquid crystal layer that is a light modulation layer is interposed between an array substrate and a counter substrate that are opposed to each other. In the portion corresponding to the display area of the array substrate, a plurality of scanning lines and a plurality of signal lines are formed in a lattice shape, and auxiliary capacitance lines are formed between the scanning lines. A thin film transistor (TFT) is formed at each intersection of the scanning line and the signal line, and a pixel electrode formed by a transparent conductive member such as ITO in each region surrounded by the scanning line and the signal line Is formed. In addition, in the peripheral area of the display area of the array substrate, a scanning line (gate) circuit connected to the scanning line, an auxiliary capacitance line voltage circuit for setting the voltage of the auxiliary capacitance line, a power supply circuit for the scanning line circuit, and an analog A circuit and the like are formed, and a driver IC is mounted on a chip.

  In the driver IC, for example, an interface circuit that converts a CPU signal (interface signal) transmitted from the set side such as a computer into a liquid crystal display signal, a GRAM circuit that stores the liquid crystal display signal, and a display timing signal are generated from the CPU signal Timing signal circuit, shift register circuit for outputting the liquid crystal display signal stored in the GRAM circuit in synchronization with the display timing signal generated by the timing signal circuit, and converting the liquid crystal display signal stored in the GRAM circuit to an analog signal Generates a digital-analog converter (DAC) circuit, an amplifier circuit that amplifies an analog signal generated by the digital-analog converter circuit, a counter-electrode voltage circuit that sends a voltage to the counter-electrode on the counter-substrate side, and a power source necessary for these circuits Power supply circuit to be provided Yes.

  The analog signal amplified by the amplifier circuit passes through the signal line via the analog switch circuit and is applied to the pixel electrode by each thin film transistor, thereby displaying an image.

  The display principle of this liquid crystal panel will be described. This liquid crystal panel performs AC inversion driving to prevent burn-in. The AC inversion drive is a drive in which the polarity of the signal line voltage (analog signal) is inverted with respect to the counter electrode voltage and applied to the pixel electrode for each frame and between adjacent pixel electrodes. As the voltage applied to the driver IC is lowered, the applied voltage of the signal line voltage becomes smaller. Therefore, in order to realize a high contrast ratio, the auxiliary capacitor line voltage is applied to each scanning line in each scanning direction to thereby increase the voltage of the pixel electrode. Has increased.

  Then, the voltage difference between the counter electrode voltage and the signal line voltage applied to the pixel electrode becomes a voltage applied to the liquid crystal layer, and the liquid crystal layer operates the shutter for the light corresponding to this voltage difference, and variously Display is possible.

At the time of gradation display, a signal line voltage corresponding to a CPU signal sent from the set side is converted into a multi-voltage analog voltage by a digital / analog converter circuit in the driver IC. For example, if 64 levels of voltage are generated for each color of red (R), green (G), and blue (B), each color can be displayed in 64 levels, and the display color is 64 × 64 × 64 =. Display of 262144 colors (about 260,000 colors) is possible (for example, see Patent Document 1).
JP 2007-47615 A

  In recent years, since there are many demands for individually adjusting the gradation characteristics of red, green, and blue, the gradation characteristics of each color are individually adjusted in the manufacturing process. However, as the voltage of the driver IC is lowered, there is a problem that it is not easy to cope with the gradation characteristics as described above. In addition, since it is not easy to deal with the gradation characteristics in this way, a yield occurs in the manufacturing process and a manufacturing loss occurs.

  The present invention has been made in view of these points, and an object of the present invention is to provide a display element that can cope with different gradation characteristics for each color without reducing the yield.

  The present invention relates to an array substrate, a counter substrate disposed opposite to the array substrate, a plurality of scanning lines and a plurality of signal lines formed in a lattice pattern so as to intersect the array substrate, and the scanning lines. And a pixel electrode formed on the array substrate corresponding to each crossing position of the signal line and a switching element formed on the array substrate and connected to the scanning line and the signal line to drive the pixel electrode And a color filter layer having colored portions of different colors formed corresponding to the pixel electrodes, and an auxiliary formed between the scanning lines of the array substrate and connected to the pixel electrodes. By adjusting the storage capacitor line for forming a capacitor, the counter electrode formed to face the pixel electrode on the counter substrate, and the voltage of each storage capacitor line for each color of the colored portion A voltage adjusting unit that adjusts a voltage difference between each pixel electrode and the counter electrode, and a voltage difference between the pixel electrode and the counter electrode, disposed between the array substrate and the counter substrate. And a light modulation layer that modulates light according to the above.

  The voltage adjustment unit adjusts the voltage difference between each pixel electrode and the counter electrode by adjusting the voltage of each auxiliary capacitance line for each color of the coloring portion.

  According to the present invention, for example, it is possible to individually adjust the gradation characteristics for each color without adjusting the gradation characteristics for each color of the colored portion in the manufacturing process or the like, and different gradations for each color without reducing the yield. It can correspond to characteristics.

  The configuration of the display element according to the first embodiment of the present invention will be described below with reference to FIGS.

  In FIG. 1, reference numeral 11 denotes a liquid crystal panel which is a liquid crystal display element as a display element. The liquid crystal panel 11 has an array substrate 12 and a counter substrate 13 arranged to face each other and bonded together by a seal portion 14. , 13 and a liquid crystal layer 15 as a light modulation layer is interposed between them, and an active matrix type color display is possible. The liquid crystal panel 11 is, for example, a so-called transmission type that modulates and transmits white planar light from a backlight (not shown) to display an image. A frame-shaped peripheral region 17 which is a non-display region located outside is formed.

The array substrate 12 has a plurality of scanning lines 22 (scanning lines 22 ₁ to 22) on the main surface of the transparent substrate having transparency and insulation, that is, the glass substrate 21 on the liquid crystal layer 15 side, at a position corresponding to the display region 16. 22 _m ) and a plurality of signal lines 23 (signal lines 23 ₁ to 23 _m ) are formed in a lattice shape, and corresponding to each signal line 23, auxiliary capacitance lines 24 are formed substantially parallel to these signal lines 23, respectively. ing. In addition, thin film transistors (TFTs) 25 as switching elements are formed at the intersections between the scanning lines 22 and the signal lines 23. The gate electrodes of the thin film transistors 25 are the scanning lines 22 and the source electrodes are the signal lines 23, respectively. And a pixel electrode 26 that is formed of a transparent conductive member such as ITO and constitutes a sub-pixel (pixel) is formed in each region surrounded by the scanning line 22 and the signal line 23. ing. That is, the pixel electrodes 26 are arranged in a matrix in the display region 16 and are electrically connected to the drain electrodes of the corresponding thin film transistors 25. Each auxiliary capacitance line 24 is arranged on the side of each pixel electrode 26 in a plan view, that is, at a position not intersecting with these pixel electrodes 26, and intersects each pixel electrode 26 with this pixel electrode 26 in a plan view. A thin film transistor 28 as an auxiliary capacitance switching element is formed between the capacitor electrode 27 formed at the position where the capacitor electrode 27 is formed. In this thin film transistor 28, the gate electrode is connected to the scanning line 22, the source electrode is connected to the auxiliary capacitance line 24, the drain electrode is connected to the capacitance electrode 27, and the thin film transistor 28 is turned on, whereby the capacitance electrode 27 and the pixel electrode 26 are connected. In the meantime, an auxiliary capacitance corresponding to a signal (voltage) applied to the auxiliary capacitance line 24 is formed. Further, an alignment film 29 for aligning liquid crystal molecules of the liquid crystal layer 15 in a predetermined direction is formed in the display region 16.

  Further, the voltage is adjusted for each of the scanning line circuit (gate circuit) 31 connected to the scanning line 22 and the auxiliary capacitance line 24 at a position corresponding to the peripheral region 17 on the main surface of the glass substrate 21 on the liquid crystal layer 15 side. Auxiliary capacitance line voltage circuit (CS circuit) 32r, 32g, 32b as a voltage adjustment unit, these auxiliary capacitance line voltage circuits 32r, 32g, 32b and analog switch circuit 33 electrically connected to each auxiliary capacitance line 24, scanning A power circuit 34 for a scanning line circuit, which is a power circuit for the line circuit 31, and an analog switch circuit 35 connected to each signal line 23 are formed, and a driver IC 36, which is a driver section, is mounted on a chip. Yes.

  The scanning line circuit 31 is disposed on the left side of the peripheral region 17.

  The auxiliary capacitance line voltage circuits 32r, 32g, 32b and the analog switch circuit 33 are arranged on the upper side of the peripheral region 17. The analog switch circuit 33 is configured to select and supply signals (voltages) from the auxiliary capacitance line voltage circuits 32r, 32g, and 32b to the auxiliary capacitance line 24.

  The scanning line circuit power supply circuit 34 is disposed at a position facing the scanning line circuit 31, that is, on the right side of the peripheral region 17.

  The analog switch circuit 35 and the driver IC 36 are disposed on the lower side of the peripheral region 17.

  In the driver IC 36, an interface circuit (I / F circuit) 41, which is an interface unit for converting a CPU signal (interface signal) SC sent from a set side such as a computer (not shown) into a liquid crystal display signal, is converted. A GRAM circuit 42 which is a storage unit for storing a liquid crystal display signal, a timing signal circuit 43 which is a timing signal generating means for generating a display timing signal from the CPU signal SC, and a liquid crystal display signal stored in the GRAM circuit 42 is a timing signal circuit 43 A shift register circuit 44 that is an output unit that outputs the signal in synchronization with the timing signal generated in step S4, a digital analog converter (DAC) circuit 45 that is a conversion unit that converts the liquid crystal display signal stored in the GRAM circuit 42 into an analog signal, This digital analog converter circuit 45 amplifies the analog signal generated It has an amplifier circuit 46 that is an amplifier that outputs to the analog switch circuit 35, a counter electrode voltage circuit 47 that sends a voltage to the counter substrate 13 side, and a power supply circuit 48 that generates power necessary for these circuits 41 to 47, etc. ing.

  On the other hand, the counter substrate 13 has a color filter layer 51 (FIGS. 2 and 3) corresponding to the display region 16 on the main surface of the transparent substrate having transparency and insulation, that is, the glass substrate 50 on the liquid crystal layer 15 side. The counter electrode 52 that is a common electrode is formed so as to cover the color filter layer 51, and the alignment film 53 is formed so as to cover the counter electrode 52.

  The color filter layer 51 is, for example, a vertical stripe type in which colored portions 51r, 51g, 51b corresponding to red, green, and blue are formed in a stripe shape along the signal line 23 direction, that is, the vertical direction, by synthetic resin, for example. Each colored portion 51r, 51g, 51b is arranged continuously in the direction of the signal line 23, ie, the vertical direction, and the colored portions 51r, 51g, 51b are sequentially arranged in the direction of the scanning line 22, ie, the horizontal direction. Has been. In the present embodiment, three corresponding pixel electrodes 26 form one pixel by the three primary color coloring portions 51r, 51g, and 51b that can form white.

  The color filter layer 51 may be provided on the array substrate 12 side. In this case, the liquid crystal panel 11 may be a transflective type or a reflective type.

  Similar to the pixel electrode 26, the counter electrode 52 is formed of a transparent conductive member such as ITO.

  The liquid crystal layer 15 is a light modulation layer formed of a predetermined liquid crystal material, and gradation display in each sub-pixel is possible by the voltage difference (voltage difference) between each pixel electrode 26 and the counter electrode 52. It has become.

  Next, the operation of the first embodiment will be described.

  The liquid crystal panel 11 performs AC inversion driving. That is, as shown in FIGS. 4 (a), 4 (b), 5 (a) and 5 (b), the counter electrode voltage Vcom is applied between the pixel electrodes 26 adjacent to each other in each frame and in the vertical direction. In contrast, the polarity of the analog signal (signal line voltage Va) is reversed and applied to the pixel electrode 26.

For example, in the odd-numbered scanning line 22 ₁ , when a pulsed gate voltage Vg + is applied to the scanning line 22 in one horizontal scanning period (1H), a gate electrode is connected to the scanning line 22 ₁ and the horizontal direction All the thin film transistors 25 and 28 adjacent to are turned on.

  The CPU signal SC sent from the set side of a computer or the like is converted into a liquid crystal display signal by the interface circuit 41 and stored in the GRAM circuit 42, and the display timing signal is converted by the timing signal circuit 43 based on the CPU signal SC. The liquid crystal display signal generated and stored in the GRAM circuit 42 by the shift register circuit 44 is output in synchronization with the timing signal generated by the timing signal circuit 43, and then converted into an analog signal by the digital / analog converter circuit 45. After being amplified by the amplifier circuit 46, it passes through the signal line 23 via the analog switch circuit 35, and is applied to each pixel electrode 26 by each turned-on thin film transistor 25. As a result, the pixel electrode voltage Vpix becomes substantially equal to the analog signal (signal line voltage Va).

  Further, as shown in FIG. 6, each auxiliary capacitance line voltage circuit 32r is generated by a signal transmitted from the driver IC 36 at the same time as the application of the analog signal (signal line voltage Va) for each color of RGB in the analog switch circuit 35. , 32g, 32b are driven to sequentially apply the auxiliary capacitance voltage Vcs to the auxiliary capacitance line 24 via the analog switch circuit 33 and the thin film transistors 28. Therefore, as shown in FIG. 5 (a) or FIG. 5 (b), in the one horizontal scanning period (1H) next to this one horizontal scanning period (1H), the auxiliary voltage corresponding to the adjusted auxiliary capacitance voltage Vcs is obtained. Since the capacitor is formed between the capacitor electrode 27 and the pixel electrode 26, the pixel electrode voltage Vpix is set relatively large.

  Then, according to the voltage difference between the set pixel electrode voltage Vpix and the counter electrode voltage Vcom, the tilt angle of the liquid crystal molecules of the liquid crystal layer 15 in each pixel differs, and the liquid crystal layer 15 operates as an optical shutter. The image is displayed with gradation.

  These operations are alternately performed with reverse polarity for each scanning line 22 and for each frame.

  As described above, according to the first embodiment, by adjusting the voltage of each auxiliary capacitance line 24 for each coloring portion 51r, 51g, 51b by the auxiliary capacitance line voltage circuits 32r, 32g, 32b, By adjusting the voltage difference between the pixel electrode 26 and the counter electrode 52, the liquid crystal layer 15 performs a shutter operation in accordance with the voltage difference to display gradation, so that the colored portions 51r and 51g are displayed in the manufacturing process, for example. , 51b, it is possible to individually adjust the gradation characteristics for each color without adjusting the gradation characteristics, and it is possible to cope with different gradation characteristics for each color without reducing the yield.

  In particular, as the voltage of the driver IC 36 is reduced, it is not easy to cope with gradation characteristics different for each color in the manufacturing process, and the manufacturing loss is reduced. By adjusting for each color of the coloring portions 51r, 51g, and 51b, even when the driver IC 36 has a low voltage, it is possible to reliably cope with different gradation characteristics for each color.

  Further, the auxiliary capacitor line 24 is formed at a position not intersecting with the pixel electrode 26, and the thin film transistor 28 is connected between the capacitor electrode 27 formed at the position intersecting with the pixel electrode 26 and the auxiliary capacitor line 24, thereby assisting. An auxiliary capacitor can be reliably formed between the capacitor electrode 27 and the pixel electrode 26 in accordance with a signal (voltage) applied to the capacitor line 24.

  Next, a second embodiment will be described with reference to FIGS. In addition, about the structure and effect | action similar to the said 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  In the second embodiment, as shown in FIG. 8, the colored portions 51r, 51g, 51b of the color filter layer 51 are continuous along the scanning line 22 direction, that is, the horizontal direction in the first embodiment. In this case, the storage capacitor line 24 is formed in parallel to each scanning line 22. Therefore, the auxiliary capacitance line voltage circuits 32r, 32g, 32b and the analog switch circuit 33 are arranged on the left side of the peripheral region 17, as shown in FIG.

  Each auxiliary capacitance line 24 is formed at a position intersecting with the pixel electrode 26 in plan view, and the auxiliary capacitance line 24 is connected to the pixel electrode 26 according to a signal (voltage) applied to the auxiliary capacitance line 24. Is formed.

Then, FIG. 9 (a), the as shown in FIG. 9 (b) and FIG. 10, for example, the scanning lines 22 ₁ of the odd frame, in one horizontal scanning period (1H), the scan line 22 pulsed gate voltage Vg + There Once applied, all of the thin film transistor 25 is a gate electrode adjacent to the horizontal direction is connected to the scan line 22 ₁ is turned on.

  The CPU signal SC sent from the set side of a computer or the like is converted into a liquid crystal display signal by the interface circuit 41 and stored in the GRAM circuit 42, and the display timing signal is converted by the timing signal circuit 43 based on the CPU signal SC. The liquid crystal display signal generated and stored in the GRAM circuit 42 by the shift register circuit 44 is output in synchronization with the timing signal generated by the timing signal circuit 43, and then converted into an analog signal by the digital / analog converter circuit 45. After being amplified by the amplifier circuit 46, it passes through the signal line 23 via the analog switch circuit 35, and is applied to each pixel electrode 26 by each turned-on thin film transistor 25. As a result, the pixel electrode voltage Vpix becomes substantially equal to the analog signal (signal line voltage Va).

  Furthermore, each auxiliary capacitance line voltage circuit 32r, 32g, 32b is generated by a signal transmitted from the driver IC 36 at the same time as the inversion of the analog signal (signal line voltage Va) for each color of RGB in the analog switch circuit 35. The auxiliary capacitance voltage Vcs is sequentially driven via the analog switch circuit 33 so as to be applied to the auxiliary capacitance line 24. For this reason, an auxiliary capacitance corresponding to the adjusted auxiliary capacitance voltage Vcs is formed between the auxiliary capacitance line 24 and the pixel electrode 26 in one horizontal scanning period (1H) next to the one horizontal scanning period (1H). As a result, the pixel electrode voltage Vpix is set relatively large.

  Then, according to the voltage difference between the set pixel electrode voltage Vpix and the counter electrode voltage Vcom, the tilt angle of the liquid crystal molecules of the liquid crystal layer 15 in each pixel differs, and the liquid crystal layer 15 operates as an optical shutter. The image is displayed with gradation.

  These operations are alternately performed with reverse polarity for each scanning line 22 and for each frame.

  In this way, by adjusting the voltage of each auxiliary capacitance line 24 for each of the coloring portions 51r, 51g, 51b by the auxiliary capacitance line voltage circuits 32r, 32g, 32b, the pixel electrode 26 is connected to the counter electrode 52. By adjusting the voltage difference, for example, the gradation characteristics for each color can be individually adjusted without adjusting the gradation characteristics for each color of the colored portions 51r, 51g, 51b in the manufacturing process, etc., and the yield is reduced. The same effects as those of the first embodiment can be obtained, such as being able to cope with different gradation characteristics for each color.

  Further, by forming the auxiliary capacitance line 24 so as to intersect with the pixel electrode 26, it is possible to easily add an auxiliary capacitance according to this signal between the pixel electrode 26 only by applying a signal (voltage) to the auxiliary capacitance line 24. Can be formed.

  In each of the above embodiments, the color filter layer 51 may have a configuration including colored portions other than red, green, and blue.

  Further, the inside of the driver IC 36 is not limited to the above configuration.

  Further, as the light modulation layer, any layer other than the liquid crystal layer 15 may be used as long as the shutter operation is performed according to the voltage difference between the pixel electrode 26 and the counter electrode 52.

It is a top view which shows the display element of the 1st Embodiment of this invention. It is a top view which shows the color filter layer of a display element same as the above. It is side surface sectional drawing which shows a display element same as the above. (a) is a table | surface which shows operation | movement in the odd frame of a display element same as the above, (b) is a table | surface which shows operation | movement in the even frame of a display element same as the above. (a) is a waveform diagram showing the voltage fluctuation during the pixel electrode writing operation on the positive polarity side of the display element, and (b) is the voltage fluctuation during the pixel electrode writing operation on the negative polarity side of the display element. FIG. It is a timing chart which shows the operation timing of the analog switch circuit and voltage adjustment part of a display element same as the above. It is a top view which shows the display element of the 2nd Embodiment of this invention. It is a top view which shows the color filter layer of a display element same as the above. (a) is a waveform diagram showing the voltage fluctuation during the pixel electrode writing operation on the positive polarity side of the display element, and (b) is the voltage fluctuation during the pixel electrode writing operation on the negative polarity side of the display element. FIG. It is a timing chart which shows the operation timing of the analog switch circuit and voltage adjustment part of a display element same as the above.

Explanation of symbols

11 Liquid crystal panels as display elements
12 Array substrate
13 Counter substrate
15 Liquid crystal layer as light modulation layer
22 scan lines
23 Signal line
24 Auxiliary capacitance line
25 Thin-film transistors as switching elements
26 Pixel electrode
27 Capacitance electrode
28 Thin-film transistors as auxiliary capacitance switching elements
32b, 32g, 32r Auxiliary capacitance line voltage circuit as voltage regulator
51 Color filter layer
51b, 51g, 51r coloring part
52 Counter electrode

Claims (3)

An array substrate;
A counter substrate disposed opposite to the array substrate;
A plurality of scanning lines and a plurality of signal lines that are formed in a lattice pattern across the array substrate;
A pixel electrode formed on the array substrate corresponding to each crossing position of the scanning line and the signal line;
A switching element formed on the array substrate and connected to the scanning line and the signal line to drive the pixel electrode;
A color filter layer comprising colored portions of different colors formed corresponding to each of the pixel electrodes;
An auxiliary capacitance line that is formed between the scanning lines of the array substrate and forms an auxiliary capacitance connected to the pixel electrode;
A counter electrode formed on the counter substrate to face the pixel electrode;
A voltage adjusting unit that adjusts a voltage difference between each pixel electrode and the counter electrode by adjusting the voltage of each auxiliary capacitance line for each color of the coloring portion;
A display element comprising: a light modulation layer which is disposed between the array substrate and the counter substrate and modulates light according to a voltage difference between the pixel electrodes and the counter electrode. The auxiliary capacitance line is formed at a position not intersecting with the pixel electrode in plan view,
A capacitor electrode formed at a position intersecting the pixel electrode in plan view;
Auxiliary capacitance connected between the scanning line, the auxiliary capacitance line, and the capacitance electrode, and forming an auxiliary capacitance between the capacitance electrode and the pixel electrode according to the voltage of the auxiliary capacitance line adjusted by the voltage adjustment unit. The display element according to claim 1, further comprising a switching element for a capacitor. The display element according to claim 1, wherein the storage capacitor line is formed to intersect with the pixel electrode in plan view.

Images