JP2009277909A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the performance of a semiconductor device with a MIS (Metal Insulator Semiconductor) transistor. <P>SOLUTION: On a principal surface s1 of a silicon substrate 1, a gate electrode GEn for nMIS is formed in an nMIS region R, a gate electrode GEp for pMIS is formed in a pMIS region Rp, and an n-type source-drain region sdn and a p-type source-drain region sdp are formed by and below them, respectively. Then a first stress film N1a having tensile stress is formed covering the principal surface s1 of the silicon substrate 1 and both the gate electrodes GEn and GEp. Further, ion implantation in the first stress film N1a in the pMIS region Rp is carried out to reduce stress. After both the gate electrodes GEn and GEp are crystallized through a heat treatment, the first stress film N1a is removed. In a step of crystallizing both the gate electrodes GEn and GEp, the tensile stress of the first stress film N1a is stored in the gate electrode Gen for nMIS. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a manufacturing method of a semiconductor device including a MIS transistor enhanced in performance using a stress memory technique.

  A semiconductor device that processes and stores a large amount of information at high speed includes a plurality of MIS (Metal Insulator Semiconductor) type field effect transistors (hereinafter simply referred to as MIS transistors), and constitutes, for example, a logic circuit or a memory array. Yes. These MIS transistors are formed on a semiconductor substrate and realize high performance of a semiconductor device by high integration by miniaturization.

  In general, a MIS transistor has a stacked structure of a gate electrode made of a metal or a metal-class conductive semiconductor, a gate insulating film made of an insulating film, and a channel region made of a semiconductor. Have Further, the structure has a source region and a drain region for conducting to the channel region. In particular, due to the electric field effect from the gate electrode through the gate insulating film, depending on the polarity of the inversion layer formed in the channel region, an n-channel MIS transistor (hereinafter simply referred to as an n-type MIS transistor) in which carriers are electrons Alternatively, it is called a p-channel MIS transistor (hereinafter simply referred to as a p-type MIS transistor) in which carriers are holes.

  2. Description of the Related Art In recent years, in semiconductor devices, a technique for applying stress to a device has been proposed for the purpose of improving the performance of a MIS transistor, such as an increase in processing speed and an improvement in driving power at a lower voltage. The characteristics of n-type MIS transistors are improved by applying tensile stress, while the characteristics of p-type MIS transistors are improved by applying compressive stress. It is known to improve. More specifically, the lattice in the channel region is distorted by the above stress, and the carrier mobility is increased. As a result, a large current flows between the source and the drain even at the same voltage, and the driving force is improved.

  For example, Japanese Patent Laying-Open No. 2005-286341 (Patent Document 1) discloses a technique for relaxing stress of a stress control film in a region by selectively performing ion implantation on a stress control film formed on an element. Etc. are disclosed. Thus, appropriate mechanical stress can be applied and removed depending on the conductivity type (n-type, p-type, etc.) of the element and the role of operation (analog, digital, etc.).

  Further, for example, in Japanese Patent Application Laid-Open No. 2005-294360 (Patent Document 2), a reaction suppressing element is selectively applied to a direct nitride film having stress formed so as to cover a MOS (Metal Oxide Semiconductor) transistor. Techniques for injection are disclosed. Thereby, by suppressing the disilation of the NiSi (nickel silicide) film formed on the gate electrode and the source / drain regions, the heat resistance can be improved and the stress of the direct nitride film can be relieved.

  Further, for example, Japanese Patent Application Laid-Open No. 2007-134718 (Patent Document 3) discloses a technique for storing a stress of a stress layer in a semiconductor device. Thereby, even if a stress layer is removed, the stress effect | action to FET (Field Effect Transistor: Field effect transistor) can be maintained.

Further, for example, in Japanese Patent Application Laid-Open No. 2007-311796 (Patent Document 4), the source and drain metal silicide layers are phase-converted by performing an annealing process on the silicon nitride cap formed on the FET. The technique of making it disclose is disclosed. Thereby, a CMOS (Complementary MOS) device having a silicide to which intrinsic stress is applied can be formed.
JP 2005-286341 A JP 2005-294360 A JP 2007-134718 A JP 2007-311796 A

  In contrast to the technique of applying stress to the MIS transistor using a stress film, the technique of storing the stress in the MIS transistor itself is called SMT (Stress Memorization Technique) technique. According to the study of the present inventor, the driving force of the MIS transistor can be more effectively improved by applying a desired stress to the MIS transistor in which the stress is stored using the SMT technique, by a stress film. .

  In the SMT technology examined by the present inventors, first, a film having high stress (for example, nitriding) is formed on the MIS transistor in a state where the polycrystalline silicon (polysilicon, poly-Si) of the gate electrode is amorphous. A silicon film is deposited. Subsequently, heat treatment (annealing) is performed in a state where the stress of the stress film is applied, whereby the stress is stored in the gate electrode when the polycrystalline silicon is crystallized.

  As described above, the direction of stress (tensile or compressive) necessary to improve the characteristics is reversed between the n-type MIS transistor and the p-type MIS transistor. Furthermore, it is known that the characteristics deteriorate when a stress opposite to the stress that improves the characteristics is applied to each transistor (for example, when a tensile stress is applied to the p-type MIS transistor). . Therefore, the present inventor examined a technique for changing the memorized stress depending on the polarity of the MIS transistor. The method will be described below.

  First, after the source / drain regions of the MIS transistor are formed by ion implantation, a cap oxide film is formed, and a silicon nitride film for applying a tensile stress is deposited thereon. Subsequently, only on the p-type MIS transistor, the silicon nitride film is removed by anisotropic dry etching, and then heat treatment is performed. Here, in the anisotropic etching of the silicon nitride film, the cap oxide film functions as an etching stopper. Thereafter, the remaining silicon nitride film is removed by isotropic wet etching. In this way, only the n-type MIS transistor can be improved in performance without applying a tensile stress that degrades the characteristics of the p-type MIS transistor.

  However, further studies by the inventor have revealed that the SMT technique based on the above method has problems. That is, in order to selectively remove the stress film on the p-type MIS transistor, it is desirable to perform anisotropic etching, but normal anisotropic etching is difficult from the viewpoint of side effects and processing accuracy. I understood that. This will be described in more detail below.

  In the SMT technique studied by the present inventor, in order to store the stress in the gate electrode of the MIS transistor, a stress film is formed after the gate electrode is formed, and a process for storing the stress is performed. Here, the gate electrode is a stepped portion on the substrate. Therefore, when anisotropic etching is performed on the stress film formed so as to cover the gate electrode, the stress film remains on the side wall of the gate electrode. In the above example, this means that a stress film that applies tensile stress remains on the p-type MIS transistor, resulting in deterioration of characteristics.

  This problem can be avoided by continuing the anisotropic etching until the stress film remaining on the side wall is completely removed. However, when such over-etching is performed, the cap oxide film serving as an etching stopper is etched, and the underlying source / drain regions and the like are also etched. When the source / drain region is etched away, the resistance value of the source / drain region increases, and as a result, the operation speed of the MIS transistor decreases. In addition, the source / drain regions etched by over-etching become shallower by the amount removed, and the leakage current increases. As a result, standby power increases.

  In order to reduce the influence of the over-etching, it is effective to form a cap oxide film as an etching stopper thicker. However, since the cap oxide film is formed between the MIS transistor and the stress film, when the cap oxide film is formed thick, the action of stress caused by the stress film on the MIS transistor is reduced. This means that in the above example, the tensile stress acting on the n-type MIS transistor is relaxed and the expected effect of improving the characteristics cannot be obtained.

  Therefore, in another study by the present inventor, an attempt was made to remove the stress film on the p-type MIS transistor by performing isotropic wet etching instead of anisotropic etching. With such wet etching, even a thin cap oxide film can sufficiently function as an etching stopper. And if it is such isotropic etching, a stress film will not remain on the side wall of the gate electrode. However, it has been found that in isotropic etching, the stress film is also etched in the lateral direction, so that it is difficult to process a fine pattern such as an SRAM (Static Random Access Memory) cell.

  Further, in another study by the present inventor, an attempt was made to crystallize the gate electrode by performing heat treatment without removing the stress film on the p-type MIS transistor and to store the tensile stress. As a result, problems such as the anisotropic etching damage to the p-type MIS transistor and processing accuracy can be avoided. However, the tensile stress is also stored in the p-type MIS transistor, and improvement in performance cannot be expected. In the state where the tensile stress is stored, it is difficult to store the compressive stress in the p-type MIS transistor by the subsequent SMT process. Even if a stress film that applies the compressive stress is deposited, the effect is not affected. It will be reduced.

  As described above, in the SMT technology, there is a trade-off relationship between improving the performance of a semiconductor device by selectively storing stress in the MIS transistor and maintaining the performance of the semiconductor device by avoiding damage due to processing. This has been clarified by the study of the present inventor.

  Therefore, an object of the present invention is to provide a technique for improving the performance of a semiconductor device including a MIS transistor.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  In the present application, a plurality of inventions are disclosed. An outline of one embodiment of the inventions will be briefly described as follows.

  A first gate electrode is formed in the first region and a second gate electrode is formed in the second region on the main surface of the semiconductor substrate, and a first conductivity type source, A drain region and a second conductivity type source / drain region are formed. Subsequently, a first stress film that applies compressive stress or tensile stress is formed so as to cover the main surface of the semiconductor substrate and both gate electrodes. Thereafter, the stress is relaxed by performing ion implantation on the first stress film in the second region. Thereafter, both gate electrodes are crystallized by heat treatment, and then the first stress film is removed. In the step of crystallizing both gate electrodes, the stress of the first stress film is stored in the first gate electrode.

  Of the plurality of inventions disclosed in the present application, effects obtained by the above-described embodiment will be briefly described as follows.

  That is, the performance of the semiconductor device including the MIS transistor can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
A method for manufacturing the semiconductor device of the first embodiment will be described in detail with reference to FIGS. 1 to 8 are fragmentary cross-sectional views of the semiconductor device during the manufacturing process of the first embodiment. During the manufacturing process of the semiconductor device of the first embodiment, the substrate is a semiconductor mainly composed of single crystal silicon, contains more acceptor impurities than donor impurities, and majority carriers are holes. In addition, a wafer-like silicon substrate (semiconductor substrate) 1 is used. Hereinafter, the conductivity polarity of the semiconductor substrate and the semiconductor region is simply referred to as p-type (second conductivity type). That is, the impurity that is introduced into the semiconductor region and becomes p-type is an acceptor impurity. Further, the silicon substrate 1 may contain more donor impurities than acceptor impurities, and the majority carriers may be electrons. Hereinafter, the conductivity polarity of the semiconductor substrate and the semiconductor region is simply referred to as n-type (first conductivity type). That is, the impurity that is introduced into the semiconductor region and becomes n-type is a donor impurity. In the drawing, the cross section of the main part of the silicon substrate 1 is shown in an enlarged manner.

  In the first embodiment, the nMIS region (first region) Rn on the silicon substrate 1 has an n-type MIS transistor (first field effect transistor), and the pMIS region (second region) Rp has a p-type MIS transistor (first field effect transistor). A method for manufacturing a semiconductor device having a second field effect transistor) will be described.

  As shown in FIG. 1, the separation part 2 is formed on the main surface s <b> 1 of the silicon substrate 1. First, for example, a shallow groove is formed in the main surface s1 of the silicon substrate 1 by photolithography and anisotropic etching. The photolithographic method is a series of steps for forming a desired resist pattern on the photoresist film by steps such as application of the photoresist film, exposure and development. Using such a photoresist film as a mask, anisotropic etching or ion implantation can be performed on the exposed region. Thereafter, the same applies to the photolithography method.

  Subsequently, an insulating film such as silicon oxide is deposited on the silicon substrate 1 including the inside of the shallow trench by a chemical vapor deposition (CVD) method or the like. After that, unnecessary silicon oxide film outside the shallow groove is polished and removed by a chemical mechanical polishing (CMP) method or the like, so that the silicon oxide film is embedded in the shallow groove. Form. In this way, the isolation part 2 having an STI (Shallow Trench Isolation) structure is formed. By forming the isolation portion 2, regions (active regions) for forming various elements such as the nMIS region Rn and the pMIS region Rp are defined on the main surface s1 of the silicon substrate 1.

  Subsequently, in the nMIS region Rn, a p-well 3p, which is a p-type semiconductor region, is formed on the main surface s1 of the silicon substrate 1. In the pMIS region Rp, an n-well 3n, which is an n-type semiconductor region, is formed on the main surface s1 of the silicon substrate 1. This is formed by a photolithography method, an ion implantation method, a heat treatment process, or the like. More specifically, it is as follows.

  First, the photoresist film formed on the silicon substrate 1 is patterned by a photolithography method or the like into a shape in which regions where the wells 3n and 3p are to be formed are opened. Thereafter, ion implantation is performed on the main surface s1 using the patterned photoresist film as an ion implantation mask. For example, when the p-well 3p is formed, impurity ions (for example, boron (B) ions) serving as acceptors are implanted. Further, for example, when forming the n-well 3n, impurity ions (for example, phosphorus (P) ions, arsenic (As) ions, etc.) serving as donors are implanted. Thereafter, by performing heat treatment, the implanted impurity ions are diffused and activated simultaneously. Hereinafter, the process of forming the semiconductor region is the same. Note that the heat treatment for diffusing and activating the impurity ions is not performed here, and may be performed at the same time as the heat treatment required in various subsequent steps.

  Next, as shown in FIG. 2, an nMIS gate electrode (first gate electrode) GEn is formed on the main surface s1 of the nMIS region Rn of the silicon substrate 1 via the gate insulating film GI. Further, a pMIS gate electrode (second gate electrode) GEp is formed on the main surface s1 of the pMIS region Rp of the silicon substrate 1 via the gate insulating film GI.

  For this purpose, first, a main surface s1 of the silicon substrate 1 is thermally oxidized to form a silicon oxide film. Subsequently, a polycrystalline silicon film is formed by, for example, a CVD method so as to cover the silicon oxide film. Thereafter, the silicon oxide film is processed into a desired shape by photolithography or etching. Thereby, the nMIS gate electrode GEn is formed in the nMIS region Rn, and the pMIS gate electrode GEp is formed in the pMIS region Rp. Both the MIS gate electrodes GEn and GEp are formed by processing a polycrystalline silicon film, and there is no distinction at this point other than the formed region. Thereafter, similarly, the silicon oxide film is processed into a planar shape similar to that of the MIS gate electrodes GEn and GEp, thereby forming the gate insulating film GI.

  Subsequently, the main surface s1 of the silicon substrate 1 in the pMIS region Rp is covered with a photoresist film or the like, and impurity ions serving as donors are implanted, whereby the n-type extension region 4n that is an n-type semiconductor region is formed in the nMIS region Rn. Form. Subsequently, impurity ions serving as acceptors are implanted to form a p-type halo region 5p, which is a p-type semiconductor region, in the nMIS region Rn. At this time, in the nMIS region Rn, the nMIS gate electrode GEn serves as an ion implantation mask. Accordingly, the n-type extension region 4n and the p-type halo region 5p are formed in a region below the side surface of the nMIS gate electrode GEn in the main surface s1 of the silicon substrate 1 in the nMIS region Rn. Here, the p-type halo region 5p is formed to be deeper than the n-type extension region 4n and to have a higher p-type impurity concentration than the p-well 3p. Either the n-type extension region 4n or the p-type halo region 5p may be formed first.

  Further, the main surface s1 of the silicon substrate 1 in the nMIS region Rn is covered with a photoresist film or the like, and impurity ions serving as acceptors are implanted, thereby forming a p-type extension region 4p which is a p-type semiconductor region in the pMIS region Rp. To do. Subsequently, impurity ions serving as donors are implanted to form an n-type halo region 5n that is an n-type semiconductor region in the pMIS region Rp. At this time, in the pMIS region Rp, the pMIS gate electrode GEp serves as an ion implantation mask. Therefore, the p-type extension region 4p and the n-type halo region 5n are formed in the region of the main surface s1 of the silicon substrate 1 in the pMIS region Rp at the lower side of the pMIS gate electrode GEp. Here, the n-type halo region 5n is formed to be deeper than the p-type extension region 4p and to have an n-type impurity concentration higher than that of the n-well 3n. Either the p-type extension region 4p or the n-type halo region 5n may be formed first.

  In the MIS transistor, the extension regions 4n and 4p are regions formed for transferring carriers between a source / drain region to be formed later and an inversion layer formed in the channel region. The required characteristics determine specifications such as depth and impurity concentration. If the specification is comparable to that of the source / drain regions, the extension regions 4n and 4p may not be formed.

  The halo regions 5n and 5p are regions formed to reduce the so-called short channel effect by locally increasing the impurity concentration of the channel region and decreasing the spread of the depletion layer. If it is not necessary to reduce the short channel effect, the halo regions 5n and 5p may not be formed.

  In the above steps, an implantation step into the nMIS region Rn for forming the n-type extension region 4n and the p-type halo region 5p, and a pMIS region Rp for forming the p-type extension region 4p and the n-type halo region 5n. Either step may be performed first.

  Subsequently, sidewall spacers 6 are formed so as to cover the sidewalls of the nMIS gate electrode GEn and the sidewalls of the pMIS gate electrode GEp.

  For this, first, a silicon oxide film is formed by CVD or the like so as to cover the main surface s1 of the silicon substrate 1 including both the MIS gate electrodes GEn and GEp. Thereafter, the entire surface of the silicon oxide film is anisotropically etched (etched back). At this time, an apparently thick silicon oxide film is formed on the side walls of the MIS gate electrodes GEn and GEp, which are stepped portions on the main surface s1, as compared with the other regions. Accordingly, the silicon oxide film remains on the side walls of the MIS gate electrodes GEn and GEp after the silicon oxide film in the flat region is completely removed by the etch back as described above. By stopping the anisotropic etching in this state, the side wall spacer 6 made of a silicon oxide film can be formed so as to cover the side walls of the MIS gate electrodes GEn and GEp.

  Next, as shown in FIG. 3, in the main surface s1 of the nMIS region Rn of the silicon substrate 1, the nMIS source electrode is formed on the side lower portion of the nMIS gate electrode GEn and on the side lower portion of the sidewall spacer 6. A drain region (first conductivity type source / drain region) sdn is formed.

  For this, first, a photoresist film 7 patterned by a photolithography method or the like is formed so as to cover the main surface s1 of the silicon substrate 1 in the pMIS region Rp. Thereafter, impurity ions serving as donors are implanted into the main surface s1 of the silicon substrate 1 in the nMIS region Rn using the photoresist film 7 as an ion implantation mask (ion implantation 100). At this time, in the nMIS region Rn, the nMIS gate electrode GEn and the sidewall spacer 6 serve as an ion implantation mask. Therefore, the n-type source / drain region sdn can be formed on the lower main surface s1 further on the side of the sidewall spacer 6 in the region on the lower side of the nMIS gate electrode GEn. The n-type source / drain region sdn is formed so as to have an impurity concentration deeper than that of the n-type extension region 4n and higher than that of the n-type extension region 4n. Then, heat treatment may be performed to diffuse or activate impurities in the n-type source / drain region sdn. However, in the manufacturing method of the first embodiment, it is more preferable not to perform heat treatment in this step. preferable. The reason will be described later in detail.

  Next, as shown in FIG. 4, in the main surface s1 of the pMIS region Rp of the silicon substrate 1, the pMIS source electrode is formed on the side lower portion of the pMIS gate electrode GEp and on the side lower portion of the sidewall spacer 6. A drain region (second conductivity type source / drain region) sdp is formed.

  For this, first, a photoresist film 8 patterned by photolithography or the like is formed so as to cover the main surface s1 of the silicon substrate 1 in the nMIS region Rn. Thereafter, impurity ions serving as donors are implanted into the main surface s1 of the silicon substrate 1 in the pMIS region Rp using the photoresist film 8 as an ion implantation mask (ion implantation 200). At this time, in the pMIS region Rp, the pMIS gate electrode GEp and the sidewall spacer 6 serve as an ion implantation mask. Therefore, the p-type source / drain region sdp can be formed on the lower main surface s1 further on the side of the sidewall spacer 6 in the region on the lower side of the pMIS gate electrode GEp. The p-type source / drain region sdp is formed so as to have an impurity concentration deeper than that of the p-type extension region 4p and higher than that of the p-type extension region 4p. Then, heat treatment may be performed to diffuse or activate impurities in the p-type source / drain region sdp. However, in the manufacturing method of the first embodiment, it is more preferable not to perform heat treatment in this step. preferable. The reason will be described later in detail.

  Through the above steps, the basic structure of the MIS transistor is formed on the silicon substrate 1. That is, the nMIS region Rn on the silicon substrate 1 includes an n-type MIS transistor (first field effect transistor) having, as a basic configuration, an nMIS gate electrode GEn, a gate insulating film GI, an n-type source / drain region sdn, and the like. Qn was formed in the p-well 3p. Further, in the pMIS region Rp on the silicon substrate 1, a p-type MIS transistor (second field effect transistor) having a pMIS gate electrode GEp, a gate insulating film GI, a p-type source / drain region sdp, and the like as a basic configuration. Qp was formed in n-well 3n.

  Next, as shown in FIG. 5, the first cap film (first protective film) is formed so as to integrally cover the main surface s1 of the silicon substrate 1, the nMIS gate electrode GEn, and the pMIS gate electrode GEp. C1a is formed. In the manufacturing method of the first embodiment, an insulating film mainly composed of silicon oxide formed by a CVD method or the like is formed as the first cap film C1a.

  Thereafter, a first stress film N1a is formed so as to cover the first cap film C1a. That is, the first stress film N1a is formed so as to integrally cover the main surface s1 of the silicon substrate 1, the nMIS gate electrode GEn, and the pMIS gate electrode GEp via the first cap film C1a. become. In the manufacturing method of the first embodiment, as the first stress film N1a, an insulating film mainly made of silicon nitride formed by a plasma CVD method or the like is formed.

  Here, as a generally known method, when a silicon nitride film is formed by a plasma CVD method or the like, the compressive stress of the formed silicon nitride film is adjusted by adjusting applied power, pressure, gas type, or the like. The direction of stress such as tensile stress and the magnitude of the stress can be arbitrarily changed. For example, the magnitude of the stress can be adjusted by irradiating the formed silicon nitride film with ultraviolet (UV) rays. Hereinafter, the same applies to a method of forming a silicon nitride film having a desired stress as the stress film.

  In the manufacturing method of the first embodiment, the first stress film N1a that applies a tensile stress to the silicon substrate 1 is formed. Here, a film that exerts a tensile stress on the silicon substrate 1 is a stress that distorts the silicon substrate 1 upward when the surface of the silicon substrate 1 on which the film is deposited is the upper surface. It is a working membrane. On the other hand, a film that exerts a compressive stress on the silicon substrate 1 is a film that exerts a stress that distorts the silicon substrate 1 in a convex manner.

  In the manufacturing method of the first embodiment, as an example, the first stress film N1a is formed so that the magnitude of the tensile stress is about 0.3 to 1.7 GPa. As an example, the first stress film N1a is formed to have a thickness of 20 to 50 nm.

  The first stress film N1a having the tensile stress as described above can improve the characteristics of the n-type MIS transistor Qn. However, the first stress film N1a can hinder the improvement of the characteristics of the p-type MIS transistor Qp. is there.

  Therefore, in the manufacturing method of the first embodiment, as shown in FIG. 6A, the first stress film in the pMIS region Rp is obtained by performing ion implantation 300 on the first stress film N1a in the pMIS region Rp. Relax the tensile stress of N1a. For this, first, a photoresist film 9 patterned by a photolithography method or the like is formed so as to cover the first stress film N1a in the nMIS region Rn. Thereafter, ion implantation 300 is performed on the first stress film N1a in the pMIS region Rp using the photoresist film 9 as an ion implantation mask. In this way, the tensile stress of the first stress film N1a in the pMIS region Rp can be relaxed. For example, ions containing silicon (Si) or germanium (Ge) are used as ions implanted to relieve stress.

  Subsequently, heat treatment is performed to crystallize the nMIS gate electrode GEn and the pMIS gate electrode GEp made of polycrystalline silicon. Here, the first stress film N1a covering the nMIS gate electrode GEn in the nMIS region Rn is not subjected to the ion implantation 300 in the previous step and has a tensile stress. Then, the nMIS gate electrode GEn is crystallized under the action of the tensile stress, whereby the tensile stress is stored in the nMIS gate electrode GEn. That is, by the heat treatment in this step, the same stress as that of the first stress film N1a can be stored in the nMIS gate electrode GEn.

  On the other hand, the first stress film N1a covering the pMIS gate electrode GEp in the pMIS region Rp is in a state in which the tensile stress is relaxed by performing the ion implantation 300 in the previous step. Therefore, the pMIS gate electrode GEp is crystallized in a state in which it does not receive the action of stress from the first stress film N1a. That is, no significant stress is stored in the pMIS gate electrode GEp in the heat treatment in this step.

  Strictly speaking, although the first stress film N1a in the pMIS region Rp has relaxed the tensile stress by the ion implantation 300, a slight tensile stress can be left unless it is completely relaxed. However, if the ion implantation 300 used in a normal process is applied regardless of a special ion species or ion implantation at a particularly high energy, the first stress film is not affected even if it remains slightly. Tensile stress can be relaxed. Hereinafter, it is described as a state where no significant stress is applied, including a state where the stress has been relaxed to a level that does not cause a problem.

  Further, it is more preferable that the heat treatment of this step is shared with the heat treatment for diffusing or activating both the source / drain regions sdn and sdp formed above. This is because the manufacturing process can be simplified. Note that the diffusion or activation of the source / drain regions sdn and sdp means that the implanted impurity ions are diffused to a desired region (depth, etc.) by performing heat treatment, and the semiconductor serving as a base material It is to form a covalent bond with a crystal to generate a carrier (activation).

  As described above, in the manufacturing method according to the first embodiment, the source / drain regions sdn and sdp are simultaneously diffused or activated by the heat treatment for crystallizing the nMIS gate electrode GEn and the pMIS gate electrode GEp. To do. For example, the source / drain regions sdn and sdp are diffused or activated by performing heat treatment at about 950 to 1150 ° C. by spike annealing. By heat treatment under such conditions, both gate electrodes GEn, GEp made of polycrystalline silicon are crystallized.

  Thereafter, by removing the first stress film N1a and the first cap film C1a, a structure as shown in FIG. 6B is formed. Even if the first stress film N1a is removed, the tensile stress stored in the nMIS gate electrode GEn is not lost and continues to act on the silicon substrate 1. Therefore, according to the manufacturing method of the first embodiment, the n-type MIS transistor Qn having the nMIS gate electrode GEn storing the tensile stress and the p-type MIS transistor Qp having the pMIS gate electrode GEp having no significant stress. And can be formed.

  Furthermore, as described above, in the manufacturing method of the first embodiment, the stress of the first stress film N1a in the pMIS region Rp is relaxed by performing the selective ion implantation 300. Therefore, it is not necessary to remove the first stress film N1a in the pMIS region Rp by anisotropic etching. Thereby, the tensile stress to the p-type MIS transistor Qp can be relaxed without causing damage due to overetching. As described above, according to the manufacturing method of the first embodiment, in the SMT technique, stress can be selectively stored in the MIS transistor while avoiding damage due to processing. As a result, the performance of the semiconductor device including the MIS transistor can be improved.

  Further, in the manufacturing method of the first embodiment, it is not necessary to selectively remove the first stress film N1a, and it may be removed entirely. Therefore, in the step after storing the tensile stress by crystallization of the nMIS gate electrode GEn, the first stress film N1a can be removed by performing isotropic etching on the entire surface of the first stress film N1a. . In the manufacturing method of the first embodiment, as an example, the first stress film N1a is removed by isotropic wet etching using hot phosphoric acid.

  Here, in the manufacturing method of the first embodiment, the first cap film C1a is formed between the silicon substrate 1 and the first stress film N1a. As the first cap film C1a, a film is formed such that the etching rate in the isotropic etching for removing the first stress film N1a is slower than that of the first stress film N1a. For example, in the description using FIG. 5 above, a silicon oxide film is formed as the first cap film C1a. The first cap film C1a, which is a silicon oxide film, has an etching rate slower than the first stress film N1a, which is a silicon nitride film, in the isotropic etching using hot phosphoric acid. Therefore, it functions as an etching stop film when the first stress film N1a is wet-etched.

  The first cap film C1a may not be formed if only the tensile stress is stored in the nMIS gate electrode GEn. However, in the manufacturing method according to the first embodiment, the first stress film N1a isotropic. It is more preferable to form the first cap film C1a as an etching stop film for etching. Thereby, the etching damage to both MIS transistors Qn and Qp can be further reduced, and the leakage current and source / drain resistance in the MIS transistors Qn and Qp can be reduced. As a result, the performance of the semiconductor device including the MIS transistor can be further improved.

  Furthermore, the thickness of the first cap film C1a in the manufacturing method of the first embodiment may be formed thinner than the cap film in the method studied by the present inventors. This is because, in the method studied by the present inventors, it is necessary to form a cap film as an etching stop film for anisotropic dry etching in order to selectively remove the stress film. On the other hand, in the manufacturing method of the first embodiment, the first stress film N1a may be removed by isotropic wet etching, and the damage given to the first cap film C1a as the etching stop film is weaker. Therefore, the first cap film C1a can be formed thinner. In the manufacturing method of the first embodiment, for example, the first cap film C1a is formed so as to have a film thickness of 5 to 10 nm.

  Thus, by forming the etching stop film formed between the stress film and the element thinner, the stress of the stress film can be applied to the element more efficiently. That is, according to the manufacturing method of the first embodiment, the tensile stress of the first stress film N1a formed on the first cap film C1a can be applied to the nMIS gate electrode GEn more strongly. Accordingly, the tensile stress of the first stress film N1a can be stored more efficiently in the nMIS gate electrode GEn. Further, this is an effect due to the fact that the first cap film C1a can be formed thin. However, in the manufacturing method of the first embodiment, the first cap film C1a is formed as a stop film for isotropic etching. The first cap film C1a can be formed thinner without worrying about damage to Qn and Qp. Therefore, according to the manufacturing method of the first embodiment, in the SMT technique, stress can be selectively stored in the MIS transistor while avoiding damage due to processing. As a result, the performance of the semiconductor device including the MIS transistor can be further improved.

  In the manufacturing method of the first embodiment, the first stress film N1a made of a silicon nitride film is removed by wet etching using hot phosphoric acid, and then the first cap film C1a made of a silicon oxide film is made of, for example, hydrofluoric acid (fluoride). Hydrogen, HF) is removed by wet etching. The wet etching of the silicon oxide film with hydrofluoric acid has a sufficiently large selection ratio with respect to the underlying silicon substrate 1 and the MIS gate electrodes GEn and GEp.

  In the subsequent process, wirings for electrical connection are formed for the terminals of both MIS transistors Qn and Qp formed as described above.

  As shown in FIG. 7, a metal silicide layer 10 is formed on both source / drain regions sdn, sdp and both MIS gate electrodes GEn, GEp, which are silicon regions exposed on the main surface s1 of the silicon substrate 1. . As the metal silicide layer 10, for example, a conductor film mainly composed of nickel silicide is formed. Here, the metal silicide layer 10 is formed in the above region in a self-aligned manner by a so-called salicide process. More specifically, first, a metal film (for example, nickel) is formed on the main surface s1 of the silicon substrate 1 by sputtering or the like. Subsequently, a silicidation reaction is caused at the interface between silicon and metal by performing heat treatment. Thereby, a metal silicide film is formed. Thereafter, by removing the excess metal film that has not been combined, the metal silicide layer 10 can be formed in the above-described region in a self-aligned manner without patterning.

  Thereafter, an etching stopper 11 and an interlayer insulating film 12 are sequentially formed so as to cover the main surface s1 of the silicon substrate 1. For the etching stopper 11 and the interlayer insulating film 12, a combination of insulating films having different etching rates for a predetermined anisotropic etching is selected. For example, the etching stopper 11 is an insulating film mainly composed of silicon nitride, and the interlayer insulating film 12 is formed as an insulating film mainly composed of silicon oxide by a CVD method or the like. The etching stopper 11 is formed so as to thinly cover at least the structure formed on the main surface s1 of the silicon substrate 1, and the interlayer insulating film 12 is formed thick so as to sufficiently embed the structure.

  Thereafter, a contact hole 13 that reaches the metal silicide layer 10 is formed so as to penetrate the interlayer insulating film 12 and the etching stopper 11. The contact hole 13 is formed by a photolithography method, an anisotropic etching method, or the like. Here, the contact hole 13 is formed by a so-called SAC (Self Align Contact) method using a difference in speed with respect to anisotropic etching between the etching stopper 11 and the interlayer insulating film 12.

  Next, as shown in FIG. 8, a contact plug 14 is formed by embedding a conductive film mainly composed of tungsten (W), for example, so as to fill the inside of the contact hole 13. For this, first, a tungsten film is formed so as to bury the contact hole 13 by, for example, sputtering. Then, the contact plug 14 is formed by removing the excess tungsten film by etching or CMP. Note that, for example, titanium nitride may be formed as a barrier film before depositing the tungsten film. The contact plug 14 thus formed is electrically connected to each terminal of the MIS transistors Qn and Qp.

  Subsequently, a wiring for taking a desired conduction is formed in the contact plug 14. First, an insulating film 15 made of a silicon oxide film is formed on the interlayer insulating film 12. Thereafter, a wiring groove 16 having a desired wiring pattern is formed in the insulating film 15 by photolithography, anisotropic etching, or the like. Thereafter, a conductor film mainly composed of, for example, copper (Cu) is formed so as to fill the wiring groove 16. Subsequently, excess copper is removed by a CMP method or the like, thereby forming a conductor wiring 17 that fills the wiring groove 16.

  In the subsequent process, by repeating the processes of FIGS. 7 and 8, the multilayer wiring layer having a desired wiring pattern is formed by repeating the formation of multilayer wiring layers.

  As described above, the n-type MIS transistor Qn storing tensile stress and the p-type MIS transistor Qp storing no significant stress are formed on the same silicon substrate 1. In particular, according to the manufacturing method of the first embodiment, it is possible to selectively store stress in the MIS transistor while avoiding damage due to processing. As a result, the performance of the semiconductor device including the MIS transistor can be further improved.

  In the manufacturing method of the first embodiment described above, the first stress film N1a having a tensile stress is formed in the step of FIG. 5, and the first stress in the pMIS region Rp is formed in the step of FIG. Ion implantation was performed on the film N1a to relax the stress. As a result, no significant tensile stress was stored in the crystallization of the pMIS gate electrode GEp, and only the nMIS gate electrode GEn could be stored. This is an SMT technique that focuses on improving the characteristics of the n-type MIS transistor Qn in the manufacturing method of the first embodiment. This is because the tensile stress is suitable for improving the characteristics of the n-type MIS transistor Qn.

  On the other hand, in another manufacturing method of the first embodiment, it is possible to replace the manufacturing process described above to obtain an SMT technique that improves the characteristics of the p-type MIS transistor Qp. More specifically, the first stress film N1a having a compressive stress is formed in the process of FIG. 5, and the stress is applied by performing ion implantation on the first stress film N1a in the nMIS region Rn in the process of FIG. ease. Thus, in the step of crystallizing the MIS gate electrodes GEn and GEp, no significant compressive stress is stored in the nMIS gate electrode GEn, and the compressive stress can be stored in the pMIS gate electrode GEp. Since the compressive stress is suitable for improving the characteristics of the p-type MIS transistor Qp, the characteristics of the p-type MIS transistor Qp can be improved without affecting the n-type MIS transistor Qn as described above.

(Embodiment 2)
A method for manufacturing the semiconductor device of the second embodiment will be described in detail with reference to FIGS. The manufacturing method of the second embodiment is the same as that of the first embodiment up to the steps described with reference to FIG.

  In the subsequent process, as shown in FIG. 9, a p-type source is formed on the main surface s <b> 1 of the pMIS region Rp of the silicon substrate 1, on the side lower portion of the pMIS gate electrode GEp and on the side lower portion of the sidewall spacer 6. -The drain region sdp is formed. 4 is performed by using the photoresist film 18 formed in the same manner as the photoresist film 8 in FIG. 4 as an ion implantation mask and performing ion implantation 400 similar to the ion implantation 200 in FIG. A p-type source / drain region sdp is formed in the same manner as in the process. At this stage, the p-type MIS transistor Qp having the pMIS gate electrode GEp, the gate insulating film GI, the p-type source / drain region sdp, and the like as basic components is formed in the n-well 3n.

  In the manufacturing method according to the second embodiment, the nMIS gate electrode GEn and the pMIS gate electrode GEp are crystallized by performing heat treatment after the above-described steps. Here, in particular, the heat treatment is performed under conditions that are the minimum necessary conditions for crystallizing both the gate electrodes GEn and GEp and that do not diffuse the previously formed p-type source / drain regions sdp. The reason will be described later in detail. More specifically, for example, the gate electrodes GEn and GEp are crystallized by performing a heat treatment at about 800 to 900 ° C. by a spike annealing method. Details of the reason for crystallizing both gate electrodes GEn and GEp at this stage will be described later.

  Next, as shown in FIG. 10, by performing ion implantation 500 on the nMIS region Rn, the nMIS gate electrode GEn crystallized in the previous step is made amorphous. For this purpose, first, a photoresist film 19 patterned by a photolithography method or the like is formed so as to cover the main surface s1 of the silicon substrate 1 in the pMIS region Rp. Thereafter, ion implantation 500 is performed on nMIS region Rn using photoresist film 19 as an ion implantation mask. The reason why the nMIS gate electrode GEn is made amorphous in this step will be described in detail later.

  In this step, considering only that the nMIS gate electrode GEn crystallized in the step of FIG. 9 is made amorphous, for example, ion species such as Si and Ge are selected regardless of polarity, and ion implantation is performed. 500 may be applied. On the other hand, in the manufacturing method of the second embodiment, in this step, it is more preferable to implant impurity ions serving as donors as the ion implantation 500. This is because the n-type source / drain regions sdn can be formed at the same time that the nMIS gate electrode GEn is made amorphous by implanting donor impurities (for example, arsenic or phosphorus) by the ion implantation 500 in the above-described manner. It is. That is, in this process, the main surface s1 of the nMIS region Rn of the silicon substrate 1 is the side lower part of the nMIS gate electrode GEn and the side lower part of the side wall spacer 6 as described in the process of FIG. An n-type source / drain region sdn similar to the above is formed. As described above, in the manufacturing method of the second embodiment, the ion implantation 500 for making the nMIS gate electrode GEn amorphous is the same as the ion implantation for forming the n-type source / drain region sdn. As a result, the manufacturing process can be further simplified.

  10 is completed, an n-type MIS transistor Qn having an nMIS gate electrode GEn, a gate insulating film GI, an n-type source / drain region sdn, and the like as basic structures is formed in the p-well 3p. It will be done.

  Next, as shown in FIG. 11, the first cap film (first protective film) is formed so as to integrally cover the main surface s1 of the silicon substrate 1, the nMIS gate electrode GEn, and the pMIS gate electrode GEp. C1b is formed. Thereafter, a first stress film N1b having a tensile stress is formed so as to cover the first cap film C1b. The first cap film C1b and the first stress film N1b in the second embodiment are respectively the same as the first cap film C1a and the first stress film N1a formed in the step of FIG. 5 of the first embodiment. Form. The same applies to the effect. In particular, also in the manufacturing method of the second embodiment, the effect of forming the first cap film C1b, the description of the film thickness of the first cap film C1b, the effect thereof, and the like of the first embodiment are described. This is the same as the specifications and effects of the first cap film C1a formed by the manufacturing method, and a duplicate description is omitted here.

  Subsequently, by performing heat treatment, the nMIS gate electrode GEn made amorphous in the process of FIG. 10 is crystallized again. Here, the tensile stress of the first stress film N1b is applied to the nMIS gate electrode GEn. Then, the nMIS gate electrode GEn is crystallized under the action of the tensile stress, whereby the tensile stress is stored in the nMIS gate electrode GEn. That is, the tensile stress similar to that of the first stress film N1b can be stored in the nMIS gate electrode GEn by the heat treatment in this step.

  On the other hand, the pMIS gate electrode GEp has not been subjected to the ion implantation 500 in the process of FIG. That is, the pMIS gate electrode GEp has been crystallized without being subjected to stress by the heat treatment in the step of FIG. 9, and has reached the formation of the first stress film N1b and the heat treatment step in the step of FIG. . At this time, even if the heat treatment is performed on the pMIS gate electrode GEp already crystallized in a state where the stress of the first stress film N1b is applied, the stress of the first stress film N1b is not stored. That is, no significant stress is stored in the pMIS gate electrode GEp even after the heat treatment in this step.

  Further, it is more preferable that the heat treatment of this step is shared with the heat treatment for diffusing or activating both the source / drain regions sdn and sdp formed above. This is because the manufacturing process can be simplified. As described above, in the manufacturing method of the second embodiment, the source / drain regions sdn and sdp are simultaneously diffused or activated by the heat treatment for crystallizing the nMIS gate electrode GEn. For example, the source / drain regions sdn and sdp are diffused or activated by performing heat treatment at about 950 to 1150 ° C. by spike annealing. By the heat treatment under such conditions, the amorphized nMIS gate electrode GEn is crystallized.

  Thereafter, the first stress film N1b and the first cap film C1b are removed in the same manner as in the process described in FIG. 6 of the first embodiment. Even if the first stress film N1b is removed, the tensile stress stored in the nMIS gate electrode GEn is not lost and continues to act on the silicon substrate 1. Therefore, according to the manufacturing method of the second embodiment, the n-type MIS transistor Qn having the nMIS gate electrode GEn storing the tensile stress and the p-type MIS transistor Qp having the pMIS gate electrode GEp having no significant stress. And can be formed.

  In this step, the method and effect of removing the first stress film N1b, the effect of forming the first cap film C1b on the removing process of the first stress film N1b, and the first cap film C1b The effect of the film thickness is the same as that described in the first embodiment.

  Further, as described above, in the manufacturing method of the second embodiment, the ion implantation 500 is selectively performed on the nMIS gate electrode GEn for storing the tensile stress, so that the first stress film N1b is formed. It is made amorphous. Thus, by selectively performing the ion implantation 500, the nMIS gate electrode GEn storing the tensile stress can be selectively formed. Therefore, according to the manufacturing method of the second embodiment, there is no need to perform processing such as selectively removing the stress film in the region where the tensile stress is not stored in the first stress film N1b. Thereby, the tensile stress to the p-type MIS transistor Qp can be relaxed without causing damage due to overetching. As described above, according to the manufacturing method of the second embodiment, in the SMT technique, it is possible to selectively store stress in the MIS transistor while avoiding damage due to processing. As a result, the performance of the semiconductor device including the MIS transistor can be further improved.

  In the subsequent process, the wiring is formed by performing the processes described in FIGS. 7 and 8 as in the first embodiment.

  As described above, the n-type MIS transistor Qn storing tensile stress and the p-type MIS transistor Qp storing no significant stress are formed on the same silicon substrate 1. In particular, according to the manufacturing method of the second embodiment, stress can be selectively stored in the MIS transistor while avoiding damage due to processing. As a result, the performance of the semiconductor device including the MIS transistor can be further improved.

  Further, in the manufacturing method of the second embodiment, when the ion implantation 500 of FIG. 10 is used in combination with an ion implantation process for forming the n-type source / drain region sdn, at least before the ion implantation 500 is performed. It is necessary to crystallize the pMIS gate electrode GEp. Further, it is desirable to perform ion implantation 400 for forming the p-type source / drain region sdp before crystallizing the pMIS gate electrode GEp so that it is not amorphized again. Therefore, for the p-type source / drain region sdp, at least a heat treatment for crystallizing the pMIS gate electrode GEp, a heat treatment for diffusing or activating the n-type source / drain region sdn to be formed later, Two heat treatments are performed.

  Therefore, in the manufacturing method of the second embodiment, as described with reference to FIG. 9, the heat treatment for crystallizing the MIS gate electrodes GEn and GEp diffuses the p-type source / drain regions sdp formed previously. It is more preferable to perform the heat treatment under such a condition that the heat treatment is not performed. This is because, at this stage, heat treatment is performed so that the p-type source / drain region sdp is not diffused, so that the overlapping diffusion in the heat treatment step for diffusing or activating the n-type source / drain region sdn later is performed. This is because it can be prevented. Thereby, the short channel effect due to the diffusion of the p-type source / drain region sdp beyond the desired region can be reduced. As a result, the performance of the semiconductor device including the MIS transistor can be further improved.

  In the manufacturing method of the second embodiment described above, in the step of FIG. 9, only the pMIS region Rp is ion-implanted 400 first, and both MIS gate electrodes GEn and GEp are crystallized by heat treatment. did. Thereafter, in the step of FIG. 10, ion implantation 500 was performed on the nMIS region Rn, and only the nMIS gate electrode GEn was made amorphous. Then, in the process of FIG. 11, the first stress film N1b having tensile stress was formed, and the nMIS gate electrode GEn was crystallized again by heat treatment. As a result, the tensile stress was not stored in the pMIS gate electrode GEp that had already been crystallized, and the tensile stress could be stored only in the nMIS gate electrode GEn. This is an SMT technique that focuses on improving the characteristics of the n-type MIS transistor Qn in the manufacturing method of the second embodiment. This is because the tensile stress is suitable for improving the characteristics of the n-type MIS transistor Qn.

  On the other hand, in another manufacturing method of the second embodiment, the SMT technique for improving the characteristics of the p-type MIS transistor Qp can be obtained by replacing the manufacturing steps described above. More specifically, in the step of FIG. 9, ion implantation 400 is first performed on the nMIS region Rn, and both the MIS gate electrodes GEn and GEp are crystallized by heat treatment. Thereafter, in the step of FIG. 10, ion implantation 500 is performed on the pMIS region Rp to make the pMIS gate electrode GEp amorphous. In the step of FIG. 11, the first stress film N1b having a compressive stress is formed, and the pMIS gate electrode GEp is recrystallized by heat treatment. As a result, the compressive stress can be stored only in the pMIS gate electrode GEp without storing the compressive stress in the nMIS gate electrode GEn that has already been crystallized. Since the compressive stress is suitable for improving the characteristics of the p-type MIS transistor Qp, the characteristics of the p-type MIS transistor Qp can be improved without affecting the n-type MIS transistor Qn as described above.

(Embodiment 3)
A method for manufacturing the semiconductor device of the third embodiment will be described in detail with reference to FIGS. The manufacturing method of the third embodiment is the same as that of the first embodiment up to the steps described with reference to FIG. That is, the n-type source / drain region sdn is formed in the nMIS region Rn, and the basic configuration of the n-type MIS transistor Qn is formed first.

  In the subsequent process, as shown in FIG. 12, the main surface s1 of the silicon substrate 1, the nMIS gate electrode GEn, and the pMIS gate electrode GEp are integrally covered to form a first cap film (first protective film). ) C1c is formed. Thereafter, a first stress film N1c having a tensile stress is formed so as to cover the first cap film C1c. The first cap film C1c and the first stress film N1c of the third embodiment are respectively the same as the first cap film C1a and the first stress film N1a formed in the step of FIG. 5 of the first embodiment. Form. The same applies to the effect. In particular, also in the manufacturing method of the third embodiment, the effects of forming the first cap film C1c, the description about the film thickness of the first cap film C1c, the effects thereof, and the like are also manufactured in the first embodiment. This is the same as the specifications and effects of the first cap film C1a described in the method, and a duplicate description is omitted here.

  Subsequently, heat treatment is performed to crystallize the nMIS gate electrode GEn and the pMIS gate electrode GEp. Here, the tensile stress of the first stress film N1c acts on both the MIS gate electrodes GEn and GEp. Then, the MIS gate electrodes GEn and GEp are crystallized under the action of the tensile stress, whereby the tensile stress is stored in both the gate electrodes GEn and GEp. That is, by the heat treatment in this step, the same tensile stress as that of the first stress film N1c is stored in the nMIS gate electrode GEn and the pMIS gate electrode GEp.

  The heat treatment in this step is the minimum necessary condition for crystallizing both the gate electrodes GEn and GEp as in the heat treatment step of FIG. 9 of the second embodiment, and is formed first. The n-type source / drain region sdn is subjected to heat treatment under conditions that do not diffuse. The reason for this is also the same as the explanation for the heat treatment step of FIG. That is, the heat treatment for activating the n-type source / drain region sdn and the like is necessary again later, and at this time, the n-type source / drain region sdn is prevented from being excessively diffused. This can reduce the short channel effect of the n-type MIS transistor Qn. More specifically, for example, the gate electrodes GEn and GEp are crystallized by performing a heat treatment at about 800 to 900 ° C. by a spike annealing method.

  Thereafter, the first stress film N1c and the first cap film C1c are removed in the same manner as the process described in FIG. 6 of the first embodiment. Even if the first stress film N1c is removed, the tensile stress stored in the nMIS gate electrode GEn and the pMIS gate electrode GEp is not lost and continues to act on the silicon substrate 1.

  In this step, the method and effect of removing the first stress film N1c, the effect of forming the first cap film C1c on the removing process of the first stress film N1c, and the first cap film C1c The effect of the film thickness is the same as that described in the first embodiment.

  Here, the tensile stress stored in the MIS gate electrodes GEn and GEp is a stress that can improve the characteristics for the n-type MIS transistor Qn, but is a stress that can hinder the improvement of the characteristics for the p-type MIS transistor Qp. is there. Therefore, in the manufacturing method of the third embodiment, the stress stored in the pMIS gate electrode GEp is relaxed in the subsequent process. More specific description will be given below.

  In the subsequent process, as shown in FIG. 13, by performing ion implantation 600 on the pMIS region Rp, among the MIS gate electrodes GEn and GEp crystallized in the previous process, the pMIS gate electrode GEp is amorphous. Qualify. For this, first, a photoresist film 20 patterned by photolithography or the like is formed so as to cover the main surface s1 of the silicon substrate 1 in the nMIS region Rn. Thereafter, ion implantation 600 is performed on the pMIS region Rp using the photoresist film 20 as an ion implantation mask. By making the pMIS gate electrode GEp amorphous in this way, the tensile stress stored in the pMIS gate electrode GEp is relaxed. Thereafter, by performing heat treatment, the pMIS gate electrode GEp that has been made amorphous in this step is crystallized again. In this heat treatment step, since crystallization is performed without applying stress due to a stress film or the like, no significant stress is stored in the pMIS gate electrode GEp.

  In this step, considering only that the pMIS gate electrode GEp crystallized in the step of FIG. 12 is made amorphous, for example, ion species such as Si and Ge are selected regardless of polarity, and ion implantation is performed. 600 may be applied. On the other hand, in the manufacturing method of the third embodiment, in this step, it is more preferable to implant impurity ions serving as acceptors as the ion implantation 600. This is because the pMIS source / drain regions sdp can be formed at the same time that the pMIS gate electrode GEp is made amorphous by implanting donor impurities by the ion implantation 600 in the above-described manner. That is, by this process, the main surface s1 of the pMIS region Rp of the silicon substrate 1 is the side lower part of the pMIS gate electrode GEp and the side lower part of the side wall spacer 6 as described in the process of FIG. A p-type source / drain region sdp similar to the above is formed. As described above, in the manufacturing method of the third embodiment, the ion implantation 600 for making the pMIS gate electrode GEp amorphous is the same as the ion implantation for forming the p-type source / drain region sdp. As a result, the manufacturing process can be further simplified.

  In this step, the p-type MIS transistor Qp having the pMIS gate electrode GEp, the gate insulating film GI, the p-type source / drain region sdp, and the like as basic structures is formed in the n-well 3n.

  Further, in the ion implantation 600 of the manufacturing method according to the third embodiment, in addition to the impurity serving as an acceptor as described above, an ion implantation of an impurity containing Si or Ge is performed, whereby the gate electrode GEp for pMIS is made amorphous. It is more preferable to improve the quality. The reason will be described below.

For example, when the pMIS gate electrode GEp is made amorphous by the ion implantation 600 in this step and the p-type source / drain region sdp is formed, boron (B) or difluoride can be used as an acceptor impurity. Boron halide (BF ₂ ) or the like is used. On the other hand, in the ion implantation 500 of the second embodiment (step of FIG. 10) and the like, when the nMIS gate electrode GEn is made amorphous and the n-type source / drain region sdn is formed, for example, Implant donor impurities such as arsenic and phosphorus. Compared with arsenic or the like used in the ion implantation 500 of the second embodiment, boron or the like used in the ion implantation 600 of the third embodiment has a small atomic weight. Therefore, in the ion implantation 600 according to the third embodiment, the pMIS gate electrode GEp can be easily made amorphous by ion implantation of Si, Ge, or the like having a larger atomic weight in addition to the impurity ions serving as acceptors. Thereby, the tensile stress memorize | stored in the gate electrode GEp for pMIS can be relieved more reliably. As a result, the performance of the semiconductor device including the MIS transistor can be further improved.

  Further, the heat treatment for recrystallization of the pMIS gate electrode GEp in the step of FIG. 13 is shared with the heat treatment for diffusion or activation of both the source / drain regions sdn and sdp formed above. Is more preferable. This is because the manufacturing process can be simplified. As described above, in the manufacturing method of the third embodiment, the source / drain regions sdn and sdp are simultaneously diffused or activated by the heat treatment for crystallizing the pMIS gate electrode GEp. For example, the source / drain regions sdn and sdp are diffused or activated by performing heat treatment at about 950 to 1150 ° C. by spike annealing. By the heat treatment under such conditions, the amorphized pMIS gate electrode GEp is crystallized.

  In the subsequent process, the wiring is formed by performing the processes described in FIGS. 7 and 8 as in the first embodiment.

  As described above, the n-type MIS transistor Qn storing tensile stress and the p-type MIS transistor Qp storing no significant stress are formed on the same silicon substrate 1 by the manufacturing method according to the third embodiment. Can be formed.

  In particular, in the manufacturing method of the third embodiment, the stress is relaxed by selectively performing ion implantation 600 on the pMIS gate electrode GEp storing the tensile stress. Thus, by selectively performing the ion implantation 600, the pMIS gate electrode GEp that does not store significant stress can be selectively formed. Therefore, according to the manufacturing method of the third embodiment, there is no need to perform processing such as selectively removing the stress film in the region where the tensile stress is not stored in the first stress film N1c. Thereby, the tensile stress to the p-type MIS transistor Qp can be relaxed without causing damage due to overetching. As described above, according to the manufacturing method of the third embodiment, in the SMT technique, it is possible to selectively store stress in the MIS transistor while avoiding damage due to processing. As a result, the performance of the semiconductor device including the MIS transistor can be further improved.

  In the manufacturing method of the third embodiment described above, the n-type source / drain region sdn of the nMIS region Rn is formed first. Subsequently, a first stress film N1c having a tensile stress was formed in the process of FIG. 12, and the tensile stress was stored by crystallizing both the MIS gate electrodes GEn and GEp by heat treatment. Thereafter, in the step of FIG. 13, ion implantation 600 was performed on the pMIS region Rp to make the pMIS gate electrode GEp amorphous. As a result, the stress of the pMIS gate electrode GEp was relieved, and the tensile stress could be stored only in the nMIS gate electrode GEn. This is an SMT technique that focuses on improving the characteristics of the n-type MIS transistor Qn in the manufacturing method of the third embodiment. This is because the tensile stress is suitable for improving the characteristics of the n-type MIS transistor Qn.

  On the other hand, in another manufacturing method of the third embodiment, the above-described manufacturing process can be replaced with the SMT technique for improving the characteristics of the p-type MIS transistor Qp. More specifically, the p-type source / drain region sdp of the pMIS region Rp is formed first. Subsequently, the first stress film N1c having a compressive stress is formed in the step of FIG. 12, and both the MIS gate electrodes GEn and GEp are crystallized by heat treatment to store the compressive stress. Thereafter, in the step of FIG. 13, ion implantation 600 is applied to the nMIS region Rn to make the nMIS gate electrode GEn amorphous. Thereby, the stress of the nMIS gate electrode GEn can be relieved, and the compressive stress can be stored only in the pMIS gate electrode GEp. Since the compressive stress is suitable for improving the characteristics of the p-type MIS transistor Qp, the characteristics of the p-type MIS transistor Qp can be improved without affecting the n-type MIS transistor Qn as described above.

(Embodiment 4)
A method of manufacturing the semiconductor device according to the fourth embodiment will be described in detail with reference to FIGS. The manufacturing method of the fourth embodiment is the same as that of the first embodiment up to the steps described with reference to FIG.

  In the subsequent process, as shown in FIG. 14, the p-type source is formed on the main surface s <b> 1 of the pMIS region Rp of the silicon substrate 1 at the side lower portion of the pMIS gate electrode GEp and at the side lower portion of the sidewall spacer 6. -The drain region sdp is formed. For this purpose, ion implantation 700 similar to the ion implantation 200 of FIG. 4 is performed using the photoresist film 21 formed in the same manner as the photoresist film 8 of FIG. 4 of the first embodiment as an ion implantation mask. Thus, the p-type source / drain region sdp is formed in the same manner as in the step of FIG. At this stage, the p-type MIS transistor Qp having the pMIS gate electrode GEp, the gate insulating film GI, the p-type source / drain region sdp, and the like as basic components is formed in the n-well 3n.

  Next, as shown in FIG. 15, the first cap film (first protective film) is formed so as to integrally cover the main surface s1 of the silicon substrate 1, the nMIS gate electrode GEn, and the pMIS gate electrode GEp. C1d is formed. The first cap film C1d of the fourth embodiment is formed in the same manner as the first cap film C1a formed in the step of FIG. 5 of the first embodiment. In particular, also in the manufacturing method of the fourth embodiment, the effects of forming the first cap film C1d, the description about the film thickness of the first cap film C1d, the effects thereof, and the like are also manufactured in the first embodiment. This is the same as the specifications and effects of the first cap film C1a described in the method, and a duplicate description is omitted here.

  Thereafter, a first stress film N1d having a compressive stress is formed so as to cover the first cap film C1d. That is, the first stress film N1d is formed so as to integrally cover the main surface s1 of the silicon substrate 1, the nMIS gate electrode GEn, and the pMIS gate electrode GEp via the first cap film C1d. become. The first stress film N1d of the fourth embodiment is the first stress film N1a formed in the process of FIG. 5 of the first embodiment except that the direction of the acting stress is not a tensile stress but a compressive stress. It forms like. In the manufacturing method of the fourth embodiment, as an example, the first stress film N1d is formed so that the magnitude of the compressive stress is about 0.3 to 1.7 GPa.

  Subsequently, heat treatment is performed to crystallize the nMIS gate electrode GEn and the pMIS gate electrode GEp. Here, the compressive stress of the first stress film N1d acts on both the MIS gate electrodes GEn and GEp. Then, the MIS gate electrodes GEn and GEp are crystallized under the action of the compressive stress, whereby the compressive stress is stored in both the gate electrodes GEn and GEp. That is, the same compressive stress as that of the first stress film N1d is stored in the nMIS gate electrode GEn and the pMIS gate electrode GEp by the heat treatment in this step.

  The heat treatment in this step is the minimum necessary condition for crystallizing both the gate electrodes GEn and GEp as in the heat treatment step of FIG. 9 of the second embodiment, and is formed first. The p-type source / drain region sdp is subjected to heat treatment under conditions that do not diffuse. The reason for this is also the same as the explanation for the heat treatment step of FIG. That is, the heat treatment for activating the p-type source / drain region sdp and the like is necessary again later, and at this time, the p-type source / drain region sdp is prevented from being excessively diffused. Thereby, the short channel effect of the p-type MIS transistor Qp can be reduced. More specifically, for example, the gate electrodes GEn and GEp are crystallized by performing a heat treatment at about 800 to 900 ° C. by a spike annealing method.

  Thereafter, the first stress film N1d and the first cap film C1d are removed in the same manner as the process described in FIG. 6 of the first embodiment. Even if the first stress film N1d is removed, the compressive stress stored in the nMIS gate electrode GEn and the pMIS gate electrode GEp is not lost and continues to act on the silicon substrate 1.

  In this step, the method and the effect of removing the first stress film N1d, the effect of forming the first cap film C1d on the removing process of the first stress film N1d, and the first cap film C1d The effect of the film thickness is the same as that described in the first embodiment.

  Next, as shown in FIG. 16, by performing ion implantation 800 on the nMIS region Rn, the nMIS gate electrode GEn crystallized in the previous step is made amorphous. For this, first, a photoresist film 22 patterned by photolithography or the like is formed so as to cover the main surface s1 of the silicon substrate 1 in the pMIS region Rp. Thereafter, ion implantation 800 is performed on nMIS region Rn using photoresist film 22 as an ion implantation mask. In this way, the nMIS gate electrode GEn can be made amorphous to reduce the compressive stress stored in the nMIS gate electrode GEn.

  Further, the ion species implanted in the ion implantation 800 of the fourth embodiment are the same as those of the ion implantation 500 described with reference to FIG. 10 in the manufacturing method of the second embodiment. That is, in the manufacturing method of the fourth embodiment, the n-type source / drain regions sdn are formed simultaneously with the amorphization of the nMIS gate electrode GEn by the ion implantation 800. The effect is the same as that described in the second embodiment.

  When the process of FIG. 16 is completed, an n-type MIS transistor Qn having the nMIS gate electrode GEn, the gate insulating film GI, the n-type source / drain region sdn and the like as basic structures is formed in the p-well 3p. It will be done.

  Next, as shown in FIG. 17, the second cap film (second protective film) is formed so as to integrally cover the main surface s1 of the silicon substrate 1, the nMIS gate electrode GEn, and the pMIS gate electrode GEp. C2 is formed. Thereafter, a second stress film N2 having a tensile stress is formed so as to cover the second cap film C2 and having a stress opposite to that of the first stress film N1d having the compressive stress in the step of FIG. . The second cap film C2 and the second stress film N2 in the fourth embodiment are respectively the same as the first cap film C1a and the first stress film N1a formed in the step of FIG. 5 of the first embodiment. Form. The same applies to the effect. In particular, also in the manufacturing method of the fourth embodiment, the effects of forming the second cap film C2, the description of the film thickness of the second cap film C2, the effects thereof, and the like are also described in the manufacturing of the first embodiment. This is the same as the specifications and effects of the first cap film C1a described in the method, and a duplicate description is omitted here.

  Subsequently, by performing heat treatment, the nMIS gate electrode GEn made amorphous in the step of FIG. 16 is crystallized again. Here, the tensile stress of the second stress film N2 acts on the nMIS gate electrode GEn. Then, the nMIS gate electrode GEn is crystallized under the action of the tensile stress, whereby the tensile stress is stored in the nMIS gate electrode GEn. That is, the tensile stress similar to that of the second stress film N2 can be stored in the nMIS gate electrode GEn by the heat treatment in this step.

  On the other hand, the pMIS gate electrode GEp has not been subjected to the ion implantation 800 in the step of FIG. That is, the pMIS gate electrode GEp is crystallized by storing the action of the compressive stress from the first stress film N1d by the heat treatment of the process of FIG. 15, and the second stress film N2 by the process of FIG. To the formation and heat treatment process. At this time, even if the pMIS gate electrode GEp that has already been crystallized by storing the compressive stress is subjected to a heat treatment in a state where the tensile stress of the second stress film N2 is applied, the tensile stress of the second stress film N2 Stress is not remembered. That is, even if the heat treatment of this step is performed, the compressive stress is stored in the pMIS gate electrode GEp while being stored.

  Further, it is more preferable that the heat treatment of this step is shared with the heat treatment for diffusing or activating both the source / drain regions sdn and sdp formed above. This is because the manufacturing process can be simplified. Thus, in the manufacturing method of the fourth embodiment, the source / drain regions sdn and sdp are simultaneously diffused or activated by the heat treatment for crystallizing the nMIS gate electrode GEn. For example, the source / drain regions sdn and sdp are diffused or activated by performing heat treatment at about 950 to 1150 ° C. by spike annealing. By the heat treatment under such conditions, the amorphized nMIS gate electrode GEn is crystallized.

  Thereafter, the second stress film N2 and the second cap film C2 are removed in the same manner as the process described in the first embodiment with reference to FIG. Even if the second stress film N2 is removed, the tensile stress stored in the nMIS gate electrode GEn is not lost and continues to act on the silicon substrate 1. Therefore, according to the manufacturing method of the fourth embodiment, the n-type MIS transistor Qn having the nMIS gate electrode GEn storing the tensile stress and the pMIS gate electrode GEp storing the compressive stress can be formed.

  In this step, the method and the effect of removing the second stress film N2, the effect of forming the second cap film C2 on the removing process of the second stress film N2, and the second cap film C2 The effect of the film thickness is the same as that described in the first embodiment.

  Furthermore, as described above, in the manufacturing method according to the fourth embodiment, the gate electrode to be subjected to stress is amorphized by ion implantation and crystallized in a state covered with a stress film. The stress similar to that of the stress film is stored. Here, the ion implantation is selectively performed to enable the above-described separation, and for example, there is no need to selectively form stress films having different acting stresses. That is, according to the manufacturing method of the fourth embodiment, it is not necessary to selectively form the first stress film N1d having compressive stress and the second stress film N2 having tensile stress. Therefore, there is no need to perform processing such as selectively removing the first stress film N1d or the second stress film N2 itself. Thereby, the n-type MIS transistor Qn storing tensile stress and the p-type MIS transistor Qp storing compressive stress can be formed without causing damage due to over-etching. As described above, according to the manufacturing method of the fourth embodiment, in the SMT technique, stress can be selectively stored in the MIS transistor while avoiding damage due to processing. As a result, the performance of the semiconductor device including the MIS transistor can be further improved.

  In the subsequent process, the wiring is formed by performing the processes described in FIGS. 7 and 8 as in the first embodiment.

  As described above, the n-type MIS transistor Qn storing tensile stress and the p-type MIS transistor Qp storing compressive stress can be formed on the same silicon substrate 1 by the manufacturing method of the fourth embodiment.

  In the above description of the manufacturing method of the fourth embodiment, the compressive stress storage technique (FIG. 14, FIG. 15, etc.) applied to the p-type MIS transistor Qp is first applied, and the tension applied to the n-type MIS transistor Qn. The example in which the stress storage technique (FIG. 16, FIG. 17, etc.) is applied later has been described. These steps may be interchanged in context. That is, after applying the tensile stress storage technique to the n-type MIS transistor Qn, the compression stress storage technique to the p-type MIS transistor Qp may be applied. Even in such a case, the n-type MIS transistor Qn and the p-type MIS transistor Qp have different directions of stress that can be applied to improve the performance. Forming things.

(Embodiment 5)
In the manufacturing method of the fifth embodiment, a stronger stress is applied by applying a stress film or the like to the MIS transistor storing the stress formed by the manufacturing method of the first to fourth embodiments. An example is shown. This will be described with reference to the cross-sectional views of FIGS. The manufacturing method of the fifth embodiment is a step following the manufacturing method of the fourth embodiment, and will be described as a step following the step described with reference to FIG.

  In the subsequent process, as shown in FIG. 18, a metal silicide layer 23 is formed on the surface of the n-type source / drain region sdn, the p-type source / drain electrode sdp, the nMIS gate electrode GEn, and the pMIS gate electrode GEp. To do. The metal silicide layer 23 of the fifth embodiment is formed in the same manner as the metal silicide layer 10 described with reference to FIG. 7 of the first embodiment.

  Here, in the manufacturing method of the first embodiment, as described with reference to FIGS. 7 and 8, the resistivity of the MIS transistors Qn and Qp formed on the main surface of the silicon substrate 1 is reduced. A contact plug 14 for electrical connection from the outside is formed through a low metal silicide layer or the like. The contact plugs 14 were formed in the interlayer insulating film 12 to insulate each other. Therefore, it is necessary to form a contact hole 13 in the interlayer insulating film 12. As shown in FIG. 7, it is desirable to form the contact hole 13 in the interlayer insulating film 12 in a self-aligned manner by the SAC method, and the etching stopper 11 for that purpose is formed. Also in the manufacturing method of the fifth embodiment, wiring is formed in the same manner as in the first embodiment except for the following points.

  Therefore, in the subsequent process, the third stress film N3 is formed so as to integrally cover the main surface s1 of the silicon substrate 1, the nMIS gate electrode GEn, and the pMIS gate electrode GEp. Next, as shown in FIG. 19, an interlayer insulating film 24 is formed so as to cover the third stress film N3.

  Here, the interlayer insulating film 24 is formed by a CVD method or the like as an insulating film mainly composed of silicon oxide, similarly to the interlayer insulating film 12 of the first embodiment. The third stress film N3 is an insulating film formed for the same purpose as the etching stopper 11 of the first embodiment. That is, one of the purposes for forming the third stress film N3 is a function as an etching stop layer when a contact hole (connection hole) CH is formed in the interlayer insulating film 24 later. Therefore, the third stress film N3 is desirably an insulating film in which the etching rate in anisotropic etching applied to the interlayer insulating film 24 and the third stress film N3 is different from the etching rate of the interlayer insulating film 24. This is because the contact hole CH can be easily formed by the SAC method by utilizing the difference in etching rate with respect to the same anisotropic etching.

  In the fifth embodiment, an insulating film mainly composed of silicon nitride is formed by the CVD method or the like as the third stress film N3 having the function as the etching stop layer with respect to the interlayer insulating film 24 made of silicon oxide. .

  Thereafter, anisotropic etching is performed on the interlayer insulating film 24 and the third stress film N3 (corresponding to the etching stopper 11 in FIG. 7) by the same method as in FIG. 7 in the first embodiment. The contact hole (connection hole) CH reaching the n-type source / drain region sdn, the p-type source / drain region sdp, the nMIS gate electrode GEn, and the pMIS gate electrode GEp is formed. Subsequently, the contact plug 25 is formed by burying the contact hole CH with, for example, a conductor film mainly made of tungsten by the same method as in FIG. 7 of the first embodiment.

  Here, in the manufacturing method of the fifth embodiment, an insulating film that applies a tensile stress to the silicon substrate 1 is formed as the third stress film N3. That is, the third stress film N3 of the fifth embodiment is a silicon nitride film that exerts a tensile stress. Such a silicon nitride film is formed by, for example, the same method as the first stress film N1a described with reference to FIG. 5 of the first embodiment.

  As described above, in the third stress film N3, not only a function as an etching stop layer but also a function as a stress film is provided, whereby stress can be applied to the MIS transistor more efficiently. That is, by forming the third stress film N3 having a tensile stress so as to cover at least the n-type MIS transistor Qn, the n-type MIS transistor Qn has a tensile stress stored in the nMIS gate electrode GEn by the SMT technique. In addition, the tensile stress by the third stress film N3 is applied.

  Thereby, according to the manufacturing method of the fifth embodiment, a large tensile stress is applied to n-type MIS transistor Qn, and the characteristics of n-type MIS transistor Qn can be further improved. Also, in the SMT technique for both the MIS gate electrodes GEn and GEp, as in the effects of the first to fourth embodiments, it is possible to effectively operate while avoiding damage due to processing. As a result, the performance of the semiconductor device including the MIS transistor can be further improved.

  On the other hand, in the p-type MIS transistor Qp, the tensile stress can hinder the improvement of characteristics. On the other hand, for example, in the p-type MIS transistor Qp formed by the manufacturing method of the fourth embodiment, compressive stress is stored in the pMIS gate electrode GEp. Therefore, in the manufacturing method of the fifth embodiment, the third stress film N3 is adjusted by adjusting the magnitude of the compressive stress stored in the pMIS gate electrode GEp and the magnitude of the tensile stress applied by the third stress film N3. It is possible to relieve the tensile stress applied from

  Further, in the manufacturing method of the fifth embodiment, a technique for selectively relaxing the tensile stress of the third stress film N3, such as relaxing the tensile stress of the third stress film N3 in the pMIS region Rp, is more effective. . The specific method will be described in detail below as another manufacturing method of the fifth embodiment.

  20 is a cross-sectional view showing a step that follows the step shown in FIG. In another manufacturing method of the fifth embodiment, after the third stress film N3 having a tensile stress is formed and before the interlayer insulating film 24 is formed, ion implantation is performed on the third stress film N3 in the pMIS region Rp. By applying 900, the tensile stress in the pMIS region Rp is relaxed.

  For this, first, a photoresist film 26 patterned by a photolithography method or the like is formed so as to cover the third stress film N3 in the nMIS region Rn. Thereafter, ion implantation 900 is performed on the third stress film N3 in the pMIS region Rp using the photoresist film 26 as an ion implantation mask. In this way, the tensile stress of the third stress film N3 in the pMIS region Rp can be relaxed. For example, ions containing silicon (Si) or germanium (Ge) are used as ions implanted to relieve stress.

  As described above, by reducing the tensile stress of the third stress film N3 in the pMIS region Rp, the p-type MIS transistor Qp is not subjected to the tensile stress of the third stress film N3, and is applied to the pMIS by the SMT technology. Only the compressive stress stored in the gate electrode GEp can be applied.

  Thereby, according to another manufacturing method of the fifth embodiment, the characteristics of the n-type MIS transistor Qn can be further improved without hindering the improvement of the characteristics of the p-type MIS transistor Qp. Also, in the SMT technique for both the MIS gate electrodes GEn and GEp, as in the effects of the first to fourth embodiments, it is possible to effectively operate while avoiding damage due to processing. As a result, the performance of the semiconductor device including the MIS transistor can be further improved.

  In the manufacturing method of the fifth embodiment, the third stress film N3 having tensile stress is formed in the nMIS region Rn where the n-type MIS transistor Qn is formed, and in the pMIS region Rp where the p-type MIS transistor Qp is formed. A technique for forming another stress film having a compressive stress is more effective. The specific method will be described in detail below as still another manufacturing method of the fifth embodiment.

  FIG. 21 is a cross-sectional view showing a step that follows the step shown in FIG. In still another manufacturing method according to the fifth embodiment, after forming the third stress film N3 having tensile stress, the process further includes the following steps before forming the interlayer insulating film 24. First, the third stress film N3 in the pMIS region Rp is removed. For this, first, a photoresist film 27 patterned by a photolithography method or the like is formed so as to cover the third stress film N3 in the nMIS region Rn. Thereafter, the third stress film N3 in the pMIS region Rp is removed by performing, for example, anisotropic etching using the photoresist film 27 as an etching mask. Thereafter, the photoresist film 27 is removed.

  Next, as shown in FIG. 22, in the pMIS region Rp, the fourth stress film N4 is formed so as to integrally cover the main surface s1 of the silicon substrate 1 and the pMIS gate electrode GEp. For this, first, a fourth stress film N4 is formed on the entire main surface s1 of the silicon substrate 1. Thereafter, a portion of the fourth stress film N4 that covers the nMIS region Rn is selectively removed by a photolithography method, an anisotropic etching method, or the like.

  In still another manufacturing method of the fifth embodiment, as the fourth stress film N4, for example, an insulating film mainly composed of silicon nitride is formed. The fourth stress film N4 made of the silicon nitride film is etched when the contact hole CH is formed in the interlayer insulating film 24 made of the silicon oxide film, like the third stress film N3 described with reference to FIG. Functions as a stop layer.

  Further, in still another manufacturing method of the fifth embodiment, as the fourth stress film N4, an insulating film mainly composed of silicon nitride that acts on the silicon substrate 1 so as to exert a compressive stress is formed. The fourth stress film N4, which is an insulating film mainly composed of silicon nitride having compressive stress, is formed, for example, in the same manner as the first stress film N1d described with reference to FIG.

  As described above, by forming the fourth stress film N4 having a compressive stress on the silicon substrate 1 in the pMIS region Rp, a larger compressive stress can be applied to the p-type MIS transistor Qp. That is, in addition to storing the compressive stress for the pMIS gate electrode GEp, the fourth stress film N4 that acts on the compressive stress is formed.

  Thereby, according to still another manufacturing method of the fifth embodiment, the stress stored in the gate electrode by the SMT technique and the stress by the stress film are effective for improving the characteristics of the bipolar MIS transistors Qn and Qp. Can be made to work. Also, in the SMT technique for both the MIS gate electrodes GEn and GEp, as in the effects of the first to fourth embodiments, it is possible to effectively operate while avoiding damage due to processing. As a result, the performance of the semiconductor device including the MIS transistor can be further improved.

  In the above description, in the manufacturing method of the fifth embodiment, an example in which an insulating film that applies tensile stress to the silicon substrate 1 is formed as the third stress film N3 has been described. Not as long. For example, in the process of FIG. 18, if an insulating film that acts on the silicon substrate 1 is formed as the third stress film N3, a larger compressive stress can be applied to the p-type MIS transistor Qp. it can.

  Further, when the third stress film N3 that acts on the compressive stress is formed in the process of FIG. 18, the ion stress 900 is applied to the nMIS region Rn in the process of FIG. 20 to reduce the compressive stress of the third stress film N3. Alleviate it. Thus, only the tensile stress stored in the nMIS gate electrode GEn by the SMT technique can be applied to the n-type MIS transistor Qn.

  Further, when the third stress film N3 that acts on the compressive stress is formed in the process of FIG. 18, the third stress film N3 that acts on the compressive stress is left in the pMIS region Rp in the process of FIG. The fourth stress film N4 that exerts tensile stress may be formed in the nMIS region Rn by removing. Thereby, stress can be applied so as to be effective for improving the characteristics of the bipolar MIS transistors Qn and Qp.

  In the above description, the manufacturing method according to the fifth embodiment has been described as a process following the manufacturing method according to the fourth embodiment. Is obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied, for example, to the industrial field of semiconductor devices necessary for performing information processing in personal computers, mobile devices, and the like.

It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; (A) is principal part sectional drawing in the manufacturing process of the semiconductor device following FIG. 5, (b) is principal part sectional drawing in the manufacturing process of the semiconductor device following (a). 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 8 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 7; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device according to Embodiment 2 of the present invention during the manufacturing process, following the manufacturing process shown in FIG. 2; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device according to Embodiment 3 of the present invention during the manufacturing process, following the manufacturing process shown in FIG. 3; FIG. 13 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 12; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device according to Embodiment 4 of the present invention during the manufacturing process, following the manufacturing process shown in FIG. 2; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 18 is an essential part cross-sectional view of the semiconductor device according to Embodiment 5 of the present invention during the manufacturing step, following the manufacturing step in FIG. 17; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 19 is a main-portion cross-sectional view of the other semiconductor device in the manufacturing process according to the fifth embodiment of the present invention, which is subsequent to FIG. 18; FIG. 19 is an essential part cross-sectional view during a manufacturing step of still another semiconductor device according to the fifth embodiment of the present invention, which is subsequent to FIG. 18; FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21;

Explanation of symbols

1 Silicon substrate (semiconductor substrate)
2 Separation part 3n n well 3p p well 4n n-type extension region 4p p-type extension region 5n n-type halo region 5p p-type halo region 6 sidewall spacers 7-9, 18-22, 26, 27 photoresist films 10, 23 Metal silicide layer 11 Etching stopper 12, 24 Interlayer insulating film 13 Contact hole 14, 25 Contact plug 15 Insulating film 16 Wiring groove 17 Conductor wiring C1a, C1b, C1c, C1d First cap film (first protective film)
C2 Second cap film (second protective film)
CH Contact hole (connection hole)
Gate electrode for GEn nMIS (first gate electrode)
GEp pMIS gate electrode (second gate electrode)
GI gate insulating film N1a, N1b, N1c, N1d first stress film N2 second stress film N3 third stress film N4 fourth stress film Rn nMIS region (first region)
Rp pMIS region (second region)
s1 main surface sdn n-type source / drain region (first conductivity type source / drain region)
sdp p-type source / drain region (second conductivity type source / drain region)
Qn n-type MIS transistor (first field effect transistor)
Qp p-type MIS transistor (second field effect transistor)

Claims (32)

A semiconductor having a first field effect transistor of a first conductivity type in a first region on a semiconductor substrate and a second field effect transistor of a second conductivity type opposite to the first conductivity type in a second region. A device manufacturing method comprising:
(A) forming a first gate electrode on the main surface of the first region of the semiconductor substrate;
(B) forming a second gate electrode on the main surface of the second region of the semiconductor substrate;
(C) forming a first conductivity type source / drain region at a lower side of the first gate electrode in a main surface of the first region of the semiconductor substrate;
(D) forming a second conductivity type source / drain region in a lower side portion of the second gate electrode in a main surface of the second region of the semiconductor substrate;
(E) A first stress film that applies compressive stress or tensile stress to the semiconductor substrate so as to integrally cover the main surface of the semiconductor substrate and the first and second gate electrodes. Forming, and
(F) relieving the stress of the first stress film in the second region by performing ion implantation on the first stress film in the second region;
(G) a step of crystallizing the first and second gate electrodes by performing a heat treatment;
(H) removing the first stress film;
A method of manufacturing a semiconductor device, wherein the same stress as that of the first stress film is stored in the first gate electrode by the heat treatment in the step (g). In the manufacturing method of the semiconductor device according to claim 1,
The first conductivity type is an n-type conductivity type, the second conductivity type is a p-type conductivity type,
In the step (e), the first stress film that applies a tensile stress to the semiconductor substrate is formed. The method of manufacturing a semiconductor device according to claim 2.
At the same time that the first and second gate electrodes are crystallized by the heat treatment in the step (g), the first conductivity type source / drain regions formed in the step (c), and the step (d) A method of manufacturing a semiconductor device, comprising diffusing or activating the formed second conductivity type source / drain region. In the manufacturing method of the semiconductor device according to claim 3,
After performing the step (d) and before performing the step (e),
(I) forming a first protective film so as to integrally cover the main surface of the semiconductor substrate and the first and second gate electrodes;
In the step (e), the first stress film is formed so as to cover the first protective film,
In the step (h), the first stress film is removed by subjecting the first stress film to isotropic etching entirely.
In the step (i), the first protective film is formed such that the etching rate in the isotropic etching in the step (h) is slower than the first stress film formed in the step (e). A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 4,
In the step (i), the first protective film is formed so as to have a film thickness of 5 to 10 nm. A semiconductor having a first field effect transistor of a first conductivity type in a first region on a semiconductor substrate and a second field effect transistor of a second conductivity type opposite to the first conductivity type in a second region. A device manufacturing method comprising:
(A) forming a first gate electrode on the main surface of the first region of the semiconductor substrate;
(B) forming a second gate electrode on the main surface of the second region of the semiconductor substrate;
(C) forming a second conductivity type source / drain region at a lower side of the second gate electrode in a main surface of the second region of the semiconductor substrate;
(D) crystallizing the first and second gate electrodes by performing heat treatment;
(E) a step of making the first gate electrode crystallized in the step (d) amorphous by ion-implanting the first region;
(F) A first stress film that applies compressive stress or tensile stress to the semiconductor substrate so as to integrally cover the main surface of the semiconductor substrate and the first and second gate electrodes. Forming, and
(G) recrystallizing the first gate electrode made amorphous in the step (e) by performing heat treatment;
(H) removing the first stress film;
A method of manufacturing a semiconductor device, wherein the same stress as that of the first stress film is stored in the first gate electrode by the heat treatment in the step (g). The method of manufacturing a semiconductor device according to claim 6.
The first conductivity type is an n-type conductivity type, the second conductivity type is a p-type conductivity type,
In the step (f), the first stress film that applies a tensile stress to the semiconductor substrate is formed. The method of manufacturing a semiconductor device according to claim 7.
In the step (e), the first gate electrode is made amorphous by performing ion implantation of impurities of the first conductivity type, and at the same time, the first surface of the main surface of the first region of the semiconductor substrate. 1. A method of manufacturing a semiconductor device, comprising: forming a first conductivity type source / drain region at a lateral lower portion of one gate electrode. The method of manufacturing a semiconductor device according to claim 8.
The first gate electrode is crystallized by the heat treatment in the step (g), and at the same time, the second conductivity type source / drain region formed in the step (c) and the step formed in the step (e). A method of manufacturing a semiconductor device, comprising diffusing or activating a first conductivity type source / drain region. In the manufacturing method of the semiconductor device according to claim 9,
The method for manufacturing a semiconductor device, wherein the heat treatment in the step (d) is performed at a lower temperature than the heat treatment in the step (g). The method of manufacturing a semiconductor device according to claim 10.
After performing the step (e) and before performing the step (f),
(I) forming a first protective film so as to integrally cover the main surface of the semiconductor substrate and the first and second gate electrodes;
In the step (f), the first stress film is formed so as to cover the first protective film,
In the step (h), the first stress film is removed by subjecting the first stress film to isotropic etching entirely.
In the step (i), the first protective film is formed such that the etching rate in the isotropic etching in the step (h) is slower than the first stress film formed in the step (f). A method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 11.
In the step (i), the first protective film is formed so as to have a film thickness of 5 to 10 nm. A semiconductor having a first field effect transistor of a first conductivity type in a first region on a semiconductor substrate and a second field effect transistor of a second conductivity type opposite to the first conductivity type in a second region. A device manufacturing method comprising:
(A) forming a first gate electrode on the main surface of the first region of the semiconductor substrate;
(B) forming a second gate electrode on the main surface of the second region of the semiconductor substrate;
(C) forming a first conductivity type source / drain region at a lower side of the first gate electrode in a main surface of the first region of the semiconductor substrate;
(D) A first stress film that applies compressive stress or tensile stress to the semiconductor substrate so as to integrally cover the main surface of the semiconductor substrate and the first and second gate electrodes. Forming, and
(E) performing a heat treatment to crystallize the first and second gate electrodes;
(F) removing the first stress film;
(G) making the second gate electrode crystallized in the step (e) amorphous by ion-implanting the second region;
(H) re-crystallizing the second gate electrode made amorphous in the step (g) by performing heat treatment,
By the heat treatment in the step (e), the same stress as that of the first stress film is stored in the first and second gate electrodes,
A method of manufacturing a semiconductor device, wherein stress similar to that of the first stress film stored in the second gate electrode is relaxed by ion implantation in the step (g). 14. The method of manufacturing a semiconductor device according to claim 13,
The first conductivity type is an n-type conductivity type, the second conductivity type is a p-type conductivity type,
In the step (d), the first stress film that forms a tensile stress on the semiconductor substrate is formed. 15. The method of manufacturing a semiconductor device according to claim 14,
In the step (g), the second gate electrode is made amorphous by performing ion implantation of an impurity having a second conductivity type, and at the same time, the first of the main surfaces of the second region of the semiconductor substrate. 2. A method of manufacturing a semiconductor device, comprising: forming a second conductivity type source / drain region at a lateral lower portion of a two-gate electrode. In the manufacturing method of the semiconductor device according to claim 15,
At the same time that the second gate electrode is crystallized by the heat treatment in the step (h), the first conductivity type source / drain regions formed in the step (c) and the step formed in the step (g) A method of manufacturing a semiconductor device, comprising diffusing or activating a second conductivity type source / drain region. In the manufacturing method of the semiconductor device according to claim 16,
The method of manufacturing a semiconductor device, wherein the heat treatment in the step (e) is performed at a lower temperature than the heat treatment in the step (h). The method of manufacturing a semiconductor device according to claim 17.
In the ion implantation in the step (g), the second gate electrode is made amorphous by performing ion implantation of an impurity containing Si or Ge in addition to the impurity of the second conductivity type. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 18.
After performing the step (c) and before performing the step (d),
(I) forming a first protective film so as to integrally cover the main surface of the semiconductor substrate and the first and second gate electrodes;
In the step (d), the first stress film is formed so as to cover the first protective film,
In the step (f), the first stress film is removed by subjecting the first stress film to isotropic etching entirely.
In the step (i), the first protective film is formed such that the etching rate in the isotropic etching in the step (f) is slower than the first stress film formed in the step (d). A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 19,
In the step (i), the first protective film is formed so as to have a film thickness of 5 to 10 nm. A semiconductor having a first field effect transistor of a first conductivity type in a first region on a semiconductor substrate and a second field effect transistor of a second conductivity type opposite to the first conductivity type in a second region. A device manufacturing method comprising:
(A) forming a first gate electrode on the main surface of the first region of the semiconductor substrate;
(B) forming a second gate electrode on the main surface of the second region of the semiconductor substrate;
(C) forming a second conductivity type source / drain region at a lower side of the second gate electrode in a main surface of the second region of the semiconductor substrate;
(D) A first stress film that applies compressive stress or tensile stress to the semiconductor substrate so as to integrally cover the main surface of the semiconductor substrate and the first and second gate electrodes. Forming, and
(E) performing a heat treatment to crystallize the first and second gate electrodes;
(F) removing the first stress film;
(G) a step of making the first gate electrode crystallized in the step (e) amorphous by ion-implanting the first region;
(H) A second stress film that applies compressive stress or tensile stress to the semiconductor substrate so as to integrally cover the main surface of the semiconductor substrate and the first and second gate electrodes. Forming, and
(I) recrystallizing the first gate electrode made amorphous in the step (g) by performing heat treatment;
(J) removing the second stress film,
By the heat treatment in the step (e), the same stress as that of the first stress film is stored in the first and second gate electrodes,
By the ion implantation in the step (g), the same stress as that of the first stress film stored in the first gate electrode is relieved,
By the heat treatment in the step (i), the same stress as that of the second stress film is stored in the first gate electrode,
The first stress film formed in the step (d) and the second stress film formed in the step (h) are stress films that exert reverse stress on the semiconductor substrate. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 21,
The first conductivity type is an n-type conductivity type, the second conductivity type is a p-type conductivity type,
In the step (d), the first stress film is formed so as to act a compressive stress on the semiconductor substrate,
In the step (h), the second stress film that applies a tensile stress to the semiconductor substrate is formed,
By the steps (d) to (j),
The first gate electrode stores the same tensile stress as that of the second stress film,
A method of manufacturing a semiconductor device, wherein the second gate electrode stores a compressive stress similar to that of the first stress film. The method of manufacturing a semiconductor device according to claim 22,
In the step (g), the first gate electrode is made amorphous by performing ion implantation of impurities of the first conductivity type, and at the same time, the first surface of the main surface of the first region of the semiconductor substrate. 1. A method of manufacturing a semiconductor device, comprising: forming a first conductivity type source / drain region at a lateral lower portion of one gate electrode. 24. The method of manufacturing a semiconductor device according to claim 23.
The first gate electrode is crystallized by the heat treatment in the step (i), and at the same time, the second conductivity type source / drain region formed in the step (c) and the step formed in the step (g). A method of manufacturing a semiconductor device, comprising diffusing or activating a first conductivity type source / drain region. The method of manufacturing a semiconductor device according to claim 24,
The method for manufacturing a semiconductor device, wherein the heat treatment in the step (e) is performed at a lower temperature than the heat treatment in the step (i). The method of manufacturing a semiconductor device according to claim 25,
After performing the step (c) and before performing the step (d),
(K) forming a first protective film so as to integrally cover the main surface of the semiconductor substrate and the first and second gate electrodes;
In the step (d), the first stress film is formed so as to cover the first protective film,
In the step (f), the first stress film is removed by subjecting the first stress film to isotropic etching entirely.
In the step (k), the first protective film is formed such that the etching rate in the isotropic etching in the step (f) is slower than the first stress film formed in the step (d). A method of manufacturing a semiconductor device. 27. A method of manufacturing a semiconductor device according to claim 26.
In the step (k), the first protective film is formed so as to have a film thickness of 5 to 10 nm. 28. The method of manufacturing a semiconductor device according to claim 27.
After performing the step (g) and before performing the step (h),
(L) forming a second protective film so as to integrally cover the main surface of the semiconductor substrate and the first and second gate electrodes;
In the step (h), the second stress film is formed so as to cover the second protective film,
In the step (j), the second stress film is removed by subjecting the second stress film to isotropic etching entirely.
In the step (l), the second protective film is formed such that the etching rate in the isotropic etching in the step (j) is slower than the second stress film formed in the step (h). A method of manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 28, wherein:
In the step (l), the second protective film is formed so as to have a film thickness of 5 to 10 nm. 30. The method of manufacturing a semiconductor device according to claim 29, further comprising:
(M) forming a third stress film so as to integrally cover the main surface of the semiconductor substrate and the first and second gate electrodes;
(N) forming an interlayer insulating film so as to cover the third stress film;
(O) By performing anisotropic etching on the interlayer insulating film and the third stress film, the first conductivity type source / drain region, the second conductivity type source / drain region, and the first gate electrode And forming a connection hole reaching the second gate electrode;
(P) burying the connection hole with a conductor film,
In the step (m), the etching rate in the anisotropic etching in the step (o) is an insulating film different from the etching rate of the interlayer insulating film formed in the step (n), and the semiconductor A method of manufacturing a semiconductor device, wherein the third stress film is formed of an insulating film that exerts a tensile stress on a substrate. The method of manufacturing a semiconductor device according to claim 30,
After performing the step (m) and before performing the step (n),
(Q) A step of relaxing the tensile stress of the third stress film in the second region by performing ion implantation on the third stress film in the second region. Production method. The method of manufacturing a semiconductor device according to claim 31,
After performing the step (m) and before performing the step (n),
(R) removing the third stress film in the second region;
(S) forming a fourth stress film so as to integrally cover the main surface of the semiconductor substrate and the second gate electrode in the second region;
In the step (s), the etching rate in the anisotropic etching in the step (o) is an insulating film different from the etching rate of the interlayer insulating film formed in the step (n), and the semiconductor A method of manufacturing a semiconductor device, wherein the fourth stress film is formed of an insulating film that exerts a compressive stress on a substrate.

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