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JP2009277873A - Wiring substrate, and semiconductor device and manufacturing method thereof - Google Patents

Wiring substrate, and semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP2009277873A
JP2009277873A JP2008127425A JP2008127425A JP2009277873A JP 2009277873 A JP2009277873 A JP 2009277873A JP 2008127425 A JP2008127425 A JP 2008127425A JP 2008127425 A JP2008127425 A JP 2008127425A JP 2009277873 A JP2009277873 A JP 2009277873A
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Prior art keywords
wiring
semiconductor chip
wiring board
electrode
protruding electrode
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Japanese (ja)
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Yoshifumi Nakamura
嘉文 中村
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Panasonic Corp
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Panasonic Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

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  • Wire Bonding (AREA)

Abstract

【課題】配線基板と半導体チップとの実装方向に制約がなく、半導体チップの電極パッドと突起電極との安定した接合を可能にする配線基板を提供する。
【解決手段】絶縁性基材と、絶縁性基材上に設けられ、半導体チップが実装される実装領域1に整列して配置されたインナーリード部を形成する複数本の導体配線2a、2bと、導体配線の各々のインナーリード部に形成された突起電極3a、3bとを備える。導体配線は、実装領域の互いに直交するX辺及びY辺にそれぞれ直交するように配置されている。X辺側及びY辺側の導体配線に設けられた突起電極はともに、導体配線上に位置する部分のX辺方向における寸法よりもY辺方向における寸法の方が長い。
【選択図】図1
There is provided a wiring substrate that enables stable bonding between an electrode pad of a semiconductor chip and a protruding electrode without restriction in the mounting direction of the wiring substrate and the semiconductor chip.
An insulating base material, and a plurality of conductor wirings 2a and 2b provided on the insulating base material and forming inner lead portions arranged in alignment with a mounting region 1 on which a semiconductor chip is mounted, and And the protruding electrodes 3a and 3b formed on the inner lead portions of the conductor wiring. The conductor wiring is arranged so as to be orthogonal to the X side and the Y side orthogonal to each other in the mounting region. Both the protruding electrodes provided on the conductor wiring on the X side and the Y side have a dimension in the Y side direction that is longer than the dimension in the X side direction of the portion located on the conductor wiring.
[Selection] Figure 1

Description

本発明は、チップオンフィルム(COF)に用いられるテープキャリア基板のような、絶縁性基材上に導体配線を設けて構成された配線基板、特に導体配線上に形成された突起電極の構造、及びそれを用いた半導体装置とその製造方法に関する。   The present invention is a wiring substrate configured by providing a conductor wiring on an insulating base material, such as a tape carrier substrate used for chip-on-film (COF), particularly a structure of a protruding electrode formed on the conductor wiring, The present invention also relates to a semiconductor device using the same and a manufacturing method thereof.

配線基板の代表的なものにテープ配線基板があり、それを使用したパッケージモジュールの一種として、COFが知られている。COFは、柔軟な絶縁性のテープ配線基板の上に半導体チップが実装され、樹脂で封止することにより実装部が保護された構造を有する。COFにおける半導体チップは、実装領域に形成されたインナーリードと呼ばれるテープ配線線上の導体配線と接合されている。   A representative wiring board is a tape wiring board, and COF is known as a kind of package module using the tape wiring board. The COF has a structure in which a semiconductor chip is mounted on a flexible insulating tape wiring substrate and the mounting portion is protected by sealing with a resin. The semiconductor chip in the COF is bonded to a conductor wiring on a tape wiring line called an inner lead formed in the mounting area.

テープ配線基板は、主たる要素として、絶縁性のフィルム基材とその面上に形成された多数本の導体配線を含む。フィルム基材としては一般的にポリイミドが、導体配線としては銅が使用される。必要に応じて導体配線上には、金属めっき被膜および絶縁樹脂であるソルダーレジストの層が形成される。   The tape wiring board includes, as main elements, an insulating film base material and a large number of conductor wirings formed on the surface thereof. Generally, polyimide is used as the film substrate, and copper is used as the conductor wiring. If necessary, a metal plating film and a solder resist layer which is an insulating resin are formed on the conductor wiring.

テープ配線基板上の導体配線と半導体チップ上の電極パッドとは、突起電極を介して接続されている。この突起電極は、予めテープ配線基板上の導体配線に対して形成しておく方法と、半導体チップ上の電極パッドに対して形成しておく方法のいずれかにより設けられる。   The conductor wiring on the tape wiring substrate and the electrode pad on the semiconductor chip are connected via a protruding electrode. This protruding electrode is provided by either a method of forming in advance with respect to the conductor wiring on the tape wiring substrate or a method of forming with respect to the electrode pad on the semiconductor chip.

テープ配線基板上の導体配線に対して突起電極を形成するための方法の一例が、特許文献1に記載されている。特許文献1に記載されたテープ配線基板について、図5を参照して説明する。図5は、テープ配線基板における半導体チップ実装部の平面図である。   An example of a method for forming a protruding electrode for a conductor wiring on a tape wiring substrate is described in Patent Document 1. The tape wiring board described in Patent Document 1 will be described with reference to FIG. FIG. 5 is a plan view of a semiconductor chip mounting portion in the tape wiring substrate.

1は半導体チップの実装部であり、複数本の導体配線2が絶縁性基材(図示せず)上に整列して設けられている。導体配線2における実装部1内に位置する部分はインナーリード部を形成し、各導体配線2のインナーリード部には、突起電極3c、3dが形成されている。突起電極3c、3dは、導体配線2の長手方向を横切って導体配線2の両側の絶縁性基材に亘り形成され、突起電極3c、3dの導体配線2の幅方向の断面形状は、中央部が両側よりも高くなっている。接合部14a、14bはそれぞれ、導体配線2に対して突起電極3c、3dが接合されている部位を示す。   Reference numeral 1 denotes a semiconductor chip mounting portion, in which a plurality of conductor wirings 2 are arranged in alignment on an insulating base material (not shown). The portion of the conductor wiring 2 located in the mounting portion 1 forms an inner lead portion, and the projecting electrodes 3 c and 3 d are formed on the inner lead portion of each conductor wiring 2. The protruding electrodes 3c and 3d are formed across the insulating base on both sides of the conductor wiring 2 across the longitudinal direction of the conductor wiring 2, and the cross-sectional shape in the width direction of the conductor wiring 2 of the protruding electrodes 3c and 3d is the center portion. Is higher than both sides. The joint portions 14 a and 14 b indicate portions where the protruding electrodes 3 c and 3 d are joined to the conductor wiring 2, respectively.

このテープ配線基板によると、導体配線2上に形成された突起電極3c、3dは、横方向に加わる力に対して実用的に十分な接続の安定性が得られる。また、突起電極3c、3dの形状が、半導体チップの電極パッドとの接続に好適である。
特許第3565835号
According to this tape wiring board, the protruding electrodes 3c and 3d formed on the conductor wiring 2 can obtain practically sufficient connection stability with respect to the force applied in the lateral direction. Further, the shape of the protruding electrodes 3c and 3d is suitable for connection to the electrode pad of the semiconductor chip.
Japanese Patent No. 3565835

上記構成のテープ配線基板においては、導体配線2の突起電極3c、3dと半導体チップの電極パッド(図示せず)の接合に超音波方式が用いられる。ここで、突起電極3cが配置された側の実装部1の辺をX辺、突起電極3dが配置された側の実装部1の辺をY辺とする。超音波方式により接合する際に、超音波の振幅には方向性がある。そのため、半導体チップのX辺側とY辺側の接合部の導体配線2の引き出し方向と超音波の振幅方向が異なることになる。すなわち、X辺側では導体配線2の長手方向に超音波が印加され、Y辺側では幅方向に超音波が印加されるような状態が発生し、突起電極3c、3dを介して接合した場合、導体配線2へかかる応力がX辺側とY辺側とで異なる。   In the tape wiring substrate having the above-described configuration, an ultrasonic method is used for bonding the protruding electrodes 3c and 3d of the conductor wiring 2 and the electrode pads (not shown) of the semiconductor chip. Here, the side of the mounting part 1 on the side where the protruding electrode 3c is arranged is the X side, and the side of the mounting part 1 on the side where the protruding electrode 3d is arranged is the Y side. When joining by the ultrasonic method, the amplitude of the ultrasonic wave has directionality. Therefore, the lead-out direction of the conductor wiring 2 at the junction on the X side and the Y side of the semiconductor chip is different from the amplitude direction of the ultrasonic waves. That is, when the ultrasonic wave is applied in the longitudinal direction of the conductor wiring 2 on the X side and the ultrasonic wave is applied in the width direction on the Y side, the bonding is performed through the protruding electrodes 3c and 3d. The stress applied to the conductor wiring 2 is different between the X side and the Y side.

例えば、半導体チップのX辺側に直交する方向に導体配線2が引き出されている場合の突起電極3cについて、導体配線2の幅方向における接合部14aの寸法(すなわち導体配線2の幅に相当)をX1、長手方向の寸法をY1とする。一方、Y辺側に直交する方向に導体配線2が引き出されている場合の突起電極3dについて、導体配線2の幅方向における接合部14bの寸法(すなわち導体配線2の幅に相当)寸法をY2、長手方向の寸法をX2とする。そして、X1<Y1かつX2>Y2とする。   For example, with respect to the protruding electrode 3c in the case where the conductor wiring 2 is drawn out in the direction orthogonal to the X side of the semiconductor chip, the dimension of the joint portion 14a in the width direction of the conductor wiring 2 (that is, the width of the conductor wiring 2) Is X1, and the longitudinal dimension is Y1. On the other hand, for the protruding electrode 3d when the conductor wiring 2 is drawn out in the direction orthogonal to the Y side, the dimension of the joint portion 14b in the width direction of the conductor wiring 2 (that is, the width of the conductor wiring 2) is Y2. The dimension in the longitudinal direction is X2. Then, X1 <Y1 and X2> Y2.

この状態で、接合時の超音波をその振幅がY辺に平行になるように印加した場合、Y辺側では、導体配線2の短い方向に振動するために導体配線2が動き、接合が不安定になり易い。一方、接合条件をY辺側にあわせると、X辺側の接合が不安定になり易くなる。   In this state, when the ultrasonic wave at the time of joining is applied so that the amplitude thereof is parallel to the Y side, the conductor wiring 2 moves on the Y side side and vibrates in the short direction of the conductor wiring 2, and the joining is not performed. It tends to be stable. On the other hand, when the joining condition is adjusted to the Y side, the joining on the X side tends to become unstable.

そこで本発明は、配線基板と半導体チップとの実装方向に制約がなく、半導体チップの電極パッドと突起電極との安定した接合を可能にする配線基板を提供することを目的とする。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a wiring board that enables stable bonding between an electrode pad of a semiconductor chip and a protruding electrode without any restriction in the mounting direction of the wiring board and the semiconductor chip.

本発明の配線基板は、絶縁性基材と、前記絶縁性基材上に設けられ、半導体チップが実装される実装領域に整列して配置されたインナーリード部を形成する複数本の導体配線と、前記導体配線の各々のインナーリード部に形成された突起電極とを備え、前記導体配線は、前記実装領域の互いに直交するX辺及びY辺にそれぞれ直交するように配置されている。前記X辺側及び前記Y辺側の前記導体配線に設けられた前記突起電極はともに、前記導体配線上に位置する部分の前記X辺方向における寸法よりも前記Y辺方向における寸法の方が長い。   The wiring board of the present invention includes an insulating base material, and a plurality of conductor wirings provided on the insulating base material and forming inner lead portions arranged in alignment with a mounting region on which a semiconductor chip is mounted; And a protruding electrode formed on each inner lead portion of the conductor wiring, and the conductor wiring is arranged so as to be orthogonal to the X side and the Y side orthogonal to each other in the mounting region. Both of the protruding electrodes provided on the conductor wiring on the X side and the Y side have a dimension in the Y side direction longer than a dimension in the X side direction of a portion located on the conductor wiring. .

本発明の半導体装置は、上記構成の配線基板と、前記配線基板上に搭載された半導体チップとを備え、前記突起電極を介して前記半導体チップの電極パッドと前記導体配線とが接続されている。   The semiconductor device of the present invention includes a wiring board having the above-described configuration and a semiconductor chip mounted on the wiring board, and the electrode pads of the semiconductor chip and the conductor wiring are connected via the protruding electrodes. .

本発明の半導体装置の製造方法は、上記構成の配線基板を用い、前記配線基板上に半導体チップを配置し、前記半導体チップの電極パッドと前記突起電極とを接続することにより、前記突起電極を介して前記電極パッドと前記導体配線とを接続する。   According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: using a wiring board having the above-described configuration; placing a semiconductor chip on the wiring board; and connecting the electrode pad of the semiconductor chip and the protruding electrode to The electrode pad and the conductor wiring are connected via each other.

本発明の配線基板によれば、半導体チップの電極パッドとテープ配線基板の突起電極との接合状態が、半導体チップのX辺側とY辺側との間で差が小さくなり、実装方向に制約がなく、安定した接合が可能になる。   According to the wiring board of the present invention, the bonding state between the electrode pad of the semiconductor chip and the protruding electrode of the tape wiring board becomes small between the X side and the Y side of the semiconductor chip, and the mounting direction is restricted. There is no problem and stable bonding is possible.

本発明は、上記構成を基本として、以下のような態様を採ることができる。   The present invention can take the following aspects based on the above configuration.

すなわち、上記構成の本発明の配線基板において、前記突起電極の前記導体配線上に位置する部分は、前記X辺側の突起電極の前記X辺方向及び前記Y辺方向における寸法に対して、前記Y辺側の突起電極の前記Y辺方向及び前記Y辺方向における寸法がそれぞれ等しいことが好ましい。   That is, in the wiring board of the present invention having the above-described configuration, the portion of the protruding electrode located on the conductor wiring has the dimensions in the X-side direction and the Y-side direction of the protruding electrode on the X side. It is preferable that the Y-side protruding electrode has the same dimension in the Y-side direction and the Y-side direction.

また、前記X辺側の導体配線は前記Y辺側の導体配線より配線幅が細いことが好ましい。   The X-side conductor wiring preferably has a narrower wiring width than the Y-side conductor wiring.

また、前記突起電極の上面は中央部が端部よりも突出していることが好ましい。   Moreover, it is preferable that the center part protrudes from the edge part on the upper surface of the said protruding electrode.

上記構成の本発明の半導体装置において、上記いずれかの構成の配線基板を用いた構成とすることができる。   In the semiconductor device of the present invention having the above-described configuration, the wiring board having any one of the above-described configurations can be used.

また、前記突起電極と、前記半導体チップのX辺側とY辺側の接合用の電極パッドとが、前記Y辺方向を振幅方向とする超音波の印加により接合された構成とすることが好ましい。   Moreover, it is preferable that the protruding electrode and the electrode pad for bonding on the X side and the Y side of the semiconductor chip are bonded by applying an ultrasonic wave having the Y side direction as an amplitude direction. .

上記構成の本発明の半導体装置の製造方法において、上記いずれかの構成の配線基板を用いることができる。   In the method for manufacturing a semiconductor device of the present invention having the above configuration, the wiring substrate having any one of the above configurations can be used.

また、前記電極パッドと前記突起電極とを接続する工程は、前記配線基板の前記Y辺方向を超音波の振幅方向に整合させて、前記配線基板の前記突起電極と前記半導体チップの電極パッドとを相対するように位置あわせをする工程と、押圧しながら超音波を印加して前記突起電極と前記電極パッドとを接合する工程とを含むことが好ましい。   Further, the step of connecting the electrode pad and the protruding electrode may be performed by aligning the Y-side direction of the wiring board with the amplitude direction of the ultrasonic wave, and the protruding electrode of the wiring board and the electrode pad of the semiconductor chip. It is preferable to include a step of aligning the electrodes so as to face each other and a step of applying ultrasonic waves while pressing to join the protruding electrodes and the electrode pads.

また、前記突起電極と前記電極パッドとを接合する工程の前に封止樹脂層を形成する工程を有することが好ましい。   Moreover, it is preferable to have the process of forming a sealing resin layer before the process of joining the said protruding electrode and the said electrode pad.

以下、本発明の実施の形態について、図面を参照しながら詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(実施の形態1)
図1(a)は、実施の形態1のテープ配線基板における導体配線2の配列を示す平面図、(b)は、同図に符号Aで示された要部の構造を示し、テープ配線基板表面側から見た平面図である。図2は、インナーリード部の斜視図である。
(Embodiment 1)
1A is a plan view showing an arrangement of conductor wirings 2 in the tape wiring board of the first embodiment, and FIG. 1B shows a structure of a main part indicated by reference numeral A in FIG. It is the top view seen from the surface side. FIG. 2 is a perspective view of the inner lead portion.

図1において、1は半導体チップの実装部を示し、絶縁性のテープ基材(図示せず)の表面に複数本の導体配線2a、2bが形成されている。導体配線2aが配列された側の実装部1の辺をX辺、導体配線2bが配列された側の実装部1の辺をY辺とする。複数本の導体配線2a、2bの端部はインナーリード部を形成し、各導体配線2のインナーリード部には、突起電極3a、3bが、導体配線2a、2bの両側に亘って形成されている。突起電極3aは半導体チップのX辺側に配列された導体配線2aに形成され、突起電極3bは半導体チップのY辺側に配列された導体配線2bに形成されている。突起電極3a、3bは、半導体チップ実装部1に、半導体チップの電極パッド(図示せず)と対向するように整列して配置されている。   In FIG. 1, reference numeral 1 denotes a mounting portion of a semiconductor chip, and a plurality of conductor wirings 2a and 2b are formed on the surface of an insulating tape base material (not shown). The side of the mounting part 1 on the side where the conductor wiring 2a is arranged is the X side, and the side of the mounting part 1 on the side where the conductor wiring 2b is arranged is the Y side. The end portions of the plurality of conductor wires 2a and 2b form inner lead portions, and the projecting electrodes 3a and 3b are formed on both sides of the conductor wires 2a and 2b on the inner lead portion of each conductor wire 2. Yes. The protruding electrode 3a is formed on the conductor wiring 2a arranged on the X side of the semiconductor chip, and the protruding electrode 3b is formed on the conductor wiring 2b arranged on the Y side of the semiconductor chip. The protruding electrodes 3a and 3b are arranged in alignment on the semiconductor chip mounting portion 1 so as to face electrode pads (not shown) of the semiconductor chip.

導体配線2aの幅方向における導体配線2a上の突起電極3aの幅(すなわち導体配線2aの幅に相当)をX1a、突起電極3aの全体の幅をX1bとし、導体配線2aの長手方向における突起電極3aの幅をY1とする。また、導体配線2bの幅方向における導体配線2b上の突起電極3bの幅(すなわち導体配線2bの幅に相当)をY2a、突起電極3bの全体の幅をY2bとし、導体配線2bの長手方向における突起電極3bの幅をX2とする。本実施の形態では、X1a<Y1、かつX2<Y2aに設定される。   The width of the protruding electrode 3a on the conductor wiring 2a in the width direction of the conductor wiring 2a (that is, the width of the conductor wiring 2a) is X1a, the entire width of the protruding electrode 3a is X1b, and the protruding electrode in the longitudinal direction of the conductor wiring 2a. The width of 3a is assumed to be Y1. Also, the width of the protruding electrode 3b on the conductor wiring 2b in the width direction of the conductor wiring 2b (that is, the width of the conductor wiring 2b) is Y2a, and the entire width of the protruding electrode 3b is Y2b. The width of the protruding electrode 3b is X2. In the present embodiment, X1a <Y1 and X2 <Y2a are set.

図3に示すように、上記構成によれば、半導体チップの電極パッド6と突起電極3a、3bとを超音波を用いて接合する場合、半導体チップのX辺側とY辺側で両方とも、突起電極3a、3bが長くなっている方向に対して同様に超音波の振幅を与えることが可能となる。これにより半導体チップのX辺側の導体配線2aとY辺側の導体配線2bとで、超音波による応力のかかり方が異なっているにもかかわらず、X辺側の突起電極3aとY辺側の突起電極3bとの間で差異なく、安定して接合をすることが可能となる。   As shown in FIG. 3, according to the above configuration, when the electrode pad 6 of the semiconductor chip and the protruding electrodes 3a and 3b are bonded using ultrasonic waves, both the X side and the Y side of the semiconductor chip are Similarly, the amplitude of the ultrasonic wave can be given to the direction in which the protruding electrodes 3a and 3b are elongated. As a result, the X-side protruding electrode 3a and the Y-side of the conductor wiring 2a on the X-side of the semiconductor chip and the conductor wiring 2b on the Y-side are different from each other in terms of the stress applied by the ultrasonic waves. Thus, it is possible to perform stable bonding without any difference between the protruding electrode 3b.

また、半導体チップのX辺側とY辺側において、導体配線2a、2b上の突起電極3a、3bの面積は等しく、縦横の構成が等しく形成されていること、すなわち、X1a=X2、Y1=Y2aであることが望ましい。これにより接合部7aと7bの面積を同等にでき、接合状態をX辺側とY辺側で同等にすることができる。   Further, the areas of the protruding electrodes 3a and 3b on the conductor wirings 2a and 2b are equal on the X side and the Y side of the semiconductor chip, and the vertical and horizontal configurations are formed equally, that is, X1a = X2, Y1 = Y2a is desirable. Thereby, the areas of the joint portions 7a and 7b can be made equal, and the joining state can be made equivalent on the X side and the Y side.

また、図2に示す突起電極3a、3bの上面は、中央部4が端部5よりも突出していることが望ましい。これにより、封止樹脂を配線基板上に先に滴下した後に配線基板に半導体チップを接合する工法において、突起電極の中央部4が突出していることにより、封止樹脂をかき分けながら電極パッドと接合することができ、安定に接続することができる。   Moreover, as for the upper surface of the protruding electrodes 3a and 3b shown in FIG. Thus, in the method of bonding the semiconductor chip to the wiring board after the sealing resin is first dropped on the wiring board, the center portion 4 of the protruding electrode protrudes, so that the sealing resin is separated and bonded to the electrode pad. Can be connected stably.

図4を参照して、本実施の形態における半導体装置の製造方法について説明する。図4(a)〜(c)は、同製造方法の各工程を示す断面図である。   With reference to FIG. 4, the manufacturing method of the semiconductor device in the present embodiment will be described. 4A to 4C are cross-sectional views showing the respective steps of the manufacturing method.

まず図4(a)に示すように、絶縁性基材であるテープ基材8上に導体配線2が形成され、半導体チップ9との接合用に導体配線2上に突起電極3が形成された、上述の構成を有する配線基板を用意する。そして、配線基板上には半導体チップ9の素子面を保護するための封止樹脂層10を形成する。さらに、突起電極3と対向するように、半導体チップ9上の電極パッド6を位置合わせする。   First, as shown in FIG. 4A, the conductor wiring 2 was formed on the tape base 8 that is an insulating base, and the protruding electrode 3 was formed on the conductor wiring 2 for joining with the semiconductor chip 9. A wiring board having the above-described configuration is prepared. Then, a sealing resin layer 10 for protecting the element surface of the semiconductor chip 9 is formed on the wiring board. Further, the electrode pad 6 on the semiconductor chip 9 is aligned so as to face the protruding electrode 3.

次に図4(b)に示すように、超音波印加用の治具11により半導体チップ9を加圧加熱し、さらには超音波を印加して、半導体チップ9の電極パッド6と配線基板上の突起電極3とを接合する。このとき図3に示すように、超音波の振幅方向と、半導体チップ9のX辺側及びY辺側の双方の突起電極3a、3bの長手方向が同じ方向であることが望ましい。また、電極パッド6には金メッキなどがほどこされていることが望ましい。突起電極としては金、銀、パラジウム、銅、ニッケル、錫、鉛などを主成分とする材料を用いることができる。突起電極3の高さは、例えば約15μmとすることができる。   Next, as shown in FIG. 4B, the semiconductor chip 9 is pressurized and heated by the ultrasonic application jig 11 and further ultrasonic waves are applied to the electrode pads 6 of the semiconductor chip 9 and the wiring substrate. The protruding electrode 3 is joined. At this time, as shown in FIG. 3, it is desirable that the ultrasonic amplitude direction and the longitudinal directions of the protruding electrodes 3 a and 3 b on both the X side and the Y side of the semiconductor chip 9 are the same direction. The electrode pad 6 is preferably plated with gold. As the protruding electrode, a material mainly composed of gold, silver, palladium, copper, nickel, tin, lead, or the like can be used. The height of the protruding electrode 3 can be about 15 μm, for example.

上記工程によれば、加熱することで封止樹脂10の硬化を半導体チップ9実装と同時に実施できる利点がある。しかしながら、半導体チップ9を実装した後に、後から封止樹脂10を注入し、加熱して封止樹脂を硬化し、半導体装置を形成することも可能である。   According to the above process, there is an advantage that the sealing resin 10 can be cured simultaneously with the mounting of the semiconductor chip 9 by heating. However, after the semiconductor chip 9 is mounted, it is possible to inject the sealing resin 10 later and to cure the sealing resin by heating to form a semiconductor device.

次に図4(c)に示すように、治具11を除去し、半導体装置が完成する。   Next, as shown in FIG. 4C, the jig 11 is removed to complete the semiconductor device.

以上の実施の形態により、半導体チップのX辺側の突起電極接続部とY辺側の突起電極接続部とで接合状態に差がなく、また導体配線の断線も抑制された接合が可能となる。従って、超音波接合による半導体チップの接合性が安定で、製造歩留まりの高い半導体装置を提供できる。   According to the above embodiment, there is no difference in the bonding state between the protruding electrode connecting portion on the X side and the protruding electrode connecting portion on the Y side of the semiconductor chip, and bonding with reduced disconnection of the conductor wiring is possible. . Therefore, it is possible to provide a semiconductor device in which the bonding property of the semiconductor chip by ultrasonic bonding is stable and the manufacturing yield is high.

本発明の配線基板によれば、超音波による接合により安定な接合状態を得ることが可能な半導体チップの実装を可能することができる。   According to the wiring board of the present invention, it is possible to mount a semiconductor chip capable of obtaining a stable bonded state by ultrasonic bonding.

(a)は本発明の実施の形態1におけるテープ配線基板の構造を示す平面図、(b)はその要部の拡大平面図(A) is a top view which shows the structure of the tape wiring board in Embodiment 1 of this invention, (b) is an enlarged plan view of the principal part 同テープ配線基板のインナーリード部の斜視図Perspective view of inner lead part of the same tape wiring board 実施の形態1におけるテープ配線基板への半導体チップの実装状態を示す平面図The top view which shows the mounting state of the semiconductor chip to the tape wiring board in Embodiment 1 実施の形態1における半導体装置の製造方法を示す断面図Sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 1 従来例のテープ配線基板における半導体チップ実装部を示す平面図A plan view showing a semiconductor chip mounting portion in a conventional tape wiring board

符号の説明Explanation of symbols

1 半導体チップの実装部
2、2a、2b 導体配線
3、3a、3b、3c、3d 突起電極
4 中央部
5 端部
6 電極パッド
7a、7b、14a、14b 接合部
8 絶縁性基材(テープ基材)
9 半導体チップ
10 封止樹脂層
11 超音波治具
DESCRIPTION OF SYMBOLS 1 Semiconductor chip mounting part 2, 2a, 2b Conductor wiring 3, 3a, 3b, 3c, 3d Projection electrode 4 Center part 5 End part 6 Electrode pad 7a, 7b, 14a, 14b Joint part 8 Insulating base material (tape base) Material)
9 Semiconductor chip 10 Sealing resin layer 11 Ultrasonic jig

Claims (9)

絶縁性基材と、
前記絶縁性基材上に設けられ、半導体チップが実装される実装領域に整列して配置されたインナーリード部を形成する複数本の導体配線と、
前記導体配線の各々のインナーリード部に形成された突起電極とを備え、
前記導体配線は、前記実装領域の互いに直交するX辺及びY辺にそれぞれ直交するように配置されている配線基板において、
前記X辺側及び前記Y辺側の前記導体配線に設けられた前記突起電極はともに、前記導体配線上に位置する部分の前記X辺方向における寸法よりも前記Y辺方向における寸法の方が長いことを特徴とする配線基板。
An insulating substrate;
A plurality of conductor wirings provided on the insulating base material and forming inner lead portions arranged in alignment with a mounting region on which a semiconductor chip is mounted;
A protruding electrode formed on each inner lead portion of the conductor wiring,
In the wiring board, the conductor wiring is arranged to be orthogonal to the X side and the Y side orthogonal to each other in the mounting region,
Both of the protruding electrodes provided on the conductor wiring on the X side and the Y side have a dimension in the Y side direction longer than a dimension in the X side direction of a portion located on the conductor wiring. A wiring board characterized by that.
前記突起電極の前記導体配線上に位置する部分は、前記X辺側の突起電極の前記X辺方向及び前記Y辺方向における寸法に対して、前記Y辺側の突起電極の前記Y辺方向及び前記Y辺方向における寸法がそれぞれ等しい請求項1に記載の配線基板。   The portion of the protruding electrode located on the conductor wiring is arranged such that the Y side direction of the protruding electrode on the Y side and the dimension in the X side direction and Y side direction of the protruding electrode on the X side The wiring board according to claim 1, wherein dimensions in the Y-side direction are equal to each other. 前記X辺側の導体配線は前記Y辺側の導体配線より配線幅が細い請求項1に記載の配線基板。   The wiring board according to claim 1, wherein the X-side conductor wiring has a narrower wiring width than the Y-side conductor wiring. 前記突起電極の上面は中央部が端部よりも突出している請求項1に記載の配線基板。   The wiring board according to claim 1, wherein a central portion of the upper surface of the protruding electrode protrudes from an end portion. 請求項1から4のいずれか1項に記載の配線基板と、
前記配線基板上に搭載された半導体チップとを備え、
前記突起電極を介して前記半導体チップの電極パッドと前記導体配線とが接続された半導体装置。
The wiring board according to any one of claims 1 to 4,
A semiconductor chip mounted on the wiring board,
A semiconductor device in which an electrode pad of the semiconductor chip and the conductor wiring are connected via the protruding electrode.
前記突起電極と、前記半導体チップのX辺側とY辺側の接合用の電極パッドとが、前記Y辺方向を振幅方向とする超音波の印加により接合されている請求項5に記載の半導体装置。   The semiconductor according to claim 5, wherein the protruding electrode and the electrode pad for bonding on the X side and the Y side of the semiconductor chip are bonded by applying an ultrasonic wave whose amplitude direction is the Y side direction. apparatus. 請求項1から4のいずれか1項に記載の配線基板を用い、
前記配線基板上に半導体チップを配置し、
前記半導体チップの電極パッドと前記突起電極とを接続することにより、前記突起電極を介して前記電極パッドと前記導体配線とを接続する半導体装置の製造方法。
Using the wiring board according to any one of claims 1 to 4,
A semiconductor chip is disposed on the wiring board,
A method for manufacturing a semiconductor device, wherein the electrode pad and the conductor wiring are connected via the protruding electrode by connecting the electrode pad of the semiconductor chip and the protruding electrode.
前記電極パッドと前記突起電極とを接続する工程は、
前記配線基板の前記Y辺方向を超音波の振幅方向に整合させて、前記配線基板の前記突起電極と前記半導体チップの電極パッドとを相対するように位置あわせをする工程と、
押圧しながら超音波を印加して前記突起電極と前記電極パッドとを接合する工程とを含む請求項7に記載の半導体装置の製造方法。
The step of connecting the electrode pad and the protruding electrode includes:
Aligning the Y-side direction of the wiring board with the amplitude direction of ultrasonic waves and aligning the protruding electrodes of the wiring board with the electrode pads of the semiconductor chip; and
The method for manufacturing a semiconductor device according to claim 7, further comprising: applying an ultrasonic wave while pressing to join the protruding electrode and the electrode pad.
前記突起電極と前記電極パッドとを接合する工程の前に封止樹脂層を形成する工程を有する請求項8に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 8, further comprising a step of forming a sealing resin layer before the step of bonding the protruding electrode and the electrode pad.
JP2008127425A 2008-05-14 2008-05-14 Wiring substrate, and semiconductor device and manufacturing method thereof Withdrawn JP2009277873A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12298820B2 (en) 2020-11-06 2025-05-13 Samsung Electronics Co., Ltd. Electronic device comprising plurality of electric objects

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12298820B2 (en) 2020-11-06 2025-05-13 Samsung Electronics Co., Ltd. Electronic device comprising plurality of electric objects

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