JP2009272820A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To read image data from one pixel array at a plurality of frame rates at the same time so that image data read specially from a pixel group with a low resolution may have a high frame rate. <P>SOLUTION: A pixel array 10 is divided into first and second pixel groups having different resolutions. Vertical scanning circuits 21 and 22 vertically scan the first and second pixel groups according to vertical synchronization signals VD1 and VD2, respectively. CDS circuits 31 and 32 read an image data for one line which is selected from the first and second pixel groups through vertical scanning by the vertical scanning circuits 21 and 22, and temporarily hold it. Horizontal scanning circuits 41 and 42 horizontally scan the CDS circuits 31 and 32 according to horizontal synchronization signals HD1 and HD2, so as to sequentially output the image data for one line held by the CDS circuits 31 and 32 from the CDS circuits 31 and 32. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device including a CMOS image sensor or the like.

  In recent years, solid-state imaging devices using CMOS image sensors have become widespread. FIG. 16 is a configuration diagram of a conventional CMOS image sensor including a pixel array in which pixels are arranged in 8 rows × 8 columns. A conventional CMOS image sensor shown in FIG. 16 includes a pixel array 101 in which pixels are arranged in 8 rows and 8 columns, a vertical scanning circuit 102 that vertically scans the pixel array 101, and one row output from the pixel array 101. A CDS circuit 103 that removes and retains noise from image data, a horizontal scanning circuit 104 that sequentially outputs image data for one row held by the CDS circuit 103 in units of pixels, and an image output from the CDS circuit 103 And an output amplifier 105 that amplifies the data and guides it to an unillustrated image processing circuit or the like provided in the subsequent stage.

  FIG. 17 is a timing chart of the CMOS image sensor shown in FIG. 16. The upper part shows the vertical synchronization signal VD, and the lower part shows the horizontal synchronization signal HD. Since the pixel array 101 is composed of eight rows of pixels, as shown in FIG. 17, if the period of the horizontal synchronization signal HD is an H period, one frame period is an 8H period. Further, since the pixel array is composed of eight columns of pixels, the CDS circuit 103 sequentially outputs image data for eight pixels one pixel at a time in accordance with the horizontal scanning by the horizontal scanning circuit 104 in the 1H period. Therefore, in one frame period, image data for 8 × 8 = 64 pixels is output from the CDS circuit 103 as one frame of image data. Therefore, the frame rate of the CMOS image sensor is determined by the period of the vertical synchronization signal VD.

  Here, in order to cope with the recent increase in the frame rate, for example, a technique of reducing the number of pixels in the vertical direction or performing multi-line simultaneous reading is employed.

  FIG. 18 is a configuration diagram of a conventional CMOS image sensor in which the number of pixels in the vertical direction is halved and 2-line simultaneous reading is performed. In FIG. 18, since the number of pixels in the vertical direction of the pixel array 101 is halved with respect to the pixel array 101 shown in FIG. 16, the number of pixel control lines is four, and 2 In order to perform simultaneous line readout, the number of output amplifiers 105 is two.

  FIG. 19 is a timing chart of the CMOS image sensor shown in FIG. 18. The upper stage shows the vertical synchronization signal VD, and the lower stage shows the horizontal synchronization signal HD. When performing two-line simultaneous readout, the CDS circuit 103 uses, for example, two output amplifiers 105 and 105 for image data for two pixels in the first column and the second column among the image data for one row to be held. The image data for two pixels in the third column and the fourth column are simultaneously output to the two output amplifiers 105, 105, so that the image data for two pixels are output simultaneously. . Therefore, the H period shown in FIG. 19 is ½ of the H period shown in FIG.

  Further, since the number of pixels in the vertical direction of the CMOS image sensor shown in FIG. 18 is ½ that of the CMOS image sensor shown in FIG. 16, one frame period is a 4H period as shown in FIG. Accordingly, one frame period shown in FIG. 19 is 1/4 of one frame period shown in FIG. 17, and the frame rate of the CMOS image sensor shown in FIG. 18 is four times the frame rate of the CMOS image sensor shown in FIG. .

In addition, as a technique related to the present invention, for example, Non-Patent Document 1 discloses a column parallel A / D conversion in which A / D conversion is performed in each column of the CMOS image sensor in order to realize high-speed operation of the CMOS image sensor. A CMOS image sensor of the type is disclosed.
Kazuya Yonemoto, “Basics and Applications of CCD / CMOS Image Sensors”, CQ Publishing Company, p. 201-203

  By the way, in recent years, in-vehicle sensors that detect obstacles by capturing an image of a front scene, image data for viewing by a passenger is acquired with high resolution, and at the same time, image data for distance measurement is acquired with low resolution. In addition, there is a desire to acquire at a high frame rate. However, the conventional CMOS image sensor shown in FIGS. 16 and 18 has a problem that it cannot meet such a demand.

  An object of the present invention is to provide a solid-state imaging device capable of simultaneously reading image data from a single pixel array at a plurality of frame rates so that the frame rate of image data read by a pixel group having a lower resolution becomes higher. That is.

  (1) The solid-state imaging device of the present invention is a solid-state imaging device including a pixel array composed of a plurality of pixels arranged in a matrix, and the pixel array increases n (n is an integer of 2 or more). Are divided into first to nth pixel groups so that the resolution decreases, and corresponding to each of the first to nth pixel groups, the first to nth pixel groups are vertically scanned according to a vertical synchronization signal. Corresponding to each of the first to nth vertical scanning circuits and the first to nth pixel groups, and the first to nth vertical scanning circuits from the first to nth vertical scanning circuits. Corresponding to each of the first to n-th readout circuits for reading out and holding the image data for one row selected by the above and the first to n-th pixel groups, and the first to n-th readout circuits according to a horizontal synchronization signal. The first to nth readout circuits are scanned horizontally by The first to n-th horizontal scanning circuits that sequentially output the image data for one row held by the first to n-th readout circuits and the image data read by the larger n pixel groups are relatively relative to each other. N types of vertical synchronization signals corresponding to the first to n-th pixel groups are generated and output to the first to n-th vertical scanning circuits so that the frame rate is increased. And a controller that generates n types of horizontal synchronization signals corresponding to the first to nth pixel groups and outputs the generated signals to the first to nth horizontal scanning circuits.

  According to this configuration, the pixel array is divided into first to nth pixel groups having different resolutions. There are n vertical scanning circuits, readout circuits, and horizontal scanning circuits corresponding to the first to nth pixel groups, respectively. The control unit generates n types of vertical synchronization signals corresponding to the first to n-th pixel groups so that the frame rate of the image data read by the pixel group having a lower resolution becomes higher. The vertical scanning circuits are controlled, and n types of horizontal synchronizing signals corresponding to the first to nth pixel groups are generated to control the first to nth horizontal scanning circuits. Therefore, it is possible to read out image data read by a pixel group having a low resolution at a high frame rate, and it is possible to read out image data from a single pixel array at a plurality of frame rates at the same time.

  (2) The pixel array is partitioned into unit pixel portions each including a predetermined number of pixels, and each unit pixel portion is partitioned into first to nth regions having different numbers of pixels in a fixed pattern. In the nth pixel group, it is preferable that the pixels in the first to nth regions of each unit pixel portion are allocated.

  According to this configuration, the pixel array is divided into unit pixel portions. The unit pixel portion is partitioned into first to nth areas having a fixed pattern and different numbers of pixels. The first to nth pixel groups are configured by assigning pixels in the first to nth regions of each unit pixel unit. Therefore, in the first to nth pixel groups, each pixel is periodically arranged at a different resolution over the entire area of the pixel array. Accordingly, the first to nth pixel groups can capture the same scene at different frame rates without unevenness.

  (3) Each pixel belonging to the first to nth pixel groups is connected to the first to nth vertical scanning circuits via a pixel control line in a row corresponding to the row to which the pixel belongs, and It is preferable that the first to nth readout circuits are connected to each other through vertical signal lines in columns corresponding to columns to which.

  According to this configuration, each pixel belonging to the first to nth pixel groups is connected to the first to nth vertical scanning circuits via the pixel control line of the row to which the pixel belongs. In addition, each pixel belonging to the first to nth pixel groups is connected to the first to nth readout circuits via a vertical signal line corresponding to the column to which the pixel belongs.

  Therefore, the first to n-th vertical scanning circuits can individually vertically scan the first to n-th pixel groups via the pixel control lines in each row. Image data can be individually read out from the first to nth pixel groups via the vertical signal lines in the column.

  (4) The first to nth pixel groups include first and second pixel groups, and the first pixel group has higher resolution than the second pixel group, and the first pixel Preferably, the group outputs a color image and the second pixel group outputs a monochrome image.

  According to this configuration, a color image is read at a low frame rate, and a monochrome image is read at a high frame rate. Therefore, for example, high-resolution color image data for human viewing and low-resolution monochrome image data for distance measurement can be simultaneously acquired, and a solid-state imaging device suitable for an in-vehicle sensor or the like is provided. be able to.

  (5) Each pixel of the first pixel group preferably includes a primary color filter.

  According to this configuration, a color image with high color separation and color reproducibility can be obtained.

  (6) Each pixel of the first pixel group preferably includes a complementary color filter.

  According to this configuration, a color image with high sensitivity and high resolution can be obtained.

  (7) The first to nth pixel groups include first and second pixel groups, and the first pixel group has higher resolution than the second pixel group, and the first and second pixel groups are Both of the two pixel groups preferably output a color image.

  According to this configuration, a high-resolution color image can be read at a low frame rate, and a low-resolution color image can be read at a high frame rate.

  (8) It is preferable that the first and second pixel groups include a primary color filter.

  According to this configuration, a color image with high color separation and color reproducibility can be obtained.

  (9) It is preferable that the first and second pixel groups include complementary color filters.

  According to this configuration, a color image with high sensitivity and high resolution can be obtained.

  (10) Each pixel of the first pixel group has a characteristic in which an output changes linearly with respect to incident light, and a characteristic in which an output changes logarithmically with respect to incident light. Each pixel of the pixel group preferably has a characteristic that the output changes linearly with respect to the incident light.

  According to this configuration, each pixel of the first pixel group has a characteristic that the output changes linearly with respect to the incident light and a characteristic that changes logarithmically. Dynamic range image data is obtained, and image data can be obtained from the second pixel group at high speed.

  (11) Each pixel of the second pixel group preferably includes a transfer gate, and further includes a booster circuit that boosts a power supply voltage and applies the boosted voltage to the transfer gate.

  According to this configuration, since a voltage higher than the power supply voltage is applied to the transfer gate of each pixel of the second pixel group, image data can be read out from the second pixel group at high speed.

  (12) It is preferable that each pixel of the second pixel group has a different type of photodiode from the photodiode of each pixel of the first pixel group in order to output image data at high speed. .

  According to this configuration, each pixel of the second pixel group can output image data at a higher speed than each pixel of the first pixel group.

  (13) It is preferable that each pixel of the first pixel group includes a complete transfer embedded type photodiode, and each pixel of the second pixel group includes a surface type photodiode.

  According to this configuration, each pixel of the first pixel group includes the complete transfer embedded photodiode with high noise suppression accuracy, and each pixel of the second pixel group does not need to transfer charges. Since the surface type photodiode is provided, high-quality image data can be read from the first pixel group, and image data can be read from the second pixel group at high speed.

  According to the present invention, it is possible to simultaneously read image data from a single pixel array at a plurality of frame rates so that the image data read by a pixel group having a lower resolution has a higher frame rate.

(Embodiment 1)
FIG. 1 is an overall configuration diagram of a solid-state imaging device 1 according to Embodiment 1 of the present invention. As shown in FIG. 1, the solid-state imaging device 1 includes a sensor unit 2, a control unit 3, an A / D conversion unit 4, an image processing unit 5, and an image memory 6. The sensor unit 2 includes a pixel array 10, two vertical scanning circuits 21 and 22, two CDS (correlated double sampling) circuits 31 and 32 (an example of a readout circuit), and two horizontal scanning circuits. 41, 42, and three output amplifiers 51, 52, 53 are provided. In the present embodiment, the sensor unit 2 is constituted by a one-chip column CDS type CMOS image sensor.

  In the pixel array 10, a plurality of pixels are arranged in a matrix with 8 rows × 8 columns. Note that 8 rows × 8 columns is an example, and may be arranged in M (M is a positive integer of 2 or more) rows × N (N is a positive integer of 2 or more) columns. Here, the pixel array 10 acquires a first pixel group for acquiring image data at a predetermined low-speed frame rate and high resolution, and acquires image data at a predetermined high-speed frame rate and low resolution higher than the low-speed frame rate. To be divided into a second pixel group. In the present embodiment, for example, four times the low speed frame rate can be adopted as the high speed frame rate. For example, 30, 60 (1 / s) can be adopted as the low-speed frame rate.

  FIG. 2 is a diagram showing a detailed configuration of the pixel array 10. As shown in FIG. 2, the pixel array 10 is partitioned into unit pixel units 11 including four pixels G <b> 1 indicated by symbols A to D arranged in a matrix of 2 rows × 2 columns. Since the pixel array 10 of FIG. 1 has pixels G1 arranged in 8 rows × 8 columns, the unit pixel units 11 are arranged in 4 rows × 4 columns. In the case of FIG. 2, in each unit pixel unit 11, the pixel A is arranged in the second row and the first column, the pixel B is arranged in the second row and the second column, and the pixel C is arranged in the first row and the first column. The pixels D are arranged in the first row and the second column.

  Each unit pixel unit 11 is partitioned into first and second regions DM1 and DM2 having a fixed pattern and different numbers of pixels. In the case of FIG. 2, three pixels G1, pixels A, B, and D, are partitioned into a first region DM1, and one pixel of pixel C is partitioned into a region DM2.

  The partition pattern of the first and second regions DM1 and DM2 in the unit pixel unit 11 is not limited to that shown in FIG. 2. For example, the pixel A is partitioned from the second region DM2 and the pixels B to D are divided. Other partition patterns may be employed such as partitioning into the first region DM1.

  In the first pixel group, the pixels A, B, and D belonging to the first region DM1 of each unit pixel unit 11 are assigned, and in the second pixel group, the pixel C belonging to the second region DM2 is assigned. Yes. As a result, the pixel array 10 is divided into two pixel groups of the first and second pixel groups.

  Therefore, the first pixel group has 8 rows and 8 columns. On the other hand, the second pixel group has four rows and four columns.

  In this way, by dividing the first and second pixel groups, it is possible to periodically arrange the pixels G1 in a constant pattern over the entire area of the pixel array 10, and the first and second pixels The pixel group can capture the same scene at different frame rates without unevenness.

  Returning to FIG. 1, the vertical scanning circuits 21 and 22 correspond to the first pixel group and the second pixel group, respectively. The vertical scanning circuit 21 is constituted by, for example, a shift register, and is connected to the first pixel group via the eight pixel control lines HL1 corresponding to the first to eighth rows of the first pixel group constituting the pixel array 10. Connected to one pixel group. The vertical scanning circuit 21 performs vertical scanning on the first pixel group by cyclically selecting the pixel control lines HL1 in the first to eighth rows in synchronization with the vertical synchronization signal VD1.

  The vertical scanning circuit 22 is configured by, for example, a shift register, and is connected to the second through four pixel control lines HL2 corresponding to the first to fourth rows of the second pixel group constituting the pixel array 10. Connected to the pixel group. Then, the vertical scanning circuit 22 cyclically selects the pixel control lines HL2 in the first to fourth rows in synchronization with the vertical synchronization signal VD2 having a frequency higher than that of the vertical synchronization signal VD1, thereby the first pixel group. Is scanned vertically. In this embodiment, the frequency of the vertical synchronization signal VD2 can be, for example, four times the frequency of the vertical synchronization signal VD1.

  In the first row and the third row shown in FIG. 2, since the pixel C of the second pixel group and the pixel D of the first pixel group are alternately arranged, one pixel control line HL1, HL2 is provided. The pixel control line HL2 is connected to the pixel C, and the pixel control line HL1 is connected to the pixel D. Further, in the second row and the fourth row shown in FIG. 2, the pixels A and B of the first pixel group are alternately arranged, and the pixels of the second pixel group are not arranged. Only the pixel control line HL1 is arranged, and the pixel control line HL1 is connected to the pixels A and B.

  Returning to FIG. 1, the CDS circuits 31 and 32 correspond to the first and second pixel groups, respectively. The CDS circuit 31 includes eight CDS circuits 311 to 318 corresponding to the first to eighth columns of the first pixel group. The CDS circuits 311 to 318 are connected to the first pixel group via eight vertical signal lines VL1 corresponding to the first to eighth columns of the first pixel group, respectively. The image data for one row of the first pixel group selected by the vertical scanning is read out, noise is removed, and then temporarily stored.

  The CDS circuit 32 includes four CDS circuits 321 to 324 corresponding to the first to fourth columns of the second pixel group. The CDS circuits 321 to 324 are connected to the second pixel group via four vertical signal lines VL2 corresponding to the first to fourth columns of the second pixel group, respectively. The image data for one row of the second pixel group selected by the 22 vertical scans is read out, and after the noise is removed, it is temporarily held.

  Here, in order to realize two-line simultaneous reading, the CDS circuits 321 and 323 are connected to the output amplifier 52, and the CDS circuits 322 and 324 are connected to the output amplifier 53.

  In the first column and the third column shown in FIG. 2, since the pixels C of the second pixel group and the pixels A of the first pixel group are alternately arranged, the vertical signal lines VL1 and VL2 are respectively provided. One by one, the vertical signal line VL2 is connected to the pixel C, and the vertical signal line VL1 is connected to the pixel A.

  In the second column and the fourth column shown in FIG. 2, the pixels D and B of the first pixel group are alternately arranged, and the pixels of the second pixel group are not arranged. Only the signal line VL1 is arranged, and the vertical signal line VL1 is connected to the pixels D and B.

  Returning to FIG. 1, the horizontal scanning circuits 41 and 42 correspond to the first and second pixel groups, respectively. The horizontal scanning circuit 41 is composed of, for example, a shift register, and cyclically selects the CDS circuits 311 to 318 constituting the CDS circuit 31 in synchronization with the horizontal synchronization signal HD1, thereby horizontally scanning the CDS circuit 31. The image data of the first to eighth columns held by the CDS circuit 31 are sequentially output from the CDS circuit 31.

  The horizontal scanning circuit 42 is composed of, for example, a shift register, and cyclically selects a set of CDS circuits 321 and 322 and a set of CDS circuits 323 and 324 in synchronization with the horizontal synchronization signal HD2, thereby allowing the CDS circuit 32 to be selected. Are scanned simultaneously, the image data of the first and second columns held by the CDS circuits 321 and 322 are simultaneously output from the CDS circuits 321 and 322, and the third and fourth columns held by the CDS circuits 323 and 324 are output. Image data is simultaneously output from the CDS circuits 323 and 324. As a result, the CDS circuit 32 simultaneously outputs the first column and second column image data, and simultaneously outputs the third column and fourth column image data to simultaneously output the two columns. Can be realized.

  The control unit 3 includes a microcomputer including a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like, and controls the solid-state imaging device 1 as a whole. In the present embodiment, the control unit 3 is configured to display the image data output from the second pixel group having a low resolution, in particular, as compared with the image data output from the first pixel group that is a pixel group having a high resolution. Two types of vertical synchronization signals VD1 and VD2 having different frequencies corresponding to the first and second pixel groups are generated and output to the vertical scanning circuits 21 and 22 so as to increase the rate, and the first and first Two types of horizontal synchronization signals HD 1 and HD 2 having different frequencies corresponding to the two pixel groups are generated and output to the horizontal scanning circuits 41 and 42.

  That is, the control unit 3 outputs the vertical synchronization signal VD1 to the vertical scanning circuit 21 and outputs the horizontal synchronization signal HD1 to the horizontal scanning circuit 41, so that the image data read by the first pixel group can be output at high speed. Read at frame rate. In addition, the control unit 3 outputs the vertical synchronization signal VD2 to the vertical scanning circuit 22 and outputs the horizontal synchronization signal HD2 to the horizontal scanning circuit 42, thereby slowing down the image data read by the second pixel group. Read at frame rate.

  3 shows a timing chart of the solid-state imaging device 1. FIG. 3A shows the vertical synchronizing signal VD1 and the horizontal synchronizing signal HD1 in the first pixel group, and FIG. 3B shows the vertical synchronizing signal VD2 in the second pixel group. A horizontal synchronization signal HD2 is shown. Hereinafter, one cycle of the horizontal synchronization signals HD1 and HD2 is referred to as an H period.

  As shown in FIG. 3A, when the H period of the first pixel group is T11, the first pixel group is composed of eight rows of pixels, and thus one frame period of the first pixel group. T1 is T1 = 8 × T11. As shown in FIG. 3B, if the H period of the second pixel group is T21, one frame period T2 of the second pixel group is composed of four rows of pixels, so that T2 = 4. × T21. Also, since the second pixel group employs two-line simultaneous reading, T21 = 1/2 × T11.

  Therefore, the frame rate of the first pixel group is 1 / T1 = 1 / (8 × T11), the frame rate of the second pixel group is 1 / T2 = 1 / (2 × T11), and the second pixel The frame rate of the group is four times the frame rate of the first pixel group.

  In order to realize the above, the control unit 3 divides or multiplies a master clock signal generated by a clock generation circuit (not shown), for example, to generate a pulse signal having a period T21 as the horizontal synchronization signal HD2, By dividing the synchronization signal HD2 by 4, a pulse signal having a period T2 is generated as the vertical synchronization signal VD2. Further, the control unit 3 divides the horizontal synchronization signal HD2 by 2 to generate a pulse signal having a cycle T11 as a horizontal synchronization signal HD1, and the horizontal synchronization signal HD1 is divided by 8 to thereby generate a vertical synchronization signal having a cycle T1. VD1 is generated.

  Returning to FIG. 1, the output amplifier 51 is connected to the CDS circuits 311 to 318, and amplifies the image data output from the CDS circuits 311 to 318 with a predetermined gain. The output amplifier 52 is connected to the CDS circuits 321 and 323, and amplifies the image data output from the CDS circuits 321 and 323 with a predetermined gain. The output amplifier 53 is connected to the CDS circuits 322 and 324 and amplifies the image data output from the CDS circuits 322 and 324 with a predetermined gain. As the gain of the output amplifiers 51 to 53, for example, a predetermined value suitable for A / D conversion by the A / D conversion unit 4 is adopted.

  There are three A / D conversion units 4 corresponding to the output amplifiers 51 to 53, respectively, and A / D-converts the image data output from the output amplifiers 51 to 53 and outputs the image data to the image processing unit 5. The image processing unit 5 performs predetermined image processing such as interpolation processing for interpolating pixels on the image data output from the A / D conversion unit 4. As shown in FIG. 2, in the first pixel group, the pixel in the first row and the first column is missing in the unit pixel portion 11. Therefore, in the present embodiment, the image processing unit 5 executes an interpolation process for interpolating the missing pixel using the peripheral pixels.

  The image memory 6 includes a storage device such as a RAM (Random Access Memory) and a hard disk, and stores image data that has been subjected to predetermined image processing by the image processing unit 5.

  Next, the operation of the solid-state imaging device 1 will be described with reference to the timing chart of FIG. First, the control unit 3 outputs the vertical synchronization signal VD1 to the vertical scanning circuit 21, outputs the horizontal synchronization signal HD1 to the horizontal scanning circuit 41, and outputs the vertical synchronization signal VD2 to the vertical scanning circuit 22, In addition, the horizontal synchronization signal HD2 is output to the horizontal scanning circuit 42 (time S1).

  Next, the vertical scanning circuit 21 selects the first row of the first pixel group, and holds in the CDS circuit 31 each image data read by each pixel G1 belonging to the first row of the first pixel group. (Period S21). In the present embodiment, as shown in FIG. 2, eight pixels C and D are alternately arranged in this order in the first row of the pixel array 10, and the second, fourth, and sixth columns. , The four pixels D in the eighth column belong to the first pixel group. Therefore, the CDS circuits 312, 314, 316 and 318 hold the image data output from these four pixels D.

  Further, the vertical scanning circuit 22 selects the first row of the second pixel group, and causes the CDS circuit 32 to hold each pixel data read by each pixel G1 belonging to the first row of the second pixel group ( Period S31). In this case, the four pixels C arranged in the first column, the third column, the fifth column, and the seventh column of the first row of the pixel array 10 belong to the second pixel group. Therefore, the CDS circuits 321 to 324 hold the image data output from these four pixels C.

  Next, the horizontal scanning circuit 41 performs horizontal scanning on the CDS circuit 31 to sequentially output the image data held in the CDS circuits 312, 314, 316, and 318 to the output amplifier 51 (period S21).

  Further, the horizontal scanning circuit 42 performs horizontal scanning on the CDS circuit 32 to sequentially output the image data held by the CDS circuits 321 to 324 to the output amplifiers 52 and 53 (period S31). In this case, the horizontal scanning circuit 42 first selects the CDS circuits 321 and 322, outputs the image data held by the CDS circuit 321 to the output amplifier 52, and outputs the image data held by the CDS circuit 322 to the output amplifier 53. To do. Subsequently, the horizontal scanning circuit 42 selects the CDS circuits 323 and 324, outputs the image data held by the CDS circuit 323 to the output amplifier 52, and outputs the image data held by the CDS circuit 324 to the output amplifier 53.

  Next, the vertical scanning circuit 21 selects the second row of the first pixel group, and causes the CDS circuit 31 to hold each image data read by each pixel G1 belonging to the second row of the first pixel group. (Period S22). In the present embodiment, as shown in FIG. 2, eight pixels A and B are alternately arranged in this order in the second row of the pixel array 10, and eight pixels in the first to eighth columns are arranged. Pixels A and B belong to the first pixel group. Therefore, the CDS circuits 311 to 318 hold the image data output from these eight pixels A and B.

  Further, the vertical scanning circuit 22 selects the second row of the second pixel group, and the CDS circuits 321 to 324 read the pixel data read by the four pixels C belonging to the second row of the second pixel group. (Period S32).

  Next, the horizontal scanning circuit 41 sequentially outputs the image data held by the CDS circuits 311 to 318 to the output amplifier 51 by horizontally scanning the CDS circuit 31 (period S22).

  Thereafter, the processes in the periods S21 and S22 are alternately repeated until the next vertical synchronization signal VD1 is output, and the image data of the third to eighth rows of the first pixel group are output to the output amplifier 51. By repeating these processes, the image data read by the first pixel group can be read at a low frame rate.

  Further, the horizontal scanning circuit 42 performs horizontal scanning on the CDS circuit 32 to sequentially output the image data held by the CDS circuits 321 to 324 to the output amplifiers 52 and 53 (period S32).

  Thereafter, the processes in the periods S31 and S32 are alternately repeated until the next vertical synchronization signal VD2 is output, and the image data of the third to fourth rows of the second pixel group are output to the output amplifiers 52 and 53. The By repeating these processes, the image data read by the second pixel group can be read at a high frame rate.

  As described above, according to the solid-state imaging device 1 of the first embodiment, the pixel array 10 is partitioned into the first and second pixel groups having different resolutions. The vertical scanning circuits 21 and 22, the CDS circuits 31 and 32, and the horizontal scanning circuits 41 and 42 correspond to the first and second pixel groups, respectively. The control unit 3 reads the vertical synchronization signals VD1 and VD2 and the horizontal synchronization signals HD1 and HD2 so that the image data read by the second pixel group is read at a higher frame rate than the image data read by the first pixel group. Is generated. Therefore, image data can be read from the pixel array 10 at a plurality of frame rates simultaneously. In this embodiment, the image data read by the second pixel group is read out at a frame rate four times that of the image data read by the first pixel group. However, the present invention is not limited to this. A value may be adopted.

(Embodiment 2)
Next, the solid-state imaging device 1 according to the second embodiment will be described. The solid-state imaging device 1 according to the second embodiment is characterized in that a color image is captured by the first pixel group. FIG. 4 is a diagram showing a detailed configuration of the pixel array 10 of the solid-state imaging device 1 according to the second embodiment. In the present embodiment, the same elements as those in the first embodiment are not described.

  In the second embodiment, R, G, and B primary color filters are provided in the first pixel group. In the example of FIG. 4, in each unit pixel unit 11, each of the three pixels of the first row, second column, second row, first column, and second row, second column that constitute the first pixel group is blue ( B), red (R), and green (G) primary color filters are provided. Further, in each unit pixel unit 11, the pixel indicated by W (white) in the first row and the first column is not provided with a primary color filter. Therefore, a monochrome image is obtained. Other configurations are the same as those of the pixel array 10 shown in FIG.

  As shown in FIG. 4, in each unit pixel unit 11, the pixels in the first row and the first column belong to the second pixel group. Therefore, in the first pixel group, the pixels in the first row and the first column of each unit pixel unit 11 are missing. Therefore, the image processing unit 5 performs color interpolation processing on the image data read by the first pixel group, and generates three full-color image data of R, G, and B composed of pixels of 8 rows × 8 columns. To do. Thereby, the missing pixel is interpolated in the image data read by the first pixel group. The first and second pixel groups output image data as in the first embodiment. Therefore, full-color image data composed of pixels of 8 rows × 8 columns and a monochrome image of 4 rows × 4 columns composed of a quarter of the number of pixels of 8 rows × 8 columns can be obtained simultaneously.

  Thus, according to the solid-state imaging device 1 according to the second embodiment, a full-color image can be obtained at a low frame rate, and a monochrome image can be obtained at a high frame rate. Therefore, for example, a high-resolution color image for human viewing and a low-resolution monochrome image for distance measurement can be acquired simultaneously, and a solid-state imaging device suitable for an in-vehicle sensor or the like can be provided.

  The arrangement of R, G, and B of the primary color filters in the unit pixel unit 11 is not limited to the arrangement shown in FIG. 4. For example, the first row and the second column are R, the second row and the first column are B, Another arrangement may be adopted so that the second row and the second column are G. Further, instead of the primary color filter, for example, a complementary color filter composed of cyan, magenta, and yellow may be employed. In this case, in the unit pixel unit 11, the colors of the complementary color filter may be arranged in the same arrangement as the arrangement of the colors of the primary color filter.

(Embodiment 3)
Next, the solid-state imaging device 1 according to Embodiment 3 will be described. The solid-state imaging device 1 according to Embodiment 3 is characterized in that a color image is captured by the first and second pixel groups. FIG. 5 is a diagram showing a detailed configuration of the pixel array 10 of the solid-state imaging device 1 according to the third embodiment. In the present embodiment, the same elements as those in the first and second embodiments are not described.

  As shown in FIG. 5, in the pixel array 10 of the third embodiment, a Bayer array primary color filter is provided in the second pixel group. The first pixel group is provided with the same primary color filter as in the second embodiment.

  Specifically, in the pixel array 10 shown in FIG. 5, the G primary color filter is provided for the pixels in the first row and the first column, and the B primary color filter is provided for the pixels in the first row and the third column. It can be seen that an R primary color filter is provided in the third row and first column, and a G primary color filter is provided in the third row and third column. Therefore, when attention is paid only to the second pixel group, it can be seen that the primary color filters are in a Bayer array.

  Then, the image processing unit 5 performs color interpolation processing on the image data read by the second pixel group in addition to the first pixel group, and performs R, G, Three full-color image data of B are generated.

  Thus, according to the solid-state imaging device 1 according to Embodiment 3, in addition to being able to obtain a full color image at a low frame rate, it is possible to obtain a full color image even at a high frame rate. In the third embodiment, the primary color filter is used for the first pixel group and the second pixel group. However, the present invention is not limited to this, and a complementary color filter may be used.

(Embodiment 4)
Next, the solid-state imaging device 1 according to Embodiment 4 will be described. The solid-state imaging device 1 according to Embodiment 4 is characterized in that the dynamic range of each pixel of the first pixel group is wider than the dynamic range of each pixel of the second pixel group. In the present embodiment, the same elements as in the first to third embodiments are not described.

  FIG. 6 is a graph showing the photoelectric conversion characteristics of each pixel constituting the pixel array 10. The vertical axis indicates the image signal (image data) linearly, and the horizontal axis indicates the incident light quantity in logarithm. In FIG. 6, K1 indicates a linear characteristic in which the output changes linearly with respect to the incident light amount, and K2 changes linearly with respect to the incident light amount up to the point P2, and output with respect to the incident light amount after the point P2. Indicates a logarithmic logarithmic characteristic that changes logarithmically. In the linear characteristic K1, when the amount of incident light increases to the point P1, the image signal is saturated and does not change any more. On the other hand, the linear log characteristic K2 has the same slope as the linear characteristic K1 up to the point P2, but after the point P2, the slope becomes smaller than the linear characteristic. For this reason, the linear log characteristic K2 has a wider dynamic range than the linear characteristic K1.

  Therefore, in the present embodiment, each pixel of the first pixel group is composed of pixels with linear log characteristics. As a result, the image picked up by the first pixel group has a wide dynamic range, and blackout and whiteout are prevented from occurring even in a scene with a light / dark difference, which makes it suitable for human viewing.

  On the other hand, the exposure time of a pixel with linear characteristics can be made shorter than that of a pixel with linear log characteristics. Therefore, each pixel of the second pixel group is composed of pixels with linear characteristics. Thereby, it becomes possible to read image data from the second pixel group at high speed, and an image suitable for sensing such as distance measurement to an obstacle and detection of an obstacle can be obtained.

  That is, in sensing, since it is important how fast an object that moves can be detected, a pixel having a linear characteristic capable of high-speed readout is suitable. Even if linear characteristics pixels are used, if the exposure time is short, whiteout is unlikely to occur. Therefore, an image suitable for sensing can be obtained by configuring the pixels of the second pixel group with pixels having linear characteristics.

  As described above, according to the solid-state imaging device 1 according to the fourth embodiment, each pixel of the first pixel group is configured with pixels having a linear log characteristic, and each pixel of the second pixel group is configured with pixels having a linear characteristic. A wide dynamic range image can be obtained from the first pixel group, and image data can be read from the second pixel group at high speed, which is suitable for sensing images and images suitable for human viewing. Can be obtained simultaneously.

(Embodiment 5)
Next, the solid-state imaging device 1 according to the fifth embodiment will be described. The solid-state imaging device 1 according to the fourth embodiment is characterized in that a voltage higher than the power supply voltage is applied to the transfer gate of each pixel of the second pixel group. In the present embodiment, the description of the same elements as in the first to fourth embodiments will be omitted.

  FIG. 7 shows a timing chart of the horizontal synchronization signal HD. The horizontal synchronization signal HD represents both the horizontal synchronization signal HD1 and the horizontal synchronization signal HD2. As shown in FIG. 7, in the 1H period, the pixel G1 reads the image data, and the CDS circuits 31 and 32 perform the CDS process on the image data output from the pixel G1, and the horizontal scanning circuits 41 and 42. Includes two periods, an “image reading” period in which the CDS circuits 31 and 32 are horizontally scanned to output image data.

  In order to realize high-speed imaging, one frame period must be shortened, and for that purpose, the 1H period must be shortened. If multi-line simultaneous readout such as 2-line and 4-line simultaneous readout is employed in the “image readout” period, the “image readout” period is ½ for 2-line simultaneous readout, and “image readout” for “4-line simultaneous readout”. The “reading” period becomes ¼, and the speed can be increased. However, the “pixel control & CDS” period cannot be shortened even if multi-line simultaneous readout is adopted. Therefore, there is a limit to shortening the 1H period.

  FIG. 8 is a circuit diagram of a typical 4T type pixel circuit, and FIG. 9 is a timing chart thereof. As shown in FIG. 8, the 4T-type pixel circuit includes one photodiode PD1 and four transistors Q1 to Q4 made of, for example, NMOS. Specifically, the photodiode PD1 has an anode grounded and a cathode connected to the transistor Q1.

  The transistor Q1 is connected to the power supply via the transistor Q2. Transistor Q4 is connected to the power supply via transistor Q3. The gate of the transistor Q3 is connected to the connection point between the transistors Q1 and Q2. Signals TX, RX, SX are applied to the gates of the transistors Q1, Q2, Q4. Hereinafter, the gates of the transistors Q1, Q2, and Q4 are referred to as a TX gate (transfer gate), an RX gate (reset gate), and an SX gate (row selection gate), respectively. The TX gate, RX gate, and SX gate are connected to the vertical scanning circuit.

  Specifically, each of the pixel control lines HL1 and HL2 includes three types of lines for passing signals TX, RX, and SX, and the TX gate, RX gate, and SX gate are vertically connected through corresponding lines. It is connected to the scanning circuits 21 and 22.

  Here, the transistor Q2 is for resetting the FD, the transistor Q1 is for transferring the charge accumulated in the photodiode PD1 to the FD, and the transistor Q4 functions as a row selection switch. Is.

  The vertical scanning circuits 21 and 22 include logic circuits that generate the signals TX, RX, and SX according to the vertical synchronization signal VD1 output from the control unit 3 and the signal output from the built-in shift register. Signals TX, RX and SX generated by the logic circuit are applied to the TX gate, RX gate and SX gate.

  In the “pixel control & CDS” period illustrated in FIG. 7, the 4T pixel circuit performs the following operations of steps ST1 to ST4 as illustrated in FIG. 9.

  Step ST1: In response to the high level of the signal RX, the RX gate is opened, and the floating diffusion (FD) is reset.

  Step ST2: In response to the high level of the signal SX, the SX gate is opened and a noise signal is output to the CDS circuit.

  Step ST3: In response to the high level of the signal TX, the TX gate is opened, and the charge accumulated in the photodiode PD1 is transferred to the FD.

  Step ST4: In response to the high level of the signal SX, the SX gate is opened, and a (noise + signal) signal is output to the CDS circuit.

  Thereafter, in the “image reading” period shown in FIG. 7, the CDS circuit subtracts the (noise + signal) signal output in step ST4 from the noise signal output in step ST2, and performs CDS processing.

  Here, in step ST3, a certain amount of time is required for the charge transfer from the photodiode PD1 to the FD, and in particular, a time of several microseconds is required to completely transfer the charge of the photodiode PD1 to the FD. End up. This is a disadvantageous condition for realizing high-speed shooting.

  FIG. 10 shows a potential diagram of the 4T type pixel circuit in the “pixel control & CDS” period. FIG. 10 is a potential diagram when the signal TX is at a high level. A high level voltage (usually equal to the power supply voltage VDD) is applied to the TX gate, and the TX gate is in an open state. Since the TX gate is in an open state, the electric charge accumulated in the photodiode PD1 is transferred to the FD. The charge of the photodiode PD1 is transferred to the FD using a potential gradient under the TX gate.

  FIG. 11 shows a potential diagram of the pixel circuit of each pixel G1 in the second pixel group in the fifth embodiment. As shown in FIG. 11, a voltage higher than the power supply voltage VDD is applied to the TX gate during charge transfer from the photodiode PD1 to the FD, the potential gradient grd under the TX gate is increased, and charges are quickly transferred from the photodiode PD1 to the FD. The time required for charge transfer can be shortened.

  In order to realize the above, in the solid-state imaging device 1 of the fifth embodiment, as shown in FIG. 12, the power supply voltage VDD is boosted to a predetermined voltage level, and the TX gate of each pixel of the second pixel group. Is further provided with a booster circuit 7 for applying to.

  The booster circuit 7 is provided in, for example, a logic circuit in the vertical scanning circuit 22 and applies a power supply voltage boosted to a predetermined level to the TX gate of each pixel of the second pixel group. The voltage level boosted by the booster circuit 7 may be a predetermined value that can increase the potential gradient grd under the TX gate to a predetermined level suitable for high-speed transfer. Note that the configuration of the pixel G1 is the same as that in FIG.

  FIG. 13 shows a timing chart of the pixel circuit shown in FIG. Steps ST1, ST2, and ST4 shown in FIG. 13 are the same as those in FIG. In step ST3, it can be seen that the signal TX is boosted by the booster circuit 7 and a voltage higher than the power supply voltage VDD is applied to the TX gate of each pixel of the second pixel group. Therefore, the potential gradient grd under the TX gate is increased, and charges can be quickly transferred from the photodiode PD1 to the FD. Note that a voltage of the power supply voltage VDD level is applied to the TX gate of each pixel G1 of the first pixel group as shown in step ST3 of FIG.

  As described above, according to the solid-state imaging device 1 according to the fifth embodiment, the voltage higher than the power supply voltage VDD is applied to the TX gate of each pixel G1 constituting the second pixel group by the booster circuit 7. Image data can be read from the pixel group at high speed.

(Embodiment 6)
Next, a solid-state imaging device 1 according to Embodiment 6 of the present invention will be described. In the solid-state imaging device 1 according to the sixth embodiment, the photodiode PD1 of each pixel of the second pixel group is configured with a surface-type photodiode capable of high-speed transfer, and the photodiode PD1 of each pixel of the first pixel group. Is composed of a complete transfer embedded type photodiode PD1 with high noise removal accuracy.

  14 shows a circuit diagram of a 3T type pixel circuit employed in the pixel G1 of the second pixel group in Embodiment 6, and FIG. 15 shows a timing chart thereof.

  The pixel G1 in the second pixel group can employ a 3T pixel circuit because the photodiode PD1 is a surface type. That is, since the concept of transferring charges is eliminated in a pixel including a surface type photodiode, charge transfer by a TX gate, which is necessary in a 4T type pixel circuit, is unnecessary.

  Therefore, in the “pixel control & CDS” period illustrated in FIG. 7, the 3T pixel circuit performs the following operations of steps ST1 to ST3 as illustrated in FIG. 15.

  Step ST1: In response to the high level of the signal SX, the SX gate is opened, and a (noise + signal) signal is output from the photodiode PD1 to the CDS circuit.

  Step ST2: The RX gate is opened in response to the high level of the signal RX, and the FD is reset.

  Step ST3: In response to the high level of the signal SX, the SX gate is opened and a noise signal is output to the CDS circuit.

  Thereafter, in the “image reading” period shown in FIG. 7, the CDS circuit subtracts the noise signal output in step ST3 from the (noise + signal) signal output in step ST1, and performs CDS processing.

  In this manner, when the 3T pixel circuit is employed, it is not necessary to apply the signal TX to the pixel G1, so that the “pixel control & CDS” period shown in FIG. 7 can be further shortened, and the frame rate can be reduced. It can be raised further.

  In the 4T type pixel circuit, as shown in FIG. 9, the noise signal output in step ST1 is the same as the noise signal (noise + signal) output in step ST4. It becomes possible to realize TrueCDS with high removal accuracy.

  On the other hand, in the 3T-type pixel circuit, as shown in FIG. 15, the noise signal output in step ST3 is a noise signal output after being reset in step ST2, and thus is output in step ST1 ( The noise signal is different from the noise signal. Therefore, TrueCDS is not realized, and the noise removal accuracy is reduced as compared with the 4T type pixel circuit.

  Therefore, in the solid-state imaging device 1 according to the sixth embodiment, the pixel G1 including the surface type photodiode PD1 that can adopt the 3T type pixel circuit is employed as each pixel G1 of the second pixel group. Image readout at a high frame rate is realized from the two pixel groups.

  On the other hand, high-quality image readout is realized by adopting the pixel G1 including the complete transfer embedded type photodiode PD1 that can adopt a 4T type pixel circuit as each pixel of the first pixel group. .

In the first to sixth embodiments, for convenience of explanation, the number of pixels of the pixel array 10 is 8 rows × 8 columns. However, this is only an example, and M (M is a positive integer of 2 or more) rows. You may arrange in xN (N is a positive integer of 2 or more) column. Further, although the first and second pixel groups and the two pixel groups are employed, the present invention is not limited to this, and the first to nth resolutions such that the resolution decreases as n (n is an integer of 2 or more) increases. These pixel groups may be adopted. In this case, each unit pixel unit 11 is partitioned into first to nth regions having different numbers of pixels in a fixed pattern, and pixels in the first to nth regions of each unit pixel unit 11 are first to nth. The pixel array 10 may be partitioned into n pixel groups. Then, n vertical scanning circuits, n CDS circuits, and n horizontal scanning circuits corresponding to each of the first to nth pixel groups may be provided. Then, the control unit 3 outputs n types of vertical synchronization signals and horizontal synchronization signals corresponding to the first to n-th pixel groups so that the frame rate of the image data output from the pixel group having a smaller number of pixels becomes higher. It only has to be generated. For example, if the period of the first to pixel groups of the vertical synchronization signal VD1~VDn of the n and VT1～VTn, if generating a vertical synchronizing signal VD1~VDn that satisfies _{VTi = (1 / k i)} · VT1 Good. However, i is 1 ≦ i ≦ n, and k _i = has a predetermined value that increases as i increases. Further, if the period of the horizontal synchronization signals HD1 to HDn of the first to nth pixel groups is HT1 to HTn, the horizontal synchronization signals HD1 to HDn satisfying HTi = (1 / j) · VTi may be generated. . However, j indicates the number of rows of the i-th pixel group when multiline simultaneous readout is not performed.

1 is an overall configuration diagram of a solid-state imaging device according to Embodiment 1 of the present invention. It is the figure which showed the detailed structure of the pixel array. 3 shows a timing chart of the solid-state imaging device. 6 is a diagram illustrating a detailed configuration of a pixel array of a solid-state imaging device according to Embodiment 2. FIG. 6 is a diagram illustrating a detailed configuration of a pixel array of a solid-state imaging device according to Embodiment 3. FIG. It is a graph which shows the photoelectric conversion characteristic of each pixel which comprises a pixel array. FIG. 10 is an explanatory diagram showing the background of the fifth embodiment. A circuit diagram of a typical 4T type pixel circuit is shown. 9 shows a timing chart of the pixel circuit of FIG. The potential diagram of a 4T type pixel circuit is shown. FIG. 10 shows a potential diagram of a pixel circuit in a fifth embodiment. FIG. 10 is a diagram illustrating a connection relationship between a pixel and a booster circuit in a solid-state imaging device according to a fifth embodiment. 13 is a timing chart of the pixel circuit shown in FIG. FIG. 25 is a circuit diagram of a 3T pixel circuit employed in a pixel of the second pixel group in the sixth embodiment. 15 is a timing chart of the pixel circuit shown in FIG. It is a block diagram of the conventional CMOS image sensor provided with the pixel array by which the pixel was arranged by 8 rows x 8 columns. It is a timing chart of the CMOS image sensor shown in FIG. It is a block diagram of a conventional CMOS image sensor that reduces the number of pixels in the vertical direction to 1/2 and performs two-line simultaneous readout. It is a timing chart of the CMOS image sensor shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 2 Sensor part 3 Control part 4 A / D conversion part 5 Image processing part 7 Booster circuit 10 Pixel array 11 Unit pixel part 21,22 Vertical scanning circuit 31,32 CDS circuit 41,42 Horizontal scanning circuit 51,52 , 53 Output amplifier D1 Photodiode G1 Pixel HD1, HD2 Horizontal synchronization signal HL1, HL2 Pixel control line PD1 Photodiode

Claims (13)

A solid-state imaging device comprising a pixel array composed of a plurality of pixels arranged in a matrix,
The pixel array is partitioned into first to nth pixel groups so that the resolution decreases as n (n is an integer of 2 or more) increases,
A first to n-th vertical scanning circuit corresponding to each of the first to n-th pixel groups and vertically scanning the first to n-th pixel groups according to a vertical synchronization signal;
Corresponding to each of the first to nth pixel groups, image data for one row selected by the vertical scanning of the first to nth vertical scanning circuits is read from the first to nth pixel groups. First to n-th readout circuits held by
A row corresponding to each of the first to n-th pixel groups and one row held by the first to n-th read circuits by horizontally scanning the first to n-th read circuits according to a horizontal synchronization signal. For the first to nth horizontal scanning circuits for sequentially outputting image data for the first to nth readout circuits,
N types of vertical synchronization signals corresponding to the first to n-th pixel groups are generated so that the frame rate of the image data read by the large pixel group is relatively high, A control unit that outputs to the nth vertical scanning circuit, generates n types of horizontal synchronization signals corresponding to the first to nth pixel groups, and outputs to the first to nth horizontal scanning circuits; A solid-state imaging device comprising: The pixel array is partitioned into unit pixel units each including a predetermined number of pixels.
Each unit pixel unit is partitioned into first to nth regions having different numbers of pixels in a fixed pattern,
2. The solid-state imaging device according to claim 1, wherein pixels in the first to n-th regions of each unit pixel unit are assigned to the first to n-th pixel groups.   Each pixel belonging to the first to nth pixel groups is connected to the first to nth vertical scanning circuit via a pixel control line in a row corresponding to the row to which the pixel belongs, and the column to which the pixel belongs. 3. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is connected to the first to n-th readout circuits via vertical signal lines in columns corresponding to. The first to nth pixel groups include first and second pixel groups,
The first pixel group has a higher resolution than the second pixel group,
The first pixel group outputs a color image;
The solid-state imaging device according to claim 1, wherein the second pixel group outputs a monochrome image.   The solid-state imaging device according to claim 4, wherein each pixel of the first pixel group includes a primary color filter.   The solid-state imaging device according to claim 4, wherein each pixel of the first pixel group includes a complementary color filter. The first to nth pixel groups include first and second pixel groups,
The first pixel group has a higher resolution than the second pixel group,
The solid-state imaging device according to claim 1, wherein both the first and second pixel groups output a color image.   The solid-state imaging device according to claim 7, wherein the first and second pixel groups include a primary color filter.   The solid-state imaging device according to claim 7, wherein the first and second pixel groups include complementary color filters. Each pixel of the first pixel group has a characteristic that the output changes linearly with respect to the incident light and a characteristic that the output changes logarithmically with respect to the incident light,
10. The solid-state imaging device according to claim 4, wherein each pixel of the second pixel group has a characteristic that an output changes linearly with respect to incident light. Each pixel of the second pixel group includes a transfer gate,
The solid-state imaging device according to claim 4, further comprising a boosting circuit that boosts a power supply voltage and applies the boosted voltage to the transfer gate.   Each of the pixels of the second pixel group is different from the photodiode of each pixel of the first pixel group in order to output image data at high speed. Item 12. The solid-state imaging device according to any one of Items 4 to 11. Each pixel of the first pixel group includes a fully transfer embedded photodiode,
The solid-state imaging device according to claim 12, wherein each pixel of the second pixel group includes a surface-type photodiode.

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