JP2009271941A5

JP2009271941A5 -

Info

Publication number: JP2009271941A5
Application number: JP2009188474A
Authority: JP
Filing date: 2009-08-17
Publication date: 2010-02-04
Anticipated expiration: 2023-07-30

Claims

A memory circuit;
A logic circuit for generating control information for matching the frequency of the internal clock signal with the frequency of the external clock signal generated externally and storing the control information in the storage circuit;
An oscillation circuit for generating an internal clock signal based on the control information held in the storage circuit;
A non-volatile storage device for storing the control information ;
A first operation mode in which the external clock signal is supplied via a terminal, and the control information for making the frequency of the internal clock signal coincide with the frequency of the external clock signal;
A second operation mode in which the oscillation circuit generates the internal clock signal based on the control information and supplies the internal clock signal to the logic circuit;
The oscillation circuit is
A voltage controlled oscillation circuit capable of controlling an oscillation frequency of the internal clock signal based on the control information generated in the first operation mode;
A D / A conversion circuit for converting the control information into an analog conversion reference voltage;
A bias circuit that forms a bias voltage based on the output voltage of the D / A converter circuit;
An external clock signal supplied via the terminal, and a selection circuit for supplying any one of the clock signals generated by the voltage-controlled oscillation circuit to the logic circuit,
The voltage controlled oscillation circuit has a ring oscillator unit in the form of a CMOS circuit, and an oscillation frequency is controlled by the bias voltage for current control with respect to the ring oscillator unit,
The bias circuit applies an operation power supply voltage in a direction to suppress fluctuations in the logic threshold voltage of the CMOS circuit to the voltage controlled oscillation circuit,
In the first operation mode, the logic circuit updates the control information in a direction to match the frequency of the internal clock signal with the frequency of the external clock signal supplied from the outside through the terminal. Generating the control information for adjusting the frequency of the clock signal;
Using the internal clock signal for the synchronous operation of the internal circuit,
The semiconductor integrated circuit, wherein the control information stored in the non-volatile memory device is loaded into the memory circuit after the semiconductor integrated circuit is reset.

The first operation mode is a frequency setting mode,
The second operation mode is a normal mode,
The first operation mode and the second operation mode are determined according to a mode signal supplied from the outside of the semiconductor integrated circuit,
The terminal is a shared terminal with the input of the external clock signal,
The internal clock signal generated by the oscillation circuit can be output to the outside of the semiconductor integrated circuit,
The semiconductor integrated circuit according to claim 1 , wherein the logic circuit generates the control information according to the mode signal .

3. The semiconductor integrated circuit according to claim 2, wherein in the first operation mode, an operation of generating and storing control information in synchronization with an external clock signal input from the terminal is performed.

3. The semiconductor integrated circuit according to claim 2, wherein in the first operation mode, the logic circuit performs an operation of generating control information in synchronization with an external clock signal.

In the first operation mode, an initial value is set in the storage circuit after reset is released, and the value of the storage circuit is updated in a direction to match the frequency of the internal clock signal with the frequency of the external clock signal. The semiconductor integrated circuit according to claim 3 or 4 .

Further comprising a sampling circuit for sampling said internal clock signal and the external clock signal,
Before Symbol logic, the direction in which the using information sampled by the sampling circuit have line frequency comparison of the internal clock signal and the external clock signal, to match the frequency of the internal clock signal to the frequency of the external clock signal 2. The semiconductor integrated circuit according to claim 1, wherein control information is generated.

7. The semiconductor integrated circuit according to claim 5, wherein the logic circuit is a CPU, and the storage circuit is a register accessible by the CPU.

And a comparison circuit that compares the frequency difference between the internal clock signal and the external clock signal.
The logic circuit is a semiconductor integrated circuit according to claim 1, wherein the generating control information to match the internal clock signal frequency using a comparison result by the comparison circuit to the external clock signal frequency.

The memory circuit is a counter;
The logic circuit is a semiconductor integrated circuit according to claim 1, characterized in that said internal clock signal and compares the difference in the frequency of the external clock signal, it counts up also counts down the counter with a comparison result.

The logic circuit receives the frequency comparison result of the external clock signal from the internal clock signal and the external externally, control information for matching the internal clock signal frequency by referring to the comparison result input to the external clock signal frequency The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is generated.

The voltage controlled oscillation circuit uses a voltage determined based on an output voltage of the D / A conversion circuit as an operation power supply voltage, and an oscillation frequency is controlled by the bias voltage.
The bias circuit has a constant current circuit including a MOS transistor that satisfies a gate-source voltage condition in which a change in drain-source current with respect to a temperature change is reduced, and the drain voltage of the MOS transistor is controlled by a control voltage. the semiconductor integrated circuit according to claim 1 or 5, wherein the output as.

The constant current circuit includes a p-channel first MOS transistor having a power supply voltage received at the source and a short circuit between the gate and the drain, and an n-channel type first MOS transistor having the circuit ground voltage received at the source and a short between the gate and the drain. A resistance element having one end coupled to the drain of the first MOS transistor and the other end coupled to the drain of the second MOS transistor;
12. The semiconductor integrated circuit according to claim 11, wherein the drain voltage of the first MOS transistor and the drain voltage of the second MOS transistor are output as control voltages.

The output voltage of the D / A conversion circuit, a semiconductor integrated circuit according to claim 12, characterized in that it is supplied as an operating power supply voltage of the voltage controlled oscillation circuit and the bias circuit through a voltage follower amplifier.

Furthermore, it has a reference voltage generating circuit for generating a reference voltage voltage variation with respect to variation in power supply voltage and temperature are compensated,
The semiconductor integrated circuit according to claim 11, wherein the pre-SL D / A converter circuit, characterized by inputting the reference voltage as the conversion reference voltage.

Before SL bias circuit claims, characterized in that to compensate for variations in the oscillation frequency of the logic threshold voltage is applied an operating power supply voltage direction of suppressing the variation ring oscillator unit according to the temperature change of the CMOS circuit to the oscillator circuit 2. The semiconductor integrated circuit according to 1.

The voltage controlled oscillation circuit has an odd number of stages of CMOS inverter delay stages constituting a ring oscillator section,
The bias circuit includes a logic threshold voltage simulation circuit unit that simulates a logic threshold voltage of the CMOS inverter delay stage, and changes an operation power supply voltage of the oscillation circuit using an output of the logic threshold voltage simulation circuit. The semiconductor integrated circuit according to claim 15.

Furthermore, have a reference voltage generating circuit for generating a reference voltage voltage variation with respect to variation in power supply voltage and temperature are compensated, the D / A conversion circuit is characterized by inputting the reference voltage as the conversion reference voltage The semiconductor integrated circuit according to claim 15.

Have a variable frequency divider for dividing a clock signal output from said oscillation circuit,
The variable divider receives the output of said selection circuit, wherein, when the second operation mode, the semiconductor integrated circuit according to claim 1 or 5, wherein the outputting the internal clock signal by dividing .

A memory circuit;
An oscillation circuit for generating an internal clock signal have groups Dzu the control information held in the storage circuit,
A non-volatile storage device for storing the control information ;
Outputting the internal clock signal generated by the oscillation circuit to the outside, a frequency setting mode for generating control information for controlling the frequency of the internal clock signal in a direction that matches the frequency of the external clock signal;
A normal mode in which the oscillation circuit generates an internal clock signal based on the control information generated in the frequency setting mode and supplies the internal clock signal to the semiconductor integrated circuit, and
The oscillation circuit has a voltage controlled oscillation circuit capable of controlling an oscillation frequency of the internal clock signal based on the control information generated in the frequency setting mode.
In the normal mode, the control information stored in the nonvolatile storage device is loaded into the storage circuit after resetting the semiconductor integrated circuit,
The output terminal of the internal clock signal is a dual-purpose terminal,
The internal clock signal can be output to the outside of the semiconductor integrated circuit in the frequency setting mode,
A semiconductor integrated circuit characterized in that the internal clock signal is used for a synchronous operation of an internal circuit.

A memory circuit;
An oscillation circuit for generating an internal clock signal have groups Dzu the control information stored in the storage circuit,
A logic circuit that counts the internal clock signal at regular intervals of periodically generated pulses and updates the control information in a direction to match the count value with an expected value;
A non-volatile storage device,
A first operation mode for updating and generating control information for matching the frequency of the internal clock signal to an expected value;
A second operation mode for generating the internal clock signal based on the control information generated in the first operation mode,
The nonvolatile memory device has control information that is initially loaded into the memory circuit in response to a reset in the first operation mode, and the expected value that is loaded into the logic circuit,
A semiconductor integrated circuit characterized in that the internal clock signal is used for a synchronous operation of an internal circuit.

It has an interval generation circuit that periodically generates a constant interval of pulses, and this interval generation circuit is either a charging operation or a discharging operation from a pulse generation circuit and a predetermined phase point of a pulse generated from the pulse generation circuit. And a detection circuit for detecting that the voltage obtained by the CR time constant circuit reaches a specified voltage, and the period from a predetermined phase point to a detection timing by the detection circuit is defined as the constant interval. 21. The semiconductor integrated circuit according to claim 20, wherein:

22. The reference voltage according to claim 21, wherein the prescribed voltage is formed based on a reference voltage generated by a reference voltage generation circuit, and the reference voltage is a voltage in which voltage fluctuations with respect to fluctuations in power supply voltage and temperature are compensated. Semiconductor integrated circuit.

The semiconductor integrated circuit according to claim 21, wherein the memory circuit is an up / down counter.

24. The semiconductor integrated circuit according to claim 23, wherein the up / down counter performs up-counting or down-counting in synchronization with a pulse generated from the pulse generating circuit.

A D / A conversion circuit that converts the control data held by the storage circuit into analog with respect to a conversion reference voltage; and a bias circuit that forms a bias voltage that changes according to the output voltage of the D / A conversion circuit. Have
Before SL oscillation circuit, a semiconductor integrated circuit according to claim 20, wherein the oscillation frequency by the bias voltage is a voltage controlled oscillator which is controlled.

2. A reference voltage generation circuit for generating a reference voltage that compensates for voltage fluctuations with respect to power supply voltage and temperature fluctuations, wherein the D / A conversion circuit inputs the reference voltage as a conversion reference voltage. 25. The semiconductor integrated circuit according to 25.

21. The semiconductor integrated circuit according to claim 20, wherein the nonvolatile memory device can electrically rewrite stored information.

A memory circuit;
A control circuit that adjusts the frequency of the internal clock signal based on a predetermined pulse signal input from the outside via a terminal ;
An oscillation circuit for generating an internal clock signal based on the control information held in the storage circuit;
A nonvolatile storage device for storing the control information,
The oscillation circuit is
A voltage controlled oscillation circuit for generating the internal clock signal based on the control information;
The output of the voltage controlled oscillation circuit is input, and at the time of normal operation, the internal clock signal is divided, and a variable frequency divider that can be changed to an arbitrary frequency is provided.
Wherein the control circuit, when the setting mode of the internal clock signal frequency, the frequency of the internal clock signal have line frequency comparison of the predetermined pulse signal, for controlling so as to match the frequency of the predetermined pulse signal and of generating the control information,
The generated control information is stored in the nonvolatile memory at the end of the control information generation,
Wherein said control information stored in the nonvolatile storage device, after the reset of the semiconductor integrated circuit during the normal operation, is loaded in the storage circuit,
The terminal is a shared terminal with a predetermined pulse signal input,
A semiconductor integrated circuit characterized in that the internal clock signal is used for a synchronous operation of an internal circuit.

29. The semiconductor integrated circuit according to claim 1, wherein the control circuit is capable of dynamically adjusting an internal clock signal.

30. The semiconductor integrated circuit according to claim 29, wherein the control circuit is capable of sequentially updating the control information by adjusting a frequency of the internal clock signal .

31. The semiconductor integrated circuit according to claim 30, wherein the variable frequency divider can adjust the internal clock signal to an arbitrary frequency by command execution by the control circuit.

Further, a selector capable of selecting the internal clock signal and the external clock signal is provided, the output of the selector is input to the variable frequency dividing circuit, and the output of the variable frequency dividing circuit is used for the synchronous operation of the internal circuit. 32. The semiconductor integrated circuit according to claim 31 , wherein the semiconductor integrated circuit is used.

A central processing unit;
An internal oscillation circuit module capable of generating an internal clock signal used for the operation of the internal circuit including the central processing unit, and
The internal oscillation circuit module is:
A register for storing control information;
A voltage controlled oscillation circuit whose oscillation frequency is controlled based on the control information;
A frequency divider for dividing the output of the voltage controlled oscillator circuit;
In the setting mode, set the initial value to the register,
The frequency of the signal supplied from the outside is compared with the oscillation frequency of the output,
When the frequency comparison result does not match, new control information is set in the register,
When the comparison result is coincident, the control information stored in the register is stored in a nonvolatile memory,
A microcomputer formed on a semiconductor chip in which the voltage-controlled oscillation circuit is controlled in oscillation frequency in accordance with the control information stored in the register from the nonvolatile memory after reset in the normal mode.

The microcomputer is
A D / A conversion circuit for analog-converting the control information stored in the register with respect to a conversion reference voltage in the normal mode;
A bias circuit that forms a bias voltage according to the control information based on the output voltage of the D / A conversion circuit,
34. The microcomputer according to claim 33, wherein the voltage-controlled oscillation circuit has a ring oscillator unit in a CMOS circuit format, and an oscillation frequency is controlled by the bias voltage for current control with respect to the ring oscillator unit.

35. The microcomputer according to claim 34, wherein when the comparison result does not match in the setting mode, new control information for matching the frequency of the internal clock signal and the signal supplied from the outside is set in the register. .

Furthermore, it has a terminal for inputting a signal supplied from the outside,
36. The microcomputer according to claim 35, wherein the terminal is multiplexed with an input terminal function of a signal supplied from the outside and other signal terminal functions.

37. The microcomputer according to claim 36, wherein the nonvolatile memory is built in the microcomputer.

37. The microcomputer according to claim 36, wherein the nonvolatile memory is formed on a semiconductor chip different from the semiconductor chip.

A central processing unit;
An oscillation circuit capable of generating an internal clock signal to be supplied to an internal circuit including a central processing unit;
And a terminal for inputting a signal supplied from the outside in the frequency setting mode,
The oscillation circuit is
A register for storing control information;
A bias circuit that generates a control voltage according to the control information;
A voltage controlled oscillation circuit in which an oscillation frequency is controlled according to a control voltage output from the bias circuit;
A frequency divider that divides the output of the voltage-controlled oscillation circuit and supplies it to an internal circuit;
When in frequency setting mode
An initial value is set in a register that stores control information for trimming the frequency of the internal clock signal,
The frequency of the signal supplied from the outside through the terminal is compared with the frequency of the internal clock signal,
When the frequency of the internal clock signal and the signal supplied from the outside is different, the control information stored in the register is changed to approximate the frequency of the signal supplied from the outside,
When the frequency matches, the change of the control information is terminated,
In normal mode, frequency control of the voltage controlled oscillation circuit is performed based on the control information changed in the frequency setting mode,
The terminal is a microcomputer formed on one semiconductor substrate in which an input terminal function of a signal supplied from the outside and other signal terminal functions are multiplexed.

The changed control information is stored in a nonvolatile memory at the time of the frequency setting mode,
When the previous SL normal mode, are stored after the reset is read out from the nonvolatile memory to the register,
40. The microcomputer according to claim 39, wherein the oscillation circuit is capable of generating an internal clock signal in accordance with control information stored in the register.