JP2009271597A - Processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a circuit scale, facilitate the control of setting timing, and also reduce power consumption by previously setting a part of address information and attribute information held in a register by a combining circuit as a constant value. <P>SOLUTION: A processor 1 includes: a processor core 11a to be connected to a bus 13; and a memory protecting device 12a which is arranged in the processor core 11a, which is a unit to monitor the address of a memory in performing access to a memory via the bus 13 and the attribute of an instruction of a program to be performed in the processor core 11a, to perform comparison with the predetermined address and attribute, and to announce the occurrence of an exception to the processor core 11a in the case of non-coincidence, and which sets a part of the predetermined address and attribute in the register via the processor core 11a, and outputs the other part of the predetermined address and attribute by the combining circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a processor, and more particularly to a processor having a memory protection device that monitors access to a memory.

  Conventionally, in a processor or a multiprocessor, a plurality of programs are executed in parallel, and one memory may be shared among the plurality of programs. For example, a host processor that operates a user interface program or an operating system (hereinafter referred to as an OS) and an application processor that operates an application program that processes audio data, video data, etc. share one SDRAM and operate. This is the case.

  When one memory is accessed by a program executed on each processor, for example, one program mistakenly writes another program or the program area or stack area of the OS, or another program intentionally. Alternatively, a malfunction such as unauthorized use of an OS program or data, that is, a memory access violation may occur.

  Possible causes of such malfunctions include program bugs, soft errors, and intentional attacks. Program bugs include, for example, stack overflow, misplacement of pointers, misunderstanding of specifications or arrangements between processors or programs, and malfunction of software IP purchased or introduced during development. A soft error is, for example, a case where information in a memory is rewritten by radiation from space. The intentional attack is, for example, a case where a malicious virus is mixed in a program downloaded by a user after commercialization.

  Therefore, a memory protection device is known as a device for monitoring such a malfunction. This memory protection device is a device that monitors the access of a certain program to the memory and prevents any other task from being adversely affected if a memory access violation occurs. If this memory protection device defines attributes such as writable and executable in each area in advance, an exception or a trap is generated before the access is executed for an attribute violation access. This memory protection device may be merged into a memory management unit (MMU).

  As such a memory protection device, a program control unit that monitors load, execution, stop, and termination of a program, a program area generation unit that generates an attribute and registers it in the attribute area for each program, and a program being executed A memory attribute management method having an access check mechanism for checking memory access in units of programs has been proposed (see, for example, Patent Document 1).

However, such a memory protection device uses a register to hold address information and attribute information. The register has a large circuit scale, and when address information and attribute information are set in the register, it is difficult to control the setting timing, and there is a problem of increasing power consumption.
JP 2001-56783 A

  Therefore, the present invention reduces the circuit scale, facilitates the control of the setting timing, and consumes a part of the address information and attribute information held in the register by setting them as constant values in advance by the combinational circuit. It is an object of the present invention to provide a processor capable of reducing power.

  According to one aspect of the present invention, a processor core connected to a bus, and the memory provided in the processor core and accessing the memory via the bus by executing a program in the processor core The address and attribute of the program executed in the processor core are compared, and the address and attribute obtained by monitoring are compared with a plurality of preset addresses and attributes, and the monitoring is performed. When the whole or part of the bit string and attribute of the address bit string obtained in this way does not match the whole or part of the bit string and attribute of the preset address, an exception of address violation or attribute violation And a unit for notifying the processor core of the occurrence of the exception, The plurality of addresses and some of the plurality of attributes are set in a register through the processor core, and the other parts of the plurality of preset addresses and the plurality of attributes are output by a combinational circuit. It is possible to provide a processor including a memory protection unit.

  According to the processor of the present invention, part of the address information and attribute information held in the register is set in advance as a constant value by the combinational circuit, thereby reducing the circuit scale, facilitating the control of the setting timing, and , Power consumption can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, the configuration of a processor according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing an overall configuration of a processor according to the present embodiment.

  As shown in FIG. 1, the processor 1 includes processor cores (hereinafter referred to as cores) 11a and 11b, memory protection devices (hereinafter referred to as APU (Address Protection Unit)) 12a and 12b, a bus 13, and a shared memory. The memory 14 is configured as a one-chip semiconductor device. In addition, in this Embodiment, although it has two cores, you may have one core or three or more cores.

  The cores 11 a and 11 b are connected to the memory 14 via the bus 13. The APUs 12a and 12b monitor access to the memory from the cores 11a and 11b, respectively. More specifically, the APU 12a monitors the address of the memory 14 when accessing the memory 14 via the bus 13 and the attribute of the instruction of the program executed in the core 11a by executing the program in the core 11a. . Similarly, the APU 12b monitors the address of the memory 14 when accessing the memory 14 via the bus 13 and the instruction attribute of the program executed in the core 11b by executing the program in the core 11b.

  Here, the attribute of the instruction is information such as the type of instruction such as read (R) and write (W), the priority, etc. with respect to the address of the memory area accessed by the program to be executed.

  Note that the memory 14 may be outside the chip. Further, the processor 1 may be configured to have local memories 15a and 15b in the cores 11a and 11b, respectively, as indicated by dotted lines in FIG.

  Here, the configuration of the cores 11a and 11b and the APUs 12a and 12b will be described with reference to the configurations of the core 11a and the APU 12a. FIG. 2 is a block diagram showing the configuration of the core and the APU.

  As shown in FIG. 2, the APU 12 a includes an address / attribute comparison unit 16. The address / attribute comparison unit 16 has a plurality of address / attribute setting units to be described later, a part of the plurality of address / attribute setting units can be set, and the other part is fixed. . The core 11a sets address information SAD and attribute information SAT in the address / attribute comparison unit 16 of the APU 12a by a setting program. Address information AD to the address bus of the bus 13 is input to the APU 12a, and attribute information ID corresponding to the input address information AD is input from the core 11a. The APU 12a compares the address information AD and the attribute information ID with the address information SAD and the attribute information SAT set through the setting program. If there is an address violation or an attribute violation, the APU 12a generates an exception signal EX. EX is output to the core 11a. That is, the APU 12a is a unit that generates an exception signal EX for address violation or attribute violation and notifies the generated exception signal EX to the core 11a.

  Specifically, the APU 12 matches the whole or part of the bit string of the input address with the whole or part of the bit string of the address set through the setting program. An attribute violation exception signal EX is generated when the input attribute does not match the attribute set through the setting program at the address. Here, the partial bit string of the address is a predetermined upper bit portion of the address. This is because whether or not the input address is included in the set memory area can be determined based on whether or not the upper bit portion indicating the range of the area matches. Therefore, in such a case, it is not necessary to compare all of the addresses. For example, if an attribute is specified for each 1 kilobyte area, it is not necessary to compare the lower 10 bits of the address. That is, the lower 10 bits of the address are masked, and only predetermined upper bits are compared.

  Here, the address violation means that the address information ID to the address bus of the bus 13 does not match the address information SAD set through the setting program or the address information output as a constant value described later. . The attribute violation means that the attribute information ID corresponding to the input address information AD does not match the attribute information SAT set through the setting program or the attribute information output as a constant value described later. Say.

  Next, a detailed configuration of the APU 12a will be described. FIG. 3 is a block diagram showing a detailed configuration of the APU.

  As shown in FIG. 3, the APU 12a includes a core interface (hereinafter referred to as a core I / F) 21, which is an interface with the core 11a, an address / attribute comparison unit 16, and an OR circuit 22. Yes. The core I / F 21 and the OR circuit 22 may be in the core 11a.

  The address / attribute comparison unit 16 includes a comparison unit 41 and a comparison unit 42. The comparison unit 41 includes an address / attribute setting unit 51, an enable signal setting unit (hereinafter referred to as EN) 52, an address comparison unit 53, an attribute comparison unit 54, and an AND circuit 55. . The comparison unit 42 includes an address / attribute setting unit 61, an EN 62, an address comparison unit 63, an attribute comparison unit 64, and an AND circuit 65.

  The setting information from the core 11a is memory area address information SAD used by the program and attribute information SAT of this memory area. Setting information from the core 11a is output to the address / attribute setting unit 51 via the core I / F 21 and set. Furthermore, the core 11a outputs enable information to the EN 52 and EN 62 via the core I / F 21 and can be set.

  The address / attribute setting unit 51 includes a register group including a plurality of registers, and holds address information SAD and attribute information SAT from the core I / F 21. Here, the address information includes start address, end address, size, and invalid area information, and the attribute information includes read (R), write (W), execute (Ex), and cache (C ) And priority information. All of these pieces of information may not be set in the address / attribute setting unit 51, and only necessary information may be set.

  The address / attribute setting unit 51 outputs the address information AD1 set via the core I / F 21 to the address comparison unit 53. Similarly, the attribute / ID setting unit 51 sets the attribute information ID1 set via the core I / F 21 to the attribute comparison unit. To 54. The address comparison unit 53 compares the address information AD to the address bus of the bus 13 with the address information AD1 from the address / attribute setting unit 51 and outputs the comparison result to the attribute comparison unit 54.

  The attribute comparison unit 54 compares the attribute information ID from the core 11 a with the attribute information AD 1 from the address / attribute setting unit 51, and outputs the comparison result to the AND circuit 55. The attribute information ID may be input to the attribute comparison unit 54 via the core I / F 21. The AND circuit 55 performs an AND operation on the output of the attribute comparison unit 54 and the output of the EN 52, and outputs the operation result on which the AND operation has been performed to the OR circuit 22.

  On the other hand, the address / attribute setting unit 61 is configured by a combinational circuit, and is configured to output address information and attribute information that do not need to be dynamically changed as constant values in advance. The combinational circuit is a circuit in which an output signal is uniquely determined by an input signal, and a predetermined output can be obtained by applying a predetermined voltage. The address information and attribute information output from the address / attribute setting unit 61 has the same signal format as the address information and attribute information held by the address / attribute setting unit 51 described above. The address / attribute setting unit 61 outputs the address information AD2 output as a constant value signal in advance by the combinational circuit to the address comparison unit 63. Similarly, the attribute information ID2 output as the constant value signal in advance by the combinational circuit. Is output to the attribute comparison unit 64. The address comparison unit 63 compares the address information AD to the address bus of the bus 13 with the address information AD2 from the address / attribute setting unit 61 and outputs the comparison result to the attribute comparison unit 64.

  The attribute comparison unit 64 compares the attribute information ID from the core 11 a with the attribute information ID 2 from the address / attribute setting unit 61 and outputs the comparison result to the AND circuit 65. The AND circuit 65 performs an AND operation on the output of the attribute comparison unit 64 and the output of the EN 62, and outputs the operation result on which the AND operation has been performed to the OR circuit 22.

  The OR circuit 22 performs an OR operation on the operation results output from the AND circuit 55 and the AND circuit 65, and outputs the operation result on which the OR operation has been performed to the core 11a. That is, the calculation result is output from the APU 12a to the core 11a as the exception signal EX.

  Specifically, the APU 12 matches the whole or part of the bit string of the input address with the whole or part of the bit string of the address set through the setting program. An attribute violation exception signal EX is generated when the input attribute does not match the attribute set through the setting program at the address.

  Here, a program for setting address information and attribute information in a register will be described. FIG. 4 is an explanatory diagram for explaining an example of a program for setting address information and attribute information in a register.

  As shown in FIG. 4, the program 71 stores programs such as an OS, a user interface, an application A, and an application B. Further, the program 71 has a hatched area indicated by arrows 72 and 73, and instructions for setting address information and attribute information in the register group of the address / attribute setting unit 51 are stored in this area. ing. Instructions for setting address information and attribute information for application A are stored in the hatched area indicated by arrow 72, and address information and attribute information for application B are set in the hatched area indicated by arrow 73. Instructions to store are stored.

  That is, the core 11a sets the address information and attribute information for the application A in the address / attribute setting unit 51 by executing the instruction stored in the shaded area indicated by the arrow 72 before executing the application A. can do.

  Similarly, the core 11a executes the instruction stored in the shaded area indicated by the arrow 73 before executing the application B, thereby causing the address / attribute setting unit 51 to send the address information and attribute information for the application B. Can be set.

  This embodiment is characterized in that part of address information and attribute information held in a register is set in advance as a constant value by a combinational circuit. For example, address information and attribute information such as application programs or tasks are set in a register via a program because the memory usage area and the like differ for each application. On the other hand, address information and attribute information such as user interface programs or tasks and OSs are set in advance as constant values by a combinational circuit because the memory use area and the like are not changed.

Next, the operation of the embodiment configured as described above will be described.
First, address information SAD and attribute information SAT for memory protection are output from the core 11a to the APU 12a. The address information SAD and attribute information SAT output from the core 11a are set in a predetermined area configured by the register of the address / attribute setting unit 51 via the core I / F 21.

  From the address / attribute setting unit 51, the address information AD1 and the attribute information ID1 set in the register are output to the address comparison unit 53 and the attribute comparison unit 54, respectively. The address comparison unit 53 compares the address information AD to the address bus of the bus 13 with the address information AD1 from the address / attribute setting unit 51, and detects whether there is an address violation. A detection result indicating whether or not there is an address violation is output to the attribute comparison unit 54.

  The attribute comparison unit 54 compares the attribute information ID from the core 11a with the attribute information ID1 from the address / attribute setting unit 51, and detects whether there is an attribute violation. The attribute comparison unit 54 outputs 1 to the AND circuit 55 when an address violation or attribute violation is detected, and outputs 0 to the AND circuit 55 when no address violation or attribute violation is detected. Further, from EN 52, when enable is valid, 1 is output to AND circuit 55, and when enable is invalid, 0 is output to AND circuit 55. The AND circuit 55 performs an AND operation on the output from the attribute comparison unit 54 and the output from the EN 52. That is, the AND circuit 55 outputs 1 to the OR circuit 22 only when an address violation or attribute violation is detected and the enable is valid.

  On the other hand, the address / attribute setting unit 61 outputs the address information AD2 and the attribute information ID2 that are previously held as constant values by the combinational circuit to the address comparison unit 63 and the attribute comparison unit 64, respectively. The address comparison unit 63 compares the address information AD to the address bus of the bus 13 and the address information AD2 from the address / attribute setting unit 61, and detects whether there is an address violation. A detection result indicating whether or not there is an address violation is output to the attribute comparison unit 64.

  The attribute comparison unit 64 compares the attribute information ID from the core 11a with the attribute information ID2 from the address / attribute setting unit 61, and detects whether there is an attribute violation. The attribute comparison unit 64 outputs 1 to the AND circuit 65 when an address violation or attribute violation is detected, and outputs 0 to the AND circuit 65 when no address violation or attribute violation is detected. Further, from EN 62, 1 is output to the AND circuit 65 when the enable is valid, and 0 is output to the AND circuit 65 when the enable is invalid. The AND circuit 65 performs an AND operation on the output from the attribute comparison unit 64 and the output from the EN 62. That is, the AND circuit 65 outputs 1 to the OR circuit 22 only when an address violation or attribute violation is detected and the enable is valid.

  In the OR circuit 22, an OR operation between the output of the AND circuit 55 and the output of the AND circuit 65 is performed. When the output of either the AND circuit 55 or the AND circuit 65 is 1, 1 is output from the OR circuit 22. That is, when an address violation or an attribute violation is detected in either the comparison unit 41 or the comparison unit 42, the result of the OR operation becomes 1, and the exception signal EX for notifying the occurrence of an exception from the OR circuit 22 is output from the core 11a. Is output.

  The enable signals output from each of EN52 and EN62 are signals for controlling the comparison unit 41 and the comparison unit 42, and by controlling these enable signals, the comparison result of the corresponding comparison unit is validated or Can be disabled.

  As described above, part of the address information and attribute information held in the register is set in advance as a constant value by the combinational circuit. As a result, the circuit area can be reduced by combining the area configured by the register into a combinational circuit, and when setting address information and attribute information in the register, the setting timing can be easily controlled, and power consumption can be reduced. Can be reduced.

  Therefore, according to the processor of the present embodiment, part of the address information and attribute information held in the register is set in advance as a constant value by the combinational circuit, thereby reducing the circuit scale and controlling the setting timing. It is easy and power consumption can be reduced.

(Application 1)
Next, application example 1 of the present embodiment will be described. In the above-described embodiment, the example in which the address / attribute setting unit 51 of the comparison unit 41 is configured by a register and the address / attribute setting unit 61 of the comparison unit 42 is configured by a combinational circuit has been described. An example in which a part of the address / attribute setting unit is configured by a register and the other part is configured by a combinational circuit will be described. Note that the configuration of the processor according to the application example 1 is the same as that shown in FIGS.

  FIG. 5 is a block diagram showing a configuration of an APU according to application example 1 of the present embodiment. In FIG. 5, the same components as those of FIG.

  The APU 12a1 shown in FIG. 5 is configured using an address / attribute setting unit 51a and an address / attribute setting unit 61a instead of the address / attribute setting unit 51 and the address / attribute setting unit 61 shown in FIG.

  In the address / attribute setting unit 51a, address information is set as a constant value in advance by a combinational circuit, and attribute information is set via the core I / F 21. The address information set in this way is output to the address comparison unit 53, and the attribute information is output to the attribute comparison unit 54.

  Similarly, in the address / attribute setting unit 61a, the address information is set as a constant value in advance by the combinational circuit, and the attribute information is set via the core I / F 21. The address information set in this way is output to the address comparison unit 63, and the attribute information is output to the attribute comparison unit 64. Other configurations and operations are the same as those in the above-described embodiment, and thus description thereof is omitted.

  As described above, the APU 12a1 according to the application example 1 is configured by combining address information with a combinational circuit and attribute information with a register. As a result, it is possible to reduce the circuit scale by making the area configured by the register a combinational circuit, and when setting the address information and attribute information in the register, the setting timing can be easily set, and the power consumption can be reduced. Can be reduced.

  Therefore, according to the processor of the application example 1, as in the above-described embodiment, a part of the address information and attribute information held in the register is set in advance as a constant value by the combinational circuit, thereby reducing the circuit scale. In addition, the setting timing can be easily controlled and the power consumption can be reduced.

  Although all of the address information is configured by a combinational circuit, a part of the address information may be configured by a combinational circuit, and the other part of the address information may be configured by a register. Alternatively, all of the address information may be configured by a register, and all of the attribute information may be configured by a combinational circuit. Alternatively, part of the attribute information may be configured by a combinational circuit, and the other part of the attribute information may be configured by a register.

(Application example 2)
Next, application example 2 of the present embodiment will be described. In the above-described embodiment, an example of a configuration having two comparison units 41 and 42 has been described, but in Application Example 2, an example of a configuration having eight comparison units will be described. Note that the configuration of the processor according to the application example 2 is the same as that in FIGS.

  FIG. 6 is a block diagram showing a configuration of an APU according to application example 2 of the present embodiment. In FIG. 6, the same components as those in FIG.

  The APU 12a2 shown in FIG. 6 is configured using an address / attribute comparison unit 16a instead of the address / attribute comparison unit 16 shown in FIG.

  The address / attribute comparison unit 16a includes eight comparison units, of which four comparison units are the comparison units 41 described above, and the remaining four comparison units are the comparison units 42 described above. In each comparison unit 41, address information and attribute information are set in the address / attribute setting unit 51 via the core I / F 21, and enable information is set in the EN 52. In each comparison unit 42, enable information is set in the EN 62 via the core I / F 21.

  Address information and attribute information are input to each comparison unit 41 and each comparison unit 42. Each comparison unit 41 and each comparison unit 42 compares the set address information with the input address information, and further compares the set attribute information with the input attribute information. Whether or not it exists is detected, and the detection result is output to the OR circuit 22. Other configurations and operations are the same as those in the above-described embodiment, and thus description thereof is omitted.

  As described above, the APU 12c according to the application example 2 includes the four comparison units 41 and the four comparison units 42. As a result, even when three or more tasks are executed in parallel, it is possible to detect whether there is an address or attribute violation for each of the tasks executed in parallel.

  Further, the APU 12a2 has a configuration in which the address information and the attribute information have a plurality of comparison units 42 that are set in advance as constant values by the combinational circuit, so that the address held in the register is the same as in the above-described embodiment. By setting a part of information and attribute information as a constant value in advance by a combinational circuit, the circuit scale can be reduced, the timing of setting can be easily controlled, and the power consumption can be reduced.

  The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the scope of the present invention.

It is a block diagram which shows the whole structure of the processor which concerns on this Embodiment. It is a block diagram which shows the structure of a core and APU. It is a block diagram which shows the detailed structure of APU. It is explanatory drawing for demonstrating the example of the program which sets address information and attribute information to a register. It is a block diagram which shows the structure of APU which concerns on the application example 1 of this Embodiment. It is a block diagram which shows the structure of APU which concerns on the application example 2 of this Embodiment.

Explanation of symbols

1 processor, 11a, 11b core, 12a, 12a1, 12a2, 12b APU, 13 bus, 14 memory, 15a, 15b local memory, 16, 16a address / attribute comparison unit, 21 core I / F, 22 OR circuit, 41, 42 comparison unit, 51, 51a address / attribute setting unit, 52 EN, 53 address comparison unit, 54 attribute comparison unit, 55 AND circuit, 61, 61a address / attribute setting unit, 62 EN, 63 address comparison unit, 64 attribute comparison Part, 65 AND circuit

Claims (5)

A processor core connected to the bus;
Provided in the processor core, and when the program is executed in the processor core, the memory address when accessing the memory via the bus and the attribute of the instruction of the program executed in the processor core are monitored. And comparing the addresses and attributes obtained by monitoring with a plurality of preset addresses and attributes, and a bit string and attributes of all or part of the bit string of the addresses obtained by monitoring, A unit that generates an address violation or attribute violation exception and notifies the processor core of the occurrence of the exception when the entire bit string of the preset address or a part of the bit string and attributes do not match. The plurality of preset addresses and some of the plurality of attributes are stored in the processor. Via the A is set to the register, the other part of the plurality of addresses and a plurality of attributes set in advance, and the memory protection unit output by the combining circuit,
A processor characterized by comprising:   2. The plurality of preset addresses, the part of the plurality of attributes, and the other part are set and output for each program executed in the processor core, respectively. Processor as described in   The plurality of predetermined addresses and the other part of the plurality of attributes include attributes corresponding to all or part of attributes of instructions of a program executed in the processor core. The processor according to 1.   The plurality of preset addresses and the other part of the plurality of attributes include addresses corresponding to all or a part of the addresses of the memory accessing the memory of the processor core. The processor according to 1.   5. The processor according to claim 1, further comprising an enable signal setting unit that outputs an enable signal for validating or invalidating the result of the comparison. 6.

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