JP2009267216A - Nonvolatile semiconductor storage device and method for manufacturing the same device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the deterioration of device characteristics by preventing the configuring atoms of a high dielectric film in a process from scattering. <P>SOLUTION: In a nonvolatile semiconductor storage device 100 in which a memory cell 110 and a transistor 120 are formed on a silicon substrate 101, at least a sidewall 127 covering the side face of a high dielectric film 124 is formed across a lower gate 122 and a silicon gate 126 on the side face of a laminate film 120T configuring the transistor 120. As the materials of the sidewall 127, a conductor for preventing the configuring atoms of the high dielectric film 124 such as SiGe from scattering is used. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the nonvolatile semiconductor memory device, for example, a nonvolatile semiconductor memory device in which memory cells and peripheral circuits are formed on the same substrate, and a method for manufacturing the nonvolatile semiconductor memory device.

  Conventionally, in a nonvolatile semiconductor memory device such as a NAND flash memory, a memory cell having a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure is adopted in order to realize miniaturization and high integration. It has become. In recent years, an insulating film on a nitride film, which is a charge storage film, is formed of a material (High-k material) having a dielectric constant higher than that of a conventional silicon oxide film for the purpose of further miniaturizing the memory cell portion. It is being considered.

  In the nonvolatile semiconductor memory device as described above, it is general that the memory cell and the peripheral circuit such as a transistor are formed on the same semiconductor substrate. At this time, by making the layer structure of the memory cell and the peripheral circuit the same structure, it is possible to perform batch processing, and thus it is possible to avoid complication of the manufacturing process (for example, Patent Documents shown below) 1).

  However, if the high dielectric film is exposed to the atmosphere in the chamber during, for example, heat treatment in the manufacturing process, the constituent atoms scatter and enter another layer such as an oxide film, forming a fixed charge on this. May end up. Especially in peripheral circuits such as transistors, high-precision threshold control is required. Therefore, if fixed charges are formed in the gate insulating film as described above, threshold control becomes difficult, and device characteristics are reduced. The problem of deterioration occurs.

JP 2005-136416 A

  Accordingly, the present invention has been made in view of the above problems, and a nonvolatile semiconductor memory device and a nonvolatile semiconductor capable of avoiding deterioration of device characteristics by preventing scattering of constituent atoms of a high dielectric film during the process It is an object of the present invention to provide a method for manufacturing a storage device.

  In order to achieve such an object, a nonvolatile semiconductor memory device according to an embodiment of the present invention includes a semiconductor substrate including a first region and a second region, a nitride film, and a first high dielectric film on the nitride film. A first stacked film formed on the first region of the semiconductor substrate via a first insulating film, a lower gate, and the lower gate. A second stacked film including an upper second high dielectric film and an upper gate on the second high dielectric film, and formed on the second region of the semiconductor substrate via a second insulating film; And a conductive sidewall formed from the lower gate to the upper gate so as to cover at least the side surface of the second high dielectric film on the side surface of the second laminated film. .

  According to another aspect of the present invention, there is provided a non-volatile semiconductor memory device manufacturing method comprising: an insulating film forming step of forming an insulating film on an upper surface of a semiconductor substrate having first and second regions; a nitride film; A first stacked film including a first high dielectric film and a control gate on the first high dielectric film is formed on the insulating film on the first region of the semiconductor substrate; a lower gate; and A second stacked film including a second nitride film on the lower gate, a second high dielectric film on the second nitride film, and an upper gate on the second high dielectric film is formed on the semiconductor substrate. A laminated film forming step formed on the insulating film in two regions, and conductivity from the lower gate to the upper gate so as to cover at least a side surface of the second high dielectric film on a side surface of the second laminated film. A sidewall forming step of forming a sidewall having It is characterized in that it comprises a.

  According to the present invention, it is possible to realize a nonvolatile semiconductor memory device and a method for manufacturing the nonvolatile semiconductor memory device that can avoid deterioration of device characteristics by preventing scattering of constituent atoms of the high dielectric film during the process. It becomes.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. Moreover, in the following description, each figure has shown only the shape, the magnitude | size, and positional relationship so that the content of this invention can be understood, Therefore, this invention was illustrated in each figure. It is not limited to only the shape, size, and positional relationship. Furthermore, the numerical value illustrated below is only an example, and therefore the present invention is not limited to the illustrated numerical value.

〔Constitution〕
FIG. 1 is a cross-sectional view schematically showing an example of the configuration of the nonvolatile semiconductor memory device 100 according to the present embodiment. Note that FIG. 1 illustrates a cross section when the memory cell 110 and the transistor 120 are each cut along a plane perpendicular to the substrate (silicon substrate 101) along the channel length direction.

  As shown in FIG. 1, the nonvolatile semiconductor memory device 100 exemplified in this embodiment includes a memory cell 110 formed on a memory cell formation region 110A (for example, a first region) in a silicon substrate 101 as a semiconductor substrate. The transistor 120 is also formed on the peripheral circuit formation region 120A (for example, the second region) in the silicon substrate 101. The silicon substrate 101 is doped with a predetermined impurity for adjusting a threshold value, for example. In addition, one or more memory cell formation regions 110A and peripheral circuit formation regions 120A are arranged on the silicon substrate 101. Each memory cell formation region 110A and peripheral circuit formation region 120A are appropriately electrically separated by an element isolation insulating film 102.

(Memory cell configuration)
A memory cell 110 in FIG. 1 includes a mesa-shaped stacked film 110T (for example, a first stacked film) formed on a silicon substrate 101 via a tunnel oxide film 111 (for example, a first insulating film), and an upper layer of the silicon substrate 101. A source 118s and a drain 118d formed in a pair of regions sandwiching a region below the stacked film 110T. The stacked film 110T includes, for example, a charge storage film 113 (for example, a nitride film), a high dielectric film 114 (for example, a first high dielectric film), a metal gate 115, and a silicon gate 116 (for example, a control gate) in order from the lower layer. It is comprised including.

In the memory cell 110 described above, the tunnel oxide film 111 formed on the upper surface of the silicon substrate 101 is an insulating film for electrically separating the silicon substrate 101 and the upper charge storage film 113 from, for example, silicon oxide (SiO 2). ₂ ) It can be composed of a film or the like. The film thickness can be about 4-5 nm, for example.

  The charge storage film 113 on the tunnel oxide film 111 is a film that functions as a so-called floating gate, and is a film that holds data by trapping tunnel electrons injected through the tunnel oxide film 111 when data is written. is there. The charge storage film 113 can be formed of, for example, a silicon oxide (SiN) film, and the film thickness can be about 5 nm, for example.

The high dielectric film 114 on the charge storage film 113 is a film for electrically separating the charge storage film 113 from the upper control gate. For example, hafnium oxide (HfO) or hafnium silicide oxynitride (HfSiON). ), Alumina (Al ₂ O ₃ ), zirconium oxide (ZrO), or the like, a high dielectric (High-k) material having a relative dielectric constant larger than that of silicon oxide (SiO ₂ ) used for the tunnel oxide film 111. It is formed using. In this way, by disposing the high dielectric film 114 between the charge storage film 113 (floating gate) and the control gate, the charge storage film 113 (floating) can be achieved as compared with the case where the silicon oxide film is disposed as in the prior art. It is possible to increase the capacitive coupling between the gate) and the control gate. As a result, the high dielectric film 114 can be thinned, and the nonvolatile semiconductor memory device 100 can be further miniaturized. In the present embodiment, the high dielectric film 114 is formed of, for example, HfO, and the thickness thereof is, for example, about 10 to 17 nm.

  The metal gate 115 on the high dielectric film 114 is a film for preventing the high dielectric film 114 and the upper silicon gate 116 from coming into direct contact. The silicon gate 116 according to the present embodiment can be formed of, for example, polysilicon having conductivity by containing impurities. Generally, when the polysilicon film and the high dielectric film are brought into contact with each other, these silicon gates 116 can be formed. In some cases, a defect occurs at the interface, resulting in an increase in the operating voltage of the semiconductor device. Furthermore, so-called phonon vibrations may occur inside the polysilicon film, which may hinder the flow of electrons. Therefore, as in the present embodiment, by providing a metal gate 115 which is a metal film between the high dielectric film 114 and the silicon gate 116 (polysilicon film), the high dielectric film 114 and the silicon gate 116 are provided. Direct contact with the (polysilicon film) can be avoided. As a result, the characteristics of the high dielectric film 114 can be fully exhibited, and the high-performance nonvolatile semiconductor memory device 100 can be realized. In the present embodiment, the metal gate 115 is formed of, for example, a laminated film of tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN), and the total film thickness is, for example, about 10 to 13 nm. . However, the present invention is not limited to this, and is formed of, for example, titanium nitride (TiN), molybdenum (Mo), gold (Au), aluminum (Al), platinum (Pt), silver (Ag), or W. Various films that can be used as a metal gate, such as a single layer film or a multilayer film including any one of them, can be used.

  As described above, the silicon gate 116 on the metal gate 115 is formed of a polysilicon film having conductivity by containing a predetermined impurity, for example. The film thickness can be about 100 nm, for example. The two layers of the silicon gate 116 and the metal gate 115 below it form a control gate in the memory cell 110.

  In addition, a source 118s and a drain 118d are formed in a pair of regions sandwiching a region below the stacked film 110T in the upper layer portion of the silicon substrate 101. The source 118s and the drain 118d are impurity diffusion regions whose resistance is lowered by injecting predetermined impurities, diffusing and activating them. In this embodiment, as the predetermined impurity, for example, a dopant having n-type conductivity such as phosphorus (P) ion or arsenic (As) ion, or p-type such as boron (B) ion. A dopant having the following conductivity can be applied. Note that a region sandwiched between the source 118s and the drain 118d in the upper layer of the silicon substrate 101 functions as a so-called channel formation region in which a channel is formed during writing or operation.

(Configuration of transistor)
1 includes a mesa-like stacked film 120T (for example, a second stacked film) formed on a silicon substrate 101 via a gate oxide film 121 (for example, a second insulating film), and a stacked film 120T. A side wall 127 formed on the side surface, and a source 128s and a drain 128d formed in a pair of regions sandwiching the region below the stacked film 120T and the side wall 127 in the upper layer portion of the silicon substrate 101 are provided. The stacked film 120T includes, for example, a lower gate 122, an insulating film 123, a high dielectric film 124 (for example, a second high dielectric film), a metal gate 125, and a silicon gate 126 (for example, an upper gate) in order from the lower layer. It consists of

  In the transistor 120, the gate oxide film 121 formed on the upper surface of the silicon substrate 101 is a film for electrically separating the upper lower gate 122 and the silicon substrate 101, for example, a tunnel oxide film in the memory cell 110. The same film (silicon oxide film) as 111 can be formed. The film thickness can also be about 4-5 nm, for example.

  The lower gate 122 on the gate oxide film 121 is an effective gate for driving the transistor 120, and can be formed of, for example, a polysilicon film having conductivity by containing a predetermined impurity. Moreover, the film thickness can be about 20 nm, for example.

  The insulating film 123, the high dielectric film 124, the metal gate 125, and the silicon gate 126 on the lower gate 122 are the same processes as the charge storage film 113, the high dielectric film 114, the metal gate 125, and the silicon gate 116 in the memory cell 110, respectively. It is the film | membrane formed by. Therefore, for the sake of simplification of description, description of these details is omitted. Note that the two layers of the silicon gate 126 and the metal gate 125 in the stacked film 120T form an upper gate in the transistor 120.

  Further, sidewalls for preventing the high dielectric film 124 formed on the peripheral circuit formation region 120A from being exposed at least on the side surface of the high dielectric film 124 in the laminated film 120T, for example, during heat treatment during the process. 127 is formed. In the present embodiment, for example, the sidewall 127 is formed on the side surface from the lower gate 122 to the silicon gate 126 in the stacked film 120T.

  The sidewall 127 is a film for preventing the constituent elements of the high dielectric film 124, in particular, metal elements from being scattered during the process, for example, during heat treatment. Thereby, it is possible to prevent the constituent atoms of the high dielectric film 124 from being scattered during the process and entering the gate oxide film 121, for example, and forming a fixed charge on the gate oxide film 121. As a result, it is possible to avoid difficulty in controlling the threshold value of the transistor 120 in the nonvolatile semiconductor memory device 100.

  In this embodiment mode, the sidewall 127 is preferably formed using a material capable of forming a reactant such as silicate or silicide by reacting with the constituent atoms of the high dielectric film 124. Thus, the reaction film 127a is formed at the interface between the high dielectric film 124 and the sidewall 127 by reacting with the constituent atoms diffused from the high dielectric film 124. It is more reliably achieved that the diffused constituent atoms are contained inside the sidewall 127. That is, the sidewall 127 not only functions as a film that physically prevents the scattering of constituent atoms, but also functions as a film that chemically prevents the scattering of constituent atoms, thereby forming the high dielectric film 124. Further enhancement of the effect of preventing atom scattering is achieved.

  Further, in this embodiment, the side wall 127 is also used as a configuration for electrically connecting an upper gate electrically connected to an upper wiring (not shown) and the like and a lower gate 122 which is an effective gate of the transistor 120. To do. Thereby, for example, a through hole is formed in an insulating film (the insulating film 123, the high dielectric film 124, etc.) in the stacked film 120T of the transistor 120, and a conductive material is embedded in the through hole to thereby form the upper gate and the lower gate 122. Therefore, it is possible to avoid the complicated configuration and manufacturing method of the nonvolatile semiconductor memory device 100 as a result. In this embodiment, the sidewall 127 is formed from the lower gate 122 to the silicon gate 126. However, if the sidewall 127 is formed from the lower gate 122 to the metal gate 125 that is at least a part of the upper gate. Good.

  For example, silicon germanium (SiGe) exists as a material having both the effect of preventing the scattering of constituent atoms of the high dielectric film 124 and conductivity. However, the present invention is not limited to this. For example, a polysilicon film, titanium (Ti) or Ti alloy film, copper (Cu) or Cu having conductivity without containing a metal element among the constituent atoms of the high dielectric film 124. Alloy film, molybdenum (Mo) or Mo alloy film, gold (Au) or Au alloy film, platinum (Pt) or Pt alloy film, silver (Ag) or Ag alloy film, tungsten (W) or W alloy film, etc. A film capable of preventing the constituent atoms of the high dielectric film 124 (114) from scattering, such as a single-layer film having conductivity, or a conductive multilayer film including any one of them. The sidewall 127 may be formed using any film as long as it has conductivity. In this embodiment, the case where the sidewall 127 is formed using SiGe is taken as an example. Moreover, the film thickness of the thickest part in the gate length direction can be about 5-10 nm, for example.

  A source 128s and a drain 128d are formed in a pair of regions sandwiching the region below the stacked film 120T in the upper layer portion of the silicon substrate 101. Since the source 128s and the drain 128d are the same as the source 128s and the drain 128d in the memory cell 110, detailed description thereof is omitted here. Note that a region sandwiched between the source 128s and the drain 128d in the upper layer of the silicon substrate 101 functions as a so-called channel formation region in which a channel is formed during operation.

〔Production method〕
Next, a method for manufacturing the nonvolatile semiconductor memory device 100 according to the present embodiment will be described in detail with reference to the drawings. 2A to 6 are diagrams schematically showing a cross-sectional structure at each process stage in the method for manufacturing the nonvolatile semiconductor memory device 100 according to the present embodiment. 2A to 6 show a cross section corresponding to the cross section shown in FIG.

  In this manufacturing method, first, a silicon substrate 101 (for example, a semiconductor substrate) doped with a predetermined impurity is prepared for threshold adjustment, and silicon is formed on the upper surface of the silicon substrate 101 using, for example, a LOCOS (Local Oxidation Of Silicon) method. An element isolation insulating film 102 (see FIG. 2A) made of an oxide film is formed. Thus, the upper layer of the silicon substrate 101 is partitioned into a plurality of element formation regions including a memory cell formation region 110A (for example, a first region) and a peripheral circuit formation region 120A (for example, a second region). Subsequently, for example, by using a thermal oxidation method, as shown in FIG. 2A, a silicon oxide film 111A (for example, an insulating film) having a film thickness of, for example, about 4 to 5 nm is formed on the upper surface of the silicon substrate 101 (see FIG. 2A). For example, an insulating film forming step). The element isolation method is not limited to the above LOCOS method, and various element isolation techniques such as an STI (Shallow Trench Isolation) method can be applied.

  Next, by using, for example, a lift-off method, a polysilicon film 122A (for example, a first conductor) having conductivity by including a predetermined impurity on the silicon oxide film 111A on the peripheral circuit formation region 120A of the silicon substrate 101 is used. Film) is selectively formed (for example, the first step). Specifically, for example, a photoresist solution is spin-coated on the entire surface of the silicon oxide film 111A on the silicon substrate 101, and this is exposed and developed, so that the silicon oxide film 111A on the peripheral circuit formation region 120A is formed. A resist film R1 having an opening (see FIG. 2B) is formed. Subsequently, polysilicon is deposited on the resist film R1 and the silicon oxide film 111A exposed through the opening by using, for example, a sputtering method. Thereby, as shown in FIG. 2B, a polysilicon film 122A having a film thickness of, for example, about 20 nm is formed on the silicon oxide film 111A on the resist film R1 and the peripheral circuit formation region 120A. Thereafter, the resist film R1 is removed by, for example, ashing or using a stripping solution such as acetone. As a result, the polysilicon film 122A on the resist film R1 is removed by lift-off, and a polysilicon film 122A is formed on the silicon oxide film 111A on the peripheral circuit formation region 120A. The predetermined impurity contained in the polysilicon film 122A may be doped at the time of deposition of polysilicon or may be doped by ion implantation after film formation.

  Next, as shown in FIG. 2C, the silicon nitride film 113A, the high dielectric film 114A, the metal film 115A, and the polysilicon are formed on the entire silicon substrate 101 on which the silicon oxide film 111A and the polysilicon film 122A are formed. A film 116A (for example, a second conductor film) is sequentially formed (for example, second to fourth steps). Specifically, first, a silicon nitride film 113A having a thickness of, for example, about 5 nm is formed on the surface of the silicon oxide film 111A and the polysilicon film 122A on the upper surface of the silicon substrate 101 by using, for example, a CVD method or a plasma nitridation method. . Subsequently, by using, for example, an ALD (Atomic Layer Deposition) method, a high dielectric film 114A made of, for example, HfO having a thickness of, for example, about 10 to 17 nm is formed on the surface of the silicon nitride film 113A. Subsequently, by using, for example, an MOCVD (Metal Organic CVD) method, a metal film 115A made of a stacked film of TaN, W, and WN, for example, on the surface of the high dielectric film 114A has a total film thickness of, for example, 10 to 13 nm. It forms so that it may become. Subsequently, a polysilicon film 116A having a thickness of, for example, about 100 nm is formed on the surface of the metal film 115A by using, for example, a sputtering method. Note that the polysilicon film 116A has conductivity by containing a predetermined impurity. The predetermined impurity may be doped at the time of polysilicon deposition or may be doped by ion implantation after film formation.

  As described above, when a laminated film including the silicon nitride film 113A, the high dielectric film 114A, the metal film 115A, and the polysilicon film 116A is formed, next, for example, by using the CVD method, the surface of the polysilicon film 116A is formed. Then, a silicon oxide film having a film thickness of, for example, about 300 nm is formed. Subsequently, the formed silicon oxide film is patterned by using a photolithography technique and an etching technique, so that mask oxidation of a pattern corresponding to the upper surface shape of the stacked film 110T in the memory cell 110 and the upper surface shape of the stacked film 120T in the transistor 120 is performed. A film M1 (see FIG. 3A) is formed. Subsequently, using the mask oxide film M1 as a mask, the polysilicon film 116A, the metal film 115A, the high dielectric film 114A, and the silicon nitride film 113A using an anisotropic dry etching technique such as RIE (Reactive Ion Etching), for example. Are sequentially etched (for example, the fifth step). As a result, as shown in FIG. 3A, the charge storage film 113 (for example, the first nitride film) and the high dielectric film 114 (for example, the first nitride film) are formed on the silicon oxide film 111A on the memory cell formation region 110A of the silicon substrate 101. A mesa-shaped stacked film 110t (for example, the first stacked film) composed of the first high dielectric film), the metal gate 115, and the silicon gate 116 (for example, the control gate) is formed, and the peripheral circuit forming region of the silicon substrate 101 is formed. A lower gate 122, an insulating film 123 (for example, a second nitride film), a high dielectric film 124 (for example, a second high dielectric film), a metal gate 125, and a silicon gate 126 (for example, an upper portion) are formed on the silicon oxide film 111A on 120A. A mesa-shaped laminated film 120t (for example, a second laminated film) formed of a gate is formed (for example, a laminated film forming step). Thus, in this embodiment mode, the memory cell 110 and the transistor 120 which is a peripheral circuit have the same stacked film structure, and thus the memory cell 110 and the transistor 120 are collectively distinguished without being distinguished from each other. By processing, the stacked film 110t of the memory cell 110 and the stacked film 120t of the transistor 120 can be formed.

Next, for example, by using the CVD method, as shown in FIG. 3B, the film thickness is, for example, about 5 to 10 nm on the entire silicon substrate 101 on which the stacked films 110t and 120t and the silicon oxide film 111A are formed. The SiGe film 127A is formed. Next, the SiGe film 127A is anisotropically dry-etched by, for example, RIE using a fluorine-based gas, and as shown in FIG. Sidewalls 117 and 127 made of a SiGe film with a thick portion having a thickness of about 5 to 10 nm are formed (for example, a sidewall formation step). Note that in anisotropic dry etching of the SiGe film 127A, a gas such as chlorine trifluoride (ClF ₃ ) can be used as an etching gas.

Next, a photoresist solution is spin-coated on the entire silicon substrate 101 on which the laminated films 110t and 120t, the sidewalls 117 and 127, and the silicon oxide film 111A are formed, and this is exposed and developed, whereby FIG. As shown in b), a resist film R2 covering the laminated film 120t and the sidewall 127 formed on the peripheral circuit formation region 120A of the silicon substrate 101 is formed. Next, while using the resist film R2 as a mask, for example, dry etching by CDE (Chemical Dry Etching) using methane (CH ₄ ) as an etching gas is performed, thereby forming a memory cell as shown in FIG. The sidewall 117 formed on the side surface of the stacked film 110t on the region 110A is selectively removed. However, the present invention is not limited to this. For example, a liquid mixture obtained by mixing hydrogen fluoride (HF), hydrogen peroxide solution (H ₂ O ₂ ), and acetic acid (CH ₃ COOH) at a ratio of 1: 2: 3 is used as an etchant. The sidewall 117 formed on the side surface of the stacked film 110t on the memory cell formation region 110A can also be removed by wet etching.

  Next, after removing the resist film R2 by ashing or using a stripping solution such as acetone, the exposed silicon oxide is etched by dry etching using a fluorine-based gas or wet etching using a phosphoric acid aqueous solution, for example. The film 111A is removed. As a result, as shown in FIG. 5B, a tunnel oxide film 111 is formed under the stacked film 110t on the memory cell formation region 110A, and a gate oxide film 121 is formed under the stacked film 120t on the peripheral circuit formation region 120A. It is formed. As a result, as shown in FIG. 5B, the charge storage film 113, the high dielectric film 114, the metal gate 115, and the silicon are formed on the memory cell formation region 110A of the silicon substrate 101 via the tunnel oxide film 111. A mesa-shaped laminated film 110T composed of the gate 116 is formed, and a lower gate 122, an insulating film 123, a high dielectric film 124, and a metal are formed on the peripheral circuit formation region 120A of the silicon substrate 101 via a gate oxide film 121. A mesa-shaped laminated film 120T composed of the gate 125 and the silicon gate 126 is formed.

  Next, for example, by using an ion implantation method, predetermined impurity ions are implanted into the upper layer of the silicon substrate 101 while using the laminated film 110T, the laminated film 120T, and the sidewall 127 as a mask. As a result, as shown in FIG. 6, an impurity implantation region 118 a is formed in the upper layer of the silicon substrate 101, and the region below the stacked film 110 </ b> T, and the region below the stacked film 120 </ b> T and the sidewall 127. Next, the silicon substrate 101 into which a predetermined impurity has been implanted is heat-treated using, for example, an annealing apparatus, thereby diffusing and activating the impurity implanted into the impurity implantation region 118a. As a result, as shown in FIG. 1, a pair of source 118s and drain 118d sandwiching the region under the stacked film 110T is formed in the upper layer of the silicon substrate 101 in the memory cell formation region 110A, and the upper layer of the silicon substrate 101 in the peripheral circuit formation region 120A. A pair of the source 128s and the drain 128d sandwiching the region under the laminated film 120T and the sidewall 127 is formed. Further, for example, in the heat treatment step at this time, the constituent atoms of the high dielectric film 124 diffuse into the sidewall 127 and react with the constituent atoms of the sidewall 127, whereby the high dielectric film 124 and the sidewall 127 are separated. A reaction film 127a is formed at the interface.

  Through the above steps, the nonvolatile semiconductor memory device 100 according to the present embodiment having the cross-sectional structure shown in FIG. 1 is manufactured. Note that after the above steps, an interlayer insulating film, a via contact, and an upper layer metal wiring are formed. However, in this embodiment, description of these steps is omitted for the sake of simplification.

  Further, the above embodiment is merely an example for carrying out the present invention, and the present invention is not limited to these, and various modifications according to specifications and the like are within the scope of the present invention. It is obvious from the above description that various other embodiments are possible within the scope of the present invention.

It is sectional drawing which shows typically an example of a structure of the non-volatile semiconductor memory device concerning embodiment of this invention. It is a figure which shows typically the cross-sectional structure in each process step in the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (1). It is a figure which shows typically the cross-sectional structure in each process step in the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (2). It is a figure which shows typically the cross-sectional structure in each process step in the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (3). It is a figure which shows typically the cross-sectional structure in each process step in the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (4). It is a figure which shows typically the cross-sectional structure in each process step in the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (5).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 Nonvolatile semiconductor memory device, 101 Silicon substrate, 110 memory cell, 110A memory cell formation area, 110T, 110t, 120T, 120t laminated film, 111 tunnel oxide film, 111A silicon oxide film, 113 charge storage film, 113A silicon nitride film 114, 114A, 124 High dielectric film, 115, 125 metal gate, 115A metal film, 116, 126 silicon gate, 116A, 122A polysilicon film, 117, 127 sidewall, 118a impurity implantation region, 118d, 128d drain, 118s, 128s source, 120 transistor, 120A peripheral circuit formation region, 121 gate oxide film, 122 lower gate, 123 insulating film, 127A SiGe film, 127a reaction film

Claims (5)

A semiconductor substrate including a first region and a second region;
A nitride film, a first high dielectric film on the nitride film, and a control gate on the first high dielectric film, and formed on the first region of the semiconductor substrate via a first insulating film A first laminated film,
A lower gate, a second high dielectric film on the lower gate, and an upper gate on the second high dielectric film are formed on the second region of the semiconductor substrate via a second insulating film. A second laminated film,
A conductive sidewall formed from the lower gate to the upper gate so as to cover at least the side surface of the second high dielectric film on the side surface of the second laminated film;
A nonvolatile semiconductor memory device comprising:   A reaction film formed by a reaction between constituent atoms of the second high dielectric film and the constituent atoms of the sidewall is provided at the interface between the second high dielectric film and the sidewall. The nonvolatile semiconductor memory device according to claim 1.   The sidewalls are SiGe film, polysilicon film, Ti or Ti alloy film, Cu or Cu alloy film, Mo or Mo alloy film, Au or Au alloy film, Pt or Pt alloy film, Ag or Ag alloy film, and 2. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is formed of a single layer or a multilayer film including at least one of W or a W alloy film. An insulating film forming step of forming an insulating film on the upper surface of the semiconductor substrate having the first and second regions;
A first stacked film including a first nitride film, a first high dielectric film on the first nitride film, and a control gate on the first high dielectric film is formed on the first region of the semiconductor substrate. Forming a lower gate; a second nitride film on the lower gate; a second high dielectric film on the second nitride film; and an upper gate on the second high dielectric film. A laminated film forming step of forming a second laminated film including the second laminated film on the insulating film on the second region of the semiconductor substrate;
Forming a sidewall having conductivity from the lower gate to the upper gate so as to cover at least the side surface of the second high dielectric film on the side surface of the second laminated film;
A method for manufacturing a non-volatile semiconductor device, comprising: The laminated film forming step includes
A first step of selectively forming a first conductor film on the insulating film on the second region of the semiconductor substrate;
A second step of forming a nitride film on the insulating film and the first conductor film on the first region of the semiconductor substrate;
A third step of forming a high dielectric film on the nitride film;
A fourth step of forming a second conductor film on the high dielectric film;
The first conductive film is formed on the insulating film on the first region by processing the second conductive film, the high dielectric film, the nitride film, and the first conductive film. A fifth step of forming the second laminated film on the insulating film on the second region;
The method of manufacturing a nonvolatile semiconductor memory device according to claim 4, comprising:

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