JP2009252858A - Package for storing semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure excellent bondability between a base and a ceramic frame, and to prevent the ceramic frame from cracking. <P>SOLUTION: The package for storing a semiconductor element includes the base 101 which is provided with a projection portion 103 for mounting a semiconductor element thereon on an upper surface and has at least the upper surface made of metal, the ceramic frame 102 which has its bottom surface 102a and inside side surface 102b covered with a metal layer 109, and a brazing filler metal 112 bonding the upper surface of the base 101 and the metal layer 109 together so that the ceramic frame 102 encloses the projection portion 103 for semiconductor element mounting on the upper surface of the base 101. A surface of the brazing filler metal 112 at a gap portion 111 between the metal layer 109 on the inside side surface 102b of the ceramic frame 102 and the base 101 is below the upper surface of the projection portion 103 for mounting the semiconductor element of the base and above an upper surface of a mounting portion of the base 101 for the ceramic frame 102. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor element storage package for storing semiconductor elements. In particular, the present invention relates to a package for housing a semiconductor element formed by joining a metal base and a ceramic frame with a brazing material.

  As a semiconductor element housing package for hermetically sealing and housing a semiconductor element, it is made of a metal such as a copper-molybdenum (CuMo) alloy or a copper-tungsten (CuW) alloy having good thermal conductivity as shown in FIG. A ceramic frame in which a bottom surface 2a, an inner surface 2b, and an upper surface 2c are coated with a metal layer (not shown) on a base 1 provided with a convex portion 1a for mounting a semiconductor element (not shown) on the upper surface. It is known that the body 2 is mounted so as to surround the semiconductor element mounting convex portion 1 a and both are brazed with a brazing material 3. The metal layer on the bottom surface 2a of the ceramic frame 2 is provided for brazing, and the metal layers on the inner side surface 2b and the upper surface 2c are provided for improving electrical characteristics.

  In such a package for housing a semiconductor element, since the metal layer is provided not only on the bottom surface 2a of the ceramic frame 2 but also on the inner surface 2b, when the ceramic frame 2 is brazed on the upper surface of the substrate 1, The excess brazing material 3 accumulates in the gap G between the inner surface 2b of the ceramic frame 2 and the base 1, and when the brazing material 3 is cooled and solidified, the ceramic frame 2 is stressed. In addition, it has become clear that cracks may occur.

  As a method for solving this problem, for example, it is conceivable to reduce the amount of brazing material to be used or increase the width or height of the gap portion G. There is a possibility that voids are generated in the brazing material 3 between the bottom surface 2a of the body 2 and the base 1, and the bonding property is impaired. On the other hand, if the width or height of the gap G is changed, there is a problem that a design change is required.

  In order to solve this type of problem in the package for housing a semiconductor element, there has been proposed a package provided with a groove or a recess for storing excessive brazing material (see, for example, Patent Document 1).

However, all of the semiconductor element storage packages disclosed in Patent Document 1 are different from the semiconductor element storage package in the shape of the joint portion between the base and the frame. It cannot be applied to.
JP 2002-198454 A

  The present invention has been made in response to the above-described problems of the prior art, and a bottom surface and an inner surface are coated with a metal layer on a base provided with a convex portion for placing a semiconductor element on the upper surface. A ceramic frame body is mounted so as to surround the semiconductor element mounting convex portion, and in a semiconductor element storage package formed by brazing, a good bonding property between the substrate and the ceramic frame body is ensured. An object of the present invention is to provide a package for housing a semiconductor element that can prevent cracks from occurring in a ceramic frame.

  (1) The invention of claim 1 (semiconductor element storage package) is provided with a base having at least a surface made of metal provided with a convex part for placing a semiconductor element on the upper surface, and a bottom surface and an inner surface being a metal layer. And a brazing material that joins the upper surface of the base body and the metal layer so that the ceramic frame body surrounds the semiconductor element mounting convex portion on the upper surface of the base body. A package for element storage, wherein the brazing material surface of the gap between the metal layer on the inner surface of the ceramic frame and the base is below the upper surface of the convex part for mounting the semiconductor element on the base; and It is configured to be positioned above the upper surface of the ceramic frame mounting portion of the base.

  In the present invention, the surface of the brazing material in the gap between the metal layer on the inner side surface of the ceramic frame and the substrate is below the upper surface of the semiconductor element mounting convex portion of the substrate, and the ceramic frame mounting portion of the substrate Therefore, the stress applied to the ceramic frame when the brazing filler metal in the gap is solidified and contracted can be reduced, and cracks in the ceramic frame due to the stress can be reduced. Can be prevented. Also, good bondability between the substrate and the ceramic frame can be ensured.

  (2) In the invention of claim 2, a spacer member is provided between the bottom surface of the opposing ceramic frame body and the upper surface of the mounting portion of the ceramic frame body of the base so that the distance between them is 10 to 30 μm. It was made to be characterized.

  In the present invention, a spacer member is provided between the bottom surface of the opposing ceramic frame body and the top surface of the mounting portion of the ceramic frame body of the substrate, so that the gap between them is 10-30 μm. It is possible to easily control the amount of the brazing material penetrating into the gap, thereby easily adjusting the position of the brazing filler metal surface in the gap to the appropriate position as described above.

  If the distance between the bottom surface of the opposing ceramic frame body and the top surface of the mounting portion of the ceramic frame body of the base is less than 10 μm, the brazing filler metal surface of the gap portion is the semiconductor element mounting convex portion of the base body. It becomes difficult to make it below the upper surface. On the other hand, if the separation distance exceeds 30 μm, the brazing material portion becomes too thick, and stress due to cooling shrinkage may be applied to the ceramic frame.

  (3) The invention of claim 3 is characterized in that the spacer member comprises a protrusion provided on the bottom surface of the ceramic frame and / or the upper surface of the mounting portion of the ceramic frame of the base.

  The present invention exemplifies a preferable spacer member, which is easy to form and can stably form a separation distance between the bottom surface of the opposing ceramic frame body and the upper surface of the mounting portion of the ceramic frame body of the substrate. Can be controlled.

  (4) The invention of claim 4 is characterized in that a recess is provided in the base below the gap between the inner surface of the ceramic frame and the base to store the molten brazing material.

  In the present invention, the base below the gap between the inner surface of the ceramic frame and the base is provided with a recess for storing the melted brazing filler metal. Can be easily adjusted to position.

  (5) The invention of claim 5 is characterized in that the width d of the gap between the inner surface of the ceramic frame and the substrate is 50 to 200 μm.

  In the present invention, since the width d of the gap between the inner surface of the ceramic frame and the substrate is 50 to 200 μm, it is not necessary to change the design of the package for housing semiconductor elements.

  (6) The invention of claim 6 is characterized in that a height h of the semiconductor element mounting convex portion is 100 to 350 μm.

  In the present invention, since the height h of the semiconductor element mounting convex portion is 100 to 350 μm, it is not necessary to change the design of the semiconductor element storage package.

  According to the present invention, a ceramic frame having a bottom surface and an inner surface coated with a metal layer on a base provided with a convex portion for placing a semiconductor element on an upper surface is provided with a convex portion for placing a semiconductor element. In a package for housing a semiconductor element, which is mounted and brazed so as to surround the substrate, it is possible to ensure good bondability between the base and the ceramic frame and to prevent cracks in the ceramic frame. As a result, it is possible to provide a package for housing a semiconductor element in which the semiconductor element is hermetically sealed.

  Embodiments according to the present invention will be described below. Although the description will be made based on the drawings, the drawings are provided for illustration only, and the present invention is not limited to the drawings. It should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Furthermore, in the following description, components having the same or substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
FIG. 1 is a perspective view showing a package for housing a semiconductor element according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view showing an enlarged main part thereof.

  As shown in FIG. 1 and FIG. 2, the package for housing a semiconductor element of this embodiment includes a base 101 and a ceramic frame body 102 joined to the base 101 via a brazing material 112. .

  The base 101 is made of a copper-molybdenum (CuMo) alloy having good thermal conductivity, and has a convex portion 103 on which the semiconductor element (not shown) is placed. The substrate 101 may be made of a metal such as a copper-tungsten (CuW) alloy or an iron-nickel-cobalt (FeNiCo) alloy called Kovar, ceramics, or the like. In the case of ceramics, at least the surface is covered with metal.

  In the present embodiment, the base body 101 has a rectangular planar shape, and the height h of the convex portion 103 is, for example, about 100 to 350 μm. Further, the base 101 is provided with a fixing portion 104 provided with a screwing hole for screwing to an external mounting substrate.

  The base 101 has both a function as a support member that supports a semiconductor element (not shown) and a function as a heat dissipation member that dissipates heat during operation of the semiconductor element.

  A metal having excellent wettability with the brazing material, for example, a nickel (Ni) layer having a thickness of about 1.0 to 2.5 μm is formed on the surface of the base 101 by plating as necessary. A gold (Au) layer having a thickness of about 2 to 3 μm may be further formed on the nickel (Ni) layer by a plating method.

The ceramic frame 102 is formed by laminating and firing a plurality of ceramic green sheets made of alumina (Al ₂ O ₃ ) or the like having a predetermined shape. Step portions 105 and 106 are formed inside and outside the ceramic frame 102, and tungsten (W) or the like is connected to the upper surface of the step portions 105 and 106 inside the ceramic frame 102. A plurality of line conductors 107 made of metallization and a metal layer 109 serving as a ground are provided. Each line conductor 107 is further joined with a lead terminal 108 for electrical connection with an external electric circuit.

  Further, a metal layer 109 made of metallization such as tungsten (W) is provided on the bottom surface 102a and the lower inner side surface 102b of the ceramic frame 102, and further metallization such as tungsten (W) is performed again on the bottom surface 102a. Thus, a plurality of bumps 110 as spacer members having a height of 5 to 25 μm are formed. On the surface of the metal layer 109 on the lower inner side surface 102b of the ceramic frame 102 and the surface of the metal layer 109 on which the bumps 110 on the bottom surface 102a are formed, a metal having excellent wettability with the brazing material, for example, thickness A nickel (Ni) layer of about 1.0 to 2.5 μm is formed by a plating method. A gold (Au) layer having a thickness of about 2 to 3 μm may be further formed on the nickel (Ni) layer by a plating method. A metal layer 109 made of metallization such as tungsten (W), a nickel (Ni) layer, and a gold (Au) layer is provided on the entire outer surface of the ceramic frame 102 excluding a portion where the line conductor 107 is formed. May be.

  The ceramic frame 102 surrounds the semiconductor element mounting convex portion 103 on the upper surface of the base body 101, and has a width d between the surface of the metal layer 109 on the lower inner side surface 102 b of the ceramic frame 102 and the base body 101. It has a gap (gap portion 111) of about 50 to 200 μm and is joined by a brazing material 112 such as silver brazing.

  In such a package for housing semiconductor elements, the bumps 110 having a height of about 5 to 25 μm are formed on the bottom surface 102 a of the ceramic frame body 102, so that the bottom surface 102 a of the ceramic frame body 102 and the ceramic frame body 102 of the base body 101 are formed. A separation distance “a” of 10 to 30 μm is ensured between the upper surface of the mounting portion.

  As a result, generation of voids in the brazing material 112 between the bottom surface 102a of the ceramic frame 102 and the upper surface of the mounting portion of the ceramic frame 102 of the base 101 is prevented, and the metal on the inner side surface 108 of the ceramic frame 102 is prevented. The surface of the brazing material 112 in the gap portion 111 between the layer 109 and the substrate 102 is below the upper surface of the semiconductor element mounting convex portion 103 of the substrate 101 and above the upper surface of the mounting portion of the ceramic frame 102 of the substrate 101. Therefore, the generation of cracks in the ceramic frame 102 can be prevented.

  On the other hand, when the bump 110 is not formed, the distance a between the bottom surface 102a of the ceramic frame 102 and the top surface of the mounting portion of the ceramic frame 102 of the base 101 is about 5 μm. When the ceramic frame body 102 and the base body 101 are joined with the same amount of brazing material as in the above embodiment, a large amount of brazing material pool is generated in the gap portion 111, and the surface of the brazing material 112 as shown in FIG. It is located above the upper surface of the semiconductor element mounting convex portion 103 of the base 101. Further, when the amount of the brazing material is reduced, the surface of the brazing material 112 in the gap portion 111 is below the upper surface of the semiconductor element mounting convex portion 103 of the base 101 and the top surface of the mounting portion of the ceramic frame 102 of the base 101. Although it comes to be positioned further upward, a void is generated in the brazing material 112 between the bottom surface 102a of the ceramic frame 102 and the upper surface of the mounting portion of the ceramic frame 102 of the base 101, and the ceramic frame 102 and the base 101 In some cases, the bonding with was not sufficient.

  As described above, in the case where the separation distance a of 10 to 30 μm is not ensured between the bottom surface 102a of the ceramic frame 102 and the upper surface of the mounting portion of the ceramic frame 102 of the base body 101, voids in the brazing material 112 can be prevented. While it is impossible to achieve both prevention of cracks in the ceramic frame 102, in the present embodiment, it is possible to achieve both of them, and excellent bonding properties between the base body 101 and the ceramic frame 102, and the ceramic frame 102. Thus, a high-quality and high-reliability package for housing a semiconductor element without cracks can be obtained.

  In the present embodiment, the bottom surface of the ceramic frame 102 is used as a spacer member for securing a separation distance a between the bottom surface 102a of the ceramic frame 102 and the top surface of the mounting portion of the ceramic frame 102 of the base 101. Although bumps 110 provided by metallization on 102 a are used, the bumps 110 may be provided on the base 101 side, or may be provided on both the bottom surface 102 a of the ceramic frame 102 and the top surface of the base 101. Further, when the base body 101 is molded, a protrusion may be provided on the upper surface, and a ceramic ball or a metal ball is interposed between the bottom surface 102a of the ceramic frame 102 and the upper surface of the base body 101. May be.

(Second Embodiment)
FIG. 4 is an enlarged sectional view showing a main part of a package for housing a semiconductor element according to the second embodiment of the present invention. In addition, in order to avoid overlapping description, description is abbreviate | omitted about the point which is common in 1st Embodiment, and only a different point is demonstrated.

  As shown in FIG. 4, in the package for housing a semiconductor device according to the second embodiment, bumps are not formed, and the base body 101 below the gap 111 between the inner side surface 102 b of the ceramic frame 102 and the base body 101 is formed. A recess 113 for storing the molten brazing material 107 is provided. In the example of FIG. 4, the concave portion 113 having a rectangular cross section is formed, but the shape is not particularly limited to such a shape. Also. The depth is not particularly limited, but is usually 50 to 200 μm.

  In the present embodiment, since at least a part of the molten brazing material 112 flows into the recess 113, the gap between the metal layer 109 on the inner surface 108 of the ceramic frame 102 and the base body 102, as in the first embodiment. 111 is configured such that the surface of the brazing material 112 is positioned below the upper surface of the semiconductor element mounting convex portion 103 of the base 101 and above the upper surface of the mounting portion of the ceramic frame 102 of the base 101. And the generation of cracks in the ceramic frame 102 can be prevented. In addition, it is possible to prevent the occurrence of voids in the brazing material 112 between the bottom surface 102a of the ceramic frame 102 and the top surface of the mounting portion of the ceramic frame 102 of the base 101.

  The present invention is not limited to the contents described in the embodiment described above, and it goes without saying that the present invention can be implemented in various modes without departing from the gist of the present invention.

1 is a perspective view showing a package for housing a semiconductor element according to a first embodiment of the present invention. It is sectional drawing which expands and shows the principal part of FIG. It is sectional drawing which shows the principal part structure of the package for semiconductor element accommodation for a comparison with 1st Embodiment. It is sectional drawing which expands and shows the principal part of the package for semiconductor element accommodation which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows schematically the structure of the conventional semiconductor element accommodation package.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Base | substrate, 102 ... Ceramic frame, 102a ... Bottom, 102b ... Inner side surface, 103 ... Semiconductor element mounting convex part, 109 ... Metal layer, 110 ... Bump, 111 ... Gap part, 112 ... Brazing material, 113 ... Concave part .

Claims (6)

A base having at least a surface made of metal provided with a convex portion for placing a semiconductor element on the upper surface;
A ceramic frame whose bottom and inner surfaces are coated with a metal layer;
A brazing material that joins the upper surface of the base body and the metal layer so that the ceramic frame body surrounds the semiconductor element mounting convex portion on the upper surface of the base body;
A package for housing a semiconductor element comprising:
The brazing material surface in the gap between the metal layer on the inner surface of the ceramic frame and the base is below the upper surface of the semiconductor element mounting convex portion of the base, and the ceramic frame is mounted on the base A package for housing a semiconductor element, wherein the package is located above the upper surface of the portion.   2. A spacer member defining a distance of 10 to 30 [mu] m between the bottom surface of the ceramic frame body and the upper surface of the mounting portion of the ceramic frame body of the base is interposed. A package for housing a semiconductor element as described.   3. The package for housing a semiconductor element according to claim 2, wherein the spacer member comprises a protrusion provided on a bottom surface of the ceramic frame body and / or an upper surface of a mounting portion of the ceramic frame body of the base body.   4. The semiconductor element storage device according to claim 1, wherein a recess is provided in a base below a gap between the inner surface of the ceramic frame and the base to store a molten brazing material. 5. package.   5. The package for housing a semiconductor element according to claim 1, wherein a width d of a gap between the inner surface of the ceramic frame and the base is 50 to 200 μm.   6. The semiconductor element storage package according to claim 1, wherein a height h of the semiconductor element mounting convex portion is 100 to 350 [mu] m.

Images