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JP2009231742A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2009231742A
JP2009231742A JP2008078287A JP2008078287A JP2009231742A JP 2009231742 A JP2009231742 A JP 2009231742A JP 2008078287 A JP2008078287 A JP 2008078287A JP 2008078287 A JP2008078287 A JP 2008078287A JP 2009231742 A JP2009231742 A JP 2009231742A
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Prior art keywords
external connection
connection lead
hole
substrate
semiconductor device
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JP2008078287A
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JP5202062B2 (en
Inventor
Noriaki Suzuki
鈴木　　教章
Katsufumi Nakanishi
克文 中西
Ryokei Suzuki
亮兄 鈴木
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Shindengen Electric Manufacturing Co Ltd
Akita Shindengen Co Ltd
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Shindengen Electric Manufacturing Co Ltd
Akita Shindengen Co Ltd
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Priority to JP2008078287A priority Critical patent/JP5202062B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a configuration in which a substrate for disposing a semiconductor chip and an external connection lead electrically connected to the semiconductor chip are formed by different members, wherein a molding resin for integrally fixing them is free from peeling of the external connection lead. <P>SOLUTION: The semiconductor device 1 is provided in which an external connection lead 11 is formed of a plate material having conductivity, an embedded portion 115 embedded in a molding resin 9 and a protruding portion 114 protruding on the outside of the molding resin 9 are provided, the embedded portion 115 consists of a disposed portion 110 disposed on a surface 5a of the substrate 5 and a discrete portion spaced from the surface 5a of the substrate 5, a plurality of through-holes 116 penetrating in the thickness direction of the discrete portion are formed on the discrete portion, and at least the penetrating directions of the two through-holes 116 are inclined relatively. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

この発明は、半導体チップを配する基板と半導体チップに電気接続される外部接続リードとを別部材により形成した構成の半導体装置に関する。   The present invention relates to a semiconductor device having a configuration in which a substrate on which a semiconductor chip is arranged and an external connection lead electrically connected to the semiconductor chip are formed by separate members.

従来の半導体装置としては、例えば図６に示すように、ダイアイランド５０１（基板）に半導体チップ５０４を固着し、ワイヤ５０５により半導体チップ５０４とダイアイランド５０１に一体に形成された吊りリード５０２（外部接続リード）とを電気接続したものがある（特許文献１参照）。また、この半導体装置では、ダイアイランド５０１、半導体チップ５０４、ワイヤ５０５及びワイヤ５０５のボンディング部分を含む吊りリード５０２の一部がモールド樹脂５０６によって封止されている。
そして、吊りリード５０２のうちモールド樹脂５０６によって封止される部分には、その厚さ方向に貫通するアンカーホール５０３（貫通孔）が形成されており、吊リード２の一部がモールド樹脂５０６によって封止された状態においては、アンカーホール５０３にも樹脂が充填される。この構成では、吊りリード５０２とモールド樹脂５０６との間にアンカー効果が生じ、このアンカー効果によって一体に形成されたダイアイランド５０１及び吊りリード５０２とモールド樹脂５０６との接着強度向上を図っている。
ところで、半導体装置には、その設計自由度を向上させるために、半導体チップを配置する基板と半導体チップに電気接続される外部接続リードとを別部材により形成したものがある。この場合には、半導体チップや基板に対する外部接続リードの配置を自由に設定することができ、また、半導体チップに流す電流の大きさに応じて外部接続リードの材質や形状を容易に変更することもできる。
実公平７−４５９６５号公報 As a conventional semiconductor device, for example, as shown in FIG. 6, a semiconductor chip 504 is fixed to a die island 501 (substrate), and a suspension lead 502 (externally formed integrally with the semiconductor chip 504 and the die island 501 by a wire 505. Connection leads) are electrically connected (see Patent Document 1). In this semiconductor device, part of the suspension lead 502 including the die island 501, the semiconductor chip 504, the wire 505, and the bonding portion of the wire 505 is sealed with the mold resin 506.
An anchor hole 503 (through hole) penetrating in the thickness direction is formed in a portion of the suspension lead 502 sealed by the mold resin 506, and a part of the suspension lead 2 is formed by the mold resin 506. In the sealed state, the anchor hole 503 is also filled with resin. In this configuration, an anchor effect is generated between the suspension lead 502 and the mold resin 506, and the die island 501 and the suspension lead 502 formed integrally with the mold resin 506 are improved by the anchor effect.
Incidentally, some semiconductor devices have a substrate on which a semiconductor chip is arranged and an external connection lead electrically connected to the semiconductor chip formed by different members in order to improve the degree of design freedom. In this case, the arrangement of the external connection leads with respect to the semiconductor chip and the substrate can be freely set, and the material and shape of the external connection leads can be easily changed according to the magnitude of the current flowing through the semiconductor chip. You can also.
No. 7-45965

しかしながら、基板と外部接続リードとを別部材により形成した場合には、特許文献１のように、外部接続リードにアンカーホールを形成するだけでは、モールド樹脂の外方に突出する外部接続リードの突出部分に様々な方向から外力が加えられた際に、外部接続リードがモールド樹脂から剥がれやすい、という問題がある。
すなわち、特許文献１のように、ダイアイランド５０１及び吊りリード５０２が一体に形成されている場合には、樹脂封止されているダイアイランド５０１もモールド樹脂に対する吊りリード５０２の剥がれを防止する役割を果たしている。これに対して、基板と外部接続リードとを別部材により形成した場合には、外部接続リードの突出部分に様々な方向から外力が加えられた際に、１つのアンカーホールによるモールド樹脂と外部接続リードとの係合部分のみに応力が集中するため、外部接続リードが剥がれやすくなる。 However, when the substrate and the external connection lead are formed of different members, as in Patent Document 1, the protrusion of the external connection lead that protrudes outward from the mold resin simply by forming an anchor hole in the external connection lead. There is a problem that when an external force is applied to the portion from various directions, the external connection lead is easily peeled off from the mold resin.
That is, as in Patent Document 1, when the die island 501 and the suspension lead 502 are integrally formed, the die island 501 sealed with resin also serves to prevent the suspension lead 502 from peeling off from the mold resin. Plays. On the other hand, when the substrate and the external connection lead are formed of different members, when external force is applied to the protruding portion of the external connection lead from various directions, the mold resin and the external connection by one anchor hole are used. Since stress concentrates only on the engaging portion with the lead, the external connection lead is easily peeled off.

本発明はこのような事情を考慮してなされたものであって、外部接続リードとモールド樹脂とが互いに剥がれることを防止して、半導体装置の信頼性向上を図ることができる導体装置を提供することを目的とする。   The present invention has been made in view of such circumstances, and provides a conductor device capable of preventing the external connection lead and the mold resin from being separated from each other and improving the reliability of the semiconductor device. For the purpose.

この課題を解決するために、本発明の半導体装置は、基板と、該基板の表面に配される半導体チップと、前記半導体チップと電気接続される外部接続リードと、前記基板、前記半導体チップ及び外部接続リードを一体に固定するモールド樹脂とを備え、前記外部接続リードは、導電性を有する板材によって形成されると共に、前記モールド樹脂内に埋設される埋設部と、前記モールド樹脂の外方に突出する突出部とを備え、前記埋設部は、前記基板の表面に配される配置部分と、前記基板の表面から離間している離間部分とからなり、当該離間部分に、前記外部接続リードの厚さ方向に貫通する貫通孔が複数形成され、少なくとも２つの前記貫通孔の貫通方向が相対的に傾斜していることを特徴としている。   In order to solve this problem, a semiconductor device of the present invention includes a substrate, a semiconductor chip disposed on the surface of the substrate, an external connection lead electrically connected to the semiconductor chip, the substrate, the semiconductor chip, and A mold resin that integrally fixes the external connection lead, and the external connection lead is formed of a conductive plate material, and is embedded in the mold resin and on the outside of the mold resin. The embedded portion includes an arrangement portion disposed on the surface of the substrate and a separation portion spaced from the surface of the substrate, and the separation portion includes a portion of the external connection lead. A plurality of through holes penetrating in the thickness direction are formed, and the through direction of at least two of the through holes is relatively inclined.

この半導体装置によれば、複数の貫通孔にモールド樹脂が充填されることで、外部接続リードとモールド樹脂とのアンカー効果が向上する。すなわち、外部接続リードの突出部に様々な方向から外力が加えられても、外部接続リードとモールド樹脂とが互いに剥がれることを防止することができる。
また、複数の貫通孔を形成することで、各貫通孔の開口面積を小さくしても、十分なアンカー効果を得ることが可能となる。そして、各貫通孔の開口面積を小さくすることで、電流が流れる外部接続リードの断面積も大きく確保することができるため、外部接続リードにより多くの電流を流すことも可能となる。 According to this semiconductor device, the anchor effect between the external connection lead and the mold resin is improved by filling the plurality of through holes with the mold resin. That is, even if an external force is applied to the protruding portion of the external connection lead from various directions, it is possible to prevent the external connection lead and the mold resin from being separated from each other.
Further, by forming a plurality of through holes, it is possible to obtain a sufficient anchor effect even if the opening area of each through hole is reduced. Further, by reducing the opening area of each through hole, it is possible to secure a large cross-sectional area of the external connection lead through which a current flows, and thus it is possible to pass a large amount of current through the external connection lead.

そして、前記半導体装置において、これら複数の前記貫通孔を前記外部接続リードの面方向に沿って千鳥状に配置した場合には、貫通孔の形成に基づく外部接続リードの剛性低下を抑制することができる。   In the semiconductor device, when the plurality of through holes are arranged in a staggered manner along the surface direction of the external connection lead, it is possible to suppress a decrease in rigidity of the external connection lead based on the formation of the through hole. it can.

さらに、前記半導体装置においては、前記貫通孔の開口部分にバリが形成されていてもよい。
この構成の半導体装置では、貫通孔のバリとモールド樹脂との間にもアンカー効果が生じるため、外部接続リードとモールド樹脂との接着強度をさらに向上することができる。 Furthermore, in the semiconductor device, burrs may be formed in the opening portions of the through holes.
In the semiconductor device having this configuration, an anchor effect also occurs between the burr of the through hole and the mold resin, so that the adhesive strength between the external connection lead and the mold resin can be further improved.

また、前記半導体装置においては、前記埋設部の離間部分に、前記板材を屈曲した屈曲部が形成され、当該屈曲部に第１の貫通孔が形成され、前記屈曲部を除く前記離間部分に第２の貫通孔が形成され、前記第１の貫通孔及び前記第２の貫通孔が相対的に傾斜していてもよい。
上記構成の外部接続リードを製造する際には、板材を屈曲させる前の状態において、埋設部の離間部分のうち、屈曲部となる部分、及び、屈曲部分とはならない平板部分に、それぞれ第１の貫通孔及び第２の貫通孔を形成すればよい。この段階においては、前述した２つの部分に形成される第１の貫通孔及び第２の貫通孔の貫通方向が、互いに同じとなっていてよい。そして、第１の貫通孔及び第２の貫通孔の形成後に、板材を屈曲して屈曲部を形成することにより、屈曲部に形成された第１の貫通孔の貫通方向が、平板部分に形成された第２の貫通孔の貫通方向に対して傾斜することになる。
すなわち、貫通孔を屈曲部に形成する場合には、貫通孔の形成時にその貫通方向を同じとすることができるため、貫通方向が相対的に傾斜する２つの貫通孔を容易に形成することができる。 Further, in the semiconductor device, a bent portion obtained by bending the plate member is formed in a separated portion of the embedded portion, a first through hole is formed in the bent portion, and a first portion is formed in the separated portion excluding the bent portion. Two through holes may be formed, and the first through hole and the second through hole may be relatively inclined.
When manufacturing the external connection lead having the above-described configuration, in the state before the plate material is bent, the first portion is provided on the portion that becomes the bent portion and the flat plate portion that does not become the bent portion, respectively. The through hole and the second through hole may be formed. In this stage, the penetration directions of the first through hole and the second through hole formed in the two portions described above may be the same. Then, after forming the first through hole and the second through hole, the plate material is bent to form a bent portion, whereby the through direction of the first through hole formed in the bent portion is formed in the flat plate portion. It will incline with respect to the penetration direction of the made 2nd through-hole.
That is, when the through hole is formed in the bent portion, since the through direction can be made the same when the through hole is formed, it is possible to easily form two through holes in which the through direction is relatively inclined. it can.

本発明によれば、外部接続リードの突出部に様々な方向から外力が加えられても、外部接続リードとモールド樹脂とが互いに剥がれることを防止でき、結果として、半導体装置の信頼性向上を図ることができる。   According to the present invention, it is possible to prevent the external connection lead and the mold resin from being peeled from each other even when an external force is applied to the protruding portion of the external connection lead from various directions. As a result, the reliability of the semiconductor device is improved. be able to.

以下、図面を参照して本発明の一実施形態について説明する。
図１に示すように、この実施形態に係る半導体装置１は、厚板状のヒートシンク３の表面３ａに、セラミック基板（基板）５及び半導体チップ７を順次重ねて配すると共に、ヒートシンク３の裏面３ｂが外方に露出するように、ヒートシンク３、セラミック基板５及び半導体チップ７をモールド樹脂９により埋設して構成されている。また、セラミック基板５の表面５ａには、半導体チップ７と同様に、複数（図示例では２つ）の外部接続リード１１が配されており、一部（図示例では１つ）の外部接続リード１１Ｂは、導電性を有する板状の接続板１３を介して半導体チップ７と電気接続されている。
ヒートシンク３は、例えば、銅（Ｃｕ）、タングステン、モリブデン等のように、放熱性の高い材料によって厚板状に形成されているが、これに加えて例えばＮｉメッキを施したものでもよい。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
As shown in FIG. 1, the semiconductor device 1 according to this embodiment has a ceramic substrate (substrate) 5 and a semiconductor chip 7 sequentially stacked on a surface 3 a of a thick plate-like heat sink 3 and a back surface of the heat sink 3. The heat sink 3, the ceramic substrate 5, and the semiconductor chip 7 are embedded with a mold resin 9 so that 3 b is exposed to the outside. Similarly to the semiconductor chip 7, a plurality (two in the illustrated example) of external connection leads 11 are arranged on the surface 5 a of the ceramic substrate 5, and a part (one in the illustrated example) of the external connection leads 11 is disposed. 11B is electrically connected to the semiconductor chip 7 via a plate-like connection plate 13 having conductivity.
The heat sink 3 is formed in a thick plate shape with a material having high heat dissipation, such as copper (Cu), tungsten, molybdenum, or the like, but may be Ni plated, for example.

セラミック基板５は、電気的な絶縁性を有するセラミック板５１の表面５１ａ及び裏面５１ｂに導電性を有する配線パターン５２，５３，５４を形成して構成されている。ここで、セラミック板５１の表面５１ａには複数の配線パターン５２，５３が形成されているが、これらは互いに電気的に絶縁されている。
半導体チップ７は、このセラミック基板５の表面５ａの中央部分に配されており、半田（不図示）を介してセラミック板５１の表面５１ａの中央部分から周縁部分の一端にわたって形成された第１配線パターン５２に固定されている。また、一の外部接続リード１１Ａは、セラミック基板５の表面５ａのうち周縁部分の一端に配されており、半田（不図示）を介して第１配線パターン５２に接合されている。すなわち、半導体チップ７と一の外部接続リード１１Ａとは、第１配線パターン５２を介して相互に電気接続されている。 The ceramic substrate 5 is configured by forming conductive wiring patterns 52, 53, and 54 on the front surface 51 a and the back surface 51 b of an electrically insulating ceramic plate 51. Here, a plurality of wiring patterns 52 and 53 are formed on the surface 51a of the ceramic plate 51, and these are electrically insulated from each other.
The semiconductor chip 7 is arranged at the central portion of the surface 5a of the ceramic substrate 5, and is formed from the central portion of the surface 51a of the ceramic plate 51 to one end of the peripheral portion via solder (not shown). It is fixed to the pattern 52. One external connection lead 11A is disposed at one end of the peripheral portion of the surface 5a of the ceramic substrate 5, and is joined to the first wiring pattern 52 via solder (not shown). That is, the semiconductor chip 7 and the one external connection lead 11 </ b> A are electrically connected to each other via the first wiring pattern 52.

そして、他の外部接続リード１１Ｂは、セラミック基板５の表面５ａのうち周縁部分の他端に配されており、半田（不図示）を介してセラミック板５１の表面５１ａのうち周縁部分の他端に形成された第２配線パターン５３に固定されている。
さらに、ヒートシンク３は、セラミック基板５の裏面５ｂに配されており、具体的には半田（不図示）を介してセラミック板５１の裏面５１ｂに形成された第３配線パターン５４に固定されている。すなわち、ヒートシンク３は、セラミック基板５によって半導体チップ７及び外部接続リード１１に対して電気的に絶縁されている。 The other external connection lead 11B is arranged at the other end of the peripheral portion of the surface 5a of the ceramic substrate 5, and the other end of the peripheral portion of the surface 51a of the ceramic plate 51 via solder (not shown). The second wiring pattern 53 is fixed to the second wiring pattern 53.
Further, the heat sink 3 is disposed on the back surface 5b of the ceramic substrate 5, and specifically, is fixed to a third wiring pattern 54 formed on the back surface 51b of the ceramic plate 51 via solder (not shown). . That is, the heat sink 3 is electrically insulated from the semiconductor chip 7 and the external connection lead 11 by the ceramic substrate 5.

また、接続板１３の両端は、それぞれ半田（不図示）を介して半導体チップ７の表面７ａ、及び、後述する他の外部接続リード１１Ｂの内部接続部１１０の表面に接合されており、これによって、半導体チップ７と他の外部接続リード１１Ｂとが電気接続されることになる。なお、図示例のように、半導体チップ７の表面７ａ及び内部接続部１１０の表面の高さ位置が互いに異なる場合には、接続板１３の中途部に屈曲した段差部１３ａを形成しておけばよい。これにより、半導体チップ７の表面７ａ及び内部接続部１１０の表面の両方に対して接続板１３を安定して接合することができる。   Further, both ends of the connection plate 13 are joined to the surface 7a of the semiconductor chip 7 and the surfaces of the internal connection portions 110 of other external connection leads 11B described later via solder (not shown), respectively. The semiconductor chip 7 and the other external connection lead 11B are electrically connected. If the height positions of the surface 7a of the semiconductor chip 7 and the surface of the internal connection portion 110 are different from each other as in the illustrated example, a stepped portion 13a that is bent in the middle of the connection plate 13 is formed. Good. As a result, the connection plate 13 can be stably bonded to both the surface 7 a of the semiconductor chip 7 and the surface of the internal connection portion 110.

各外部接続リード１１は、図１及び図２に示すように、導電性を有する板材を２箇所において屈曲させて断面視クランク形状に形成して構成されており、セラミック基板５の表面５ａをなす配線パターン５２，５３に固定される平板状の内部接続部（配置部分）１１０と、第１屈曲部１１１を介して内部接続部１１０に連ねて形成された平板状の垂直板部１１２と、第２屈曲部１１３を介して垂直板部１１２に連ねて形成された平板状の突出部１１４とを備えている。なお、垂直板部１１２は、外部接続リード１１をセラミック基板５に固定した状態において、セラミック基板５の表面５ａから上方に延びるように配される。また、突出部１１４は、セラミック基板５の面方向に沿ってセラミック基板５から離れるように延出している。   As shown in FIGS. 1 and 2, each external connection lead 11 is formed by bending a conductive plate material at two locations to form a crank shape in cross section, and forms a surface 5a of the ceramic substrate 5. A flat plate-like internal connection portion (arrangement portion) 110 fixed to the wiring patterns 52 and 53, a flat plate-like vertical plate portion 112 formed continuously to the internal connection portion 110 via the first bent portion 111, and a first And a flat plate-like protruding portion 114 formed continuously to the vertical plate portion 112 via the two bent portions 113. The vertical plate portion 112 is arranged to extend upward from the surface 5 a of the ceramic substrate 5 in a state where the external connection leads 11 are fixed to the ceramic substrate 5. Further, the protruding portion 114 extends away from the ceramic substrate 5 along the surface direction of the ceramic substrate 5.

ここで、内部接続部１１０、第１屈曲部１１１、垂直板部１１２及び第２屈曲部１１３は、モールド樹脂９内に埋設される埋設部１１５を構成しており、突出部１１４は、モールド樹脂９の外方に突出している。また、埋設部１１５のうち第１屈曲部１１１、垂直板部１１２及び第２屈曲部１１３は、セラミック基板５の表面５ａから離間した位置に配され、埋設部１１５の離間部分をなしている。さらに、内部接続部１１０は、その幅方向（図２におけるＸ軸方向）に沿って垂直板部１１２及び突出部１１４よりも幅広に形成されており、内部接続部１１０と配線パターン５２，５３との接合面積の拡大を図っている。また、内部接続部１１０の幅広部分には、第１屈曲部１１１も連ねて形成されており、これによって内部接続部１１０の幅広部分の剛性向上が図られている。   Here, the internal connection portion 110, the first bent portion 111, the vertical plate portion 112, and the second bent portion 113 constitute an embedded portion 115 embedded in the mold resin 9, and the protruding portion 114 is the mold resin. 9 protrudes outward. In addition, the first bent portion 111, the vertical plate portion 112, and the second bent portion 113 of the embedded portion 115 are arranged at positions separated from the surface 5 a of the ceramic substrate 5, and form a separated portion of the embedded portion 115. Furthermore, the internal connection part 110 is formed wider than the vertical plate part 112 and the protrusion part 114 along the width direction (X-axis direction in FIG. 2), and the internal connection part 110 and the wiring patterns 52 and 53 The joint area is expanded. Further, the first bent portion 111 is also formed at the wide portion of the internal connection portion 110 so that the rigidity of the wide portion of the internal connection portion 110 is improved.

垂直板部１１２には、図２から図４に示すように、その厚さ方向に貫通する貫通孔１１６が複数（図示例では５つ）形成されている。各貫通孔１１６の開口部分には、貫通孔１１６の形成時に生じるバリ（かえり）１１７が形成されている。そして、複数の貫通孔１１６は、垂直板部１１２の面方向に沿って、具体的には垂直板部１１２の幅方向（Ｘ軸方向）に沿って千鳥状に配列されている。また、全ての貫通孔１１６の貫通方向は相対的に傾斜している。   As shown in FIGS. 2 to 4, the vertical plate portion 112 has a plurality of through holes 116 (five in the illustrated example) penetrating in the thickness direction. At the opening portion of each through-hole 116, a burr 117 that is generated when the through-hole 116 is formed is formed. The plurality of through holes 116 are arranged in a staggered manner along the surface direction of the vertical plate portion 112, specifically, along the width direction (X-axis direction) of the vertical plate portion 112. Moreover, the penetration direction of all the through holes 116 is relatively inclined.

すなわち、図示例において、突出部１１４に近い側に形成される３つの貫通孔１１６Ａ，１１６Ｂ，１１６Ｃのうち幅方向の真ん中に形成される第１貫通孔１１６Ａの貫通方向は、垂直板部１１２の面方向（ＸＺ平面に沿う方向）に直交している。さらに、図３，４において第１貫通孔１１６Ａの右側に形成された第２貫通孔１１６Ｂ、及び、第１貫通孔１１６Ａの左側に形成された第３貫通孔１１６Ｃの貫通方向は、それぞれ第１貫通孔１１６Ａの貫通方向に対してＸ軸方向に傾斜しており、また、互いに逆向きに傾斜している。なお、図３において、Ｙ軸方向に沿って紙面の手前側から奥側に向かう方向で考えた場合、第２貫通孔１１６Ｂの貫通方向は左向きに傾斜しており、第３の貫通孔１１６Ｃの貫通方向は右向きに傾斜している。   That is, in the illustrated example, the through direction of the first through hole 116A formed in the middle of the width direction among the three through holes 116A, 116B, and 116C formed on the side close to the protruding portion 114 is the vertical plate portion 112. It is orthogonal to the surface direction (direction along the XZ plane). 3 and 4, the second through hole 116B formed on the right side of the first through hole 116A and the third through hole 116C formed on the left side of the first through hole 116A are respectively in the first through direction. It inclines in the X-axis direction with respect to the through direction of the through hole 116A, and inclines in opposite directions. In FIG. 3, when considering the direction from the front side to the back side of the paper surface along the Y-axis direction, the penetrating direction of the second through hole 116B is inclined leftward, and the third through hole 116C The penetration direction is inclined to the right.

そして、内部接続部１１０に近い側に形成される２つの貫通孔１１６Ｄ，１１６Ｅの貫通方向は、第１貫通孔１１６Ａの貫通方向に対してＺ軸方向に傾斜しており、また、互いに逆向きに傾斜している。なお、図３において、Ｙ軸方向に沿って紙面の手前側から奥側に向かう方向で考えた場合、Ｘ軸方向に沿って第２貫通孔１１６Ｂ側に寄せて配された第４貫通孔１１６Ｄの貫通方向は上向きに傾斜しており、また、第３貫通孔１１６Ｃ側に寄せて配された第５貫通孔１１６Ｅの貫通方向は下向きに傾斜している。図１に示すように、これら複数の貫通孔１１６内には、いずれもモールド樹脂９が充填されている。   And the penetration direction of two penetration holes 116D and 116E formed in the side near internal connection part 110 inclines in the Z-axis direction to the penetration direction of the first penetration hole 116A, and is opposite to each other. It is inclined to. In FIG. 3, when considering the direction from the near side to the back side of the sheet along the Y-axis direction, the fourth through-hole 116 </ b> D arranged close to the second through-hole 116 </ b> B along the X-axis direction. The through direction is inclined upward, and the through direction of the fifth through hole 116E arranged close to the third through hole 116C is inclined downward. As shown in FIG. 1, the plurality of through holes 116 are filled with a mold resin 9.

複数の貫通孔１１６は、例えば打抜き加工等によって形成され、この形成時に前述したバリ１１７が発生する。なお、貫通孔１１６の形成加工は、単独で行われてもよいが、例えば、プレス加工等により板材を切断して屈曲部１１１，１１３形成前の外部接続リード１１を形成する際、あるいは、この平板状の外部接続リード１１に折り曲げ加工を施して屈曲部１１１，１１３を形成する際に、同時に形成されてもよい。また、屈曲部１１１，１１３は、前述した板材の切断時に同時に形成されてもよく、この際に貫通孔１１６を同時に形成してもよい。   The plurality of through-holes 116 are formed, for example, by punching or the like, and the above-described burrs 117 are generated during the formation. The through hole 116 may be formed by a single process. For example, when forming the external connection lead 11 before forming the bent portions 111 and 113 by cutting the plate material by pressing or the like, When the bent portions 111 and 113 are formed by bending the flat external connection lead 11, they may be formed at the same time. Further, the bent portions 111 and 113 may be formed at the same time as the above-described cutting of the plate material, and at this time, the through hole 116 may be formed at the same time.

以上のように構成された半導体装置１を製造する際には、はじめに、ヒートシンク３の表面３ａにセラミック基板５、半導体チップ７、外部接続リード１１及び接続板１３を順次重ねて配置する。そして、この配置状態において、リフローにより半田を溶融、固化させることで、ヒートシンク３、セラミック基板５、半導体チップ７、外部接続リード１１及び接続板１３が一体に固定される。
その後、一体固定されたヒートシンク３、セラミック基板５、半導体チップ７、外部接続リード１１及び接続板１３をモールド樹脂９成形用の金型内に入れ、金型内に溶融した樹脂を流し込む。これにより、モールド樹脂９が形成され、半導体装置１の製造が完了する。なお、樹脂を流し込む際には、外部接続リード１１の貫通孔１１６内にもモールド樹脂９が充填される。 When manufacturing the semiconductor device 1 configured as described above, first, the ceramic substrate 5, the semiconductor chip 7, the external connection lead 11, and the connection plate 13 are sequentially stacked on the surface 3 a of the heat sink 3. In this arrangement state, the heat sink 3, the ceramic substrate 5, the semiconductor chip 7, the external connection lead 11, and the connection plate 13 are integrally fixed by melting and solidifying the solder by reflow.
Thereafter, the heat sink 3, the ceramic substrate 5, the semiconductor chip 7, the external connection lead 11 and the connection plate 13 that are integrally fixed are placed in a mold for molding the mold resin 9, and the molten resin is poured into the mold. Thereby, the mold resin 9 is formed and the manufacture of the semiconductor device 1 is completed. When the resin is poured, the mold resin 9 is also filled in the through hole 116 of the external connection lead 11.

以上説明したように、上記実施形態による半導体装置１によれば、貫通方向が互いに異なる複数の貫通孔１１６が外部接続リード１１に形成されているため、これら複数の貫通孔１１６にモールド樹脂９が充填されることで、外部接続リード１１とモールド樹脂９とのアンカー効果が向上する。すなわち、外部接続リード１１の突出部１１４に様々な方向から外力が加えられても、外部接続リード１１とモールド樹脂９とが互いに剥がれることを防止することができる。したがって、半導体装置１の信頼性向上を図ることができる。
また、複数の貫通孔１１６を形成することで、各貫通孔１１６の開口面積を小さくしても、十分なアンカー効果を得ることが可能となる。そして、各貫通孔１１６の開口面積を小さくすることで、電流が流れる外部接続リード１１の断面積も大きく確保することができるため、外部接続リード１１により多くの電流を流すことも可能となる。 As described above, according to the semiconductor device 1 according to the above embodiment, since the plurality of through holes 116 having different through directions are formed in the external connection lead 11, the mold resin 9 is formed in the plurality of through holes 116. By filling, the anchor effect between the external connection lead 11 and the mold resin 9 is improved. That is, even if an external force is applied to the protruding portion 114 of the external connection lead 11 from various directions, it is possible to prevent the external connection lead 11 and the mold resin 9 from being separated from each other. Therefore, the reliability of the semiconductor device 1 can be improved.
In addition, by forming the plurality of through holes 116, a sufficient anchor effect can be obtained even if the opening area of each through hole 116 is reduced. Further, by reducing the opening area of each through-hole 116, it is possible to secure a large cross-sectional area of the external connection lead 11 through which current flows, and thus it is possible to pass a large amount of current through the external connection lead 11.

さらに、これら複数の貫通孔１１６が千鳥状に配置されているため、貫通孔１１６の形成に基づく外部接続リード１１の剛性低下を抑制することもできる。
また、貫通孔１１６の開口部分にバリ１１７を形成しておくことにより、バリ１１７とモールド樹脂９との間にもアンカー効果が生じるため、外部接続リード１１とモールド樹脂９との接着強度をさらに向上することができる。 Further, since the plurality of through holes 116 are arranged in a staggered manner, it is possible to suppress a decrease in rigidity of the external connection lead 11 based on the formation of the through holes 116.
Further, since the burr 117 is formed in the opening portion of the through-hole 116, an anchor effect is also generated between the burr 117 and the mold resin 9, so that the adhesive strength between the external connection lead 11 and the mold resin 9 is further increased. Can be improved.

以上、本発明の実施形態である半導体装置について説明したが、本発明の技術的範囲はこれに限定されることはなく、本発明の技術的思想を逸脱しない範囲で適宜変更可能である。
例えば、貫通孔１１６の数及び貫通方向は、上記実施形態に限らず、少なくとも複数の貫通孔１１６が形成されていればよく、また、複数の貫通孔１１６のうち少なくとも２つの貫通孔１１６の貫通方向が相対的に傾斜していればよい。したがって、その他の貫通孔１１６については、その貫通方向が同じであっても構わない。 Although the semiconductor device according to the embodiment of the present invention has been described above, the technical scope of the present invention is not limited to this, and can be appropriately changed without departing from the technical idea of the present invention.
For example, the number and the through direction of the through holes 116 are not limited to the above-described embodiment, and it is sufficient that at least a plurality of through holes 116 are formed. The direction should just be inclined relatively. Therefore, the other through holes 116 may have the same penetration direction.

また、複数の貫通孔１１６は、垂直板部１１２に形成されるとしたが、少なくとも埋設部１１５のうちセラミック基板５の表面５ａから離間している離間部分に形成されていればよい。したがって、例えば図５に示すように、屈曲部１１１，１１３及び垂直板部１１２にそれぞれ貫通孔１１６が形成されてもよい。なお、当該図示例においては、第２屈曲部１１３に一の貫通孔１１６が形成されており、垂直板部１１２に他の貫通孔１１６が形成されている。
ここで、この構成の外部接続リード１１を製造する際には、外部接続リード１１をなす板材を屈曲させる前の状態（図５における２点鎖線）において、第２屈曲部１１３となる部分、及び、垂直板部１１２となる部分（屈曲部にはならない平板部分）にそれぞれ貫通孔１１６を形成すればよい。この段階においては、前述した２つの部分に形成される貫通孔１１６の貫通方向が同じとなっていてもよい。 In addition, although the plurality of through holes 116 are formed in the vertical plate portion 112, it is sufficient that they are formed at least in a separated portion of the embedded portion 115 that is separated from the surface 5a of the ceramic substrate 5. Therefore, for example, as shown in FIG. 5, through holes 116 may be formed in the bent portions 111 and 113 and the vertical plate portion 112, respectively. In the illustrated example, one through hole 116 is formed in the second bent portion 113, and another through hole 116 is formed in the vertical plate portion 112.
Here, when manufacturing the external connection lead 11 having this configuration, in the state before the plate material forming the external connection lead 11 is bent (two-dot chain line in FIG. 5), The through-holes 116 may be formed in portions that become the vertical plate portions 112 (flat plate portions that do not become bent portions). At this stage, the penetration directions of the through holes 116 formed in the two portions described above may be the same.

そして、貫通孔１１６の形成後に板材を屈曲して第２屈曲部１１３を形成すると、第２屈曲部１１３に形成された貫通孔１１６の貫通方向が、垂直板部１１２に形成された貫通孔１１６の貫通方向に対して傾斜することになる。具体的に、第２屈曲部１１３の貫通孔１１６の貫通方向は、垂直板部１１２に対する第２屈曲部１１３の屈曲方向（図５における矢印Ｒ）に傾斜することになる。
したがって、貫通孔１１６を屈曲部１１１，１１３に形成する場合には、複数の貫通孔１１６の形成時にその貫通方向を同じとすることができるため、貫通方向が相対的に傾斜する２つの貫通孔１１６を容易に形成することができる。 Then, when the second bent portion 113 is formed by bending the plate material after the through hole 116 is formed, the through direction of the through hole 116 formed in the second bent portion 113 is the through hole 116 formed in the vertical plate portion 112. It will incline with respect to the penetration direction. Specifically, the penetration direction of the through hole 116 of the second bent portion 113 is inclined in the bending direction of the second bent portion 113 with respect to the vertical plate portion 112 (arrow R in FIG. 5).
Therefore, when the through-hole 116 is formed in the bent portions 111 and 113, since the through-direction can be made the same when forming the plurality of through-holes 116, the two through-holes in which the through-direction is relatively inclined 116 can be easily formed.

さらに、外部接続リード１１は、屈曲部１１１，１１３を形成して構成されるとしたが、特に屈曲部１１１，１１３を形成せずに、少なくともモールド樹脂９内に埋設される埋設部とモールド樹脂９から外方に突出する突出部とを備えていればよい。すなわち、外部接続リード１１は例えば平板状に形成されていてもよく、この場合でも、埋設部のうちセラミック基板５の表面５ａから離間している部分に、上記実施形態と同様の貫通孔１１６が形成されていればよい。   Further, the external connection lead 11 is formed by forming the bent portions 111 and 113. However, the external connection lead 11 does not particularly form the bent portions 111 and 113, and at least the embedded portion and the mold resin embedded in the mold resin 9. What is necessary is just to provide the protrusion part which protrudes outward from 9. FIG. That is, the external connection lead 11 may be formed, for example, in a flat plate shape. Even in this case, a through hole 116 similar to that in the above embodiment is formed in a portion of the embedded portion that is separated from the surface 5a of the ceramic substrate 5. It only has to be formed.

また、半導体チップ７と他の外部接続リード１１Ｂとは、接続板１３によって電気接続されるとしたが、半導体チップ７と他の外部接続リード１１Ｂとの間に流れる電流が小さい場合には、例えばワイヤによって電気接続されてもよい。
さらに、セラミック基板５は、配線パターン５２〜５４を形成して構成されるとしたが、少なくともヒートシンク３や半導体チップ７、外部接続リード１１を固定できるように構成されていればよく、例えばセラミック板５１のみによって構成されてもよいし、あるいは、導電性を有する基板としてもよい。
なお、配線パターン５２〜５４を形成しない場合、半導体チップ７の一の外部接続リード１１Ａとの電気接続には、例えば上記実施形態の接続板１３のように別途導電性の板部材を用いてもよい。また、セラミック基板５が導電性を有する基板である場合には、例えば、電気絶縁性を有する接着剤等を介して半導体チップ７やヒートシンク３、外部接続リード１１を基板に接着すればよい。 Further, the semiconductor chip 7 and the other external connection lead 11B are electrically connected by the connection plate 13, but when the current flowing between the semiconductor chip 7 and the other external connection lead 11B is small, for example, It may be electrically connected by a wire.
Furthermore, although the ceramic substrate 5 is formed by forming the wiring patterns 52 to 54, it may be configured to fix at least the heat sink 3, the semiconductor chip 7, and the external connection leads 11, for example, a ceramic plate It may be constituted only by 51 or may be a conductive substrate.
In the case where the wiring patterns 52 to 54 are not formed, a conductive plate member may be used for electrical connection with one external connection lead 11A of the semiconductor chip 7 as in the connection plate 13 of the above-described embodiment, for example. Good. When the ceramic substrate 5 is a conductive substrate, for example, the semiconductor chip 7, the heat sink 3, and the external connection lead 11 may be bonded to the substrate through an adhesive having electrical insulation.

上記実施形態においては、ヒートシンク３を備える半導体装置１について説明したが、本発明は、半導体チップ７を配置する基板５と、半導体チップ７に電気接続される外部接続リード１１とを別部材により形成し、これらをモールド樹脂９により一体に固定した構成の半導体装置に適用することができる。   In the above embodiment, the semiconductor device 1 including the heat sink 3 has been described. However, in the present invention, the substrate 5 on which the semiconductor chip 7 is arranged and the external connection lead 11 electrically connected to the semiconductor chip 7 are formed by separate members. However, these can be applied to a semiconductor device having a configuration in which these are integrally fixed by a mold resin 9.

本発明の一実施形態である半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which is one Embodiment of this invention. 図１の半導体装置を構成する外部接続リードを示す斜視図である。FIG. 2 is a perspective view showing an external connection lead constituting the semiconductor device of FIG. 1. 図２の外部接続リードを示す正面図である。FIG. 3 is a front view showing an external connection lead of FIG. 2. 図３のＡ−Ａ矢視断面図である。It is AA arrow sectional drawing of FIG. 図１の半導体装置を構成する外部接続リードの変形例を示す要部拡大断面図である。FIG. 9 is an enlarged cross-sectional view of a main part showing a modification of the external connection lead constituting the semiconductor device of FIG. 従来の半導体装置の一例を示す概略斜視図である。It is a schematic perspective view which shows an example of the conventional semiconductor device.

符号の説明Explanation of symbols

１ 半導体装置
５ セラミック基板（基板）
５ａ 表面
７ 半導体チップ
９ モールド樹脂
１１ 外部接続リード
１１０ 内部接続部（配置部分）
１１１ 第１屈曲部
１１３ 第２屈曲部
１１４ 突出部
１１５ 埋設部
１１６ 貫通孔
１１７ バリ 1 Semiconductor Device 5 Ceramic Substrate (Substrate)
5a Surface 7 Semiconductor chip 9 Mold resin 11 External connection lead 110 Internal connection part (arrangement part)
111 First bent portion 113 Second bent portion 114 Protruding portion 115 Buried portion 116 Through hole 117 Burr

Claims (4)

基板と、該基板の表面に配される半導体チップと、前記半導体チップと電気接続される外部接続リードと、前記基板、前記半導体チップ及び外部接続リードを一体に固定するモールド樹脂とを備え、
前記外部接続リードは、導電性を有する板材によって形成されると共に、前記モールド樹脂内に埋設される埋設部と、前記モールド樹脂の外方に突出する突出部とを備え、
前記埋設部は、前記基板の表面に配される配置部分と、前記基板の表面から離間している離間部分とからなり、
当該離間部分に、前記外部接続リードの厚さ方向に貫通する貫通孔が複数形成され、
少なくとも２つの前記貫通孔の貫通方向が相対的に傾斜していることを特徴とする半導体装置。 A substrate, a semiconductor chip disposed on the surface of the substrate, an external connection lead electrically connected to the semiconductor chip, and a mold resin that integrally fixes the substrate, the semiconductor chip and the external connection lead;
The external connection lead is formed of a conductive plate material, and includes an embedded portion embedded in the mold resin, and a protruding portion protruding outward of the mold resin,
The buried portion is composed of an arrangement portion arranged on the surface of the substrate and a separation portion separated from the surface of the substrate,
A plurality of through-holes penetrating in the thickness direction of the external connection lead are formed in the separated portion,
A semiconductor device, wherein a through direction of at least two through holes is relatively inclined. 複数の前記貫通孔が、前記外部接続リードの面方向に沿って千鳥状に配置されていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the plurality of through holes are arranged in a staggered manner along a surface direction of the external connection lead. 前記貫通孔の開口部分にバリが形成されていることを特徴とする請求項１又は請求項２に記載の半導体装置。   The semiconductor device according to claim 1, wherein a burr is formed in an opening portion of the through hole. 前記埋設部の離間部分に、前記板材を屈曲した屈曲部が形成され、
当該屈曲部に第１貫通孔が形成され、前記屈曲部を除く前記離間部分に第２貫通孔が形成され、前記第１貫通孔及び前記第２貫通孔が相対的に傾斜していることを特徴とする請求項１から請求項３のいずれか１項に記載の半導体装置。 A bent portion formed by bending the plate material is formed in a separation portion of the embedded portion,
A first through hole is formed in the bent portion, a second through hole is formed in the separated portion excluding the bent portion, and the first through hole and the second through hole are relatively inclined. The semiconductor device according to claim 1, wherein the semiconductor device is characterized in that:
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JP2019021684A (en) * 2017-07-12 2019-02-07 株式会社東芝 Semiconductor package
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