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JP2009212263A - Electronic circuit module - Google Patents

Electronic circuit module Download PDF

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JP2009212263A
JP2009212263A JP2008052899A JP2008052899A JP2009212263A JP 2009212263 A JP2009212263 A JP 2009212263A JP 2008052899 A JP2008052899 A JP 2008052899A JP 2008052899 A JP2008052899 A JP 2008052899A JP 2009212263 A JP2009212263 A JP 2009212263A
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Prior art keywords
circuit
electronic
circuit module
insulating substrate
electronic circuit
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JP2008052899A
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Hiroyuki Ishiwata
宏行 石綿
Ichiji Ofune
一司 小舟
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Alps Alpine Co Ltd
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Alps Electric Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic circuit module, can suppress the cost of isolation countermeasures between electronic circuits or circuit blocks, while being capable of attaining isolation between the electronic components or the circuit blocks using a simple configuration and easily miniaturizing the module. <P>SOLUTION: The electronic circuit module 1 includes an insulating board 2, a plurality of electronic components loaded on the insulating board 2 and a ground electrode formed to the insulating board 2. In the electronic circuit module, a plurality of shielding chip components 5, connected to the ground electrode respectively, are arranged between the electronic components requiring at least isolation out of a plurality of electronic parts loaded on the insulating board 2 or between the circuit blocks 3 and 4 composed of a plurality of electronic components. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、同一基板上に送信回路と受信回路のようにアイソレーションを要する電子部品又は複数の電子部品からなる回路ブロックが搭載される電子回路モジュールに関する。   The present invention relates to an electronic circuit module in which an electronic component requiring isolation or a circuit block composed of a plurality of electronic components such as a transmission circuit and a reception circuit is mounted on the same substrate.

従来より、高周波信号を送受信する電子回路モジュールでは、主に送信回路と受信回路との間にアイソレーション対策が施されている。たとえば、同一基板上に搭載する送信回路と受信回路との配設位置を物理的に離したり、送信回路と受信回路との間に電磁シールド用の複数の仕切り板を設けたりしている(例えば、特許文献1又は特許文献2参照)。
特開平11−274970号公報 特開2000−269678号公報
Conventionally, in an electronic circuit module that transmits and receives a high-frequency signal, measures against isolation are mainly provided between a transmission circuit and a reception circuit. For example, the arrangement positions of the transmission circuit and the reception circuit mounted on the same substrate are physically separated, or a plurality of partition plates for electromagnetic shielding are provided between the transmission circuit and the reception circuit (for example, Patent Document 1 or Patent Document 2).
Japanese Patent Laid-Open No. 11-274970 JP 2000-269678 A

ところで、近年の携帯電話機等の送受信機は小型化が求められており、これに伴い送受信回路等を搭載した電子回路モジュールを小型化する必要がある。この場合において、従来のように、送受信回路間やその他回路ブロック間に複数の仕切り板を設けてしまうと、これら仕切り板が電子回路モジュールの小型化の妨げになると共に、電子部品又は回路ブロック同士を接続する接続コネクタ用の開口を仕切り板に形成する必要があるので、簡単に送受信回路等の電磁シールドを実現することができない問題がある。さらに、搭載される製品に応じて異なる部品やレイアウト等に合わせて、仕切り板の加工に供する加工治具を変える必要があるので、製造コストが増大する問題もある。   By the way, recent transmitters and receivers such as mobile phones are required to be downsized. Accordingly, it is necessary to downsize an electronic circuit module equipped with a transmitter / receiver circuit and the like. In this case, if a plurality of partition plates are provided between the transmission / reception circuits and other circuit blocks as in the prior art, these partition plates prevent the electronic circuit module from being downsized, and the electronic components or circuit blocks are connected to each other. Since it is necessary to form an opening for the connection connector for connecting to the partition plate, there is a problem that an electromagnetic shield such as a transmission / reception circuit cannot be easily realized. Furthermore, since it is necessary to change the processing jig used for the processing of the partition plate in accordance with different parts and layouts depending on the product to be mounted, there is a problem that the manufacturing cost increases.

本発明は、かかる点に鑑みてなされたものであり、電子部品又は回路ブロック間のアイソレーション対策用のコストを抑制できると共に、簡単な構成で電子部品又は回路ブロック間のアイソレーションを図ることができ、モジュールの小型化が容易な電子回路モジュールを提供することを目的とする。   The present invention has been made in view of the above points, and can suppress the cost for measures against isolation between electronic components or circuit blocks, and can achieve isolation between electronic components or circuit blocks with a simple configuration. An object of the present invention is to provide an electronic circuit module that can be easily downsized.

本発明の電子回路モジュールは、絶縁基板と、前記絶縁基板上に搭載された複数の電子部品と、前記絶縁基板に形成されたグランド電極とを備えた電子回路モジュールであって、前記絶縁基板上に搭載された複数の電子部品のうち少なくともアイソレーションを要する電子部品間又は複数の電子部品で構成される回路ブロック間に、前記グランド電極にそれぞれ接続された複数のシールド用チップ部品を配列したことを特徴とする。   The electronic circuit module of the present invention is an electronic circuit module comprising an insulating substrate, a plurality of electronic components mounted on the insulating substrate, and a ground electrode formed on the insulating substrate. A plurality of shielding chip components respectively connected to the ground electrode are arranged between electronic components that require at least isolation among a plurality of electronic components mounted on the circuit block or between circuit blocks constituted by a plurality of electronic components. It is characterized by.

この構成によれば、少なくともアイソレーションを要する電子部品間又は回路ブロック間に、グランド電位に維持されたシールド用チップ部品が配列されるので、それらの間に簡易のシールド壁が形成され、仕切り板を設けることなくアイソレーションを図ることができ、電子回路モジュールの小型化を図ることができる。また、従来のように複数の電磁シールド用の仕切り板を設ける必要がないので、シールドに供するコストを抑制することができる。   According to this configuration, since the shielding chip parts maintained at the ground potential are arranged at least between the electronic parts or circuit blocks that require isolation, a simple shield wall is formed between them, and the partition plate Isolation can be achieved without providing an electronic circuit module, and the electronic circuit module can be downsized. Moreover, since it is not necessary to provide a plurality of partition plates for electromagnetic shield as in the conventional case, the cost for providing the shield can be suppressed.

本発明は、上記電子回路モジュールにおいて、前記シールド用チップ部品は、誘電体を挟んで電極が積層される積層型チップコンデンサであり、当該積層型チップコンデンサの少なくとも1つの電極が前記グランド電極に接続していることが好ましい。   According to the present invention, in the electronic circuit module, the shielding chip component is a multilayer chip capacitor in which electrodes are stacked with a dielectric interposed therebetween, and at least one electrode of the multilayer chip capacitor is connected to the ground electrode. It is preferable.

この場合、積層型チップコンデンサは、誘電体を挟んだ電極が狭い間隔で多数積層されているので、電磁シールド効果をより高くすることができる。なお、積層型チップコンデンサの両電極をグランド電極に接続していてもよい。   In this case, in the multilayer chip capacitor, since a large number of electrodes sandwiching a dielectric are stacked at a narrow interval, the electromagnetic shielding effect can be further enhanced. Note that both electrodes of the multilayer chip capacitor may be connected to the ground electrode.

本発明は、上記電子回路モジュールにおいて、第1の回路ブロックが高周波信号を送信する送信回路であり、第2の回路ブロックが高周波信号を受信する受信回路であり、少なくとも送信回路のRF部と受信回路のRF部との境界部に前記シールド用チップ部品を配列したことを特徴とする。   According to the present invention, in the electronic circuit module, the first circuit block is a transmission circuit that transmits a high-frequency signal, and the second circuit block is a reception circuit that receives the high-frequency signal. The shielding chip component is arranged at a boundary portion with the RF portion of the circuit.

これにより、送信回路のRF部と受信回路のRF部との境界部といったモジュール内でも干渉が起きやすい個所にシールド用チップ部品を配列したことで、信号干渉を効果的に抑制することができる。   As a result, the signal chip interference can be effectively suppressed by arranging the shielding chip parts at locations where interference is likely to occur even within the module, such as the boundary between the RF section of the transmission circuit and the RF section of the reception circuit.

本発明は、上記電子回路モジュールにおいて、前記絶縁基板上に搭載された電子部品及び前記シールド用チップ部品を覆う金属性カバーを有し、前記シールド用チップ部品と前記金属性カバーとの間隔が、前記第1及び第2の回路ブロックを伝搬する信号が放射された場合の空気中での1/4波長よりも短いことが好ましい。   The present invention, in the electronic circuit module, having a metallic cover that covers the electronic component mounted on the insulating substrate and the shielding chip component, the gap between the shielding chip component and the metallic cover, It is preferable that the wavelength is shorter than a quarter wavelength in air when a signal propagating through the first and second circuit blocks is emitted.

この場合、シールド用チップ部品と金属性カバーの対向面との間隔を、信号周波数の波長の1/4以下にしたので、シールド用チップ部品と金属性カバーとの対向面との間隙から信号が漏れることをさらに防止することができる。   In this case, since the distance between the shielding chip part and the facing surface of the metallic cover is ¼ or less of the wavelength of the signal frequency, the signal is transmitted from the gap between the shielding chip part and the facing surface of the metallic cover. Leakage can be further prevented.

本発明によれば、電子部品間又は回路ブロック間のアイソレーション対策用のコストを抑制できると共に、仕切り板を用いることなくアイソレーションを図ることができ、容易にモジュールの小型化を図ることができる。   ADVANTAGE OF THE INVENTION According to this invention, while being able to suppress the cost for the countermeasure against isolation between electronic components or between circuit blocks, isolation can be aimed at without using a partition plate, and size reduction of a module can be achieved easily. .

以下、図面を参照して、本発明の実施の形態について詳細に説明する。
図1は、本発明の実施の形態に係る電子回路モジュールの模式図である。図1に示す電子回路モジュール1は、絶縁基板2上に第1及び第2の回路ブロックとなる送信回路3及び受信回路4が設けられている。送信回路3及び受信回路4の間には、回路ブロック間を遮るように複数のシールド用チップ部品5が並んで設けられている。送信回路3及び受信回路4、シールド用チップ部品5、その他の回路ブロック及び電子部品を含むモジュール全体は、図2(a)に示す金属性カバー10で覆っている。なお、本実施の形態では、電子回路モジュール1として、高周波信号を送受信する無線通信機器の送受信回路に用いられる送受信回路モジュールを例に挙げて説明するが、送信回路3及び受信回路4以外であってもアイソレーションが必要な電子回路モジュールであれば適用可能である。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic diagram of an electronic circuit module according to an embodiment of the present invention. The electronic circuit module 1 shown in FIG. 1 is provided with a transmission circuit 3 and a reception circuit 4 serving as first and second circuit blocks on an insulating substrate 2. Between the transmission circuit 3 and the reception circuit 4, a plurality of shielding chip parts 5 are provided side by side so as to block the circuit blocks. The entire module including the transmission circuit 3 and the reception circuit 4, the shielding chip component 5, other circuit blocks and electronic components is covered with a metallic cover 10 shown in FIG. In the present embodiment, the electronic circuit module 1 will be described by taking a transmission / reception circuit module used in a transmission / reception circuit of a wireless communication device that transmits / receives a high-frequency signal as an example. However, any electronic circuit module that requires isolation can be applied.

先に、本実施の形態における電子回路モジュール1の回路構成について簡単に説明する。
図6は、送信回路3及び受信回路4を含んだ電子回路モジュール1の概略的な回路構成図である。送信回路3は、変調回路36及び高周波増幅器37を備えた送信IC32、IC外に付設された送信用フィルタ33、マッチング回路34とから主に構成されている。マッチング回路34は端子35を介してアンテナに接続されている。変調回路36には、送信用ベースバンドIC(図示省略)から送信信号が入力端子31を介して入力される。一方、受信回路4は、アンテナ端子41に接続する高周波フィルタ42、ローノイズアンプ(LNA)46及び復調回路47を備えた受信IC43と、IC外に付設された受信用フィルタ44から主に構成されている。復調回路47から出力される復調信号は出力端子45を介して受信用ベースバンドIC(図示省略)に出力される。
First, the circuit configuration of the electronic circuit module 1 in the present embodiment will be briefly described.
FIG. 6 is a schematic circuit configuration diagram of the electronic circuit module 1 including the transmission circuit 3 and the reception circuit 4. The transmission circuit 3 mainly includes a transmission IC 32 having a modulation circuit 36 and a high frequency amplifier 37, a transmission filter 33 attached outside the IC, and a matching circuit 34. The matching circuit 34 is connected to the antenna via a terminal 35. A transmission signal is input to the modulation circuit 36 via the input terminal 31 from a transmission baseband IC (not shown). On the other hand, the reception circuit 4 is mainly composed of a reception IC 43 including a high frequency filter 42 connected to the antenna terminal 41, a low noise amplifier (LNA) 46, and a demodulation circuit 47, and a reception filter 44 attached outside the IC. Yes. The demodulated signal output from the demodulation circuit 47 is output to a receiving baseband IC (not shown) via the output terminal 45.

図2及び図3は本実施の形態に係る電子回路モジュール1の構成図である。図2(a)は、本実施の形態に係る電子回路モジュール1の回路搭載面がカバーに覆われた状態を示す外観斜視図であり、同図(b)は、電子回路モジュール1のカバーを開放した状態を示す外観斜視図である。図3は電子回路モジュール1のカバーを外した状態での平面図である。以下の説明では、「上」、「下」、「左」、「右」は、図2に示す方向に従うものとする。   2 and 3 are configuration diagrams of the electronic circuit module 1 according to the present embodiment. 2A is an external perspective view showing a state in which the circuit mounting surface of the electronic circuit module 1 according to the present embodiment is covered with a cover, and FIG. 2B shows the cover of the electronic circuit module 1. It is an external appearance perspective view which shows the state open | released. FIG. 3 is a plan view of the electronic circuit module 1 with the cover removed. In the following description, “upper”, “lower”, “left”, and “right” follow the directions shown in FIG.

図2(a)に示すように、電子回路モジュール1は、平面視略矩形形状の絶縁基板2の主面(上面)にアイソレーションが必要な複数の電子回路部品(電子部品及び回路ブロック)が実装されており、薄い箱状の金属性カバー10が絶縁基板2の主面全体を覆っている。金属性カバー10は、平面視略矩形形状に形成されると共に絶縁基板2の主面全域に対応する大きさに形成された天板10aと、絶縁基板2に固定するための複数(4つ)の取付部10bとを備えている。取付部10bは、折り曲げ加工により、天板10aの角部近傍から絶縁基板側に向かって略L字状に折り曲げられており、絶縁基板2の主面に形成された固定パターン12に半田付けされる(後述する図4参照)。これにより、金属性カバー10は、絶縁基板2への固定を介して絶縁基板2の下面に形成されたグランドパターン(後述する)に接続するので、金属性カバー10が覆う複数の回路部品から金属性カバー10外への電磁波及び金属性カバー10外部から内部への電磁波を遮断することができる。   As shown in FIG. 2A, the electronic circuit module 1 includes a plurality of electronic circuit components (electronic components and circuit blocks) that require isolation on the main surface (upper surface) of the insulating substrate 2 having a substantially rectangular shape in plan view. A thin box-shaped metallic cover 10 is mounted so as to cover the entire main surface of the insulating substrate 2. The metallic cover 10 is formed in a substantially rectangular shape in plan view, and has a top plate 10 a formed in a size corresponding to the entire main surface of the insulating substrate 2, and a plurality (four) for fixing to the insulating substrate 2. Mounting portion 10b. The mounting portion 10b is bent into a substantially L shape from the vicinity of the corner of the top plate 10a toward the insulating substrate by bending, and is soldered to the fixed pattern 12 formed on the main surface of the insulating substrate 2. (See FIG. 4 described later). Thereby, the metallic cover 10 is connected to a ground pattern (described later) formed on the lower surface of the insulating substrate 2 through fixing to the insulating substrate 2, so that the metal cover 10 is made of a plurality of circuit components covered by the metallic cover 10. Electromagnetic waves to the outside of the conductive cover 10 and electromagnetic waves from the outside to the inside of the metallic cover 10 can be blocked.

図2(b)及び図3に示すように、絶縁基板2の最上面となる主面2aには上記複数のIC回路3,4及び電子部品33,34,42,44が実装されている。絶縁基板2の主面2aには、送信回路3及び受信回路4が基板2の領域を2分割するように配設されている。また、絶縁基板2の主面2aには、回路構成上必要であるコイル、コンデンサ、抵抗等の各種の電子部品15が設けられている。   As shown in FIGS. 2B and 3, the plurality of IC circuits 3 and 4 and the electronic components 33, 34, 42 and 44 are mounted on the main surface 2 a which is the uppermost surface of the insulating substrate 2. On the main surface 2 a of the insulating substrate 2, the transmission circuit 3 and the reception circuit 4 are disposed so as to divide the region of the substrate 2 into two. The main surface 2a of the insulating substrate 2 is provided with various electronic components 15 such as a coil, a capacitor, and a resistor that are necessary for the circuit configuration.

本実施の形態では、マッチング回路34及び送信回路3のマッチング回路側の一部と、受信用フィルタ44及び受信回路4の受信用フィルタ側の一部との間に、磁気シールド壁として機能する複数のシールド用チップ部品5が配列されている。後述するように、シールド用チップ部品5の端子はホット側に接続されずに、グランドパターンに接続されている。なお、シールド用チップ部品5の配列は図2(b)及び図3に示す配列例に限定されない。対象電子部品間又は回路ブロック間のアイソレーションを図れる配置であれば、配置状態は限定されない。   In the present embodiment, a plurality of functions that function as magnetic shield walls between a part of the matching circuit 34 and the transmission circuit 3 on the matching circuit side and a part of the reception filter 44 and the reception circuit 4 on the reception filter side. The chip components 5 for shielding are arranged. As will be described later, the terminals of the shielding chip component 5 are not connected to the hot side but are connected to the ground pattern. Note that the arrangement of the shielding chip parts 5 is not limited to the arrangement examples shown in FIGS. The arrangement state is not limited as long as the arrangement can achieve isolation between target electronic components or circuit blocks.

図4は、図3のA−A線に沿った断面図である。図4に示すように、本例ではシールド用チップ部品5として、誘電体を挟んで多数の電極が狭い間隔で積層されてなる積層型チップコンデンサを用いている。積層型チップコンデンサは、内部の電極の積層方向が積層型チップコンデンサの配設方向と直交する向きになるように、絶縁基板2の主面に実装されていることが望ましいが、それ以外の配設方向であってもアイソレーション効果を期待できる。また、積層型チップコンデンサは、少なくとも1つの電極がビア14を介してグランドパターン13に接続されている。本実施の形態では、積層型チップコンデンサの両電極が、ビア14を介してグランドパターン13に接続されている。グランドパターン13がグランド電極となる。これにより、積層型チップコンデンサ内部の電位がグランド電位と同電位となるので、送受信回路相互間の信号干渉を防止する効果を高めることができる。   4 is a cross-sectional view taken along line AA in FIG. As shown in FIG. 4, in this example, a multilayer chip capacitor in which a large number of electrodes are laminated at a narrow interval with a dielectric in between is used as the shielding chip component 5. The multilayer chip capacitor is preferably mounted on the main surface of the insulating substrate 2 so that the internal electrode stacking direction is perpendicular to the multilayer chip capacitor disposition direction. Isolation effect can be expected even in the installation direction. In the multilayer chip capacitor, at least one electrode is connected to the ground pattern 13 via the via 14. In the present embodiment, both electrodes of the multilayer chip capacitor are connected to the ground pattern 13 via the via 14. The ground pattern 13 becomes a ground electrode. As a result, the potential inside the multilayer chip capacitor becomes the same as the ground potential, so that the effect of preventing signal interference between the transmitting and receiving circuits can be enhanced.

また絶縁基板2は、マザーボード等と接続するための複数の外部接続端子が形成されており、絶縁基板2の主面2a又は中間導電層2b,2cに形成されたパターン等とビア14を介して電気的に接続可能に構成されている。   The insulating substrate 2 is formed with a plurality of external connection terminals for connecting to a mother board or the like, and via the vias 14 and the patterns formed on the main surface 2a of the insulating substrate 2 or the intermediate conductive layers 2b and 2c. It is configured to be electrically connectable.

また、シールド用チップ部品5の上面部と、当該上面部と対向する金属性カバー10の対向面(天板10aの裏面)との間隔Dは、当該電子回路モジュール1の送信回路3、受信回路4等を伝搬する信号が放射された場合の空気中での1/4波長よりも短いことが好ましい。例えば、対象とする周波数帯域が2010MHz〜2025MHzであれば、間隔Dは37mm以下であれば良いことになる。これにより、電子回路モジュール1の上面側からの信号の漏れ出しを抑制でき、送受信回路相互間又は他の電子部品との干渉をさらに防止することができる。   The distance D between the upper surface portion of the shielding chip component 5 and the facing surface of the metallic cover 10 facing the upper surface portion (the back surface of the top plate 10a) is determined by the transmission circuit 3 and the reception circuit of the electronic circuit module 1. It is preferable that the wavelength is shorter than a quarter wavelength in the air when a signal propagating 4 etc. is emitted. For example, if the target frequency band is 2010 MHz to 2025 MHz, the distance D may be 37 mm or less. Thereby, the leakage of the signal from the upper surface side of the electronic circuit module 1 can be suppressed, and interference between the transmission / reception circuits or other electronic components can be further prevented.

このように、本実施の形態によれば、絶縁基板2上に設けられた送信回路3及び受信回路4間に、グランドパターン13に接続したシールド用チップ部品5を配列して磁気シールド壁を形成したので、磁気シールド用の仕切り板を設けなくても送信回路3と受信回路4との間のアイソレーションを実現することができる。また、仕切り板を設ける必要が無いことから、電子回路モジュール1の小型化の障害を一つ取り除くことができ、小型化が容易になるといった効果も奏することができる。また、シールド用チップ部品5を積層型チップコンデンサで構成した場合には、当該積層型チップコンデンサは、誘電体を挟んだ電極が狭い間隔で多数積層されているので、電磁シールド効果をより向上させる。また、電子回路モジュールの回路部品としても使用されるため、従来のように新たにシールド用材料を用意する必要がないので、シールドに供するコストを抑制することができる。また、回路部品の実装位置やレイアウト等の自由度を改善することもできる。   As described above, according to the present embodiment, the shield chip component 5 connected to the ground pattern 13 is arranged between the transmission circuit 3 and the reception circuit 4 provided on the insulating substrate 2 to form a magnetic shield wall. Therefore, isolation between the transmission circuit 3 and the reception circuit 4 can be realized without providing a partition plate for magnetic shield. In addition, since there is no need to provide a partition plate, one obstacle to miniaturization of the electronic circuit module 1 can be removed, and an effect of facilitating miniaturization can be achieved. Further, when the shielding chip component 5 is constituted by a multilayer chip capacitor, the multilayer chip capacitor has a large number of electrodes sandwiching a dielectric, and the electromagnetic shielding effect is further improved. . Moreover, since it is used also as a circuit component of an electronic circuit module, it is not necessary to prepare a new shielding material as in the prior art, so that the cost for the shield can be suppressed. In addition, the degree of freedom of the circuit component mounting position and layout can be improved.

また、本発明は上記実施の形態に限定されず、種々変更して実施することが可能である。上記実施の形態にいて、添付図面に図示されている大きさや形状などについては、これに限定されず、本発明の効果を発揮する範囲内で適宜変更することが可能である。その他、本発明の目的の範囲を逸脱しない限りにおいて適宜変更して実施することが可能である。   The present invention is not limited to the above-described embodiment, and can be implemented with various modifications. In the above-described embodiment, the size, shape, and the like illustrated in the accompanying drawings are not limited thereto, and can be appropriately changed within a range in which the effect of the present invention is exhibited. In addition, various modifications can be made without departing from the scope of the object of the present invention.

上記実施の形態では、送受信回路間に複数のシールド用チップ部品5を、絶縁基板2の短辺方向に一列に並べた構成としたが、この構成に限定されるものではなく、シールド用チップ部品5を複数列並べて構成してもよい。この場合、図5に示すように、例えば、第1列目の複数のシールド用チップ部品5の間隙を埋めるように、第2列目の複数のシールド用チップ部品51をずらして設けることが好ましい。これにより、送受信回路間のシールド効果を更に高めることができる。また、送信回路3側のマッチング回路34と、受信回路4側の受信フィルタ42との間が最も干渉するので、かかる境界部分だけシールド用チップ部品5の間隔を狭くしたり、複数列にしたりしても良い。   In the above embodiment, a plurality of shielding chip components 5 are arranged in a row in the short side direction of the insulating substrate 2 between the transmission and reception circuits. However, the present invention is not limited to this configuration. 5 may be arranged in a plurality of rows. In this case, as shown in FIG. 5, for example, the plurality of shield chip components 51 in the second row are preferably provided so as to be offset so as to fill the gaps between the plurality of shield chip components 5 in the first row. . Thereby, the shielding effect between transmission-and-reception circuits can further be improved. Further, since the interference between the matching circuit 34 on the transmission circuit 3 side and the reception filter 42 on the reception circuit 4 side is the most, the interval between the shielding chip parts 5 may be narrowed at a boundary portion or may be arranged in a plurality of rows. May be.

また、シールド用チップ部品5は、積層型チップコンデンサに限定されるものではなく、部品内部の電位をグランド電位に保つものであれば、その他のチップコンデンサ又はチップインダクタで構成してもよい。   Further, the shielding chip component 5 is not limited to the multilayer chip capacitor, and may be composed of other chip capacitors or chip inductors as long as the potential inside the component is maintained at the ground potential.

本発明は、小型の送受信機に使用される電子回路モジュールに適用可能である。   The present invention can be applied to an electronic circuit module used in a small transceiver.

本発明の実施の形態に係る電子回路モジュールの主要部を示す模式図The schematic diagram which shows the principal part of the electronic circuit module which concerns on embodiment of this invention (a)本実施の形態に係るカバーに覆われた電子回路モジュールを示す外観斜視図、(b)カバーを開放した電子回路モジュールを示す外観斜視図(A) External perspective view showing an electronic circuit module covered with a cover according to the present embodiment, (b) External perspective view showing an electronic circuit module with the cover opened. 上記実施の形態に係る電子回路モジュールを示す平面図The top view which shows the electronic circuit module which concerns on the said embodiment 図3のA−A線の断面図Sectional view of the AA line of FIG. シールド用チップ部品を複数列並べた状態を示す模式図Schematic diagram showing the state in which multiple rows of shielding chip parts are arranged 本実施の形態に係る電子回路モジュールの回路図Circuit diagram of electronic circuit module according to the present embodiment

符号の説明Explanation of symbols

1 電子回路モジュール
2 絶縁基板
3 送信回路
4 受信回路
10 金属性カバー
13 グランドパターン(グランド電極)
32 送信IC
33 送信用フィルタ
34 マッチング回路
36 変調回路
42 高周波フィルタ
43 受信IC
44 受信用フィルタ
46 ローノイズアンプ(LNA)
47 復調回路
DESCRIPTION OF SYMBOLS 1 Electronic circuit module 2 Insulation board 3 Transmission circuit 4 Reception circuit 10 Metallic cover 13 Ground pattern (ground electrode)
32 Transmitting IC
33 Transmission Filter 34 Matching Circuit 36 Modulation Circuit 42 High Frequency Filter 43 Receiver IC
44 Receiving filter 46 Low noise amplifier (LNA)
47 Demodulator circuit

Claims (4)

絶縁基板と、前記絶縁基板上に搭載された複数の電子部品と、前記絶縁基板に形成されたグランド電極とを備えた電子回路モジュールであって、
前記絶縁基板上に搭載された複数の電子部品のうち少なくともアイソレーションを要する電子部品間又は複数の電子部品で構成される回路ブロック間に、前記グランド電極にそれぞれ接続された複数のシールド用チップ部品を配列したことを特徴とする電子回路モジュール。
An electronic circuit module comprising an insulating substrate, a plurality of electronic components mounted on the insulating substrate, and a ground electrode formed on the insulating substrate,
A plurality of shielding chip components respectively connected to the ground electrode between a plurality of electronic components which are mounted on the insulating substrate, between electronic components requiring isolation, or between circuit blocks composed of a plurality of electronic components. An electronic circuit module characterized by arranging the above.
前記シールド用チップ部品は、誘電体を挟んで電極が積層される積層型チップコンデンサであり、当該積層型チップコンデンサの少なくとも1つの電極が前記グランド電極に接続していることを特徴とする請求項1記載の電子回路モジュール。   The shield chip component is a multilayer chip capacitor in which electrodes are stacked with a dielectric interposed therebetween, and at least one electrode of the multilayer chip capacitor is connected to the ground electrode. The electronic circuit module according to 1. 第1の回路ブロックが高周波信号を送信する送信回路であり、第2の回路ブロックが高周波信号を受信する受信回路であり、少なくとも送信回路のRF部と受信回路のRF部との境界部に前記シールド用チップ部品を配列したことを特徴とする請求項1又は請求項2に記載の電子回路モジュール。   The first circuit block is a transmission circuit that transmits a high-frequency signal, and the second circuit block is a reception circuit that receives a high-frequency signal, and at least at the boundary between the RF unit of the transmission circuit and the RF unit of the reception circuit The electronic circuit module according to claim 1, wherein the shielding chip parts are arranged. 前記絶縁基板上に搭載された電子部品及び前記シールド用チップ部品を覆う金属性カバーと前記シールド用チップ部品との間隔が、前記第1及び第2の回路ブロックを伝搬する信号が放射された場合の空気中での1/4波長よりも短いことを特徴とする請求項3に記載の電子回路モジュール。   When a signal propagating through the first and second circuit blocks is radiated at intervals between the electronic component mounted on the insulating substrate and the metallic cover that covers the shielding chip component and the shielding chip component The electronic circuit module according to claim 3, wherein the electronic circuit module is shorter than a quarter wavelength in the air.
JP2008052899A 2008-03-04 2008-03-04 Electronic circuit module Withdrawn JP2009212263A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011014659A (en) * 2009-06-30 2011-01-20 Murata Mfg Co Ltd Composite electronic component module
CN102281707A (en) * 2010-06-11 2011-12-14 株式会社村田制作所 Circuit module
WO2017179586A1 (en) * 2016-04-15 2017-10-19 株式会社村田製作所 Surface-mounted shield member and circuit module
JP2021140992A (en) * 2020-03-06 2021-09-16 住友電気工業株式会社 Multi-core cable with connector
US11178778B2 (en) 2017-06-29 2021-11-16 Murata Manufacturing Co., Ltd. High frequency module
CN113811995A (en) * 2019-04-29 2021-12-17 高通股份有限公司 Surface mount passive components and dies shorted together

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011014659A (en) * 2009-06-30 2011-01-20 Murata Mfg Co Ltd Composite electronic component module
CN102281707A (en) * 2010-06-11 2011-12-14 株式会社村田制作所 Circuit module
JP2011258886A (en) * 2010-06-11 2011-12-22 Murata Mfg Co Ltd Circuit module
US8897028B2 (en) 2010-06-11 2014-11-25 Murata Manufacturing Co., Ltd. Circuit module
WO2017179586A1 (en) * 2016-04-15 2017-10-19 株式会社村田製作所 Surface-mounted shield member and circuit module
JPWO2017179586A1 (en) * 2016-04-15 2018-10-11 株式会社村田製作所 Surface mount type shield member and circuit module
US11178778B2 (en) 2017-06-29 2021-11-16 Murata Manufacturing Co., Ltd. High frequency module
CN113811995A (en) * 2019-04-29 2021-12-17 高通股份有限公司 Surface mount passive components and dies shorted together
JP2021140992A (en) * 2020-03-06 2021-09-16 住友電気工業株式会社 Multi-core cable with connector
JP7404938B2 (en) 2020-03-06 2023-12-26 住友電気工業株式会社 Multi-core cable with connector

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