JP2009211224A - Memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory system for more shortening a time required since a reset request is received until it is actually shifted to reset processing than a conventional manner. <P>SOLUTION: This memory system is provided with a DRAM 20 having a WC 21: an FS 12 which performs readout/write-in by page unit, and performs deletion by block unit; an MS 11 which performs readout/write-in by track unit, and performs deletion by block unit; an FSIB 12a being the input buffer of the FS 12; an MSIB 11a being the input buffer of the MS; and a controller which performs the storage processing of data. The MSIB 11a is provided with an FSBB 12ac which stores the data written in the WC 21, and the controller saves the data written in the WC 21 to the FSBB 12ac when receiving a reset request from a host device. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory system including a nonvolatile semiconductor memory.

  Non-volatile semiconductor memory, such as NAND flash memory, erases data that is erased once in blocks and then written, or that performs writing / reading in pages. Some units have fixed / write / read units.

  On the other hand, a unit in which a host device such as a personal computer writes / reads data to / from a secondary storage device such as a hard disk is called a sector. The sector is determined independently of the unit of erasing / writing / reading of the nonvolatile semiconductor memory.

  For example, the block size (block size) of the nonvolatile semiconductor memory is 512 kB and the page size (page size) is 4 kB, whereas the sector size (sector size) of the host device is It is determined as 512B.

  As described above, the erase / write / read unit of the nonvolatile semiconductor memory may be larger than the write / read unit of the host device.

  Therefore, when a secondary storage device of a personal computer such as a hard disk is configured using a non-volatile semiconductor memory, data of a small size from the personal computer as a host device is stored in the block size and page size of the non-volatile semiconductor memory. It is necessary to write in conformity.

  Further, in order to rewrite data in the nonvolatile semiconductor memory, the data must be erased. The time required for this erasure is longer than that for writing, and the erasing unit is a block unit larger than the unit of the page to be written, so it is necessary to erase even the part where writing is not required. (For example, refer to Patent Document 1).

JP 2002-366423 A

  The present invention provides a memory system capable of shortening the time required from when a reset request is received until the actual reset processing is started.

  According to one aspect of the present invention, a first storage unit as a cache memory for writing composed of a volatile semiconductor storage element that is read / written to / from a host device in a first unit; A second storage unit including a non-volatile semiconductor storage element that is read / written in units of and is erased in a third unit that is a natural number multiple of 2 or more of the second unit; A third semiconductor memory element is formed of a nonvolatile semiconductor memory element in which reading / writing is performed in a fourth unit that is a natural fraction of two or more of the third unit, and erasing is performed in the third unit. A memory unit and a non-volatile semiconductor memory element that is read / written in the second unit and erased in the third unit, and functions as an input buffer of the second memory unit 1 input buffer A second input that is configured by a nonvolatile semiconductor memory element that is read / written in the fourth unit and erased in the third unit, and functions as an input buffer of the third memory unit A buffer, a first process for writing a plurality of data consisting of the first unit from a host device to the first storage unit, and a plurality of data written to the first storage unit for the first, A second process for kicking out to the second input buffer, and a plurality of data written in the first and second input buffers are kicked out to the second and third storage units, respectively, and stored in the second storage unit. And a controller that executes a third process for expelling a plurality of written data to a second input buffer, wherein the first input buffer is greater than or equal to the first storage unit Memory And having a save buffer for storing data written in the first storage unit, the controller writing to the first storage unit when receiving a reset request from the host device. A memory system is provided that saves the stored data in the save buffer.

  Further, according to one aspect of the present invention, a first storage unit serving as a cache memory for writing composed of a volatile semiconductor storage element that is read / written to / from the host device in a first unit; A second storage unit configured by a nonvolatile semiconductor storage element that is read / written in the second unit and erased in a third unit that is a natural number multiple of 2 or more of the second unit. Read / write is performed in a fourth unit which is a natural fraction of two or more of the third unit, and erase is performed in the third unit. 3 storage units, a fourth storage unit composed of a nonvolatile semiconductor memory element that is read / written in the second unit and erased in the third unit, and the second unit Read / write in units of A first input buffer that is configured by a nonvolatile semiconductor memory element that is erased in the third unit and functions as an input buffer of the second memory unit; and read / write in the fourth unit And a second input buffer functioning as an input buffer of the third storage unit, and reading in the second unit A third input buffer that is configured by a nonvolatile semiconductor memory element that is written and erased in the third unit and functions as an input buffer of the fourth memory unit; A first process for writing a plurality of data in a first unit to the first storage unit, and a plurality of data written to the first storage unit to the first and second input buffers. The second process and the plurality of data written in the first and second input buffers are respectively driven out to the second and third storage units, and the plurality of data written in the second storage unit A third process for expelling data to the second input buffer and a plurality of data written in the second storage unit are expelled to the fourth storage unit in a third unit and written to the fourth storage unit And a controller that executes a fourth process for expelling the plurality of pieces of data to a third input buffer in a third unit, wherein the first input buffer includes the first input buffer A storage buffer having a storage capacity larger than that of the storage unit and storing data written in the first storage unit, and the controller receives the reset request from the host device; Data written to memory part 1 A memory system is provided that saves data in the save buffer.

  ADVANTAGE OF THE INVENTION According to this invention, the memory system which can shorten the time required after receiving a reset request | requirement until it actually shifts to a reset process can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

First, terms used in this specification are defined.
Physical page: A unit that can be written / read collectively in the NAND memory chip. The physical page size is 4 kB, for example. However, redundant bits such as error correction codes added in the SSD to main data (user data, etc.) are not included. Normally, 4 kB + redundant bit (for example, several tens of bytes) is a unit to be simultaneously written in the memory cell, but for convenience of explanation, it is defined as described above.
Logical page: A write / read unit set in the SSD, and is associated with one or more physical pages. The logical page size is, for example, 4 kB in the 8-bit normal mode and 32 kB in the 32-bit double speed mode. However, redundant bits are not included.
Physical block: the smallest unit that can be independently erased inside the NAND memory chip, and is composed of a plurality of physical pages. The physical block size is, for example, 512 kB. However, redundant bits such as an error correction code added to the main data in the SSD are not included. Normally, 512 kB + redundant bit (for example, several tens of kB) is a unit to be erased at the same time, but for convenience of explanation, it is defined as described above.
Logical block: An erasing unit set in the SSD, and is associated with one or more physical blocks. The logical block size is, for example, 512 kB in the 8-bit normal mode and 4 MB in the 32-bit double speed mode. However, redundant bits are not included.
Sector: The minimum access unit from the host. The sector size is, for example, 512B.
Cluster: A management unit that manages “small data” in the SSD. The cluster size is equal to or larger than the sector size, and is determined so that a natural number multiple of 2 or more of the cluster size becomes the logical page size.
Track: A management unit that manages “big data” in the SSD. It is determined that a natural number multiple of 2 or more of the cluster size is a track size, and a natural number multiple of 2 or more of the track size is a logical block size.
Free block (FB): A logical block on a NAND flash memory to which no use is assigned. Use it after erasing it when assigning usages.
Bad block (BB): A physical block on a NAND flash memory that cannot be used as a storage area due to many errors. For example, a physical block for which the erase operation has not ended normally is registered as a bad block BB.
Write efficiency: A statistical value of the erase amount of a logical block with respect to the amount of data written from a host within a predetermined period. The smaller the size, the smaller the consumption of the NAND flash memory.
Valid cluster: A cluster that holds the latest data.
Invalid cluster: A cluster that holds data that is not up-to-date.
Valid track: A track that holds the latest data.
Invalid track: A track that holds data that is not up-to-date.
Compaction: Extracting only valid clusters and valid tracks from the logical block within the management target and rewriting them into a new logical block.

[First Embodiment]
FIG. 1 is a block diagram illustrating a configuration example of an SSD (Solid State Drive) 100. The SSD 100 is connected to a host device 1 such as a personal computer or a CPU core via a memory connection interface such as an ATA interface (ATA I / F) 2 and functions as an external memory of the host device 1. Further, the SSD 100 can transmit / receive data to / from the debugging / manufacturing inspection device 200 via the communication interface 3 such as an RS232C interface (RS232C I / F). The SSD 100 includes a NAND flash memory (hereinafter abbreviated as a NAND memory) 10 as a nonvolatile semiconductor memory, a drive control circuit 4 as a controller, a DRAM 20 as a volatile semiconductor memory, a power supply circuit 5, and a status display. LED 6, a temperature sensor 7 for detecting the temperature inside the drive, and a fuse 8.

  The power supply circuit 5 generates a plurality of different internal DC power supply voltages from an external DC power supply supplied from the power supply circuit on the host device 1 side, and supplies these internal DC power supply voltages to each circuit in the SSD 100. The power supply circuit 5 detects the rise or fall of the external power supply, generates a power-on reset signal, and supplies it to the drive control circuit 4. The fuse 8 is provided between the power supply circuit on the host device 1 side and the power supply circuit 5 inside the SSD 100. When an overcurrent is supplied from the external power supply circuit, the fuse 8 is blown to prevent malfunction of the internal circuit.

  In this case, the NAND memory 10 includes four parallel operation elements 10a to 10d that perform four parallel operations, and one parallel operation element includes two NAND memory packages. Each NAND memory package includes a plurality of stacked NAND memory chips (for example, 1 chip = 2 GB). In the case of FIG. 1, each NAND memory package is constituted by four stacked NAND memory chips, and the NAND memory 10 has a capacity of 64 GB. When each NAND memory package is constituted by eight stacked NAND memory chips, the NAND memory 10 has a capacity of 128 GB.

  The DRAM 20 functions as a data transfer cache and work area memory between the host device 1 and the NAND memory 10. Further, instead of the DRAM 20, FeRAM may be used. The drive control circuit 4 controls data transfer between the host device 1 and the NAND memory 10 via the DRAM 20 and controls each component in the SSD 100. In addition, the drive control circuit 4 supplies a status display signal to the status display LED 6 and receives a power-on reset signal from the power supply circuit 5 to send a reset signal and a clock signal to each part in the own circuit and the SSD 100. It also has a function to supply.

  Each NAND memory chip is configured by arranging a plurality of physical blocks, which are data erasing units. FIG. 2A is a circuit diagram illustrating a configuration example of one physical block included in the NAND memory chip. Each physical block includes (p + 1) NAND strings arranged in order along the X direction (p is an integer of 0 or more). The selection transistors ST1 included in each of the (p + 1) NAND strings have drains connected to the bit lines BL0 to BLp and gates commonly connected to the selection gate line SGD. In addition, the selection transistor ST2 has a source commonly connected to the source line SL and a gate commonly connected to the selection gate line SGS.

  Each memory cell transistor MT is composed of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a stacked gate structure formed on a semiconductor substrate. The stacked gate structure includes a charge storage layer (floating gate electrode) formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a control gate electrode formed on the charge storage layer with an inter-gate insulating film interposed therebetween. It is out. In the memory cell transistor MT, the threshold voltage changes according to the number of electrons stored in the floating gate electrode, and data is stored according to the difference in threshold voltage. The memory cell transistor MT may be configured to store 1 bit, or may be configured to store multiple values (data of 2 bits or more).

  In addition, the memory cell transistor MT is not limited to a structure having a floating gate electrode, but a threshold is obtained by trapping electrons at the interface of a nitride film as a charge storage layer such as a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type. A structure capable of adjusting the value may be used. Similarly, the memory cell transistor MT having the MONOS structure may be configured to store 1 bit, or may be configured to store multiple values (data of 2 bits or more).

  In each NAND string, (q + 1) memory cell transistors MT are arranged such that their current paths are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. That is, the plurality of memory cell transistors MT are connected in series in the Y direction so that adjacent ones share a diffusion region (source region or drain region).

  The control gate electrodes are connected to the word lines WL0 to WLq in order from the memory cell transistor MT located closest to the drain side. Therefore, the drain of the memory cell transistor MT connected to the word line WL0 is connected to the source of the selection transistor ST1, and the source of the memory cell transistor MT connected to the word line WLq is connected to the drain of the selection transistor ST2.

  The word lines WL0 to WLq connect the control gate electrodes of the memory cell transistors MT in common between the NAND strings in the physical block. That is, the control gate electrodes of the memory cell transistors MT in the same row in the block are connected to the same word line WL. The (p + 1) memory cell transistors MT connected to the same word line WL are handled as one page (physical page), and data writing and data reading are performed for each physical page.

  The bit lines BL0 to BLp connect the drains of the selection transistors ST1 in common between the blocks. That is, NAND strings in the same column in a plurality of blocks are connected to the same bit line BL.

  FIG. 2B is a schematic diagram showing a threshold distribution in a quaternary data storage system in which, for example, 2 bits are stored in one memory cell transistor MT. In the quaternary data storage system, any one of the quaternary data “xy” defined by the upper page data “x” and the lower page data “y” can be held in the memory cell transistor MT.

  For example, data “11”, “01”, “00”, and “10” are assigned to the quaternary data “xy” in order of the threshold voltage of the memory cell transistor MT. Data “11” is an erased state in which the threshold voltage of the memory cell transistor MT is negative.

  In the lower page write operation, data “10” is written to the memory cell transistor MT of data “11” (erased state) selectively by writing lower bit data “y”. The threshold distribution of the data “10” before the upper page write is located approximately between the threshold distributions of the data “01” and the data “00” after the upper page write. It may be broader than the threshold distribution. In the upper page write operation, upper bit data “x” is selectively written into the memory cell of data “11” and the memory cell of data “10”, respectively, and data “01” and data “00” is written.

  FIG. 3 is a block diagram illustrating an example of a hardware internal configuration of the drive control circuit 4. The drive control circuit 4 includes a data access bus 101, a first circuit control bus 102, and a second circuit control bus 103. A processor 104 that controls the entire drive control circuit 4 is connected to the first circuit control bus 102. A boot ROM 105 storing a boot program for booting each management program (FW: firmware) stored in the NAND memory 10 is connected to the first circuit control bus 102 via a ROM controller 106. . The first circuit control bus 102 is connected to a clock controller 107 that receives a power-on reset signal from the power supply circuit 5 shown in FIG. 1 and supplies a reset signal and a clock signal to each unit.

The second circuit control bus 103 is connected to the first circuit control bus 102. The second circuit control bus 103 has an I ² C circuit 108 for receiving data from the temperature sensor 7 shown in FIG. 1, and a parallel IO (PIO) circuit for supplying a status display signal to the status display LED 6 109, a serial IO (SIO) circuit 110 for controlling the RS232C I / F3 is connected.

  An ATA interface controller (ATA controller) 111, a first ECC (Error Checking and Correction) circuit 112, a NAND controller 113, and a DRAM controller 114 are provided on both the data access bus 101 and the first circuit control bus 102. It is connected. The ATA controller 111 transmits and receives data to and from the host device 1 via the ATA interface 2. An SRAM 115 used as a data work area work area and a firmware development area is connected to the data access bus 101 via an SRAM controller 116. The firmware stored in the NAND memory 10 is transferred to the SRAM 115 by a boot program stored in the boot ROM 105 at startup.

  The NAND controller 113 includes a NAND I / F 117 that performs interface processing with the NAND memory 10, a second ECC circuit 118, and a DMA transfer control DMA controller 119 that performs access control between the NAND memory 10 and the DRAM 20. The second ECC circuit 118 encodes the second correction code, and encodes and decodes the first error correction code. The first ECC circuit 112 decodes the second error correction code. The first error correction code and the second error correction code are, for example, a Hamming code, a BCH (Bose Chaudhuri Hocqenghem) code, an RS (Reed Solomon) code, an LDPC (Low Density Parity Check) code, or the like. It is assumed that the error correction code has a higher correction capability than the first error correction code.

As shown in FIGS. 1 and 3, in the NAND memory 10, four parallel operation elements 10a to 10d are connected in parallel to the NAND controller 112 in the drive control circuit 4 via four channels (4ch) each having 8 bits. It is connected. Depending on the combination of whether the four parallel operation elements 10a to 10d are operated independently or in parallel, or whether the double speed mode (Multi Page Program / Multi Page Read / Multi Block Erase) of the NAND memory chip is used, The following three access modes are provided.
(1) 8-bit normal mode In this mode, only one channel is operated and data is transferred in 8-bit units. Writing / reading is performed with a physical page size (4 kB). Also, erasure is performed with a physical block size (512 kB). One logical block is associated with one physical block, and the logical block size is 512 kB.
(2) 32-bit normal mode This mode operates in parallel with 4 channels and transfers data in units of 32 bits. Writing / reading is performed with physical page size × 4 (16 kB). Further, erasure is performed with physical block size × 4 (2 MB). One logical block is associated with four physical blocks, and the logical block size is 2 MB.
(3) 32-bit double speed mode In this mode, the 4ch parallel operation is performed, and further, writing / reading is performed using the double speed mode of the NAND memory chip. Writing / reading is performed with physical page size × 4 × 2 (32 kB). Further, erasure is performed with physical block size × 4 × 2 (4 MB). One logical block is associated with eight physical blocks, and the logical block size is 4 MB.

In the 32-bit normal mode or the 32-bit double speed mode operating in parallel with 4 channels, 4 or 8 physical blocks operating in parallel serve as an erasing unit as the NAND memory 10, and 4 or 8 physical pages operating in parallel are written as the NAND memory 10. Unit and readout unit. In the following operations, the 32-bit double speed mode is basically used, and for example, 1 logical block = 4 MB = 2 ⁱ track = 2 ^j page = 2 ^k cluster = 2 ^l sector (i, j, k, l Is a natural number and a relationship of i <j <k <l is established).

  A logical block accessed in the 32-bit double speed mode is in units of 4 MB, and 8 (2 × 4 ch) physical blocks (1 physical block = 512 KB) are associated with each other. When a bad block BB managed in units of physical blocks is generated, the bad block BB becomes unusable. In such a case, a combination of eight physical blocks associated with the logical block becomes a bad block BB. It is changed not to include.

  FIG. 4 is a block diagram illustrating a functional configuration example of firmware realized by the processor 104. The functions of the firmware realized by the processor 104 are roughly classified into a data management unit 120, an ATA command processing unit 121, a security management unit 122, a boot loader 123, an initialization management unit 124, and a debug support unit 125.

  The data management unit 120 controls data transfer between the NAND memory 10 and the DRAM 20 and various functions related to the NAND memory 10 via the NAND controller 112 and the first ECC circuit 114. The ATA command processing unit 121 performs data transfer processing between the DRAM 20 and the host device 1 in cooperation with the data management unit 120 via the ATA controller 110 and the DRAM controller 113. The security management unit 122 manages various types of security information in cooperation with the data management unit 120 and the ATA command processing unit 121.

  The boot loader 123 loads each management program (firmware) from the NAND memory 10 to the SRAM 120 when the power is turned on. The initialization manager 124 initializes each controller / circuit in the drive control circuit 4. The debug support unit 125 processes the debug data supplied from the outside via the RS232C interface. The data management unit 120, the ATA command processing unit 121, and the security management unit 122 are mainly functional units realized by the processor 104 executing each management program stored in the SRAM 114.

  In the present embodiment, functions realized by the data management unit 120 will be mainly described. The data management unit 120 provides functions requested by the ATA command processing unit 121 to the NAND memory 10 and the DRAM 20 as storage devices (responses to various commands such as a write request, a cache flush request, and a read request from the host device). ), Management of the correspondence between the address area and the NAND memory 10, protection of management information, provision of a high-speed and efficient data read / write function using the DRAM 10 and the NAND memory 10, and reliability of the NAND memory 10 Secure it.

  FIG. 5 shows functional blocks formed in the NAND memory 10 and the DRAM 20. A write cache (WC) 21 and a read cache (RC) 22 configured on the DRAM 20 are interposed between the host 1 and the NAND memory 10. The WC 21 temporarily stores write data from the host device 1, and the RC 22 temporarily stores read data from the NAND memory 10. In order to reduce the amount of erasure to the NAND memory 10 at the time of writing, the logical block in the NAND memory 10 is processed by the data management unit 120 by the preceding storage area (FS: Front Storage) 12 and the intermediate storage area (IS: Intermediate Storage). 13 and main storage area (MS: Main Storage) 11 are assigned to each management area. The FS 12 manages data from the WC 21 in cluster units, which are “small units”, and stores small data for a short period of time. The IS 13 manages data overflowing from the FS 12 in cluster units, which are “small units”, and stores small data for a long period of time. The MS 11 stores data from the WC 21, FS 12, and IS 13 for a long period in units of tracks that are “large units”. For example, the storage capacity has a relationship of MS> IS, FS> WC.

  If a small management unit is applied to all the storage areas of the NAND memory 10, the size of a management table to be described later will be enlarged and will not fit in the DRAM 20. Therefore, management with a small management unit is not limited to recently written data and NAND. Each storage of the NAND memory 10 is configured so as to have only small data with low writing efficiency to the memory 10.

  FIG. 6 shows a more detailed functional block diagram related to the writing process (WR process) from the WC 21 to the NAND memory 10. An FS input buffer (FSIB) 12a for buffering data from the WC 21 is provided at the front stage of the FS 12. Further, an MS input buffer (MSIB) 11a for buffering data from WC21, FS12, or IS13 is provided in the preceding stage of MS11. The MS 11 is provided with a track pre-stage storage area (TFS) 11b. The TFS 11b is a buffer having a FIFO (First in First Out) structure interposed between the MSIB 11a and the MS 11, and the data recorded in the TFS 11b is data having a higher update frequency than the data directly written in the MS 11 from the MSIB 11a. . Any of the logical blocks in the NAND memory 10 is assigned to the MS 11, MSIB 11 a, TFS 11 b, FS 12, FSIB 12 a, and IS 13.

Next, specific functional configurations of the components shown in FIGS. 5 and 6 will be described in detail. When reading or writing to the SSD 100, the host device 1 inputs an LBA (Logical Block Addressing) as a logical address via the ATA interface. As shown in FIG. 7, LBA is a logical address in which a serial number from 0 is assigned to a sector (size: 512B). In the present embodiment, as a management unit of each component WC21, RC22, FS12, IS13, and MS11 in FIG. 5, a logical cluster address composed of a bit string from the lower (1-k + 1) th bit of the LBA And a logical track address composed of an upper bit string from the lower (l−i + 1) bits of the LBA. One cluster = 2 ^(1-k) sectors and one track = 2 ^(ki) clusters.

Read cache (RC) 22
The RC 22 will be described. The RC 22 is an area for temporarily storing Read data from the NAND memory 10 (FS12, IS13, MS11) in response to a Read request from the ATA command processing unit 121. In this embodiment, the RC 22 is managed by, for example, an m-line, n-way (m is a natural number of 2 ⁽ ki ⁾ or more, n is a natural number of 2 or more) set associative method, and one cluster per entry Can hold minute data. The line is determined by the LSB (ki) bits of the logical cluster address. Note that the RC 22 may be managed by a full associative method or may be managed by a simple FIFO method.

-Write cache (WC) 21
The WC 21 will be described. The WC 21 is an area for temporarily storing write data from the host device 1 in response to a write request from the ATA command processing unit 121. m-line, n-way (m is a natural number of 2 ^(ki) or more, n is a natural number of 2 or more), and is managed by a set associative method, and one entry can hold data for one cluster. The line is determined by the LSB (ki) bits of the logical cluster address. For example, a writable way is searched in the order of way1 to wayn. Also, the tracks registered in the WC 21 are managed by LRU (Least Recently Used) by the FIFO structure of the WC track management table 24 described later so that the order of the oldest update is known. Note that the WC 21 may be managed by a full associative method. WC21 may differ from RC22 in the number of lines and the number of ways.

Data written by the Write request is temporarily stored on the WC 21. The method for determining data to be expelled from the WC 21 to the NAND memory 10 follows the following rules.
(I) When the writable way of the line determined by the tag is the last (in the present embodiment, nth) free way, that is, when the last free way is used, Of the registered tracks, the oldest updated track is checked out based on the LRU.
(Ii) When the number of different tracks registered in the WC 21 exceeds a predetermined number, in the LRU order, the eviction of tracks whose number of clusters in the WC belonging to the track is less than the predetermined number is determined.

  The truck to be driven is determined according to the above policy. At that time, all data included in the same track is evicted, and if the amount of data evicted exceeds 50% of the track size, for example, it is evicted to MS11, and if not, it is evicted to FS12.

Further, when track eviction occurs under the condition (i) and when eviction to MS11, the tracks in WC21 until the number of eviction tracks is 2 ⁱ (originally 2 ^{i + 1} when 2 ⁱ or more). Of these, tracks that satisfy the condition that the amount of data to be evicted exceeds 50% of the track size are selected by the policy (i) and added to the evicting candidates. In other words, if there are less than 2 ⁱ tracks to be evicted, select tracks with 2 ^(k−i−1) or more valid clusters until there are 2 ⁱ tracks from the oldest one in the WC. Add to eviction candidates.

Also, when track flush is performed under the conditions in, the data is flushed to the FS 12, the data amount of expelled LRU order above of tracks in WC21 until the number of clusters expelled is 2 ^k pieces of track size (i) A track that satisfies the condition that it is less than 50% is searched, and the cluster is added to the candidate for eviction. In other words, the tracks in the WC are traced in order from the oldest, and the clusters are extracted from the track having less than 2 ^(ki-1) valid clusters, and the number of valid clusters is 2 ^(ki-1). When the number is reached, the clusters are expelled to the FSIB 12a in units of logical blocks. However, if 2 ^(k−i−1) pieces are not found, the FSIB 12a is evicted in units of logical pages. Note that the threshold value of the number of effective clusters for determining whether the eviction to the FS 12 is in units of logical blocks or units of logical pages is not limited to a value of ^{one (1)} logical block of 2 ⁽ ki ^-1) . The value may be slightly less than one logical block.

  Also, in the Cache Flush request from the ATA command processing unit 121, all the contents of the WC 21 are the same as above (if the amount of data to be evicted exceeds 50% of the track size, go to the MS 11 and if not, go to the FS 12). Then, it is driven out to FS12 or MS11.

-Previous storage area (FS) 12
Next, the FS 12 will be described. The FS 12 is a FIFO that manages data in cluster units. The FS 12 is a buffer for assuming that the data passing through the FS 12 is updated more frequently than the IS 13 in the subsequent stage. In other words, in the FIFO structure of the FS 12, the valid cluster (latest cluster) passing through the FIFO is invalidated when rewriting to the same address from the host is performed, so the cluster passing through the FS 12 It can be considered that the update frequency is higher than that of the cluster evicted from IS13 or MS11.

  The provision of the FS 12 reduces the possibility that frequently updated data will be mixed in the compaction process in the subsequent IS13. When the number of valid clusters held by the logical block itself holding the old cluster becomes 0 due to invalidation, the logical block is released and assigned to the free block FB. If the logical block is invalidated, a new free block FB is acquired and assigned to the FS 12.

  When movement of cluster data from the WC 21 to the FS 12 occurs, the cluster is written into the logical block assigned to the FSIB 12a. When there are blocks in which all pages have been written in the FSIB 12a, these blocks are moved from the FSIB 12a to the FS 12 by the CIB processing described later. During the move from the FSIB 12 a to the FS 12, if the number of blocks of the FS 12 exceeds a predetermined upper limit value permitted as the FS 12, the oldest block is evicted from the FS 12 to the IS 13 or the MS 11. For example, a track whose effective cluster ratio in the track is 50% or more is written to the MS 11 (TFS 11b), and the block in which the effective cluster remains is moved to the IS 13.

  There are two types of data movement between components in the NAND memory 10: Move and Copy. Move is a method that does not rewrite actual data, only by changing pointers in a management table, which will be described later. Copy is a method of actually rewriting data stored in one component to the other component in page units, track units, or block units.

-Middle storage area (IS) 13
Next, IS13 will be described. In the IS 13, data management is performed in cluster units as in the FS 13. As described above, the data stored in the IS 13 can be regarded as data with a low update frequency. When a logical block moves (Move) from the FS 12 to the IS 13, that is, an eviction from the FS 12 occurs, the eviction target logical block that was previously managed by the FS 12 becomes a management target block of the IS 13 by changing the pointer. When the number of blocks of IS13 exceeds a predetermined upper limit allowed as IS13 due to the movement of the logical block from FS12 to IS13, that is, when the number of writable free blocks FB in IS falls below a threshold value, from IS13 Data expulsion and compaction processing to the MS 11 is executed, and the number of blocks of the IS 13 is returned to a specified value.

In IS13, the following eviction process and compaction process are executed using the number of valid clusters in the track.
Number of effective clusters in the track × effective cluster coefficient (the number is weighted depending on whether or not the track exists in the logical block where the invalid track exists in the MS 11, and the number is larger than the case where the track does not exist ) Sort in order, collect 2 ^{i + 1} tracks (2 logical blocks) having a large product value, make them a natural number multiple of the logical block size, and drive them to the MSIB 11a.
· The total number valid clusters smallest number two logical blocks is, for example, if 2 ^k (for one logical block) or a predetermined set value, and repeats the above steps (the two in IS This is done until a free block FB can be created from the logical block).
Valid clusters 2 ^k pieces collected from the cluster logical blocks with a smallest number of sequentially, and compaction is performed in the IS 13.
Although the two logical blocks having the smallest number of valid clusters are selected here, this number is not limited to two and may be two or more. The predetermined set value may be equal to or less than the number of clusters that can be accommodated in the number of logical blocks one less than the number of logical block to be selected.

Main storage area (MS) 11
Next, the MS 11 will be described. The MS 11 manages data in units of tracks. The data stored in the MS 11 can be regarded as having a low update frequency. When track data is copied or moved from WC21, FS12, or IS13 to MS11, the track is written to a logical block allocated to MSIS11a. On the other hand, when only a part of the data (cluster) in the track is written from the WC or the like, the track data in the existing MS and the new data are merged to create new track data and then stored in the MSIB 11a. A passive merge described later is performed. When invalid tracks are accumulated in the MS 11 and the number of logical blocks allocated to the MS 11 exceeds the upper limit of the number of blocks allowed for the MS 11, a compaction process is performed and an invalid free block FB is generated. make.

For the compaction processing of the MS 11, for example, the following method focusing on only the number of valid tracks in the logical block is performed.
Select in order from logical blocks with few valid tracks until invalid free blocks FB can be created by combining invalid tracks.
Compaction is performed while performing passive merging to integrate tracks contained in the selected logical block with data in the WC21, FS12, and IS13.
-2 ⁱ track integrated logical block is output to TFS 11b (2 ⁱ track MS compaction), 2 ⁱ track less than 2 ⁱ track is output to MSIB 11a (less than 2 ⁱ track compaction), more Create an invalid free block FB.

  The TFS 11b is a FIFO that manages data in units of tracks. The TFS 11b is a buffer for assuming that the data passing through the TFS 11b has a higher update frequency than the MS 11 in the subsequent stage. That is, in the FIFO structure of the TFS 11b, the valid track (latest track) passing through the FIFO is invalidated when rewriting to the same address from the host is performed, so that the track passing through the TFS 11b It can be considered that the update frequency is higher than that of the track evicted from MS11 to MS11.

  FIG. 8 shows a management table for the data management unit 120 to control and manage the components shown in FIGS. As described above, the data management unit 120 has a function of bridging the ATA command processing unit 121 and the NAND memory 10, and stores the data stored in the DRAM 20 in the DRAM layer management unit 120 a that manages data stored in the DRAM 20. The logical NAND layer management unit 120b that manages the data, and the physical NAND layer management unit 120c that manages the NAND memory 10 as a physical storage device. The RC cluster management table 23, the WC track management table 24, and the WC cluster management table 25 are controlled by the DRAM layer management unit 120a. The track management table 30, the FS / IS management table 40, the MS logical block management table 35, the FS / IS logical block management table 42, and the FS / IS intra-cluster management table 44 are managed by the logical NAND layer management unit 120b. The logical-physical conversion table 50 is managed by the physical NAND layer management unit 120c.

  The RC 22 is managed by an RC cluster management table 23 that is a reverse lookup table. In the reverse lookup table, the logical address stored at the storage device position can be searched. The WC 21 is managed by a WC cluster management table 25 that is a reverse lookup table and a WC track management table 24 that is a forward lookup table. In the forward lookup table, the storage device position where the data corresponding to the logical address exists can be searched from the logical address.

  The FS12 (FSIB12a), IS13, and MS11 (TFS11b, MSIB11a) in the NAND memory 10 are a track management table 30, an FS / IS management table 40, an MS logical block management table 35, an FS / IS logical block management table 42, and an FS / IS. The logical address is managed by the intra-IS cluster management table 44. The logical address and the physical address of the FS 12 (FSIB 12a), IS 13 and MS 11 (TFS 11b, MSIB 11a) in the NAND memory 10 are converted by the logical / physical conversion table 50. Each of these management tables is stored in an area on the NAND memory 10, and is read from the NAND memory 10 onto the DRAM 20 and used when the SSD 100 is initialized.

RC cluster management table 23 (reverse lookup)
First, the RC cluster management table 23 will be described with reference to FIG. As described above, the RC 22 is managed by an n-way set associative method that is indexed by the logical cluster address LSB (ki) bits. The RC cluster management table 23 is a table for managing the tag of each entry of RC (cluster size × m-line × n-way) 22, and each tag includes a multi-bit status flag 23 a and a logical track address. 23b. In the status flag 23a, in addition to the Valid bit indicating whether or not the entry may be used (valid / invalid), a bit indicating whether or not the entry is waiting to be read from the NAND memory 10, A bit indicating whether or not to wait for reading to the ATA command processing unit 121 is included. The RC cluster management table 23 functions as a reverse lookup table for retrieving a logical track address that matches the LBA from the tag storage position on the DRAM 20.

WC cluster management table 25 (reverse lookup)
Next, the WC cluster management table 25 will be described with reference to FIG. As described above, the WC 21 is managed by the n-way set associative method that is indexed by the logical cluster address LSB (ki) bits. The WC cluster management table 25 is a table for managing the tag of each entry of the WC (cluster size × m-line × n-way) 21. Each tag includes a multi-bit status flag 25a and a sector position bit. It is composed of a map 25b and a logical track address 25c.

In the status flag 25a, in addition to the Valid bit indicating whether or not the entry may be used (valid / invalid), a bit indicating whether or not the entry is waiting to be evicted to the NAND memory 10, A bit indicating whether or not to wait for writing from the ATA command processing unit is included. The sector position bit map 25b shows, in 2 ^(1-k) bits, which of 2 ^(1-k) sectors included in one cluster holds valid data. With this sector position bitmap 25b, the same sector unit management as the LBA can be performed in the WC21. The WC cluster management table 25 functions as a reverse lookup table for retrieving a logical track address that matches the LBA from the tag storage position on the DRAM 20.

WC track management table 24 (forward lookup)
Next, the WC track management table 24 will be described with reference to FIG. The WC track management table 24 manages information in which the clusters stored on the WC 21 are grouped in units of tracks. The order registered in the WC 21 between tracks by a linked list structure having a FIFO function ( LRU). Note that the LRU may be expressed in the order last updated by the WC 21. Each list entry includes a logical track address 24a, the number of valid clusters 24b in the WC 21 included in the logical track address, a way-line bitmap 24c, and a next pointer 24d indicating a pointer to the next entry. The WC track management table 24 functions as a forward lookup table because necessary information is obtained from the logical track address 24a.

The way-line bitmap 24c is map information indicating which entry in the m × n entry in the WC 21 the valid cluster included in the logical track address in the WC 21 is stored. In some entries, the Valid bit is “1”. The way-line bitmap 24c is composed of, for example, (1 bit (Valid) + log ₂ n bits (n-way)) × m bits (m-line). The WC track management table 24 has a linked list structure, and only information relating to logical track addresses existing in the WC 21 is entered.

・ Track management table 30 (forward lookup)
Next, the track management table 30 will be described with reference to FIG. The track management table 30 is a table for managing logical data positions on the MS 11 in units of logical track addresses. When data is held in the FS 12 or the IS 13 in units of clusters, basic information about them and In addition, a pointer to detailed information is also held. It is configured in an array format with the logical track address 30a as an index. Each entry using the logical track address 30a as an index includes information such as a cluster bitmap 30b, a logical block ID 30c + a track position 30d in a logical block, a cluster table pointer 30e, an FS cluster number 30f, and an IS cluster number 30g. The track management table 30 functions as a forward lookup table because it obtains necessary information such as a logical block ID (corresponding to a storage device position) in which a logical track corresponding to the logical track address is stored using a logical track address as an index. To do.

The cluster bitmap 30b is a bitmap in which 2 ^(ki) clusters belonging to one logical track address range are divided into, for example, 8 in ascending order of the cluster address. Each of the 8 bits is represented by 2 ^{(ki-). 3)} Indicates whether a cluster corresponding to one cluster address exists in the MS 11, FS 12 or IS 13. When the bit is “0”, it indicates that the cluster to be searched is surely present in the MS 11, and when the bit is “1”, the cluster may exist in the FS 12 or IS 13. Show.

The logical block ID 30c is information for identifying a logical block ID in which a logical track corresponding to the logical track address is stored. The intra-logical block track position 30d indicates the storage position of the track corresponding to the logical track address (30a) in the logical block specified by the logical block ID 30c. Since one logical block is composed of a maximum of 2 ⁱ effective tracks, the track position 30d in the logical block identifies 2 ⁱ track positions with i bits.

  The cluster table pointer 30e is a pointer to the top entry of each list of the FS / IS management table 40 having a linked list structure. If the search of the cluster bitmap 30b indicates that there is a possibility that the cluster exists in the FS 12 / IS 13, the search of the FS / IS management table 40 is executed using the cluster table pointer 30e. The number of FS clusters 30f indicates the number of valid clusters existing in the FS 12. The IS cluster number 30 g indicates the number of effective clusters existing in the IS 13.

FS / IS management table 40 (forward lookup)
Next, the FS / IS management table 40 will be described with reference to FIG. The FS / IS management table 40 is a table for managing the location of data held in the FS 12 (including the FSIB 12a) or the IS 13 in units of logical clusters. As shown in FIG. 13, it is configured in an independent linked list format for each logical track address, and the pointer to the head entry of each list is held in the field of the cluster table pointer 30e of the track management table 30 as described above. Has been. FIG. 13 shows a linked list for two logical track addresses. Each entry includes a logical cluster address 40a, a logical block ID 40b, a cluster position 40c in a logical block, an FS / IS block ID 40d, and a next pointer 40e. The FS / IS management table 40 includes necessary information from the logical cluster address 40a to the logical block ID 40b in which the logical cluster corresponding to the logical cluster address is stored and the intra-logical block cluster position 40c (corresponding to the storage device position). Therefore, it functions as a forward lookup table.

The logical block ID 40b is information for identifying the logical block ID in which the logical cluster corresponding to the logical cluster address 40a is stored. The intra-logical block cluster position 40c indicates the storage position of the cluster corresponding to the logical cluster address 40a in the logical block specified by the logical block ID 40b. Since one logical block is composed of a maximum of 2 ^k effective clusters, the intra-logical block cluster position 40c identifies 2 ^k positions with k bits. In the FS / IS block ID 40d, an FS / IS block ID that is an index of an FS / IS logical block management table 42 described later is registered. The FS / IS block ID is information for identifying a logical block belonging to FS12 or IS13, and an FS / IS block ID 40d in the FS / IS management table 40 is an FS / IS logical block management table 42 described later. Registered for a link with. The next pointer 40e indicates a pointer to the next entry in the same list linked for each logical track address.

MS logical block management table 35 (reverse lookup)
Next, the MS logical block management table 35 will be described with reference to FIG. The MS logical block management table 35 is a table for centrally managing information on logical blocks used in the MS 11 (which logical track is stored, whether additional recording is possible, etc.). In the MS logical block management table 35, information on logical blocks belonging to FS12 (including FSIB12) and IS13 is also registered. The MS logical block management table 35 is configured in an array format using the logical block ID 35a as an index. In the case of the NAND memory 10 having 128 GB of entries, the MS logical block management table 35 can have up to 32K entries. Each entry includes a track management pointer 35b for 2 ⁱ tracks, a valid track number 35c, a writable head track 35d, and a Valid flag 35e. The MS logical block management table 35 functions as a reverse lookup table because necessary information such as a logical track address stored in the logical block is obtained from the logical block ID 35a corresponding to the storage device position.

The track management pointer 35b holds a logical track address corresponding to every 2 ⁱ track positions in the logical block specified by the logical block ID 35a. Using this logical track address, the track management table 30 using the logical track address as an index can be searched. The number of valid tracks 35c indicates the number of valid tracks (up to 2 ⁱ ) among the tracks stored in the logical block specified by the logical block ID 35a. The writable head track position 35d is a track start position (0 to 2 ⁱ -1, 2 ⁱ at the end of additional writing) when the logical block specified by the logical block ID 35a is a block being additionally written. Show. The Valid flag 35e is “1” when the logical block entry is managed as the MS 11 (including the MSIB 11a).

FS / IS logical block management table 42 (reverse lookup)
Next, the FS / IS logical block management table 42 will be described with reference to FIG. The FS / IS logical block management table 42 is configured in an array format using the FS / IS block ID 42a as an index, and information on logical blocks used as the FS 12 or IS 13 (corresponding to logical block ID, FS / IS internal cluster) This is a table for managing an index to the management table 44, whether additional writing is possible, and the like. The FS / IS logical block management table 42 is accessed mainly using the FS / IS block ID 40d in the FS / IS management table 40. Each entry includes a logical block ID 42b, an intra-block cluster table 42c, a valid cluster number 42d, a writable head page 42e, and a Valid flag 42f. The MS logical block management table 35 functions as a reverse lookup table because necessary information such as the logical cluster stored in the logical block is obtained from the FS / IS block ID 42a corresponding to the storage device position.

Among the logical blocks registered in the MS logical block management table 35, the logical block ID 42b is registered with a logical block ID corresponding to a logical block belonging to FS12 (including FSIB12) and IS13. In the intra-block cluster table 42c, an index to a later-described intra-FS / IS intra-cluster management table 44 indicating which logical cluster address designated by each logical cluster address is recorded at each cluster position in the logical block is registered. . The number of valid clusters 42d indicates the number of valid clusters among clusters stored in the logical block designated by the FS / IS block ID 42a (maximum 2 ^k pieces). The writable first page position 42e is a writable first page position (0 to 2 ^j -1 when the logical block specified by the FS / IS block ID 42a is a block being additionally written, 2 ⁱ at the end of the additional writing. ). The Valid flag 42f is “1” when this logical block entry is managed as FS12 (including FSIB12) or IS13.

-FS / IS cluster management table 44 (reverse lookup)
Next, the FS / IS intra-cluster management table 44 will be described with reference to FIG. The FS / IS intra-cluster management table 44 is a table showing which logical cluster is recorded at each cluster position in the logical block used as the FS 12 or IS 13. Each logical block has 2 ^j pages × 2 ^(k−j) clusters = 2 ^k entries, and information corresponding to the 0th to 2 ^k −1st cluster positions in the logical block is arranged in a continuous area. Is done. Further the ^{2 k-number} of logical blocks information table including belongs to FS12 and IS13 and (P pieces) amount corresponding held, block cluster table 42c of the FS / IS logical block management table 42, the P number Position information (pointer) for the table. The position of each entry 44a arranged in the continuous area indicates the cluster position in one logical block, and the content of each entry 44a is FS so that it can be identified which logical cluster is stored at the cluster position. A pointer to a list including the corresponding logical cluster address managed by the / IS management table 40 is registered. That is, the entry 44a does not indicate the head of the linked list, but a pointer to one list including the corresponding logical cluster address in the linked list is registered.

・ Conversion table 50 (forward lookup)
Next, the logical-physical conversion table 50 will be described with reference to FIG. The logical-physical conversion table 50 is configured in an array format using the logical block ID 50a as an index, and the number of entries can have a maximum of 32K entries in the case of the 128 GB NAND memory 10. The logical-physical conversion table 50 is a table for managing information about conversion between logical block IDs and physical block IDs and lifetime. Each entry includes a physical block address 50b, an erase count 50c, and a read count 50d. The logical-physical conversion table 50 functions as a forward lookup table because necessary information such as a physical block ID (physical block address) is obtained from the logical block ID.

  The physical block address 50b indicates eight physical block IDs (physical block addresses) belonging to one logical block ID 50a. The erase count 50c indicates the erase count of the logical block ID. Bad block (BB) management is performed in units of physical blocks (512 KB), but the number of erasures is managed in units of one logical block (4 MB) in the 32-bit double speed mode. The read count 50d indicates the read count of the logical block ID. The erase count 50c can be used, for example, in a wear leveling process for leveling the number of rewrites of the NAND flash memory. The read count 50d can be used in a refresh process for rewriting data held in a physical block having a deteriorated retention characteristic.

The management table shown in FIG. 8 is summarized for each management target as follows.
RC management: RC cluster management table WC management: WC cluster management table, WC track management table MS management: track management table 30, MS logical block management table 35
FS / IS management: track management table 30, FS / IS management table 40, MS logical block management table 35, FS / IS logical block management table 42, FS / IS intra-cluster management table 44

  The MS structure management table (not shown) manages the structure of the MS area including MS11, MSIB11a, and TFS11b. Specifically, it manages logical blocks assigned to MS11, MSIB11a, and TFS11b. ing. In addition, in the FS / IS structure management table (not shown), the structure of the FS / IS area including FS12, FSIB12a, and IS13 is managed. Specifically, logical blocks allocated to FS12, FSIB12a, and IS13 I manage.

Read Process Next, the read process will be described with reference to the flowchart shown in FIG. When the Read command and the LBA as the read address are input from the ATA command processing unit 121, the data management unit 120 searches the RC cluster management table 23 shown in FIG. 9 and the WC cluster management table 25 shown in FIG. (Step S100). Specifically, a line corresponding to the LSB (ki) bit (see FIG. 7) of the cluster address of the LBA is selected from the RC cluster management table 23 and the WC cluster management table 25, and entered in each way of the selected line. The tracked logical track addresses 23b and 25c are compared with the track address of the LBA (step S110). If there is a matching way, a cache hit is determined and the hit RC cluster management table 23 or WC cluster management table 25 The data of WC21 or RC22 corresponding to the corresponding line and the corresponding way is read and sent to the ATA command processing unit 121 (step S115).

  If the data management unit 120 does not hit the RC 22 or the WC 21 (step S110), the data management unit 120 searches the NAND memory 10 where the search target cluster is stored. First, the data management unit 120 searches the track management table 30 shown in FIG. 12 (step S120). Since the track management table 30 is indexed by the logical track address 30a, only the entry of the logical track address 30a that matches the logical track address specified by the LBA is checked.

  First, the corresponding bit is selected from the cluster bitmap 30b based on the logical cluster address of the LBA to be checked. If the corresponding bit indicates “0”, it means that the cluster surely has the latest data in the MS (step S130). In this case, the logical block ID and the track position where this track exists are obtained from the logical block ID 30c and the intra-logical block track position 30d in the entry of the same logical track address 30a, and the LSB (k− i) By calculating the offset from the track position using the bit, the position where the cluster data corresponding to the cluster address in the NAND memory 10 is stored can be calculated. Specifically, in the logical NAND layer management unit 120b, the logical block ID 30c, the track position 30d in the logical block acquired from the track management table 30 as described above, and the LSB (ki) bit of the logical cluster address of the LBA. To the physical NAND layer management unit 120c.

  In the physical NAND layer management unit 120c, the physical block address (physical block ID) corresponding to the logical block ID 30c is acquired from the logical-physical conversion table 50 shown in FIG. 17 using the logical block ID as an index (step S160), and further acquired. The track position (track start position) in the physical block ID is calculated from the track position 30d in the logical block, and the track start position in the physical block ID is calculated from the LSB (ki) bits of the LBA cluster address. By calculating the offset from, cluster data in the physical block can be acquired. The cluster data acquired from the MS 11 of the NAND memory 10 is sent to the ATA command processing unit 121 via the RC 22 (step S180).

  On the other hand, if the corresponding bit indicates “1” in the search of the cluster bitmap 30b based on the cluster address of the LBA, there is a possibility that the cluster is stored in the FS 12 or the IS 13 (step S130). In this case, the entry of the cluster table pointer 30e in the entry of the corresponding logical track address 30a in the track management table 30 is extracted, and the linked link corresponding to the corresponding logical track address in the FS / IS management table 40 is used by using this pointer. The list is searched sequentially (step S140). Specifically, an entry of the logical cluster address 40a that matches the logical cluster address of the LBA in the linked list of the corresponding logical track address is searched, and if an entry of the matching logical cluster address 40a exists (step S150) ), The logical block ID 40b and the intra-logical block cluster position 40c in the matched list are acquired, and the cluster data in the physical block is acquired using the logical-physical conversion table 50 in the same manner as described above (steps S160 and S180). . Specifically, the physical block address (physical block ID) corresponding to the acquired logical block ID is acquired from the logical-physical conversion table 50 (step S160), and the cluster position in the acquired physical block ID is further converted into the logical block. By calculating from the cluster position in the logical block acquired from the entry in the inner cluster position 40c, the cluster data in the physical block can be acquired. The cluster data acquired from the FS 12 or the IS 13 of the NAND memory 10 is sent to the ATA command processing unit 121 via the RC 22 (step S180).

  If there is no cluster to be searched by searching the FS / IS management table 40 (step S150), the entry in the track management table 30 is searched again to determine the position on the MS 11 (step S170).

Write Process Next, the write process will be described with reference to the flowchart shown in FIG. Data written by a Write command other than FUA (bypassing the DRAM cache and performing direct writing to the NAND) is always stored once on the WC 21 and then written to the NAND memory 10 according to the conditions. In the writing process, an eviction process and a compaction process may occur. In this embodiment, the write process is largely divided into two stages, a write cache flush process (hereinafter referred to as WCF process) and a clean input buffer process (hereinafter referred to as CIB process). Steps S300 to S320 show from the Write request from the ATA command processing unit 121 to WCF processing, and steps S330 to the final step show CIB processing.

  The WCF process is a process of copying data in the WC 21 to the NAND memory 10 (FSIB 12a of the FS 12 or MSIB 11a of the MS 11), and a write request or a cache flush request from the ATA command processing unit 121 is completed only by this process. be able to. As a result, the processing delay of the write request of the ATA command processing unit 121 that has started processing can be limited to the time for writing to the NAND memory 10 corresponding to the capacity of the WC 21 at the maximum.

  The CIB process includes a process of moving the data of the FSIB 12a written by the WCF process to the FS 12, and a process of moving the data of the MSIB 11a written by the WCF process to the MS 11. When CIB processing is started, there is a possibility that data movement and compaction processing between each component (FS12, IS13, MS11, etc.) in the NAND memory 10 may occur in a chain, and the time required for the entire processing varies greatly depending on the state. To do.

  First, details of the WCF processing will be described. When a Write command and an LBA as a write address are input from the ATA command processing unit 121, the DRAM layer management unit 120 searches the WC cluster management table 25 shown in FIG. 10 (Steps S300 and S305). The state of the WC 21 is defined by the state flag 25a (for example, 3 bits) of the WC cluster management table 25 shown in FIG. Most typically, the status of the status flag 25a changes in the order of Invalid (usable) → Waiting for writing from the ATA → Valid (unusable) → Waiting for eviction to NAND → Invalid (usable). First, the write destination line is determined from the LBA cluster address LSB (ki) bits, and n ways of the determined line are searched. When the same logical track address 25c as the input LBA is stored in n ways of the determined line (step S305), this entry is overwritten, so this entry is reserved for cluster writing (Valid (Cannot be used) → Waiting for writing from ATA).

  Then, the DRAM layer management unit 120a notifies the ATA command processing unit 121 of the DRAM address corresponding to the corresponding entry. When writing by the ATA command processing unit 121 is completed, the status flag 25a of the corresponding entry in the WC cluster management table 25 is set to Valid (unusable), and necessary data is registered in the fields of the sector position bitmap 25b and the logical track address 25c. To do. Also, the WC track management table 24 is updated. Specifically, when the same LBA address as the already registered logical track address 24a is input in each list of the WC track management table 24, the number of WC clusters 24b and the way-line bitmap 24c in the corresponding list are displayed. At the same time, the next pointer 24d is changed so that the list becomes the latest list. When an LBA address different from the registered logical track address 24a is input in each list of the WC track management table 24, a new logical track address 24a, a WC cluster number 24b, a way-line bitmap 24c, A list having each entry of the next pointer 24d is created and registered as the latest list. The table is updated as described above, and the writing process is completed (step S320).

  On the other hand, when the same logical track address 25c as the input LBA is not stored in the n ways of the determined line, it is determined whether or not eviction to the NAND memory is necessary (step S305). . That is, first, it is determined whether or not the writable way in the determined line is the last nth way. The writable way is a way having an invalid (usable) state flag 25a or a way having a valid (unusable) and waiting state flag 25a for NAND. When the status flag 25a is waiting to be ejected to the NAND, it means that the evicting is started and waiting for the end of the ejection. If the writable way is not the last n-th way and the writable way is a way having an Invalid state flag 25a, this entry is used for cluster writing. (Invalid (can be used) → Waiting for writing from ATA). Then, the ATA command processing unit 121 is notified of the DRAM address corresponding to the entry, and the ATA command processing unit 121 executes the writing. Then, similarly to the above, the WC cluster management table 25 and the WC track management table 24 are updated (step S320).

  When the writable way is not the last nth way and the writable way is Valid (unusable) and has a status flag 25a waiting to be ejected to NAND. This entry is reserved for cluster writing (Valid (unusable) and waiting to be evicted to NAND → Valid (unusable) and evicting to NAND and waiting for writing from ATA). When the eviction is completed, the status flag 25a is set to wait for writing from the ATA, the DRAM address corresponding to the entry is notified to the ATA command processing unit 121, and the ATA command processing unit 121 executes the writing. Then, similarly to the above, the WC cluster management table 25 and the WC track management table 24 are updated (step S320).

The above process is a case where the eviction process need not be triggered when a write request from the ATA command processing unit 121 is input. On the other hand, the following description is a case in which the eviction process is triggered after a write request is input. In step S305, when the writable way in the determined line is the last nth way, the condition described in the section (i) of the method for determining the data to be expelled from the WC 21 to the NAND memory 10 described above, That is,
(I) When the writable way of the line determined by the tag is the last (in the present embodiment, nth) free way, that is, when the last free way is used, A track to be driven out, that is, an entry in the WC 21 is selected based on the confirmation of the eviction of the oldest updated track based on the LRU among the registered tracks.

When the DRAM layer management unit 120a determines the track to be ejected based on the above policy, as described above, the clusters to be ejected are all clusters in the WC 21 included in the same track, and the cluster amount to be ejected is 50% of the track size. Is exceeded, that is, if the number of valid clusters in the WC is 2 ⁽ ki ^-1) or more in the eviction confirmed track, eviction is performed to the MSIB 11a (step S310). If the number of valid clusters in the WC is less than 2 ^(ki-1) among the confirmed tracks, it is driven out to the FSIB 12a (step S315). Details of the eviction from the WC 21 to the MSIB 11a and the eviction from the WC 21 to the FSIB 12a will be described later. The status flag 25a of the selected eviction entry is shifted from Valid (unusable) to wait for eviction to the NAND memory 10.

  This determination of the eviction destination is executed using the WC track management table 24. That is, in the WC track management table 24, an entry for the number of WC clusters 24b indicating the number of valid clusters is registered for each logical track address. By referring to the entry for the number of WC clusters 24b, the entry from the WC 21 is performed. It is determined whether the destination is FSIB 12a or MSIB 11a. In addition, since all clusters belonging to the logical track address are registered in the bitmap format in the way-line bitmap 24c, refer to this way-line bitmap 24c when evicting. It is possible to easily know the storage position in the WC 21 of each cluster to be evicted.

In addition, after the writing process or after the writing process, the following conditions described above,
(Ii) When the number of tracks registered in the WC 21 exceeds a predetermined number,
Even if the above is established, the eviction process to the NAND memory 10 is executed in the same manner as described above.

WC → MSIB (Copy)
Next, when eviction from the WC 21 to the MSIB 11a occurs due to the determination based on the number of effective clusters (the number of effective clusters is 2 ^(ki-1) or more), as described above, the following procedure is performed. Execute (Step S310).
1. Refer to the WC cluster management table 25, refer to the sector position bitmap 25b in the tag corresponding to the cluster to be evicted, and if the sector position bitmaps 25b are not all “1”, they are included in the NAND memory 10. Intra-track sector padding, which will be described later, is performed by merging with sectors in the same cluster. In addition, a passive merge process is executed in which clusters that do not exist in the WC 21 in the track are read from the NAND memory 10 and merged.
2. If tracks decided to be flushed is smaller than 2 ^i, adds tracks decided flush with valid cluster 2 ^(k-i-1) or more until the 2 ⁱ pieces to old tracks in WC 21.
3. If there are 2 ⁱ or more tracks to be copied, 2 ⁱ units are written as a set and written to the MSIB 11a in units of logical blocks.
4.2 Write tracks that could not be made into ⁱ sets to the MSIB 11a in units of tracks.
5. Clusters and tracks that already existed on the FS, IS, and MS after the copy are completed are invalidated.

  The update process of each management table associated with the copy process from the WC 21 to the MSIB 11a will be described. The status flag 25a in the entries corresponding to all the clusters in the WC 21 belonging to the evicted track in the WC cluster management table 25 is set to Invalid, and thereafter writing to these entries becomes possible. Further, the list corresponding to the evicted track in the WC track management table 24 is invalidated, for example, by changing or deleting the next pointer 24d of the previous list.

  On the other hand, when a track movement from the WC 21 to the MSIB 11a occurs, the track management table 30 and the MS logical block management table 35 are updated accordingly. First, the logical track address 30a that is an index of the track management table 30 is searched to determine whether or not the logical track address 30a corresponding to the moved track is already registered. If already registered, update the fields of the cluster bitmap 30b of the corresponding index (because it is moving to the MS11 side, so that all the corresponding bits are set to “0”), the logical block ID 30c + the track position 30d in the logical block. . When the logical track address 30a corresponding to the moved track is not registered, the cluster bitmap 30b, the logical block ID 30c + the track position 30d in the logical block is registered for the entry of the corresponding logical track address 30a. Further, according to the change of the track management table 30, entries such as the logical block ID 35a, the corresponding track management pointer 35b, the number of valid tracks 35c, and the writable head track 35d in the MS logical block management table 35 are updated as necessary. .

  When track writing to the MS 11 from another area (FS12, IS13) or the like, or when track writing in the MS by the compaction process inside the MS 11 occurs, the effective cluster in the WC 21 included in the track to be written is included. Are simultaneously written to the MS. There is such a passive merge as a write from the WC 21 to the MS 11. When such a passive merge is performed, those clusters are deleted (invalidated) from the WC 21.

WC → FSIB (Copy)
Next, when eviction from the WC 21 to the FSIB 12a occurs due to the determination based on the number of effective clusters (the number of effective clusters is less than 2 ^(ki-1)) , as described above, the following procedure is performed. Execute.
1. If the sector position bitmap 25b in the tag corresponding to the cluster to be evicted in the WC cluster management table 25 is referred to and the sector position bitmaps 25b are not all “1”, the sectors in the same cluster included in the NAND memory 10 And merge sectors in the cluster.
2. The tracks in the WC follow in chronological order 2 ^(k-i-1) clusters are extracted from tracks that you do not only have an effective cluster of less than number, if the number of valid cluster becomes 2 ^k number logical them all cluster in FSIB12a Write in blocks.
If 3.2 ^k pieces are not found, all tracks having an effective cluster number of less than 2 ^(ki-1) are written in the FSIB 12a by the required number of logical pages.
4). After the copy is completed, the same cluster that was already copied on the FS and IS is invalidated.

  The update process of each management table associated with the copy process from the WC 21 to the FSIB 12a will be described. The status flag 25a in the entries corresponding to all the clusters in the WC 21 belonging to the evicted track in the WC cluster management table 25 is set to Invalid, and thereafter writing to these entries becomes possible. Further, the list corresponding to the evicted track in the WC track management table 24 is invalidated, for example, by changing or deleting the next pointer 24d of the previous list. On the other hand, when cluster movement from the WC 21 to the FSIB 12a occurs, the cluster table pointer 30e of the track management table 30, the number of FS clusters 30f, etc. are updated accordingly, and the logical block ID 40b of the FS / IS management table 40, cluster within the logical block The position 40c and the like are updated. For clusters that did not originally exist in the FS 12, a list to the linked list of the FS / IS management table 40 is added. Along with this update, the corresponding portions of the MS logical block management table 35, the FS / IS logical block management table 42, and the FS / IS intra-cluster management table 44 are updated.

CIB Processing When the WCF processing as described above is completed, the logical NAND layer management unit 120b then moves the data of the FSIB 12a written by the WCF processing to the FS 12, and the data of the MSIB 11a written by the WCF processing. A CIB process including a process of moving to the MS 11 is executed. When the CIB process is started, there is a possibility that data movement or compaction process between blocks occurs in a chain as described above, and the time required for the entire process varies greatly depending on the state. In this CIB process, basically, the CIB process in the MS 11 is first performed (step S330), then the CIB process in the FS 12 is performed (step S340), and then the CIB process in the MS 11 is performed again. Is performed (step S350), then CIB processing is performed at IS13 (step S360), and finally CIB processing is performed again at MS11 (step S370). If a loop occurs in the procedure during the eviction process from the FS 12 to the MSIB 11a, the eviction process from the FS 12 to the IS13, or the eviction process from the IS 13 to the MSIB 11a, the order may not be as described above. CIB processing in MS11, FS12 and IS13 will be described separately.

CIB Process of MS 11 First, the CIB process in the MS 11 will be described (step S330). When movement of track data from WC21, FS12, IS13 to MS11 occurs, the track data is written to MSIB 11a. After the writing to the MSIB 11a is completed, as described above, the track management table 30 is updated to change the logical block ID 30c where the track is arranged, the intra-block track position 30d, and the like (Move). When new track data is written in the MSIB 11a, the track data originally existing in the MS 11 or the TFS 11b is invalidated. This invalidation processing is realized by invalidating the track from the entry of the logical block in which the old track information is stored in the MS logical block management table 35. Specifically, the pointer of the corresponding track in the field of the track management pointer 35b in the corresponding entry of the MS logical block management table 35 is deleted, and the number of valid tracks is decremented by one. When all the tracks in one logical block are invalidated by this track invalidation, the Valid flag 35e is invalidated. Due to such invalidation or the like, a block of the MS 11 includes an invalid track, and if this is repeated, the use efficiency of the block may be reduced, and a usable logical block may be insufficient.

  When such a situation occurs, the data management unit 120 performs compaction processing when the number of logical blocks allocated to the MS 11 exceeds the upper limit of the number of blocks allowed for the MS 11. Create an invalid free block FB. The invalid free block FB is returned to the physical NAND layer management unit 120c. Then, after reducing the number of logical blocks allocated to the MS 11, the logical NAND layer management unit 120b acquires a new writable free block FB from the physical NAND layer management unit 120c. The compaction process is a physical NAND layer management unit that collects valid clusters of a logical block targeted for compaction into a new logical block or copies valid tracks in the logical block targeted for compaction to another logical block. This is a process for creating an invalid free block FB to be returned to 120c and improving the utilization efficiency of the logical block. When performing compaction, if there are valid clusters on the WC, FS, and IS for the track area targeted for compaction, passive merge is performed to merge all of them. Further, the logical block registered in the TFS 11b is not included in the compaction target.

Hereinafter, an example of the eviction from the MSIB 11a to the MS 11 or the TFS 11b and the compaction process on the condition that a full block exists in the MSIB 11a will be specifically described.
1. By referring to the Valid flag 35e of the MS logical block management table 35, if there is an invalid logical block in the MS 11, that block is set as an invalid free block FB.
2. The logical block that has become full in the MSIB 11a is driven out to the MS 11. Specifically, the above-described MS structure management table (not shown) is updated, and the corresponding logical block is transferred from under MSIB management to under MS management.
3. It is determined whether or not a situation occurs in which the number of logical blocks allocated to the MS 11 exceeds the upper limit of the number of blocks allowed for the MS 11, and if so, the following MS compaction is executed. .
4). By referring to the field of the effective track number 35c in the MS logical block management table 35, the logical blocks not included in the TFS 11b having invalidated tracks are sorted by the effective track number.
5. Compaction is performed by collecting tracks from logical blocks with a small number of valid tracks. At this time, the compaction is performed by copying one logical block (2 ⁱ tracks) at a time. If the compaction target track has valid clusters in WC21, FS12, and IS13, they are also merged.
6). The logical block of the compaction source is set as an invalid free block FB.
7). When one logical block composed of valid 2 ⁱ tracks is obtained by compaction, move to the head of the TFS 11b.
8). When an invalid free block FB can be created by copying the valid track in the logical block to another logical block, the number of valid tracks less than 2 ⁱ tracks is additionally written in the track unit to the MSIB 11a.
9. The logical block of the compaction source is set as an invalid free block FB.
10. When the number of logical blocks allocated to the MS 11 falls below the upper limit value of the number of blocks allowed for the MS 11, the MS compaction process is terminated.

Next, the CIB process in the FS 12 will be described (step S340). When logical pages on which all pages have been written are created in the FSIB 12a by the cluster write processing from the WC 21 to the FSIB 12a, those blocks in the FSIB 12a are moved from the FSIB 12a to the FS 12. Along with this Move, a situation occurs in which an old logical block is evicted from the FS 12 having a FIFO structure composed of a plurality of logical blocks.

The eviction from the FSIB 12a to the FS 12 and the block eviction from the FS 12 are specifically realized as follows.
1. When there is an invalid logical block in the FS 12 by referring to the Valid flag 35e of the FS / IS logical block management table 42, the block is set as an invalid free block FB.
2. The block that has become full in the FSIB 12a is driven out to the FS 12. Specifically, the FS / IS structure management table (not shown) described above is updated, and the corresponding block is transferred from under FSIB management to under FS management.
3. It is determined whether or not a situation occurs in which the number of logical blocks allocated to the FS 12 exceeds the upper limit of the number of blocks allowed for the FS 12, and if so, the following eviction is executed.
4). First, the cluster data in the oldest logical block to be evicted is determined to be moved directly to the MS 11 without moving to the IS 13 (in practice, since the management unit of the MS is a track, Decision).
(A) Scan valid clusters in the logical block to be evicted sequentially from the top of the page.
(A) A search is made by referring to the field of the number of FS clusters 30 f in the track management table 30 to determine how many valid clusters the FS belongs to.
(C) If the number of effective clusters in a track is equal to or greater than a predetermined threshold (for example, 50% of 2 ^k-i ), that track is set as a candidate for egress to MS.
5. Write the track to MS11 to MSIB 11a.
6). If the eviction track remains, further eviction to the MSIB 11 is executed.
7). If a valid cluster still exists in the logical block to be evicted after the processes 2 to 4, the logical block is moved to the IS 13.
Note that when the FS 12 is evicted to the MSIB 11a, immediately after that, the above-described CIB processing in the MS 11 is executed (step S350).

IS13 CIB Processing Next, the CIB processing in IS13 will be described (step S360). A logical block is added to IS13 by the above block movement from FS12 to IS13, but there is a situation in which the upper limit of the number of blocks manageable to IS13 composed of a plurality of logical blocks is exceeded. appear. When such a situation occurs, the IS 13 first carries out one or more logical blocks to the MS 11 and then executes IS compaction. Specifically, the following procedure is executed.
1. The tracks included in the IS 13 are sorted by the number of effective clusters in the track × the effective cluster coefficient, and 2 ^{i + 1} tracks (two logical blocks) having a large product value are collected and driven out to the MSIB 11a.
2. When the total number of effective clusters of 2 ^{i + 1} logical blocks with the smallest number of effective clusters is, for example, 2 ^k (one logical block) or more which is a predetermined set value, the above steps are repeated.
3. After the above eviction, 2 ^k clusters are collected in order from the logical block with the smallest number of valid clusters, and compaction is performed in the IS 13.
4). A compaction source logical block whose valid cluster is lost is returned as an invalid free block FB.
Note that when the eviction from the IS 13 to the MSIB 11a occurs, immediately after that, the above-described CIB processing in the MS 11 is executed (step S370).

FIG. 20 shows combinations of input and output in the data flow between the components and what triggers the data flow. The data is basically written in the FS 12 by the cluster eviction from the WC 21, but when the intra-cluster sector filling (cluster filling) is necessary accompanying the eviction from the WC 21 to the FS 12, the FS 12, IS 13, MS 11 Data is copied. In the WC 21, the sector (512B) unit can be managed by identifying the presence / absence of 2 ^(1-k) sectors in the cluster address by the sector position bitmap 25b in the tag of the WC cluster management table 25. Is possible. On the other hand, the management unit of FS12 and IS13, which are functional elements in the NAND memory 10, is a cluster, and the management unit of the MS 11 is a track. Thus, since the management unit in the NAND memory 10 is larger than the sector, when data is written from the WC 21 to the NAND memory 10, data having the same cluster address as the data to be written exists in the NAND memory 10. In this case, it is necessary to merge the sector in the cluster written in the NAND memory 10 from the WC 21 and the sector in the same cluster address existing in the NAND memory 10 before writing to the NAND memory 10.

  This process includes the intra-cluster sector filling process (cluster filling) and the intra-track sector filling process (track filling) shown in FIG. 20. If these processes are not performed, correct data cannot be read. Therefore, when data is expelled from the WC 21 to the FSIB 12a or the MSIB 11a, the WC cluster management table 25 is referred to, the sector position bitmap 25b in the tag corresponding to the cluster to be expelled is referred to, and all the sector position bitmaps 25b are When it is not “1”, the intra-cluster sector filling or the intra-track sector filling is performed by merging with the sector in the same cluster or the same track included in the NAND memory 10. For this processing, the work area of the DRAM 20 is used, and data is written from the work area of the DRAM 20 to the MSIB 11a or written to the FSIB 12a.

In the IS 13, data is basically written by moving the block from the FS 12 (Move), or data is written by compaction inside the IS. In the MS 11, data can be written from all locations. At that time, since the MS 11 can write data only in units of tracks, filling with the MS's own data may occur. In addition, when writing in units of tracks, fragmented data in other blocks is also written by passive merging. Further, the MS 11 also has writing by MS compaction. In passive merging, when one of the three components of WC21, FS12, or IS13 causes track eviction or logical block eviction (ejecting 2 ⁱ tracks) from MS11, one configuration The valid clusters in the other two components included in the track (or logical block) to be ejected by the element and the valid clusters in the MS 11 are collected in the work area of the DRAM 20 and one track worth from the work area of the DRAM 20. Is written in the MSIB 11a.

  FIG. 21 is a diagram showing a detailed configuration of the NAND memory in the present embodiment, and shows a detailed configuration of the FS unit 12Q, the IS unit 13Q, and the MS unit 11Q shown in FIG.

  When the secondary storage device of the host device 1 is configured by the SSD 100 and the reset request is received from the host device 1, the content held in the WC 21 provided between the NAND memory 10 and the host device 1 is stored. Then, the reset process must be performed after reflecting in the NAND memory 10.

  However, since the NAND memory 10 cannot be overwritten, the WCF process and the CIB process described above must be performed in order to write the contents of the WC 21. This process is performed for the valid clusters stored in the WC 21. Therefore, there is a possibility that a lot of time may be spent from the time when the reset request is received from the host device until the actual shift to the reset process. Based on such knowledge, the main part of the present embodiment relating to a memory system capable of shortening the time required from when a reset request is received until the actual reset processing is performed will be described below.

-WC Configuration As described above, the WC 21 is managed in the m-line, n-way (m is a natural number of 2 ^(ki) or more, n is a natural number of 2 or more) set associative method, and the WC 21 The data registered in is managed by the LRU.

FS Configuration The FS unit 12Q includes an FS input buffer (FSIB) 12a and an FS12. As described above, the FS 12 is a FIFO in which data is managed in cluster units, and data writing is performed in units of pages for 2 ^(k−j) clusters. The FS 12 has a capacity for many logical blocks. An FS input buffer (FSIB) 12a to which data evicted from the WC 21 is input is provided at the front stage of the FS 12.

  The FSIB 12a includes an FS full block buffer (FSFB) 12aa, an FS additional write buffer (FS additional write IB) 12ab, and an FS bypass buffer (hereinafter referred to as FSBB) 12ac. The FSFB 12aa has a capacity for one to a plurality of logical blocks, the FS additional recording IB 12ab has a capacity for one to a plurality of logical blocks, and the FSBB 12ac also has a capacity for one to a plurality of logical blocks (for example, 4 MB). With a capacity of If the eviction data from the WC 21 is equivalent to one logical block, the block-unit data is copied to the FSFB 12aa, and if not, the page-unit additional write is performed to the FS additional IB 12ab.

  The FSBB 12ac does not end the CIB process even after a predetermined time when a write command accompanied by a flush (eject) from the WC 21 is issued during the execution of the CIB process. This is used to save the contents stored in the WC 21 as they are when a reset request from the host apparatus 1 is generated.

IS configuration The IS unit 13Q includes an IS input buffer (ISIB) 13a, an IS 13, and an IS compaction buffer 13c. For example, the ISIB 13a has a capacity for one to a plurality of logical blocks, the IS compaction buffer 13c has a capacity for one logical block, and the IS 13 has a capacity for many logical blocks. The IS compaction buffer 13c is a buffer for performing compaction in IS13.

  As described above, the IS 13 manages data in units of clusters as in the FS 12, and data is written in units of blocks. When a logical block is moved from the FS 12 to the IS 13, that is, an eviction from the FS 12 occurs, the logical block to be evicted that was previously managed by the FS 12 is changed to a management target block of the IS 13 (specifically, ISIB 13 a) by changing the pointer. It becomes. When the number of blocks in IS13 exceeds a predetermined upper limit due to the movement of the logical block from FS12 to IS13, data eviction and compaction processing from IS13 to MS11 is executed, and the number of blocks in IS13 is returned to the specified value.

MS Configuration The MS unit 11Q includes an MSIB 11a, a track pre-stage buffer (TFS) 11b, and an MS (MS body) 11.

  The MSIB 11a includes one to a plurality of (four in this embodiment) MS full block input buffer (hereinafter referred to as MSFB) 11aa and one to a plurality of (two in this embodiment) additional input buffer (hereinafter referred to as MS additional recording). IB) 11ab. One MSFB 11aa has a capacity for a logical block, and the MSFB 11aa is used for writing in units of logical blocks. One MS additional recording IB 11ab has a capacity corresponding to a logical block, and the MS additional recording IB 11ab is used at the time of track additional writing.

  In the MSFB 11aa, a logical block evicted from the WC 21, a logical block evicted from the FS 12, or a logical block evicted from the IS 13 is copied. A logical block copied to one MSFB 11aa is directly moved to the MS 11 without passing through the TFS 11b. After Move to MS11, free block FB is assigned as MSFB11aa.

  In the MS additional recording IB 11ab, the logical track evicted from the WC 21 or the logical track evicted from the FS 12 is additionally copied. The full block in the MS additional recording IB 11ab additionally written in such a track unit is moved to the TFS 11b. After the move to the TFS 11b, the free block FB is assigned as the MS additional recording IB 11ab.

  Although not shown in FIG. 21, the MSFB 11aa and the MS additional recording IB 11ab also have inputs for the above-described passive merging. That is, in passive merging, when track eviction or block eviction from one of the three components WC21, FS12, or IS13 to MS11 occurs, the track to be evacuated by one component (or The effective clusters in the other two components included in the block) and the effective clusters in the MS 11 are collected in the work area of the DRAM 20 and written from the work area of the DRAM 20 to the MS additional recording IB 11ab as data for one track. One block of data is written to the MSFB 11aa.

The TFS 11b is a buffer having a capacity corresponding to a large number of logical blocks and having a FIFO structure interposed between the MS additional recording IB 11ab and the MS 11. On the input side of the TFS 11b having the FIFO structure, a full block of the MS additional recording IB 11ab to be additionally written in a track unit is moved, and is composed of effective 2 ⁱ tracks formed by the compaction processing in the MS 11. The one logical block thus moved is moved from the MS compaction buffer 11c. The MS compaction buffer 11c is a buffer for performing compaction in the MS 11. The TFS 11b has a FIFO structure like the FS 12, and the valid track passing through the FIFO is invalidated when there is a rewrite to the same track address from the host, and the oldest block overflowing from the FIFO structure is , Move to MS11. Accordingly, the track passing through the TFS 11b can be regarded as having a higher update frequency than the track included in the block directly written from the MSFB 11aa to the MS 11.

The MS compaction processing is performed in MS, and 2 ⁱ track MS compaction for constituting one logical block collects 2 ⁱ number of valid tracks, 2 ⁱ track to perform compaction collects valid tracks smaller in number than 2 ⁱ track There are two types of less than MS compaction. 2 In the ^i- track MS compaction, the MS compaction buffer 11c is used, and the logical block after compaction is moved to the head of the TFS 11b. In MS compaction of less than 2 ⁱ tracks, the data is copied to the MS additional recording IB 11ab for each track.

(Bypass mode)
Here, the bypass mode will be described. The bypass mode is a mode in which data written to the WC 21 is always evicted after the Write command is completed, and is directly written to the MS 11 (MSIB 11a) without passing through the FS unit 12Q and the IS unit 13Q. In a general memory system, a predetermined time is provided as a time for the data management unit 120 to process a command requested from a host device. That is, the data management unit 120 must keep the response process (command response process) for the command requested from the host device within the specified time.

  Therefore, for example, when the time required for CIB processing exceeds a specified time, special measures are required. As a case where the time required for executing the CIB process exceeds the specified time, execution of the compaction process for eliminating the fragmentation of the IS 13 can be considered. This is because in the IS13 compaction process, clusters of at least one logical block must be collected. The processing mode for performing the “special response” is referred to as a bypass mode here. Note that the FSBB 12ac shown in FIG. 21 is a buffer for saving a valid cluster in the WC 21 when the bypass mode is shifted, and is a buffer dedicated to the bypass mode that is used only when the bypass mode is shifted.

  The FSBB 12ac (FSIB 12a) manages data in units of clusters, similar to the data managed on the WC 21, but the MSIB 11a manages data in units of tracks, unlike the data managed on the WC 21. ing. For this reason, for example, when there are many clusters with different addresses in the WC 21, if the data of the WC 21 is saved on the MSIB 11a, tracks for the different addresses must be prepared as a result of collecting the clusters for each address. In addition, a huge capacity area must be secured for evacuation. On the other hand, when data is stored in the FSIB 12a (FSBB 12ac), data management is performed by the same cluster management as the WC 21, so only the same number of clusters as the number of entries of the WC 21 is sufficient, and the capacity of the WC 21 is at most. That's fine. Therefore, it is desirable to provide the FSBB 12ac, which is a buffer dedicated to the bypass mode, in the FSIB 12a.

  In this embodiment, the DRAM 20 corresponds to the first storage unit in the claims, the FS 12 in the NAND memory 10 also corresponds to the second storage unit, and the MS 11 also has the third storage unit. Corresponding to the storage unit, FSIB12a (FSFB12ab, FS additional recording IB12ab, FSBB12ac) also corresponds to the first input buffer, MSIB11a (MSFB11ab, MS additional recording IB11ab) also corresponds to the second input buffer, and FSBB12ac is Similarly, it corresponds to the save buffer. In the claims, the first unit corresponds to a sector, the second unit corresponds to a page, the third unit corresponds to a block, and the fourth unit corresponds to a track.

(Bypass mode-operation flow)
Next, an operation flow in the bypass mode will be described. FIG. 22 is a flowchart illustrating an example of an operation flow in the bypass mode.

  As shown in FIG. 22, first, it is assumed that when the CIB process in the normal write process is being executed (step S800), the ATA command processing unit 121 issues a write command that requires a flash process ( Step S801). At this time, a process for determining whether or not the CIB process is completed is executed (step S802). If the CIB process has been completed (step S802, Yes), the normal process (write command process) is executed without shifting to the bypass mode (step S803), and this flow is exited.

  On the other hand, when the CIB process has not been completed (No at Step S802), a determination process is performed as to whether or not a predetermined time has elapsed since the Write command (Step S801) was issued. In this determination process, for example, a timer mounted on an SSD or a host device is used, the elapsed time after the Write command is issued is measured, and this elapsed time is compared with a predetermined time. The predetermined time here is a time shorter than a specified time. For example, if the limit (specified time) of command response processing to the host side is “T1”, for example, “T2 ( The time “T2 <T1)” corresponds to the “predetermined time”.

  Here, when the predetermined time has not elapsed since the issuance of the Write command (step S804, No), the processing returns to the above-described step S802. On the other hand, when a predetermined time has elapsed since the issuance of the Write command (step S804, Yes), data having a valid cluster in the WC 21 is saved in the FSBB 12e of the FSIB 12a (step S805). Thereafter, the data in each buffer of the MSIB 11a is expelled to the MS 11 or the TFS 11b (step S806), and the CIB process is interrupted (step S807). Next, the data specified in the write process accepted in step S801 is additionally written to the MSIB 11a via the WC21 (step S808). Thereafter, the CIB process is resumed (step S809), the CIB process completion determination process is performed (step S810), and when the CIB process is completed (step S810, Yes), the process flow in the bypass mode is exited.

  Here, some supplementary explanation regarding the bypass mode described above will be added. In the above processing flow, the processing in steps S805 to S810 corresponds to the processing in the bypass mode. During the process in the bypass mode, a write process is performed via the WC 21 by a Write command issued from the ATA command processing unit 121, and a flush process is immediately performed on the MSIB 11 after the completion of the write process. At this time, no additional recording process is performed on the FSIB 12a. For the Cache Flush command, since all data in the WC 21 has already been evicted, it is possible to send a command completion notification to the host device without accessing the NAND memory 10. .

  In the bypass mode, when the append process for the MSIB 11a is completed, the CIB process is resumed regardless of the conditions. If a Write command is issued again from the ATA command processing unit 121 during this process, the CIB process is performed until the same condition as “bypass mode start” is reached, that is, until a predetermined time elapses from the Write command. If the CIB process is not completed by a predetermined time, a write process for the MS via the WC 21 is executed as in the above-described float. Thereafter, this process is repeated until the bypass mode end condition is reached. Note that if the CIB process is completed before the timeout occurs, the bypass mode ends and the normal mode is restored.

  By the way, when the data written in the WC 21 is stored in the NAND memory 10 as described above, since the condition selection is performed at the time of writing, the data written in the WC 21 is completely transferred to the NAND memory 10. It takes time to save. Such saving processing and saving processing of the saved data in the NAND memory 10 are also executed when a reset request is received from the host device side. In other words, when a reset request is received, it is necessary to turn off the power and then turn on the power again after performing the above saving process. However, when selecting the conditions for determining the data storage destination as described above, after the reset request is issued from the host device side, the power is turned on again and becomes usable. There was a problem of spending a lot of time.

  Therefore, in the memory system according to the present embodiment, when the data management unit 120 receives a reset request from the host device side, the data management unit 120 stores the data stored in the WC 21 in the FSBB 12ac of the FSIB 12a and the storage in the FSBB 12ac. After the process is completed, a process of turning off the power is performed. As a result, it is not necessary to make a determination such as determination of the storage destination of the data stored in the WC 21 at the time of normal saving processing and saving processing of the saved data. Here, as described above, this FSBB 12ac is provided to temporarily store the effective cluster in the WC by interrupting the IS compaction process when a Write command with WCF is issued during the IS compaction process. This area has a capacity capable of storing the contents stored in the WC. Therefore, in this embodiment, when a reset request is received, the data of the WC 21 is stored in the FSBB 12ac.

  In addition, when the power is turned on again, the data management unit 120 performs processing for restoring the data stored in the FSBB 12ac of the FSIB 12a to the WC 21, and returns the memory system to the state immediately before the reset request is issued. it can.

  In this description, the bypass buffer for temporarily storing the data of the WC 21 when receiving the reset request is provided in the FSIB 12a. However, the bypass buffer may be provided in the MSIB 11a.

  As described above, in the memory system according to this embodiment, when a reset request is issued, the data stored in the WC 21 is directly saved without executing saving processing of the saved data. Since the data is stored in the FSBB 12ac of the FSIB 12a, the time from when the reset request is received until the power of the memory system is turned off, or when the power is turned on, compared to the case where the saving and data saving processing is executed. This has the effect of shortening the time until the system becomes available. In addition, since the WC 21 is restored using the data stored in the FSBB 12ac of the FSIB 12a, the state before the reset request is issued can be restored.

The block diagram which shows the structural example of SSD. The figure which shows the example of a structure of one block contained in a NAND memory chip, and threshold value distribution in a quaternary data storage system. The block diagram which shows the hardware internal structural example of a drive control circuit. The block diagram which shows the function structural example of a processor. The block diagram which shows the function structure formed in NAND memory and DRAM. FIG. 3 is a more detailed functional block diagram related to a writing process from a WC to a NAND memory. The figure which shows a LBA logical address. The figure which shows the structural example of the management table in a data management part. The figure which shows an example of RC cluster management table. The figure which shows an example of a WC cluster management table. The figure which shows an example of a WC track management table. The figure which shows an example of a track management table. The figure which shows an example of a FS / IS management table. The figure which shows an example of MS logic block management table. The figure which shows an example of a FS / IS logical block management table. The figure which shows an example of the cluster management table in FS / IS. The figure which shows an example of a logical-physical conversion table. 10 is a flowchart showing an example of operation of read processing. The flowchart which shows the operation example of a writing process. The figure which shows the combination of the input and output in the flow of data between each component, and its generation factor. FIG. 3 is a diagram showing a detailed configuration of a NAND memory in this embodiment. The flowchart which shows an example of the operation | movement flow at the time of bypass mode.

Explanation of symbols

  10 NAND memory, 50 logical-physical conversion table, 120 data management unit, 120b data management unit (logical NAND layer), 120c data management unit (physical NAND layer), 200 bad block management table (BB management table), 210 reserved block management Table (RB block management table), 220 Free block management table (FB management table), 230 Active block (AB) management table.

Claims (5)

A first storage unit as a cache memory for writing composed of a volatile semiconductor storage element that is read / written to / from the host device in a first unit;
A second storage unit configured by a nonvolatile semiconductor storage element that is read / written in the second unit and erased in a third unit that is a natural number multiple of 2 or more of the second unit. When,
A third semiconductor memory element is formed of a nonvolatile semiconductor memory element in which reading / writing is performed in a fourth unit that is a natural fraction of two or more of the third unit, and erasing is performed in the third unit. A storage unit;
A first input buffer configured by a non-volatile semiconductor memory element that is read / written in the second unit and erased in the third unit and functions as an input buffer of the second memory unit When,
A second input buffer configured by a non-volatile semiconductor memory element that is read / written in the fourth unit and erased in the third unit and functions as an input buffer of the third memory unit When,
A first process for writing a plurality of data consisting of the first unit from a host device to the first storage unit; and a plurality of data written to the first storage unit for the first and second data The second process that drives out to the input buffer, and the plurality of data written to the first and second input buffers are driven out to the second and third storage units, respectively, and written to the second storage unit A third process for expelling a plurality of data to the second input buffer;
A memory system comprising:
The first input buffer has a storage capacity larger than that of the first storage unit, and has a save buffer for storing data written in the first storage unit,
When the controller receives a reset request from the host device, the controller saves data written in the first storage unit to the save buffer.   The controller further has a function of restoring the data saved in the save buffer to the first storage unit when the power of the memory system is turned on from off by the reset request. The memory system according to claim 1.   The controller is a case where a write processing command that requires eviction of data written in the first storage unit is issued from the host device, and the third processing exceeds a predetermined time 2, the processing determined to exceed the predetermined time is interrupted, and the data written in the first storage unit is stored in the save buffer. Memory system. A first storage unit as a cache memory for writing composed of a volatile semiconductor storage element that is read / written to / from the host device in a first unit;
A second storage unit configured by a nonvolatile semiconductor storage element that is read / written in the second unit and erased in a third unit that is a natural number multiple of 2 or more of the second unit. When,
A third semiconductor memory element is formed of a nonvolatile semiconductor memory element in which reading / writing is performed in a fourth unit that is a natural fraction of two or more of the third unit, and erasing is performed in the third unit. A storage unit;
A fourth storage unit including a nonvolatile semiconductor storage element that is read / written in the second unit and erased in the third unit;
A first input buffer configured by a non-volatile semiconductor memory element that is read / written in the second unit and erased in the third unit and functions as an input buffer of the second memory unit When,
A second input buffer configured by a non-volatile semiconductor memory element that is read / written in the fourth unit and erased in the third unit and functions as an input buffer of the third memory unit When,
A third input buffer configured by a non-volatile semiconductor memory element that is read / written in the second unit and erased in the third unit and functions as an input buffer of the fourth memory unit When,
A first process for writing a plurality of data consisting of the first unit from a host device to the first storage unit; and a plurality of data written to the first storage unit for the first and second data The second process for kicking out to the input buffer and the plurality of data written to the first and second input buffers are respectively kicked to the second and third storage units and written to the second storage unit. A third process for expelling the plurality of data to the second input buffer, and expelling the plurality of data written in the second storage unit to the fourth storage unit in a third unit, A controller that executes a fourth process for driving out a plurality of data written in the unit to a third input buffer in a third unit;
A memory system comprising:
The first input buffer has a storage capacity larger than that of the first storage unit, and has a save buffer for storing data written in the first storage unit,
When the controller receives a reset request from the host device, the controller saves data written in the first storage unit to the save buffer.   The controller is a case where a write process command that requires eviction of data written in the first storage unit is issued from the host device, and among the third to fourth processes When it is determined that at least one of the processes exceeds a predetermined time, the process determined to exceed the predetermined time is interrupted, and the data written in the first storage unit is stored in the save buffer The memory system according to claim 4.

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