JP2009200355A - Tft substrate, method of manufacturing the same, and liquid crystal display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a TFT substrate having high dielectric strength and high quality. <P>SOLUTION: The TFT substrate includes TFTs 32 each of which includes a gate electrode 52, a source electrode and a drain electrode 56, scanning lines each of which is electrically connected to the gate electrode 52 and signal lines each of which is electrically connected to the source electrode. At least one of the gate electrode 52, the source electrode, the drain electrode 56, the scanning line, and the signal line has a main wiring layer 70 and a barrier layer 72 formed on the main wiring layer 70, at least part of the barrier layer 72 is composed of titanium nitride, and a nitriding rate in the vicinity of a lower surface of the barrier layer 72, which is brought into contact with the main wiring layer 70, is lower than that in the vicinity of the upper surface of the barrier layer 72. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a TFT (Thin Film Transistor) substrate used in a liquid crystal display device or the like.

  Conventionally, electrical wiring (scanning lines, signal lines, TFT gate electrodes, source electrodes, TFTs) disposed on a TFT substrate for the purpose of improving the quality of an electrical device having a TFT (Thin Film Transistor) substrate, reducing power consumption, etc. Improvements continue to the material and structure (including the drain electrode).

  The TFT substrate of the liquid crystal display device is required to use low-resistance electrical wiring as the liquid crystal panel becomes larger. For this reason, aluminum (Al) having a small specific resistance is often used as a material for electrical wiring in a liquid crystal display device. However, when only Al is used as the material for the electrical wiring, since Al has a relatively low melting point, fine protrusions called hillocks are formed on the surface of the Al layer in the subsequent heating process, and the electric charges are caused by the hillocks. There was a problem that a crack occurred in an insulating layer or the like laminated on the wiring. If a crack occurs in the insulating layer, the withstand voltage is lowered and the reliability of the device is lowered.

In order to prevent hillocks in the Al layer, Patent Document 1 discloses that an electric wiring having a multilayer structure in which a layer made of a high melting point material such as titanium (Ti) or titanium nitride (TiN) is laminated on the Al layer. Has been.
JP 2000-208773 A

  However, as a result of studies by the inventors of the present application, it has been found that the following problems occur when the above-described multi-layered electric wiring is used.

  FIG. 10 is a cross-sectional view schematically showing a partial cross-sectional shape of the TFT 32 ′ in the liquid crystal display device 100 ′ of the reference example. In the liquid crystal display device 100 ', the above-described multilayer structure is applied to the gate electrode 52'.

  As shown in FIG. 10, the TFT 32 ′ of the liquid crystal display device 100 ′ includes a gate electrode (gate metal layer) 52 ′ formed on the glass substrate 50 and a gate insulating layer stacked on the gate electrode 52 ′. 76, a semiconductor layer 58 formed on the gate insulating layer 76, a drain electrode (drain metal layer) 56 stacked on the gate insulating layer 76 and the semiconductor layer 58, a source electrode (not shown), and a drain electrode 56 And a protective layer (insulating layer) 86 laminated on the source electrode. Both the gate insulating layer 76 and the protective layer 86 are made of silicon nitride (SiN).

  The gate electrode 52 ′ has a two-layer structure of a main wiring layer 70 made of Al and a barrier layer 72 ′ made of Ti or TiN formed on the main wiring layer 70. The semiconductor layer 58 includes an intrinsic semiconductor layer 77 and an ohmic contact layer 78 on the intrinsic semiconductor layer 77. The drain electrode 56 has a three-layer structure in which a main wiring layer 80 made of Al is sandwiched between an upper barrier layer 82 and a lower barrier layer 83 both made of molybdenum nitride (MoN).

  When manufacturing the TFT 32 ′ having such a configuration, the barrier layer 72 ′ is formed by patterning Ti or TiN laminated by a sputtering method by a photolithography method. At this time, the side surface of the barrier layer 72 ′ is a substrate. It becomes a steep surface that is nearly perpendicular to the surface. When the side surface of the barrier layer 72 ′ is steep, when the gate insulating layer 76 is stacked on the barrier layer 72 ′ by a plasma enhanced chemical vapor deposition (plasma CVD) method, the gate is formed by a step at the end of the barrier layer 72 ′. There is a problem in that the insulating layer 76 has a non-uniform film quality and the withstand voltage decreases. More specifically, the material or density of the gate insulating layer 76 becomes discontinuous at the position indicated by the broken line 87 in FIG. There is also a problem that cracks are likely to occur at the position indicated by the broken line 87, starting from the end of the barrier layer 72 '. If a crack occurs in the gate insulating layer 76, not only the dielectric breakdown voltage is lowered, but also the main wiring layer 70 is easily eroded by the penetration of the chemical used in the subsequent process, and the quality of the device is remarkably lowered.

  In addition, when the above-described multi-layered electric wiring is applied to a scanning line (gate bus line), a signal line (data bus line), or a source electrode or drain electrode of a TFT, for the reasons described above, an insulating property is provided. There is a risk of lowering the device quality.

  An object of the present invention is to provide a high-quality TFT substrate provided with an insulating layer having a high insulating property on an electric wiring having a high electric conductivity.

  The TFT substrate according to the present invention includes a TFT having a gate electrode, a source electrode, and a drain electrode, a scanning line electrically connected to the gate electrode, a signal line electrically connected to the source electrode, and the gate. A first insulating layer formed on the electrode and the scan line; and a second insulating layer formed on the source electrode, the drain electrode, and the signal line, the gate electrode, the source At least one of the electrode, the drain electrode, the scanning line, and the signal line has a main wiring layer and a barrier layer formed on the main wiring layer, and the main wiring layer is made of aluminum (Al ) And copper (Cu), a second metal selected from the group consisting of titanium (Ti) and molybdenum (Mo), wherein at least a part of the barrier layer is formed from a first metal selected from the group consisting of copper (Cu). Of a nitride, oxynitride rate in the vicinity of the lower surface in contact with the main wiring layer of the barrier layer is lower than the nitriding ratio in the vicinity of the upper surface of the barrier layer.

  In one embodiment, the barrier layer includes a first barrier layer in contact with the main wiring layer, and a second barrier layer formed on the first barrier layer, and the first barrier layer is the second metal. The second barrier layer is made of a nitride of the second metal.

  In one embodiment, the nitridation rate of the second barrier layer is 0.5% or more.

  In one embodiment, the barrier layer includes a first barrier layer in contact with the main wiring layer and a second barrier layer formed on the first barrier layer, and the first barrier layer and the second barrier layer. However, each of them is made of a nitride of the second metal, and the nitridation rate of the second barrier layer is higher than the nitridation rate of the first barrier layer.

  In one embodiment, the nitridation rate of the first barrier layer is 0.5% or more, and the nitridation rate of the second barrier layer is 3.0% or less.

  In one embodiment, the barrier layer is formed of a nitride of the second metal, and the nitridation rate of the barrier layer increases from the lower surface contacting the main wiring layer to the upper surface of the barrier layer. .

  In one embodiment, the difference between the nitridation rate of the portion forming the lower surface of the barrier layer and the nitridation rate of the portion forming the upper surface is 0.5% or more.

  In one embodiment, an average inclination angle of the side surface of the barrier layer with respect to the substrate surface is 80 degrees or less.

  A liquid crystal display device according to the present invention includes the above TFT substrate and a counter substrate facing the TFT substrate with a liquid crystal layer interposed therebetween.

A TFT substrate manufacturing method according to the present invention includes a TFT having a gate electrode, a source electrode, and a drain electrode, a scanning line electrically connected to the gate electrode, and a signal line electrically connected to the source electrode. , And at least one of the gate electrode, the source electrode, the drain electrode, the scanning line, and the signal line has a main wiring layer and a barrier layer formed on the main wiring layer A method for manufacturing a substrate, wherein the main wiring layer is formed by sputtering using a first metal selected from the group consisting of aluminum and copper as a target material, and the barrier layer is made of titanium and molybdenum. A second step of forming by sputtering using a second metal selected from the group consisting of a target material, and the step in the second step. In at least some Ttaringu, sputtering gas is used containing nitrogen (N _2), nitride ratio close lower layer portion to the main wiring layer is lower than the nitriding rate of the upper portion above said lower portion Thus, the barrier layer is formed.

  In one embodiment, the barrier layer includes a first barrier layer in contact with the main wiring layer and a second barrier layer formed on the first barrier layer, and the second step includes the second metal. Forming the first barrier layer by sputtering using a target material, and forming the second barrier layer by sputtering using the second metal as a target material and a gas containing nitrogen as a sputtering gas. Including.

  In one embodiment, the nitrogen flow rate ratio of the sputtering gas is 15% or more.

  In one embodiment, the barrier layer includes a first barrier layer in contact with the main wiring layer and a second barrier layer formed on the first barrier layer, and the second step includes the second metal. And forming the first barrier layer and the second barrier layer by sputtering using a nitrogen-containing gas as a sputtering gas, and a nitrogen flow ratio of the sputtering gas used for forming the second barrier layer Is higher than the nitrogen flow ratio of the sputtering gas used to form the first barrier layer.

  In one embodiment, the nitrogen flow ratio of the sputtering gas used for forming the first barrier layer is 15% or more, and the nitrogen flow ratio of the sputtering gas used for forming the second barrier layer is 60% or less. .

  In one embodiment, in the second step, the barrier layer is formed by sputtering using the second metal as a target material and a gas containing nitrogen as a sputtering gas, and a nitrogen flow ratio of the sputtering gas is set to the sputtering gas. As the process proceeds, it becomes higher.

  In one embodiment, the difference between the nitrogen flow rate ratio of the sputtering gas at the start of the sputtering and the nitrogen flow rate ratio of the sputtering gas at the end of the sputtering is 15% or more.

  In one embodiment, after the second step, a step of forming a resist layer on the gate electrode and the scanning line, or on the source electrode, the drain electrode, and the signal line, and the resist A step of patterning a layer by photolithography, and a step of etching the main wiring layer and the barrier layer through the patterned resist layer. An inclined surface having an average inclination angle of 80 degrees or less is formed.

  In one embodiment, in the step of performing the etching process, a plurality of etching processes with different etching conditions are performed.

  According to the present invention, since the side surface of the electrical wiring of the TFT substrate can be inclined with respect to the substrate surface, the material or density of the insulating layer laminated on the electrical wiring can be discontinuous. In addition, cracks in the insulating layer can be prevented. Accordingly, it is possible to provide a highly reliable TFT substrate and liquid crystal display device with excellent insulation.

  Hereinafter, a configuration of a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings. However, the present invention is not limited to the embodiment described below.

(Embodiment 1)
FIG. 1 schematically shows the structure of the liquid crystal display device 100 according to the first embodiment of the present invention, FIG. 2 shows the circuit configuration of the TFT substrate 10 of the liquid crystal display device 100, and FIG. 3 shows one pixel in the TFT substrate 10. Each of the 30 configurations is schematically shown.

  As shown in FIG. 1, the liquid crystal display device 100 includes a TFT substrate 10 and a counter substrate 12 that face each other with a liquid crystal layer interposed therebetween, and polarizing plates 20 attached to the outer surfaces of the TFT substrate 10 and the counter substrate 12, respectively. 22 and a backlight unit 24 that emits display light.

  As shown in FIG. 2, a plurality of scanning lines (gate bus lines) 34 and a plurality of signal lines (data bus lines) 36 are arranged on the TFT substrate 10 so as to be orthogonal to each other. A TFT 32 is formed for each pixel 30 in the vicinity of the intersection of the signal line 36 and the signal line 36. The pixel 30 is defined as a region separated by two adjacent scanning lines 34 and two adjacent signal lines 36, and each pixel 30 is made of ITO (Indium Tin Oxide), and is electrically connected to the drain electrode of the TFT 32. Connected pixel electrodes 38 are arranged. A storage capacitor line (also called a storage capacitor line or Cs line) 40 extends in parallel with the scanning line 34 between two adjacent scanning lines 34.

  As shown in FIG. 1, the scanning line 34 and the signal line 36 are connected to the scanning line driving circuit 14 and the signal line driving circuit 16, respectively. The scanning line 34 is supplied with a scanning signal for switching on / off of the TFT 32 from the scanning line driving circuit 14 according to the control by the control circuit 18, and the signal line 36 is driven by the signal line according to the control by the control circuit 18. A display signal (voltage applied to the pixel electrode 38) is supplied from the circuit 16.

  As shown in FIG. 3, the TFT 32 includes a gate electrode (gate metal layer) 52 electrically connected to the scanning line 34, a semiconductor layer 58 formed on the gate electrode 52, and a semiconductor layer 58. A source electrode (source metal layer) 54 and a drain electrode (drain metal layer) 56 are formed. The source electrode 54 is electrically connected to the signal line 36, and the drain electrode 56 is electrically connected to the pixel electrode 38 through a contact hole 62 formed in the insulating layer.

  On the auxiliary capacitance line 40, an auxiliary capacitance electrode (also called a storage capacitance electrode or Cs electrode) 60 is formed with an insulating layer interposed therebetween. The auxiliary capacitance electrode 60 is electrically connected to the auxiliary capacitance 40 through a contact hole 64 formed in the insulating layer, and the auxiliary capacitance electrode 60, the pixel electrode 38, and a dielectric material sandwiched between them. As a result, an auxiliary capacitor (Cs) is formed.

  Next, the laminated structure of the TFT 32 will be described in more detail with reference to FIG.

  FIG. 4 is a diagram schematically showing a cross section of a portion of the TFT 32 indicated by A-A ′ in FIG. 3. As shown in this figure, the TFT 32 includes a gate electrode 52 formed on the glass substrate 50, a gate insulating layer (first insulating layer) 76 stacked on the gate electrode 52, and a gate insulating layer 76. The semiconductor layer 58 formed thereon, the drain electrode 56 and the source electrode 54 formed on the gate insulating layer 76 and the semiconductor layer 58, and a protective layer (first layer) stacked on the drain electrode 56 and the source electrode 54. 2 insulating layers) 86. Both the gate insulating layer 76 and the protective layer 86 are made of silicon nitride (SiN) and have thicknesses of, for example, 350 nm and 330 nm, respectively.

  The gate electrode 52 has a multilayer structure including a main wiring layer 70 made of aluminum (Al) and a barrier layer 72 formed on the main wiring layer 70. The main wiring layer 70 has a thickness of, for example, 150 nm. The main wiring layer 70 may be formed of copper (Cu). The barrier layer 72 includes a first barrier layer 74 made of titanium (Ti) and a second barrier layer 75 made of titanium nitride (TiN) formed on the first barrier layer 74. The thicknesses of the first barrier layer 74 and the second barrier layer 75 are, for example, 90 nm and 20 nm, respectively. The first barrier layer 74 may be formed of molybdenum (Mo), and the second barrier layer 75 may be formed of molybdenum (Mo) nitride.

  The second barrier layer 75 preferably has a nitridation ratio (a ratio of N atoms in TiN) of 0.5% or more. Since the first barrier layer 74 is made of Ti, its nitridation rate is 0%. Therefore, the nitriding rate in the vicinity of the lower surface of the barrier layer 72 in contact with the main wiring layer 70 (that is, the nitriding rate of the first barrier layer 74) is lower than the nitriding rate in the vicinity of the upper surface of the barrier layer 72.

  Note that the first barrier layer 74 can also be formed of TiN. In that case, the first barrier layer 74 is laminated so that the nitridation rate of the second barrier layer 75 is lower than that of the second barrier layer 75. The preferred nitridation rate of the first barrier layer 74 is 0.5% or more, and the preferred nitridation rate of the second barrier layer 75 is 3.0% or less.

  The side surfaces of the barrier layer 72 are inclined at an average of 65 degrees with respect to the surface of the glass substrate 50. The average inclination angle of the side surface of the barrier layer 72 is preferably 80 degrees or less.

The semiconductor layer 58 includes an intrinsic semiconductor layer 77 made of intrinsic amorphous silicon and an ohmic contact layer 78 made of n ⁺ amorphous silicon formed on the intrinsic semiconductor layer 77. The thicknesses of the intrinsic semiconductor layer 77 and the ohmic contact layer 78 are, for example, 120 nm and 30 nm, respectively.

  The drain electrode 56 has a three-layer structure in which a main wiring layer 80 made of Al is sandwiched between an upper barrier layer 82 and a lower barrier layer 83 both made of molybdenum nitride (MoN). The thicknesses of the lower barrier layer 83, the main wiring layer 80, and the upper barrier layer 82 are, for example, 50 nm, 100 nm, and 40 nm, respectively.

  The scanning line 34 shown in FIG. 3 may be formed in the same structure as the gate electrode 52, and the structure of the gate electrode 52 may be employed for the main wiring layer 80 and the upper barrier layer 82 of the drain electrode 56. Further, the signal line 36 and the source electrode 54 can be formed in the same structure as the drain electrode 56.

  Next, a manufacturing method of the TFT substrate 10 will be described with reference to FIG. 5A to 5D show a method for manufacturing the gate electrode 52 in the TFT substrate 10.

First, as shown in FIG. 5A, an Al layer 70a having a thickness of 150 nm is laminated on the upper surface of the glass substrate 50 by sputtering. Next, a Ti layer 74a having a thickness of 90 nm is stacked on the stacked Al layer 70a by sputtering, and a TiN layer 75a having a thickness of 20 nm is stacked thereon by reactive sputtering using N ₂ gas. The Ti layer 74a is laminated by sputtering using Ti as a target material and argon (Ar) gas as a sputtering gas, and the TiN layer 75a uses Ti as a target material and uses argon (Ar) gas and N ₂ gas. Laminated by sputtering. The flow ratio of Ar gas and N ₂ gas is, for example, 7: 3. Note that Mo may be used as the target material, the Ti layer 74a may be a Mo layer, and the TiN layer 75a may be a molybdenum nitride (MoN) layer. When the TiN layer 75a is stacked, the nitrogen flow ratio of the sputtering gas is preferably 15% or more.

  The Ti layer 74a may be formed of TiN. In this case, a sputtering gas having a nitrogen flow ratio lower than the nitrogen flow ratio of the sputtering gas used for forming the TiN layer 75a (TiN upper layer) is used for forming the layer (TiN lower layer). The nitrogen flow rate ratio of the sputtering gas used for forming the TiN lower layer is preferably 60% or less.

  Thereafter, a resist film 90 is formed on the TiN layer 75a by a spin coating method, and the resist film 90 is patterned by using a photolithography method, whereby the stacked structure shown in FIG. 5B is obtained.

Next, this stacked structure is dry-etched from above to obtain the structure shown in FIG. As this etching gas, for example, a mixed gas of chlorine (Cl ₂ ) and boron trichloride (BCl ₃ ) is used. The etching time is, for example, 130 seconds. Next, etching using Cl ₂ gas is performed for 40 seconds, for example, and the structure shown in FIG. 5D is obtained. Thereafter, the resist film 90 is removed by a resist stripping solution, and the gate electrode 52 having a three-layer structure including the main wiring layer 70, the first barrier layer 74, and the second barrier layer 75 is completed.

  By using the above etching method, a side surface inclined with respect to the substrate surface can be formed in the gate electrode 52. In the step of forming the gate electrode 52, the scanning line 34 in the TFT substrate 10 is simultaneously formed by the same method.

  Next, as shown in FIGS. 3 and 4, a gate insulating layer 76 made of SiN having a thickness of 350 nm is stacked on the entire surface of the substrate by plasma CVD. At this time, since the side surface of the gate electrode 52 (particularly the barrier layer 72) is inclined and there is no steep slope or step under the gate insulating layer 76, the gate insulating layer is not changed significantly. 76 can be stacked. As a result, generation of cracks in the gate insulating layer 76 can be eliminated, and a decrease in dielectric strength can also be suppressed.

Thereafter, 120 nm of amorphous silicon and 30 nm of n ⁺ amorphous silicon are stacked on the entire surface of the substrate by plasma CVD. Next, a photoresist film is formed on the n ⁺ amorphous silicon by spin coating. Thereafter, the photoresist film is patterned by photolithography to form a photoresist mask for patterning n ⁺ amorphous silicon. Next, after etching the n ⁺ amorphous silicon into a predetermined shape using a dry etching method, the photoresist mask is removed using a resist stripping solution.

  Next, a 50 nm thick MoN layer, a 100 nm thick Al layer, and a 40 nm thick MoN layer are sequentially formed by sputtering, and a photoresist film is formed on the entire surface, and then these layers are formed. The drain electrode 56 including the lower barrier layer 83, the main wiring layer 80, and the upper barrier layer 82 is formed by patterning by photolithography. At this time, for example, an aqueous solution in which 67.3 wt% phosphoric acid, 5.2 wt% nitric acid, and 10 wt% acetic acid are mixed is used as the etchant. In this step, the source electrode 54 and the signal line 36 are also formed at the same time.

Thereafter, n ⁺ amorphous silicon is etched by dry etching using a fluorine-based gas and a chlorine-based gas, and the amorphous silicon is further half-etched to complete the ohmic contact layer 78 and the intrinsic semiconductor layer 77. Thereafter, the photoresist mask is removed with a resist stripping solution.

  Next, a protective layer 86 is obtained by stacking SiN to a thickness of 330 nm by plasma CVD. Thereafter, a contact hole 62 reaching the drain electrode 56 is formed in the protective layer 86 using a photolithography method. Next, ITO is laminated to a thickness of 70 nm by sputtering, and the pixel electrode 38 is formed using photolithography, thereby completing the TFT substrate 10.

(Embodiment 2)
FIG. 6 is a cross-sectional view showing a laminated structure of TFTs 32 of the TFT substrate 10 in the liquid crystal display device 100 according to the second embodiment of the present invention. The configuration of the liquid crystal display device 100 of the second embodiment, the structure of the TFT substrate 10 and the structure of the pixel 30 are the same as those of the first embodiment shown in FIGS. .

  FIG. 6 is a diagram schematically showing a cross section of a portion indicated by A-A ′ in FIG. 3 of the TFT 32 in the second embodiment. As shown in this figure, the TFT 32 includes a gate electrode 52 formed on the glass substrate 50, a gate insulating layer (first insulating layer) 76 stacked on the gate electrode 52, and a gate insulating layer 76. The semiconductor layer 58 formed thereon, the drain electrode 56 and the source electrode 54 formed on the gate insulating layer 76 and the semiconductor layer 58, and a protective layer (first layer) stacked on the drain electrode 56 and the source electrode 54. 2 insulating layers) 86. Both the gate insulating layer 76 and the protective layer 86 are made of SiN and have thicknesses of, for example, 350 nm and 330 nm, respectively.

  The gate electrode 52 has a multilayer structure including a main wiring layer 70 made of Al and a barrier layer 72 formed on the main wiring layer 70. The main wiring layer 70 has a thickness of, for example, 150 nm. The main wiring layer 70 may be formed of Cu. The barrier layer 72 is made of TiN and has a thickness of 90 nm, for example. The barrier layer 72 may be formed of MoN. The nitridation rate of the barrier layer 72 increases from the lower surface in contact with the main wiring layer 70 of the barrier layer 72 toward the upper surface, and the nitridation rate of the material forming the lower surface of the barrier layer 72 and the portion forming the upper surface The difference from the nitriding rate of the material is 0.5% or more. The side surface of the barrier layer 72 is inclined 65 degrees with respect to the surface of the glass substrate 50. The inclination angle of the side surface of the barrier layer 72 is preferably 80 degrees or less.

  Since the structures and materials of the gate insulating layer 76, the semiconductor layer 58, the drain electrode 56, the source electrode 54, and the protective layer 86 stacked on the gate electrode 52 are the same as those in Embodiment 1, the description thereof is omitted. Is omitted.

  The scanning line 34 may be formed in the same structure as the gate electrode 52 of the second embodiment, and the structure of the gate electrode 52 may be employed for the main wiring layer 80 and the upper barrier layer 82 of the drain electrode 56. The signal line 36 and the source electrode 54 can be formed in the same structure as the drain electrode 56.

  Next, a manufacturing method of the TFT substrate 10 will be described with reference to FIG. 7A to 7D show a method for manufacturing the gate electrode 52 in the TFT substrate 10.

  First, as shown in FIG. 7A, an Al layer 70a having a thickness of 150 nm is laminated on the upper surface of the glass substrate 50 by sputtering. Next, a TiN layer 72a having a thickness of 90 nm is laminated on the laminated Al layer 70a by sputtering.

The TiN layer 72a is laminated by sputtering using Ti gas as a target material and Ar gas and N ₂ gas. At this time, the nitrogen flow rate ratio of the sputtering gas is continuously increased as the sputtering process proceeds. Sputtering is performed. The flow rate ratio between Ar gas and N ₂ gas is, for example, 10: 0 at the start of sputtering and 6: 4 at the end of sputtering.

  The TiN layer 72a may be a MoN layer using Mo as the target material. The difference between the nitrogen flow ratio of the sputtering gas at the start of sputtering and the nitrogen flow ratio of the sputtering gas at the end of sputtering is preferably 15% or more. By performing a plurality of etching processes with different etching conditions, the nitriding rate of the TiN layer 72a may be increased continuously or discontinuously from the lower surface to the upper surface. Further, by forming a Ti layer or a TiN layer and then performing a nitrogen plasma treatment from the upper surface thereof, it is possible to obtain a TiN layer 72a having an upper nitriding rate higher than a lower nitriding rate.

  Thereafter, a resist film 90 is formed on the TiN layer 72a by a spin coating method, and the resist film 90 is patterned by using a photolithography method, whereby the stacked structure shown in FIG. 7B is obtained.

Next, this stacked structure is dry-etched from above to obtain the structure shown in FIG. As this etching gas, for example, a mixed gas of Cl ₂ and BCl ₃ is used. The etching time is, for example, 130 seconds. Next, etching using Cl ₂ gas is performed for 40 seconds, for example, and the structure shown in FIG. 7D is obtained. Thereafter, the resist film 90 is removed by a resist stripping solution, and the two-layered gate electrode 52 including the main wiring layer 70 and the barrier layer 72 is completed.

  By using the above etching method, a side surface inclined with respect to the substrate surface can be formed in the gate electrode 52. In the step of forming the gate electrode 52, the scanning line 54 in the TFT substrate 10 is simultaneously formed by the same method.

  Next, a gate insulating layer 76 made of SiN having a thickness of 350 nm is laminated on the entire surface of the substrate by plasma CVD. At this time, since the side surface of the gate electrode 52 (particularly the barrier layer 72) is inclined and there is no steep slope or step under the gate insulating layer 76, the gate insulating layer is not changed significantly. 76 can be stacked. As a result, generation of cracks in the gate insulating layer 76 can be eliminated, and a decrease in dielectric strength can also be suppressed.

Thereafter, 120 nm of amorphous silicon and 30 nm of n ⁺ amorphous silicon are stacked on the entire surface of the substrate by plasma CVD. Next, a photoresist film is formed on the n ⁺ amorphous silicon by spin coating. Thereafter, the photoresist film is patterned by photolithography to form a photoresist mask for patterning n ⁺ amorphous silicon. Next, after etching the n ⁺ amorphous silicon into a predetermined shape using a dry etching method, the photoresist mask is removed using a resist stripping solution.

  Next, a 50 nm thick MoN layer, a 100 nm thick Al layer, and a 40 nm thick MoN layer are sequentially formed by sputtering, and a photoresist film is formed on the entire surface, and then these layers are formed. The drain electrode 56 including the lower barrier layer 83, the main wiring layer 80, and the upper barrier layer 82 is formed by patterning by photolithography. At this time, for example, an aqueous solution in which 67.3 wt% phosphoric acid, 5.2 wt% nitric acid, and 10 wt% acetic acid are mixed is used as the etchant. In this step, the source electrode 54 and the signal line 36 are also formed at the same time.

Thereafter, n ⁺ amorphous silicon is etched by dry etching using a fluorine-based gas and a chlorine-based gas, and the amorphous silicon is further half-etched to complete the ohmic contact layer 78 and the intrinsic semiconductor layer 77. Thereafter, the photoresist mask is removed with a resist stripping solution.

  Next, a protective layer 86 is obtained by stacking SiN to a thickness of 330 nm by plasma CVD. Thereafter, a contact hole 62 reaching the drain electrode 56 is formed in the protective layer 86 using a photolithography method. Next, ITO is laminated to a thickness of 70 nm by sputtering, and the pixel electrode 38 is formed using photolithography, thereby completing the TFT substrate 10.

  FIG. 8A is a diagram illustrating a side surface of a TFT gate electrode 52 according to the present invention (corresponding to the first embodiment), and FIG. 8B is a diagram illustrating a side surface of a TFT gate electrode 52 ′ according to a reference example. FIG.

  The gate electrode 52 shown in FIG. 8A includes a 120 nm Al layer, a first TiN layer having a thickness of 80 nm obtained using a sputtering gas having a nitrogen flow ratio of 15%, and a sputter having a nitrogen flow ratio of 45%. A layered structure composed of a second TiN layer having a thickness of 10 nm obtained using gas is obtained by dry etching from above, and the main wiring layer 70 is formed from the Al layer, and the first barrier is formed from the first TiN layer. The layer 74 is formed from the second TiN layer to the second barrier layer 75, respectively.

In the dry etching process, the laminated structure is etched to the glass interface using a mixed gas of chlorine (Cl ₂ ) and boron trichloride (BCl ₃ ), for example. The etching time is, for example, 130 seconds. Next, the side surface of the laminated structure is etched using Cl ₂ gas. The etching time is 40 seconds, for example. At this time, since the etching rate of TiN having a high N concentration is higher than that of TiN having a low N concentration, the gate electrode 52 having the structure shown in FIG. 8A is obtained.

  The gate electrode 52 ′ shown in FIG. 8B includes a main wiring layer 70 made of Al having a thickness of 120 nm and a barrier layer 72 ′ made of Ti having a thickness of 90 nm.

  8A and 8B, the side surface of the gate electrode 52 according to the present invention has a gentler slope than the side surface of the gate electrode 52 ′ according to the reference example. There are relatively few irregularities.

  FIG. 9A is a diagram showing the side surface of the gate electrode 52 of the second TFT according to the present invention, and FIG. 9B is a diagram showing the side surface of the gate electrode 52 ′ of the second TFT according to the reference example. It is.

  The gate electrode 52 shown in FIG. 9A has an Al layer with a thickness of 100 nm, a first TiN layer with a thickness of 10 nm obtained using a sputtering gas with a nitrogen flow ratio of 30%, and a nitrogen flow ratio of 40%. With respect to a laminated structure composed of a second TiN layer having a thickness of 70 nm obtained by using a sputtering gas and a third TiN layer having a thickness of 10 nm obtained by using a sputtering gas having a nitrogen flow ratio of 60%, The main wiring layer 70 is formed from the Al layer, and the barrier layer 72 is formed from the first to third TiN layers.

In the dry etching process, the laminated structure is etched to the glass interface using a mixed gas of chlorine (Cl ₂ ) and boron trichloride (BCl ₃ ), for example. The etching time is, for example, 100 seconds. Further, the side surface of the laminated structure is over-etched (additional etching) using the same mixed gas. The etching time is, for example, 30 seconds. At this time, the etching rate increases in the order of the Al layer, the first TiN layer, the second TiN layer, and the third TiN layer (Al layer <first TiN layer <second TiN layer <third TiN layer), and the gate shown in FIG. 9A. An electrode 52 is obtained.

  The gate electrode 52 ′ shown in FIG. 9B includes a main wiring layer 70 made of Al having a thickness of 100 nm and a barrier layer 72 ′ made of Ti having a thickness of 90 nm.

  As can be seen by comparing FIGS. 9A and 9B, the side surface of the gate electrode 52 according to the present invention is formed more gently than the side surface of the gate electrode 52 ′ according to the reference example. There are relatively few irregularities.

  According to the present invention, the side surface of the electrical wiring such as the gate electrode of the TFT substrate can be a slope inclined with respect to the substrate surface, and the slope can be a smooth surface with less unevenness. It is possible to prevent the material or density of the insulating layer laminated on the electric wiring from becoming discontinuous, and to prevent the occurrence of cracks in the insulating layer. Accordingly, it is possible to provide a high-quality TFT substrate having a high withstand voltage.

  The present invention is suitably used for electrical equipment such as a liquid crystal display device having a TFT substrate.

It is the perspective view which represented typically the structure of the liquid crystal display device 100 of Embodiment 1 by this invention. 3 is a plan view schematically showing a circuit configuration of a TFT substrate 10 in the liquid crystal display device 100 of Embodiment 1. FIG. 3 is a plan view schematically showing the configuration of one pixel 30 in the TFT substrate 10 of Embodiment 1. FIG. 2 is a cross-sectional view schematically illustrating a configuration of a TFT in the TFT substrate 10 of Embodiment 1. FIG. (A)-(d) is sectional drawing which represented the manufacturing method of TFT of Embodiment 1 typically. FIG. 5 is a cross-sectional view schematically showing a configuration of a TFT in a TFT substrate 10 of Embodiment 2. (A)-(d) is sectional drawing which represented the manufacturing method of TFT of Embodiment 2 typically. (A) is the figure showing the side surface of the gate electrode of TFT by this invention, (b) is the figure showing the side surface of the gate electrode of TFT by a reference example. (A) is the figure showing the side surface of the gate electrode of the other TFT by this invention, (b) is the figure showing the side surface of the gate electrode of the other TFT by a reference example. It is sectional drawing which represented typically the structure of TFT of a reference example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 TFT substrate 12 Opposite substrate 14 Scan line drive circuit 16 Signal line drive circuit 18 Control circuit 20, 22 Polarizing plate 24 Backlight unit 30 Pixel 32, 32 'TFT
34 Scan lines (gate bus lines)
36 Signal line (source bus line)
38 pixel electrode 40 auxiliary capacity line (storage capacity line, Cs line)
50 Glass substrate 52, 52 'Gate electrode (gate metal layer)
54 Source electrode (source metal layer)
56 Drain electrode (drain metal layer)
58 Semiconductor layer 60 Auxiliary capacitance electrode (storage capacitance electrode, Cs electrode)
62, 64 Contact hole 70 Main wiring layer 72, 72 ′ Barrier layer 74 First barrier layer 75 Second barrier layer 76 Gate insulating layer 77 Intrinsic semiconductor layer 78 Ohmic contact layer 80 Main wiring layer 82 Upper barrier layer 83 Lower barrier layer 86 Insulating layer (protective layer)
90 resist layer (mask resist)
100, 100 'liquid crystal display device

Claims (18)

A TFT having a gate electrode, a source electrode, and a drain electrode;
A scanning line electrically connected to the gate electrode;
A signal line electrically connected to the source electrode;
A first insulating layer formed on the gate electrode and the scanning line;
A second insulating layer formed on the source electrode, the drain electrode, and the signal line,
At least one of the gate electrode, the source electrode, the drain electrode, the scanning line, and the signal line has a main wiring layer and a barrier layer formed on the main wiring layer,
The main wiring layer is formed of a first metal selected from the group consisting of aluminum (Al) and copper (Cu);
At least a part of the barrier layer is made of a nitride of a second metal selected from the group consisting of titanium (Ti) and molybdenum (Mo),
A TFT substrate having a nitridation rate in the vicinity of the lower surface of the barrier layer in contact with the main wiring layer lower than that in the vicinity of the upper surface of the barrier layer. The barrier layer includes a first barrier layer in contact with the main wiring layer, and a second barrier layer formed on the first barrier layer,
The first barrier layer is formed of the second metal;
2. The TFT substrate according to claim 1, wherein the second barrier layer is formed of a nitride of the second metal.   The TFT substrate according to claim 2, wherein the nitridation ratio of the second barrier layer is 0.5% or more. The barrier layer includes a first barrier layer in contact with the main wiring layer, and a second barrier layer formed on the first barrier layer,
The first barrier layer and the second barrier layer are each formed of a nitride of the second metal;
The TFT substrate according to claim 1, wherein a nitridation rate of the second barrier layer is higher than a nitridation rate of the first barrier layer.   The TFT substrate according to claim 4, wherein the nitridation rate of the first barrier layer is 0.5% or more and the nitridation rate of the second barrier layer is 3.0% or less. The barrier layer is formed of a nitride of the second metal;
2. The TFT substrate according to claim 1, wherein a nitridation ratio of the barrier layer increases from a lower surface in contact with the main wiring layer of the barrier layer toward an upper surface.   The TFT substrate according to claim 6, wherein a difference between a nitridation ratio of a portion forming the lower surface of the barrier layer and a nitridation ratio of a portion forming the upper surface is 0.5% or more.   The TFT substrate according to claim 1, wherein an average inclination angle of a side surface of the barrier layer with respect to the substrate surface is 80 degrees or less. A TFT substrate according to any one of claims 1 to 8,
And a counter substrate facing the TFT substrate across a liquid crystal layer. A TFT having a gate electrode, a source electrode, and a drain electrode;
A scanning line electrically connected to the gate electrode;
A signal line electrically connected to the source electrode,
A method for manufacturing a TFT substrate, wherein at least one of the gate electrode, the source electrode, the drain electrode, the scanning line, and the signal line includes a main wiring layer and a barrier layer formed on the main wiring layer. Because
A first step of forming the main wiring layer by sputtering using a first metal selected from the group consisting of aluminum and copper as a target material;
A second step of forming the barrier layer by sputtering using a second metal selected from the group consisting of titanium and molybdenum as a target material,
In at least a part of the sputtering in the second step, a sputtering gas containing nitrogen (N ₂ ) is used, and the nitriding rate of the lower layer portion close to the main wiring layer is higher than that of the upper layer portion located on the lower layer portion. A method for manufacturing a TFT substrate, wherein the barrier layer is formed to be lower than a nitriding rate. The barrier layer includes a first barrier layer in contact with the main wiring layer; and a second barrier layer formed on the first barrier layer;
The second step includes the step of forming the first barrier layer by sputtering using the second metal as a target material, and the sputtering by using a gas containing nitrogen as a sputtering gas using the second metal as a target material. The manufacturing method of Claim 10 including the process of forming a 2nd barrier layer.   The manufacturing method according to claim 11, wherein a nitrogen flow ratio of the sputtering gas is 15% or more. The barrier layer includes a first barrier layer in contact with the main wiring layer, and a second barrier layer formed on the first barrier layer,
The second step includes a step of forming the first barrier layer and the second barrier layer by sputtering using the second metal as a target material and a gas containing nitrogen as a sputtering gas,
The manufacturing method according to claim 10, wherein a nitrogen flow ratio of a sputtering gas used for forming the second barrier layer is higher than a nitrogen flow ratio of a sputtering gas used for forming the first barrier layer.   The nitrogen flow rate ratio of the sputtering gas used for forming the first barrier layer is 15% or more, and the nitrogen flow rate ratio of the sputtering gas used for forming the second barrier layer is 60% or less. The manufacturing method as described. In the second step, the barrier layer is formed by sputtering using the second metal as a target material and a gas containing nitrogen as a sputtering gas,
The manufacturing method according to claim 10, wherein a nitrogen flow ratio of the sputtering gas increases as the sputtering process proceeds.   The manufacturing method according to claim 15, wherein a difference between a nitrogen flow ratio of the sputtering gas at the start of the sputtering and a nitrogen flow ratio of the sputtering gas at the end of the sputtering is 15% or more. Furthermore, after the second step, forming a resist layer on the gate electrode and the scanning line, or on the source electrode, the drain electrode, and the signal line;
Patterning the resist layer by photolithography,
Etching the main wiring layer and the barrier layer through the patterned resist layer, and
The manufacturing method according to any one of claims 10 to 16, wherein an inclined surface having an average inclination angle of 80 degrees or less with respect to the substrate surface is formed in the barrier layer by the etching process.   The manufacturing method according to claim 17, wherein in the step of performing the etching process, a plurality of etching processes having different etching conditions are performed.

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