JP2009176784A - Method of manufacturing thin film epitaxial wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a thin film epitaxial wafer by simply suppressing and controlling auto-doping of impurities from a heavily doped underlying silicon wafer. <P>SOLUTION: On the major surface of an underlying silicon wafer to which arsenic, phosphorus or boron is added at a dopant concentration of 1×10<SP>19</SP>/cm<SP>3</SP>, a silicon epitaxial layer is grown by low pressure vapor phase epitaxy at a deposition temperature in the range of 1,000-1,100°C in a reactor of deposition gas containing SiH<SB>4</SB>gas under a pressure in the range of 1999.83 Pa (15 Torr)-2666.44 Pa (20 Torr). A single wafer vapor phase epitaxial growth system is employed in this vapor phase epitaxy, the underlying silicon wafer is brought into a state for rotating horizontally in a reaction chamber, and deposition gas is suitably made to flow down onto the major surface of an underlying silicon wafer from above. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a thin film epitaxial wafer, and more particularly, to a method for manufacturing a thin film epitaxial wafer that suppresses and controls autodoping of impurities from an underlying silicon wafer containing high concentration impurities.

  A silicon epitaxial wafer (hereinafter sometimes abbreviated as an epitaxial wafer) obtained by vapor-phase-growing a silicon epitaxial layer (hereinafter sometimes abbreviated as an epitaxial layer) on the main surface of an underlying silicon wafer as a substrate of an epitaxial layer is For example, it is used for manufacturing semiconductor devices in which Bipolar transistors, BiCMOS elements, power transistors, Schottky barrier elements and the like are manufactured. Depending on these semiconductor devices, a thin film epitaxial layer having an epitaxial layer thickness of, for example, 5 μm or less and a thickness variation within ± 1.0% within the wafer surface is required.

  However, in the vapor phase growth of a thin film epitaxial layer, generally, a particle (Crystal Originated Particle: COP) due to a so-called crystal is easily generated. This COP is caused by crystal lattice vacancies, and becomes a factor of reducing the manufacturing yield of semiconductor devices with higher performance. Therefore, a technique for suppressing the generation of COP in the thin film epitaxial layer has been proposed (see, for example, Patent Document 1).

  On the other hand, in a semiconductor device mounted with, for example, a low breakdown voltage power transistor or a semiconductor element using a Schottky barrier, a region doped with high-concentration arsenic (As), phosphorus (P), or boron (B) serves as a buried layer. It is locally provided on the main surface of the underlying silicon wafer. Alternatively, the entire underlying silicon wafer contains a high concentration of impurities (dopant) and has a low resistivity. Then, a thin film epitaxial layer having a low resistivity and a high resistivity is formed on the underlying silicon wafer having such a high concentration dopant.

  However, when vapor-phase-growing a high resistivity silicon epitaxial layer on the heavily doped underlying silicon wafer, the dopant diffuses out from the back surface or main surface of the underlying silicon wafer and is taken back into the thin film epitaxial layer. So-called impurity auto-doping is likely to occur. This auto-doping impairs the steepness of the resistivity profile (hereinafter also referred to as impurity profile) in the transition region between the main surface of the underlying silicon wafer and the epitaxial layer, or causes the resistivity of the epitaxial layer to fluctuate below a required value. . And it becomes a big factor which deteriorates the electrical property of a semiconductor device and reduces the manufacturing yield.

  Therefore, conventionally, in order to suppress autodoping from the back surface of the underlying silicon wafer when the epitaxial layer is vapor-phase grown, an insulating film such as a silicon oxide film or a polycrystalline silicon film is formed on the back surface of the underlying silicon wafer. The technique of coating the film has been taken. In addition, in order to suppress auto-doping from the main surface of the underlying silicon wafer during vapor phase growth of the epitaxial layer, supply of dopant gas is stopped at the initial stage of vapor phase growth and a non-doped cap layer is formed at a relatively low temperature. Then, a method is employed in which a desired epitaxial layer is vapor-phase grown (see, for example, Patent Document 2).

  Furthermore, a method of combining a method of coating the back surface of the underlying silicon wafer with the silicon oxide film for preventing autodoping and a method of forming a cap layer at the initial stage of the vapor phase growth has been proposed (for example, (See Patent Document 3). In the vapor phase growth of the epitaxial layer by this method, a well-known vertical (pancake type) or barrel (cylinder type) vapor phase growth apparatus is used. Then, the steepness of the impurity profile of the epitaxial layer, which is important for device characteristics, is improved as compared with the conventional case, and a thin film epitaxial layer is formed. However, this method necessitates the formation of the oxide film and the various cleaning and etching processes associated therewith, and the number of manufacturing steps of the silicon epitaxial wafer is increased, resulting in an increase in manufacturing cost.

As another method for suppressing autodoping, a method of reducing the pressure in the reaction vessel for vapor phase growth has been proposed (for example, see Patent Document 4). In this case, the dopant diffused outward from the back surface and the main surface of the underlying silicon wafer is less likely to be taken into the epitaxial layer because the amount per unit volume in the reaction vessel is reduced by the reduced pressure environment. In the vapor phase growth of an epitaxial layer disclosed in Patent Document 4, a single wafer type vapor phase growth apparatus in which a base silicon wafer rotates in a reaction vessel is used. Then, autodoping of arsenic and boron impurities is easily suppressed, and a steep impurity profile of the epitaxial layer is obtained.
Japanese Patent No. 3763631 JP-A-8-203831 JP 2005-150364 A JP-A-8-264458

By the way, in recent years, for example, in a semiconductor device having a low breakdown voltage power transistor, a Schottky barrier diode, etc., in a silicon epitaxial wafer, the steepness of the resistivity profile of the epitaxial layer, which is important for the device characteristics, and the high thickness of the epitaxial layer. There has been a strong demand for uniformity and cost reduction of epitaxial wafers. Here, in the semiconductor device such as the low breakdown voltage power transistor and the Schottky barrier diode, for example, the n-conductivity type epitaxial layer is a thin film having an effective thickness of about 1 to 4 μm, and has an aperture of 8 inches, for example. The in-plane variation in the epitaxial wafer is required to be about ± 0.00 several μm. The underlying silicon wafer has an resistivity of about 0.005 Ω · cm, and becomes an n ⁺ type silicon wafer doped with an extremely high concentration of arsenic impurity.

  However, in the silicon epitaxial wafer manufacturing methods disclosed so far including the above-mentioned patent documents, the steepness of the resistivity profile of the thin film epitaxial layer as described above, the high uniformity of the film thickness of the epitaxial layer, and the epitaxial wafer It is not possible to find a method that can reduce both costs.

  The present invention has been made in view of the above-described circumstances, and contains high-concentration impurities without forming an auto-dope-preventing film on the back surface of the underlying silicon wafer or forming a cap layer on the main surface of the underlying silicon wafer. An object of the present invention is to provide a method of manufacturing a thin film epitaxial wafer that can easily suppress and control the autodoping of impurities from an underlying silicon wafer. Furthermore, it aims at making the film thickness of a silicon epitaxial layer highly uniform and reducing the cost of a silicon epitaxial wafer easy.

In order to achieve the above object, a method for producing a thin film epitaxial wafer according to the present invention forms a silicon epitaxial layer on a main surface of an underlying silicon wafer to which a dopant having a concentration of 1 × 10 ¹⁹ / cm ³ or more is added. A method for producing a thin film epitaxial wafer, wherein the temperature of the underlying silicon wafer disposed in a reaction vessel is controlled within a range of 1000 to 1100 ° C., and the reaction vessel supplied with a film forming gas containing SiH ₄ gas A silicon epitaxial layer having the same conductivity type as that of the underlying silicon wafer and having a lower dopant concentration than that of the underlying silicon wafer on the main surface of the underlying silicon wafer by setting the pressure in the range of 1999.83 Pa to 2666.44 Pa. Vapor phase growth.

  In a preferred aspect of the invention, a single wafer vapor phase growth apparatus is used, and the base silicon wafer is horizontally rotated in the reaction vessel so that the main surface of the base silicon wafer is above the base silicon wafer. The silicon epitaxial layer is vapor-phase grown by flowing down the film forming gas.

  With the configuration of the present invention, autodoping of impurities from a base silicon wafer containing high-concentration impurities can be achieved without forming a coating for preventing autodoping on the backside of the base silicon wafer or forming a cap layer on the main surface of the base silicon wafer. A thin film epitaxial layer can be formed with simple suppression and control. Furthermore, it is possible to facilitate the uniform thickness of the epitaxial layer and the cost reduction of the silicon epitaxial wafer.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a reduced pressure vapor phase growth apparatus for explaining a method of manufacturing a thin film epitaxial wafer according to an embodiment of the present invention. FIG. 2 is a table showing a film formation condition map composed of film formation temperature and film formation pressure in the low pressure vapor phase growth of the epitaxial layer.

In the thin-film epitaxial wafer manufacturing method according to the present embodiment, a thin silicon epitaxial layer is formed on the main surface of the underlying silicon wafer to which arsenic, phosphorus, or boron is added in a dopant concentration of 1 × 10 ¹⁹ / cm ³ or more. Is formed by reduced pressure vapor phase growth. In this vapor phase growth, for example, a single wafer type reduced pressure vapor phase growth apparatus as shown in FIG. 1 is used. In this reduced pressure vapor phase growth apparatus, a rotating body unit 12 on which a base silicon wafer W is placed is placed in a chamber 11 which is a reaction vessel, and a gas rectifying plate 13 is opened above the rotating body unit 12. Yes. Here, the gas rectifying plate 13 has a large number of gas discharge ports 14. The rotating unit 12 includes a heater (not shown) that heats the underlying silicon wafer W to a required film forming temperature.

In the low-pressure vapor phase growth, the film forming gas 15 is supplied into the chamber 11 from the gas supply port 16, rectified through the gas discharge port 14 of the gas rectifying plate 13, and placed on the rotating body unit 12. It flows down toward the silicon wafer W. Here, the deposition gas 15 is, for example, a hydrogen (H ₂ ) carrier gas, a monosilane (SiH ₄ ) source gas, and a dopant such as phosphine (PH ₃ ), arsine (AsH ₃ ), or diborane (B ₂ H ₆ ). Composed of gas. At this time, the rotating body unit 12 rotates at a high speed, for example, indicated as the rotation direction R.

  The film-forming gas 15 flowing down hits the main surface of the underlying silicon wafer W, and then is rectified as a laminar flow in the horizontal direction along the main surface and flows from the central portion to the peripheral portion. At this time, on the main surface of the underlying silicon wafer W, the source gas and the dopant gas in the film-forming gas 15 are thermally reacted, and an epitaxial layer having a required resistivity is vapor-phase grown. The thermally decomposed film forming gas 15 passes through a gas discharge port 18 as exhaust gas 17 and is discharged out of the chamber 11 by an exhaust pump (not shown).

  In the low-pressure vapor phase growth, as shown in FIG. 2, the film forming temperature of the underlying silicon wafer W is controlled in the range of 1000 to 1100 ° C., and the pressure of the film forming gas 15 in the chamber 11 is set to 1999. It is important to set a range of 83 Pa (15 Torr) to 2666.44 Pa (20 Torr). In FIG. 2, a circle mark is attached at an appropriate film formation condition, and an x mark is attached at an inappropriate film formation condition.

Here, when the film forming temperature is lower than 1000 ° C., the details will be described later, but the steepness of the resistivity profile in the epitaxial layer is lowered due to auto-doping from the underlying silicon wafer W, which is inappropriate. On the other hand, when the film forming temperature exceeds 1100 ° C., the deterioration rate of various members in the chamber 11 under a reduced pressure is large, and discharge with the above-described heater is likely to occur, which is not practical. On the other hand, if the film forming pressure is less than 1999.83 Pa (15 Torr), the heater is likely to cause electric discharge, which is inappropriate. When the film forming pressure exceeds 2666.44 Pa (20 Torr), silicon deposition occurs due to thermal decomposition of SiH ₄ in the space in the chamber 11 in the low pressure vapor phase growth, and particles are generated, which is not practical.

  Furthermore, in the above-described reduced-pressure vapor phase growth of the epitaxial layer, autodoping from the underlying silicon wafer W can be easily suppressed within the range of the film formation temperature and film formation pressure indicated by the circles in FIG. It was found that the required resistivity profile can be freely controlled. This will be described with reference to FIG. 3 and FIG. Here, FIG. 3 shows an example of a SR (Spreading Resistance) value profile in the depth direction of the epitaxial wafer, and is a diagram for explaining a method of quantifying the degree of autodoping. FIG. 4 is a graph showing the relationship between the sagging rate of the SR value profile by autodoping and the film forming conditions.

  In FIG. 3, the horizontal axis represents the depth from the surface of the epitaxial layer, and the vertical axis represents the SR values of the epitaxial layer and the underlying silicon wafer in logarithmic representation. In an epitaxial wafer, the dopant concentration is greatly reduced from the underlying silicon wafer to the epitaxial layer. As shown in FIG. 3, in the transition region between the underlying silicon wafer and the epitaxial layer, a region in which the dopant concentration rapidly decreases and the SR value rapidly increases, and the dopant concentration gradually decreases and the SR value gradually increases. There is an area. The former is a region where high-concentration impurities of the underlying silicon wafer are solid-phase diffused in the epitaxial layer, and the latter is a region formed by the auto-doping.

Therefore, as shown in FIG. 3, the difference between the SR value of the underlying silicon wafer and the SR value of the surface region of the epitaxial layer is defined as length A ₀ , and the SR region profile curve shows the surface region of the epitaxial layer. A point where the length A _{0/10 is} lowered from the SR value is defined as a point P ₁ . Further, an extension of the profile of the SR value by solid-phase diffusion of the high concentration impurity is a point P ₂ the place crossing the SR value of the surface region of the epitaxial layer. Then, the depth from the surface of the epitaxial layer of the point _{P 1} and _{P 2} and _L 1, _{L 2} respectively, the ratio _L 1 _{/ L} 2 for _{L 2} of _{L 1} a (% indication) and sag rate SR value definition To do. The sagging rate of the SR value is a simple numerical value of the degree of auto-doping, and the larger the sagging rate, the steeper SR value profile indicates that auto-doping is reduced.

FIG. 4 shows the sagging rate of the SR value of the epitaxial layer of the epitaxial wafer on the vertical axis, and the deposition temperature of the epitaxial layer on the horizontal axis. Here, in the figure, the ◯ marks indicate the case where the film forming pressure is 1999.83 Pa (15 Torr), and the ◇ marks indicate the case where the film forming pressure is 266.44 Pa (20 Torr). In the low-pressure vapor phase epitaxy of the epitaxial layer, the resistivity of the same conductivity type with a film thickness of 5 μm is formed on the main surface of an 8 inch diameter underlying silicon wafer added to an arsenic dopant concentration of 1 × 10 ¹⁹ / cm ³ or more. A silicon epitaxial layer having a thickness of 1 Ω · cm was formed.

  It can be seen from FIG. 4 that when the film forming temperature is 1100 ° C., the sagging rate of the SR value is approximately 100%, and autodoping hardly occurs. The droop rate of this SR value decreases as the film forming temperature decreases. The decrease is gentle when the film formation temperature is in the range of 1100 to 1040 ° C., and the degree of decrease increases within the range of 1040 to 1000 ° C., and the droop rate of the SR value is 60 at the film formation temperature of 1000 ° C. %. When the film formation temperature is in the range of 1000 to 1100 ° C., the sagging rate of the SR value is substantially constant when the film formation pressure is in the range of 1999.83 Pa (15 Torr) to 2666.44 Pa (20 Torr).

  From the sag rate of the SR value shown in FIG. 4, it can be seen that the film forming temperature is preferably in the range of 1040 to 1100 ° C. in order to reduce autodoping and make the SR value profile steep. In particular, at 1070 to 1100 ° C. at which the sagging rate of SR value is 90% or more, the epitaxial wafer can be used also for a semiconductor device having a Schottky barrier diode that requires the steepest impurity profile. Further, even when the epitaxial layer is grown under reduced pressure vapor phase in the range of 1000 to 1040 ° C., the sagging rate of SR value is 60% or more, and the film thickness of the epitaxial layer in the plane of the epitaxial wafer. Since the variation of the sagging rate becomes small as in the case of the above, it can be used for manufacturing various semiconductor devices including a low breakdown voltage power transistor.

  In addition, when the film formation temperature is in the range of 1000 to 1100 ° C., the epitaxial layer is vapor-phase grown by so-called supply rate limiting. Therefore, if the film formation pressure is controlled within the above range, the epitaxial layer is controlled. Can be easily adjusted by the film formation time so as to obtain the required film thickness.

  In this embodiment, autodoping of impurities from a base silicon wafer containing high-concentration impurities can be performed easily without forming a film for preventing autodoping on the back surface of the base silicon wafer or forming a cap layer on the main surface of the base silicon wafer. Thus, a thin film epitaxial layer can be formed. Further, the epitaxial layer can be freely controlled so as to have a resistivity profile required for semiconductor device characteristics. And it becomes easy to make the film thickness of the epitaxial layer highly uniform and to reduce the cost of the silicon epitaxial wafer. It should be noted that the dopant that diffuses out from the back surface of the underlying silicon wafer is distributed on the outer peripheral side of the wafer by the horizontal rotation of the underlying silicon wafer and the flow of the film forming gas in the single-wafer vacuum vapor phase growth apparatus as described above. Since it is forced to flow, it is difficult to be taken into the epitaxial layer.

  Next, the effects of the present invention will be specifically described by way of examples, but the present invention is not limited to the following examples. In the low-pressure vapor phase growth of the epitaxial layer, the underlying silicon wafer has a diameter of 8 inches and an arsenic-doped resistivity of 0.006 Ω · cm. Then, by using the low-pressure vapor phase growth apparatus described in FIG. 1, the film formation pressure is set to 1999.83 Pa (15 Torr) using a monosilane gas flow rate of 0.3 SLM and a hydrogen gas flow rate of 50 SLM as a film formation gas. An epitaxial layer having a thickness of 5 μm and a thickness variation within the wafer plane of ± 1.0% was grown by reduced pressure vapor phase growth.

  Here, Example 1 is vapor phase growth with a film forming temperature of 1100 ° C., and Example 2 has a film forming temperature of 1070 ° C. The resistivity of the epitaxial layer was set to 1 Ω · cm. Further, Example 3 is vapor phase growth at a film forming temperature of 1040 ° C. and Example 4 is a film forming temperature of 1010 ° C., and the resistivity of the epitaxial layer is set to 0.5 Ω · cm. The growth rate of the epitaxial layer in each example is 1 μm / min.

(Examples 1-4)
The SR value profiles of the epitaxial wafers of these examples are collectively shown in FIG. As shown in FIG. 5, in Examples 1 and 2, there is almost no auto-doping, and the resistivity profile in the thin film epitaxial layer has high steepness. In Example 3 and Example 4, as described with reference to FIG. 4, the sagging rate of the SR value is reduced to 80 to 70%, and a little auto-doping occurs. However, even in the epitaxial layers formed in Examples 3 and 4, the uniformity of the epitaxial layer film thickness and the sagging rate in the epitaxial wafer surface is extremely high, and the low breakdown voltage power with uniform device characteristics such as breakdown voltage A transistor can be manufactured.

  As described above, the steepness of the resistivity profile of the thin film epitaxial layer and the uniform thickness of the thin film epitaxial layer are easy, and a silicon epitaxial wafer suitable for a semiconductor device having a low breakdown voltage power transistor, a Schottky barrier diode, etc. is low. It was confirmed that it can be manufactured at a low cost.

  Although the preferred embodiments of the present invention have been described above, the above-described embodiments do not limit the present invention. Those skilled in the art can make various modifications and changes in specific embodiments without departing from the technical idea and technical scope of the present invention.

  In the above embodiment, the underlying silicon wafer and the epitaxial layer are shown in the case of the n conductivity type, but even if they are the p conductivity type, they are formed in the same manner and have the same effect.

  Further, the vapor phase growth apparatus used for forming the silicon epitaxial layer in the above embodiment is not limited to the single-wafer type reduced pressure vapor phase growth apparatus described above.

It is typical sectional drawing of the reduced pressure vapor phase growth apparatus for using for description of the manufacturing method of the thin film epitaxial wafer concerning embodiment of this invention. It is the table | surface which showed the film-forming condition map which consists of the film-forming temperature and film-forming pressure in the low pressure vapor phase growth of the epitaxial layer of embodiment of this invention. It is a figure which shows an example of the SR value profile of the depth direction of the epitaxial wafer in embodiment of this invention, and uses for description of the method of quantifying the degree of auto dope. It is a graph which shows the relationship between the sagging rate of the profile of SR value by auto dope in embodiment of this invention, and film-forming conditions. It is a figure which shows the profile of SR value of the epitaxial wafer in the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Chamber 12 Rotating body unit 13 Gas rectifier plate 14 Gas discharge port 15 Deposition gas 16 Gas supply port 17 Exhaust gas 18 Gas discharge port W Underground silicon wafer R Rotation direction

Claims (5)

A method for producing a thin film epitaxial wafer, wherein a silicon epitaxial layer is formed on a main surface of an underlying silicon wafer to which a dopant having a concentration of 1 × 10 ¹⁹ / cm ³ or more is added,
Controlling the temperature of the underlying silicon wafer disposed in the reaction vessel in a range of 1000 to 1100 ° C .;
The pressure in the reaction vessel supplied with the film-forming gas containing SiH ₄ gas is set in the range of 1999.83 Pa to 2666.44 Pa;
A method for producing a thin film epitaxial wafer, comprising vapor-phase-growing a silicon epitaxial layer having the same conductivity type as that of the underlying silicon wafer and having a dopant concentration lower than that of the underlying silicon wafer on a main surface of the underlying silicon wafer.   Using a single-wafer vapor phase growth apparatus, the base silicon wafer is horizontally rotated in the reaction vessel, and the film forming gas is allowed to flow onto the main surface of the base silicon wafer from above the base silicon wafer. The method for producing a thin film epitaxial wafer according to claim 1, wherein the silicon epitaxial layer is vapor-phase grown.   3. The method of manufacturing a thin film epitaxial wafer according to claim 1, wherein the temperature of the underlying silicon wafer is controlled in a range of 1040 to 1100 ° C. 4.   4. The silicon epitaxial layer is vapor-phase grown so that the thickness thereof is 5 μm or less and the variation in the thickness within a wafer surface is within ± 1.0%. The manufacturing method of the thin film epitaxial wafer of description. 5. The vapor phase growth is performed so that the resistivity of the base silicon wafer is 0.006 Ω · cm or less and the resistivity of the silicon epitaxial layer is 0.5 to 1 Ω · cm. Manufacturing method of thin film epitaxial wafer.

Images