JP2009176331A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device which has a small refresh busy rate, small in current consumption for data retention, and is advantageous at miniaturization. <P>SOLUTION: The storage device comprises a plurality of memory cells including floating bodies, a plurality of bit lines connected to drain layers, a plurality of word lines connected to gate electrodes, and sense amplifiers for reading or writing logical data from or in the memory cells, and simultaneously refreshes a plurality of the memory cells by simultaneously driving one or a plurality of the bit lines and a plurality of the word lines to create bipolar operation for making first currents larger than a predetermined current flow into the memory cells storing first logical data which show charges stored in the body is larger and second currents smaller than a predetermined current into the memory cells storing second logical data which show charges stored in the body is small. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, for example, an FBC (Floating Body Cell) memory that stores information by accumulating electric charges in a floating body of a field effect transistor (FET).

  2. Description of the Related Art In recent years, there is an FBC memory device as a semiconductor memory device that is expected to replace a 1T (Transistor) -1C (Capacitor) type DRAM. In the FBC memory device, an FET (Field Effect Transistor) having a floating body (hereinafter also referred to as a body) is formed on an SOI (Silicon On Insulator) substrate, and depending on the number of majority carriers accumulated in the body. Data “1” or data “0” is stored. For example, in an FBC composed of an N-type FET, a state where the number of holes accumulated in the body is large is data “1”, and a state where the number is small is data “0”. A memory cell storing data “0” is called a “0” cell, and a memory cell storing data “1” is called a “1” cell.

  The FBC is superior to the conventional DRAM in size reduction. However, the capacitance of the body that stores the charge is smaller than the capacitance of the conventional DRAM capacitor. For this reason, although the leakage current from the body of the FBC is smaller than the leakage current from the capacitor of the DRAM, the FBC is shorter than that of the DRAM with respect to the data retention time. Therefore, the refresh operation must be executed frequently. As a result, the ratio of the time during which normal reading / writing is prohibited (refresh busy rate) increases, and further, there arises a problem that the current required to hold data becomes larger than that of a conventional DRAM. In particular, in a portable device, a large current consumption becomes a serious problem.

  In addition, since the FBC memory writes data by passing a current through the memory cell, it is necessary to increase the size of the driver for driving the current. Therefore, although the memory cell itself is small, the size of the entire memory (chip size) is not so small. That is, the ratio of the memory cells to the chip (cell efficiency) is small.

Furthermore, when a voltage having a large absolute value is applied to a bit line in reading or writing data, unselected memory cells connected to the bit line may be affected. This is called bit line disturb and shortens the retention time of the memory cell.
US Patent Application Publication No. 2006/0131650

  Provided is a semiconductor memory device having a small refresh busy rate, a low current consumption during data retention, and an excellent miniaturization.

A semiconductor memory device according to an embodiment of the present invention is provided between a source layer, a drain layer, and between the source layer and the drain layer, and accumulates charges to store logic data, or charges A plurality of memory cells arranged in a two-dimensional manner, including an electrically floating body region that emits light, and a gate electrode provided on the body region via a gate insulating film,
A plurality of bit lines connected to drain layers of the plurality of memory cells;
A plurality of word lines connected to gate electrodes of the plurality of memory cells; and
A sense amplifier connected to the bit line and reading logical data from the memory cell or writing logical data;
When executing a refresh operation for recovering the deterioration of the logic data of the memory cell, the memory cell storing the first logic data indicating a state of a large amount of accumulated charges in the body region has a first current greater than a predetermined current. One or more so as to cause a bipolar action of flowing a second current less than the predetermined current in a memory cell that stores a second logic data indicating a state in which the accumulated charge in the body region is low. A plurality of the memory cells are simultaneously refreshed by simultaneously driving the bit line and the plurality of word lines.

  The semiconductor memory device according to the present invention has a small refresh busy rate, a low current consumption during data retention, and is excellent in miniaturization.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a diagram showing an example of the configuration of an FBC memory device according to the first embodiment of the present invention. The FBC memory device includes a memory cell MC, word lines WLL0 to WLLn, WLR0 to WLRn (hereinafter also referred to as WL), bit lines BLL0 to BLLm, BLR0 to BLRm (hereinafter also referred to as BL), a sense amplifier S / A, a row decoder RD, a WL driver WLD, a column decoder CD, and a CSL driver CSLD.

  The memory cells MC are two-dimensionally arranged in a matrix and constitute memory cell arrays MCAL and MCAR (hereinafter also referred to as MCA). The word line WL extends in the row direction and has a function as a gate (first gate electrode) of the memory cell MC. N word lines WL are provided on the left and right sides of the sense amplifier S / A. The bit line BL extends in the column direction and is connected to the source or drain of the memory cell MC. There are m bit lines BL on the left and right sides of the sense amplifier S / A. The word line WL and the bit line BL are orthogonal to each other, and a memory cell MC is provided at each intersection. This is called a cross-point type cell. Note that the row direction and the column direction are names for convenience, and the row direction and the column direction may be interchanged.

  In the data read / write operation, one of the bit line pairs BLL and BLR connected to both sides of the sense amplifier S / A transmits data of the memory cell MC, and the other passes the reference current Iref. The reference current Iref is a current approximately halfway between the current flowing through the “0” cell and the current flowing through the “1” cell. In order to generate the reference current Iref, a dummy cell, a dummy word line, an averaging circuit, a dummy cell write circuit, and the like are required, but are omitted here. The sense amplifier S / A allows a current to flow to the memory cell MC via one bit line BL. As a result, a current corresponding to the data in the memory cell MC flows through the sense node in the sense amplifier S / A. The sense amplifier S / A identifies the logical value “1” or “0” of data depending on whether the current flowing through the sense node is higher or lower than the reference current Iref. Such a method of storing one bit in one memory cell is called a 1 cell / bit (single cell) method.

  Alternatively, in the data read / write operation, one of the bit line pairs BLL and BLR connected to both sides of the sense amplifier S / A is used as reference data for the other data, and the other data is used as one data. The reference data may be used. In this case, the two selected memory cells connected to the bit line pair BLL and BLR must store complementary data (data “1” and data “0”). That is, since two memory cells store 1 bit, this method is called a 2 cell / bit (twin cell) method. This embodiment can be applied to both single-cell and twin-cell systems. Further, the present embodiment can be applied to other methods.

  The row decoder RD decodes a row address in order to select a specific word line among the plurality of word lines WL. The WL driver WLD activates the selected word line by applying a voltage to the selected word line.

  The column decoder CD decodes a column address in order to select a specific column among a plurality of columns. The CSL driver CSLD reads data from the sense amplifier S / A to the DQ buffer (not shown) by applying a potential to the selected column selection line CSL. The sense amplifier S / A can read data out of the memory via the DQ buffer. Alternatively, the sense amplifier S / A can write data from the outside of the memory into the memory cell via the DQ buffer. The voltage polarity indicates a positive or negative voltage from the reference potential when the ground potential or the source potential is used as a reference. The polarity of data indicates complementary data “1” or data “0”.

  FIG. 2 is a cross-sectional view showing an example of the structure of the memory cell MC. Memory cell MC is provided on an SOI substrate including support substrate 10, BOX layer 20, and SOI layer 30. A source 60 and a drain 40 are provided in the SOI layer 30. The floating body 50 is formed in the SOI layer 30 between the source 60 and the drain 40. The body 50 is a semiconductor having a conductivity type opposite to that of the source 60 and the drain 40. In the present embodiment, the memory cell MC is an N-type FET. The body 50 is electrically floating by being partially or entirely surrounded by the source 60, the drain 40, the BOX layer 20, the gate insulating film 71, and STI (Shallow Trench Isolation) (not shown). The FBC memory can store logical data (binary data) according to the number of majority carriers in the body 50.

  The gate insulating film 71 is provided on the upper surface of the body 50. The word line (gate electrode) WL is provided on the upper surface of the body 50 via the gate insulating film 71.

  As shown in FIG. 2, when the FBC is made of an N-type FET, data can be stored by accumulating holes in the P-type body 50. For convenience, a state where the number of holes is large is defined as data “1”, and a state where the number of holes is small is defined as data “0”.

  An example of a method in which the sense amplifier S / A writes data “1” to the memory cell MC will be described. Using the potential of the N-type source layer 60 connected to the source line SL as a reference (0V), the potential of the word line WL as the gate electrode G is set to the positive voltage VWLHW, and the potential of the N-type drain layer 40 connected to the bit line BL is set to the positive voltage. Set to VBLH. Let Vth be the threshold voltage of the memory cell MC. At this time, if a relationship of VBLH> VWLHW−Vth is established, the memory cell MC is biased to a saturation region, and causes impact ionization. Impact ionization generates a large number of hole-electron pairs. Electrons generated by impact ionization are sucked into the drain layer 40, and holes generated by impact ionization are accumulated in a potential well formed in the body 50. As a result, data “1” is written into the memory cell MC.

  An example of a method in which the sense amplifier S / A writes data “0” to the memory cell MC will be described. The potential of the word line WL is raised to VWLHW, and the potential of the bit line BL is set to the negative potential VBLL. As a result, the pn junction between the body 50 and the drain layer 40 is forward-biased, and the holes accumulated in the body 50 are released to the bit line BL. As a result, the number of holes stored in the body 50 decreases, and data “0” is written into the memory cell MC.

  An example of how the sense amplifier S / A reads data from the memory cell MC will be described. The potential of the bit line BL is set to VBLR, and the potential of the word line WL is set to VWLHR. VBLR is set to a relatively small positive potential that satisfies VBLR <VWLHR−Vth. Note that VWLHR may be equal to VWLHW. As a result, the memory cell MC is biased to a linear region. At this time, the current flowing between the drain and the source varies depending on the number of holes stored in the body 50 (body effect). Therefore, the current flowing through the “1” cell is larger than the current flowing through the “0” cell. The sense amplifier S / A discriminates the polarity of the data stored in the memory cell MC by identifying this current difference.

  In the data holding state, the potential of the word line WL is set to the deep negative potential VWLL. The potential of the bit line BL is set to 0 V, which is the same as the potential of the source line SL. By setting the word line potential to a deep negative potential VWLL, the body potential of the “1” cell is made negative, and the PN junction between the body and the source and the PN junction between the body and the drain are reversed biased. As a result, the leakage current of the “1” cell is reduced and the data retention characteristic is improved. Further, when data “0” is written to a selected memory cell connected to a certain bit line, the potential of the bit line is set to a negative potential VBLL. At this time, if the word line potential is set to the deep negative potential VWLL, the data “0” is not erroneously written to the non-selected “1” cell connected to the bit line. That is, setting the word line potential to the deep negative potential VWLL serves to prevent the data deterioration phenomenon (“0” disturb) of the non-selected “1” cell when writing data “0”.

  Another method by which the sense amplifier S / A reads data from the memory cell MC will be described. Bipolar action can be used as a data reading method. For example, in the data holding state, the source potential of the memory cell MC is set as a reference (0 V), and the potential of the word line WL is set to a negative potential. At the time of reading, the potential of the word line WL is raised to, for example, the source potential (0V), and the drain potential is raised from the source potential (0V) to the positive potential. Thereby, the parasitic npn bipolar transistor including the n-type source 60, the p-type body 50, and the n-type drain 40 is turned on only in the “1” cell. The current between the collector (drain) and the emitter (source) flows constantly even though the base (body) is floating. This is because impact ionization is caused by a current between the collector and the emitter, and holes are generated in the base. This is because positive feedback is generated in the parasitic npn bipolar transistor and the base current can be continuously supplied. The body voltage of the “1” cell at this time is determined by the balance between the current generated by impact ionization and the forward current of the pn junction flowing out to the source. For example, the body voltage is about 0.7 to 1V. On the other hand, since the number of holes accumulated in the body of the “0” cell is smaller than that of the “1” cell, the positive feedback loop does not occur in the “0” cell. Therefore, the body voltage of the “0” cell remains low.

  As a result, although the potentials of the bit line, word line, and source line in the “1” cell are equal to those potentials in the “0” cell, the parasitic bipolar transistor of the “1” cell is turned on, and “0” The parasitic bipolar transistor of the cell remains off. Thereby, the sense amplifier S / A can detect the data stored in the memory cell MC.

  Next, the autonomous refresh operation according to this embodiment will be described. The autonomous refresh operation according to the present embodiment uses a bipolar action. First, in the data holding state, as described above, the potential of the word line WL is set to the deep negative potential VWLL with reference to the source potential (0 V), and the potential of the bit line BL may be the same as the source potential. The refresh operation is an operation for recovering the deterioration of the logical data of the memory cell MC.

  When autonomous refresh is executed from the data holding state, the potential of the word line WL rises to a potential VWLR that is lower than the threshold voltage Vth1 of the “1” cell and equal to or higher than VWLL. That is, the potential VWLR of the word line WL is set so as to satisfy VWLL ≦ VWLR <Vth1.

  The potential of the bit line BL is raised to the positive potential VBLR. When the voltage VBLR is sufficiently high, as shown in FIG. 2, holes accumulated in the body (base) flow out to the source side (emitter side) as a forward current (base current) IE, and electrons flow to the source side (emitter). Flows from the side) through the body (base) to the drain side (collector side). The flow of electrons from the body to the drain is a collector current IC, which is a current obtained by amplifying the forward current IE. As a result, a so-called bipolar action occurs in the memory cell MC.

  In the “1” cell, the collector current IC is larger than the predetermined current value IC0. In this case, electrons ionize silicon atoms and generate a large number of conduction electron-hole pairs (impact ionization). The electrons generated at this time are emitted to the drain side (collector side), but the holes remain in the body (base). In IC> IC0, the number of holes generated by impact ionization is larger than the number of holes flowing to the emitter side. As a result, the base can continue to maintain a forward bias with respect to the emitter, and the bipolar action continues constantly. Therefore, the amplified collector current IC continues to flow in the memory cell MC, and the body potential rises. When the body potential (base potential) rises, the forward current IE increases, so the amount of holes accumulated in the body 50 does not increase beyond a certain value and is in an equilibrium state. Thereby, the autonomous refresh of the “1” cell is completed.

  In the “0” cell, the collector current IC is smaller than the predetermined current value IC0. In this case, since the number of holes generated by impact ionization is smaller than the number of holes flowing out to the emitter side due to the forward bias of the PN junction, the base potential decreases with the outflow of holes due to the forward current IE. Therefore, a steady bipolar action does not occur, and the collector current IC gradually disappears. Thereby, the autonomous refresh of the “0” cell is completed.

  As described above, in order to autonomously refresh both the “1” cell and the “0” cell simultaneously, IC> IC0 for the “1” cell, and IC <IC for the “0” cell. It is necessary to set the potential VWLR of the word line WL and the potential VBLR of the bit line BL so as to be IC0. As described above, the potential VWLR of the word line WL needs to satisfy VWLL ≦ VWLR <Vth1. Since the threshold voltage Vth1 of the “1” cell is lower than the threshold voltage Vth0 of the “0” cell, VWLR is naturally lower than Vth0.

  Since the optimum potential VBLR of the bit line BL varies depending on the configuration of the memory cell MC and the potential of the word line WL, the condition cannot be qualitatively shown. explain.

  FIG. 3 shows experimental results showing the relationship between the drain current and drain voltage of a certain memory cell MC. Here, the size (L / W) of the memory cell MC is 0.15 μm / 2.0 μm. Lines L1 to L4 show the results when the gate voltage (word line potential) is 0.125V, 0.150V, 0.175V and 0.200V, respectively.

  In this experiment, the drain current Id (collector current IC) when the drain voltage Vd is once increased and then decreased is measured. When the drain voltage Vd exceeds a certain voltage, the drain current Id increases rapidly. Alternatively, when the drain voltage Vd falls below a certain voltage, the drain current Id suddenly decreases. The drain voltage Vup at which the drain current Id suddenly rises is a point where impact ionization occurs, and the drain voltage Vdown at which the drain current Id suddenly falls is a point where impact ionization stops. Accordingly, the broken-line circle C1 indicates the state of the “1” cell, and the broken-line circle C0 indicates the state of the “0” cell.

  When the gate voltage is 0.175 V or more, as shown by lines L3 and L4, the drain voltage Vup at which the drain current Id suddenly increases is substantially equal to the drain voltage Vdown at which the drain current Id suddenly decreases. On the other hand, when the gate voltage is 0.150 V or less, the drain voltage Vup at which the drain current Id suddenly increases is different from the drain voltage Vdown at which the drain current Id suddenly decreases. That is, when the gate voltage is less than a predetermined value, hysteresis appears between the drain voltage and the drain current. In the specific example shown in FIG. 3, when the gate voltage is about 0.15 V or less, hysteresis appears between the drain voltage and the drain current. Furthermore, even if the gate voltage is negative, hysteresis appears between the drain voltage and the drain current (FIG. 8).

In the autonomous refresh according to the present embodiment, the drain voltage Vd is set between the drain voltage Vup and the drain voltage Vdown. For example, when the gate voltage is 0.125V (L1), the drain voltage Vd is set within a range of about 3.35V to about 3.55V. When the gate voltage is 0.150V (L2), the drain voltage Vd is set within a range of about 3.25V to about 3.35V. As a result, even if the drain voltage of the “1” cell (the potential of the bit line BL) is equal to the drain voltage of the “0” cell, impact ionization occurs in the “1” cell, and impact ionization does not occur in the “0” cell. . In other words, by setting the drain voltage Vd within the above range, the drain current Id (collector current IC) of the “1” cell becomes larger than the predetermined current value IC0, and the drain current Id of the “0” cell. (Collector current IC) is smaller than a predetermined current value IC0. Predetermined current value IC0 is in the range of about ^{10 -11} A to about ^{10 -8} A. As described above, by controlling the gate voltage and the drain voltage, autonomous refresh using the bipolar action can be simultaneously executed in the “1” cell and the “0” cell.

  When the gate voltage is 0.175 V or higher (L3 and L4), the drain voltage Vup is almost equal to the drain voltage Vdown, so that the “1” cell and the “0” cell cannot be autonomously refreshed simultaneously.

  Thus, the inventors of the present invention have focused on the fact that the memory cell MC itself has a function of amplifying data by a bipolar action. By utilizing this bipolar action, the memory cell MC itself can amplify and rewrite data. The advantage of this autonomous refresh is that the sense amplifier S / A does not need to detect data during refresh. Therefore, the autonomous refresh according to the present embodiment can simultaneously refresh a plurality of memory cells MC connected to the same bit line BL. Thereby, as will be described later, the power consumption can be reduced and the refresh busy rate can be reduced as compared with the conventional refresh method.

  4 to 8 are timing charts showing an autonomous refresh operation according to the present embodiment. The source potential is maintained at the ground potential (0 V). In the data holding state, the potential of the word line WL is set to the deep negative potential VWLL, and the potential of the bit line BL is set to the ground potential similarly to the source potential.

  When the autonomous refresh operation is entered, from t1 to t2, first, the word line driver WLD raises the potential of the word line WL from VWLL to the positive potential VWLR. As a result, the body potential Vbody1 of the “1” cell and the body potential Vbody0 of the “0” cell both rise due to capacitive coupling between the body and the gate. At this time, the word line driver WLD may drive a plurality of word lines WL simultaneously.

  From t3 to t4, the column selection line driver CSLD raises the potential of the bit line BL from the source potential to the positive potential VBLR. As a result, the body potential Vbody1 of the “1” cell and the body potential Vbody0 of the “0” cell further increase due to capacitive coupling between the body and the drain. At this time, the column selection line driver CSLD may drive a plurality of bit lines BL simultaneously.

  The body potential Vbody1 of the “1” cell is higher than the body potential Vbody0 of the “0” cell. Therefore, after t4, as described above, impact ionization occurs due to the bipolar action in the “1” cell, and holes are accumulated in the body 50. In the “0” cell, holes are emitted from the body 50 by the forward current IE. That is, since IC> IC0 in the “1” cell and IC <IC0 in the “0” cell, the difference between the body potential of the “1” cell and the body potential of the “0” cell is changed from ΔVb_before to ΔVb_after (ΔVb_after> ΔVb_before).

  From t5 to t6, the word line driver WLD returns the potential of the word line WL from VWLR to VWLL. From t7 to t8, the column selection line driver CSLD returns the potential of the bit line BL from VBLR to the source potential. Thereby, the autonomous refresh operation using the bipolar action according to the present embodiment is completed, and the memory cell MC is again in the holding state.

  As shown in FIG. 5, the potential of the bit line BL may be raised first, and then the potential of the word line WL may be raised. That is, the order in which the potential of the bit line BL and the potential of the word line WL are raised does not matter.

  In FIG. 6, the potential of the word line WL at the time of data retention is set to a negative potential VWLL1 (VWLL1> VWLL) shallower than that shown in FIGS. As a result, a forward bias is applied to the body-source PN junction and the body-drain PN junction of the “1” cell. In this case, although the data in the “1” cell is deteriorated, the storage state of the “0” cell is stabilized. This is because, since the potential of the word line WL is a shallow negative potential, holes are not accumulated much in the body 50 of the “0” cell.

  The autonomous refresh according to the present embodiment is an operation of supplying holes to the “1” cell by impact ionization. Therefore, it can be said that the data holding state of FIG. 6 is suitable for autonomous refresh using the bipolar action according to the present embodiment.

  FIG. 7 differs from the timing chart of FIG. 6 in that the potential of the bit line BL is raised first, and then the potential of the word line WL is raised. Thus, the order of raising the potential of the bit line BL and the potential of the word line WL is not limited.

  In FIG. 8, only the potential of the bit line BL is raised without raising the potential of the word line WL. That is, the potential of the word line WL during the autonomous refresh is set to a negative potential substantially equal to the potential VWLL of the word line WL in the data holding state. In this case, the potential VWLL of the word line WL is lower than the potential VWLR of the word line WL shown in FIGS. 4 to 7, but the potential VBLR1 of the bit line BL is set to the potential of the bit line BL shown in FIGS. By setting higher than VBLR, autonomous refresh by bipolar action becomes possible.

(Autonomous refresh operation in active mode)
In the data holding mode (standby state) in which the operation of writing data from the outside or reading the data to the outside is not executed for a certain period or longer, access to the memory cell MC does not occur. On the other hand, in the active mode, it is necessary to access the memory cells MC irregularly in order to read data to the outside or write data from the outside. The active mode is a state in which a period from an access for reading data to the outside or writing data from the outside to the next access is less than a certain period. In the data read / write operation, the sense amplifier S / A executes a conventional refresh operation in which data in the memory cell MC is once read and this data is written back to the memory cell MC. Therefore, even when access to the memory cell MC frequently enters, the autonomous refresh may be executed in the same cycle as the cycle in the data holding mode.

  Originally, when the access for reading / writing data does not enter for a predetermined period or more, the data deterioration of the memory cell MC becomes a problem. Therefore, in a situation where access frequently enters the memory cell MC, the autonomous refresh functions in the same manner as in the data holding mode.

  However, when access for reading / writing data enters fairly frequently, there is a concern about disturbing the memory cell MC. In such a case, it is effective to change the operation voltage of the autonomous refresh so that the component of the current component that fluctuates due to disturbance can be ignored (so as to be relatively small).

  FIG. 9 is a timing chart showing operations of the word line WL and the bit line BL in the active mode and the data holding mode. For example, as shown in FIG. 9, the word line potential VWL and the bit line potential VBL in the active mode are set higher than those in the data holding mode. That is, the word line potential VWL and the bit line potential VBL in the active mode are separated from the source potential VSL more than those in the data holding mode. Thereby, the impact ionization in the active mode can be increased more than that in the data holding mode.

  Since the current component due to disturbance increases in the active mode compared to the data holding mode, it is effective to increase the impact ionization current and the forward current. At this time, the DC current passed through the memory cell MC also increases, but a large average current flows originally in the active mode. For this reason, the increment of impact ionization current and forward current is negligible. That is, current consumption hardly increases. However, in the data holding mode, since it is necessary to realize a low data holding current, an increase in impact ionization current and forward current becomes significant. Therefore, the impact ionization current and the forward current in the data retention mode are preferably lower than those in the active mode.

  However, as described with reference to FIG. 3, in the active mode and the data holding mode, the drain current Id of the “1” cell is larger than the predetermined current value Id0, and the drain current Id of the “0” cell is predetermined. It is necessary to set the bit line potential and the word line potential to be smaller than the current value Id0.

  At the time of autonomous refresh, the number of word lines WL activated simultaneously and the number of bit lines BL activated simultaneously are arbitrary. For example, one word line WL and all bit lines BL may be activated as in a conventional refresh operation, and all memory cells MC connected to the activated word line WL may be simultaneously refreshed. In this case, the current consumption in the data holding mode is the same as the conventional one. Although the potential of the drain 40 of the memory cell MC connected to the inactive unselected word line WL rises, the gate potential remains low. Therefore, the bipolar action does not occur in the “1” cell and the “0” cell.

Active means that an element or circuit is turned on or driven, and inactive means that an element or circuit is turned off or stopped. Therefore, it should be noted that a HIGH (high potential level) signal may be an activation signal, and a LOW (low potential level) signal may be an activation signal. For example, the NMOS transistor is activated by setting the gate to HIGH. On the other hand, the PMOS transistor activates all word lines WL and one bit line BL activated by setting the gate to LOW, and simultaneously activates all memory cells MC connected to the activated bit line BL. You may refresh. In this case, the current consumption in the data holding mode is as follows: the number 2n of the word lines WL, the capacity CWL of the word lines WL, the driving amplitude ΔVWL of the word lines WL, the number of bit lines 2 m, the capacity CBL of the bit lines, and the driving amplitude of the bit lines. Depends on ΔVBL. The current consumption in the data holding mode may be decreased or increased as compared with the conventional case. In this case, the gate potential of the memory cell MC connected to the inactive non-selected bit line rises, but the drain potential remains low. Therefore, no bipolar action occurs in the “1” cell and the “0” cell.

  All the word lines WL and all the bit lines BL may be activated to refresh all the memory cells MC in the memory cell array at the same time. In this case, the current consumption in the data holding mode is lower than in the conventional case. In this case, the current required for the operation of the peripheral circuit can also be reduced.

  FIG. 10 is a graph showing the relationship between the number of word lines WL activated simultaneously and the current in the data holding mode. The horizontal axis indicates the number of word lines WL that are simultaneously activated at the time of refresh, and the vertical axis indicates data of a 1 gigabit FBC memory having 32 × 16 units (2 Mb × 32 × 16) of a 2 megabit memory cell array MCA. The current in the holding mode is shown. The current in the data holding mode is a current required for autonomously refreshing the 1 gigabit FBC memory. Two 2-megabit memory cell arrays are provided on the left and right of the sense amplifier S / A as shown in FIG. Each memory cell array includes, for example, 512 word lines WL and 4096 bit lines BL.

  As an example, the capacitance CWL of the word line WL is 300 fF, the voltage amplitude ΔVWL of the word line WL is 1 V, the capacitance of the bit line BL is 100 fF, the voltage amplitude ΔVBL of the bit line BL is 3.5 V, and the peripheral circuit related to the refresh operation Assume that the charge capacity CPERI is 200 pF and the voltage amplitude ΔVPERI of the peripheral circuit is 1.8V. The worst cell retention time TRET is set to 5 ms. Also, it is assumed that the refresh cycle time τref is 50 ns.

  Sixteen 64-Mbit memory cells MC are refreshed in parallel in units of 64 Mbits. In the 64 Mbit memory, refresh is executed for every two 2 Mbit memory cell arrays sharing the row decoder RD. It was assumed that the DC current flowing through the “1” cell during refresh was 2 μA, and the time τ1 for refreshing the memory cell was 3 ns. The influence of the DC current flowing through the memory cell on the current in the data holding mode depends on the retention time (for example, 5 ms) of the memory cell and does not depend on the number of word lines and bit lines activated simultaneously. If half of the “1” cells and “0” cells exist, the average value of the DC current flowing through the 1 gigabit FBC memory in the data holding mode is 0.644 mA.

  FIG. 10 shows the current consumption in the data holding mode of the 1 Gbit memory with respect to the number of word lines activated simultaneously in the 2 Mbit memory cell array. For each of 512, 1024, 2048, and 4096 bit lines activated simultaneously, the current consumption in the data holding mode of the 1 Gbit memory is shown by curves L1 to L4.

  In the conventional refresh operation, one word line is activated and memory cells connected to 4096 bit lines are activated. In this case, the current in the data holding mode is about 100 mA. On the other hand, in the autonomous refresh operation according to the above embodiment, 512 word lines can be activated and memory cells connected to 4096 bit lines can be activated. That is, in the autonomous refresh operation, all the memory cells in the 2Mbit memory cell array can be refreshed simultaneously. In this case, the current in the data holding mode is about 0.84 mA. That is, the current consumption in the data holding mode by the autonomous refresh operation is 1/100 or less compared to that of the conventional refresh.

  Note that there is an offset current that does not depend on the number of word lines and bit lines that are simultaneously activated but depends on the degree of integration of the memory cells. This offset current is due to the DC current of the memory cell. Therefore, in this embodiment, the DC current of the memory cell for 1 Gbit becomes the offset current. Therefore, in order to further reduce the current consumption in the data holding mode, it is necessary to reduce the offset current. In order to decrease the offset current, the DC current may be decreased or the refresh period may be lengthened.

Of the currents required in the data holding mode, the current Iret1 (also referred to as AC component) required for charging the bit line and the word line can be generalized as follows. Consider an N × M bit memory array consisting of N word lines and M bit lines. If the minimum value of the retention time of all memory cells is TRET, M bit lines must be charged / discharged every TRET / N in the same refresh operation as that of a conventional DRAM. Assuming that the word line capacitance and voltage amplitude are CWL and VWL, and the bit line capacitance and voltage amplitude are CBL and VBL, respectively, the AC component Iret1 of the current required for data retention of the entire memory cell array is expressed as shown in Equation 1. The
Iret1 = (CWL.VWL + M.CBL.VBL) / (TRET / N) = N (CWL.VWL + M.CBL.VBL) / TRET (Formula 1)

On the other hand, when all memory cells are refreshed simultaneously, all word lines WL and all bit lines BL are activated every time TRET elapses. Therefore, the AC component Iret2 of the current necessary for holding data relating to the memory cell array in this case is expressed as in Expression 2.
Iret2 = (N · CWL · VWL + M · CBL · VBL) / TRET (Formula 2)

The difference ΔIret = Iret1−Iret2 of the AC component of the data holding current is expressed as Equation 3.
ΔIret = (NM−1) · CBL · VBL / TRET≈ (N · M) · CBL · VBL / TRET (Formula 3)

  This is almost the same value as the charge / discharge current of the bit line in the conventional refresh operation. Since N · CWL · VWL << (N · M) M · CBL · VBL, the AC component of the data holding current in the autonomous refresh according to the present embodiment is almost negligible when compared with the data holding current in the conventional refresh. Small enough.

  Further, regarding current consumption in a peripheral circuit (also referred to as a column-related peripheral circuit) provided for driving the bit line BL, the conventional refresh requires charging / discharging the peripheral circuit N times during TRET. In the autonomous refresh according to the present embodiment, it is sufficient to charge and discharge the peripheral circuit once during TRET. Also in the column peripheral circuit, the current consumption of the column peripheral circuit in the autonomous refresh according to the present embodiment is small enough to be ignored as compared with the current consumption of the column peripheral circuit in the conventional refresh. In the above calculation, the influence of the DC current flowing in the memory cell during refresh is ignored.

  FIG. 11 is a graph showing the relationship between the number of simultaneously activated word lines WL and the refresh busy rate. The horizontal axis indicates the number of word lines WL that are simultaneously activated during refresh, and the vertical axis indicates the refresh busy rate. The refresh busy rate means a time ratio of the autonomous refresh period to the one cycle period TRET in the data holding mode. For example, a refresh busy rate of 100% is a state in which a refresh operation is always required in a data holding state. Therefore, the lower the refresh busy rate, the better as long as data can be held.

  When the number of word lines WL simultaneously activated in the refresh operation is 1, the refresh busy rate is about 8% or more even if the bit lines BL (4096 lines) of all the columns are activated simultaneously. In the conventional refresh operation, only one word line must be activated at the same time. In this case, even if the bit lines BL (4096 lines) of all the columns are activated simultaneously, the refresh busy rate cannot be made lower than about 8%.

  The autonomous refresh operation according to the present embodiment can simultaneously activate a plurality of word lines. For example, when the number of word lines WL simultaneously activated in the refresh operation is 512 and the number of bit lines BL simultaneously activated in the refresh operation is 4096 (all memory cells in the memory cell array are simultaneously When refreshing), the refresh busy rate can be reduced to about 0.016%.

  If the number of memory cells to be refreshed at the same time is large, the current peak becomes large, and noise may become a problem. When such a problem occurs, the memory cell array may be divided into certain blocks and refreshed for each block. For example, a 64 megabit memory cell may be divided into 128 and 512 Kbit memory cells may be refreshed simultaneously. In this case, the current peak is reduced and the refresh busy rate is increased. However, the refresh busy rate is about 2% (0.016% × 128), and is still within a practical range.

(Second Embodiment)
FIG. 12 is a timing diagram showing an operation of the FBC memory according to the second embodiment of the present invention. In the second embodiment, immediately after data reading to the outside of the memory or data writing from the outside of the memory, all the memory cells connected to the selected bit line activated at the time of reading or writing are autonomously refreshed. Reading is a method in which the sense amplifier S / A detects the current of the memory cell MC. Data “1” is written by impact ionization of the memory cell MC, and data “0” is written by forward biasing the PN junction between the body and the drain by setting the bit line to a negative potential. Of course, other writing methods or reading methods may be used.

  After the reading or writing is executed, autonomous refresh of all the memory cells MC connected to the selected bit line BL is executed after t10. At this time, refresh is not performed on the memory cells MC connected to the non-selected bit line BL. The autonomous refresh here is an autonomous refresh according to the above embodiment. Thus, immediately after reading or writing, all the memory cells MC connected to the selected bit line to be read or written may be autonomously refreshed.

When data “1” is written, the selected bit line is raised to a high level potential. For this reason, GIDL occurs in an unselected “0” cell connected to the selected bit line, and data “0” is degraded (“1” bit line disturb). At the time of writing data “0”, the selected bit line is lowered to the low level potential. For this reason, holes in the non-selected “1” cell connected to the selected bit line may flow out due to a forward bias between the body and the drain (“0” bit line disturb).
In the second embodiment, since all the memory cells MC connected to the selected bit line are autonomously refreshed immediately after reading or writing, “1” bit line disturbance and “0” bit line disturbance are effectively suppressed. Can do.

(Third embodiment)
FIG. 13 is a diagram showing an example of the configuration of the FBC memory according to the third embodiment of the present invention. In the third embodiment, a sense amplifier S / A is provided for each of m (m ≧ 2) bit lines BL. A bit line selector BLS is provided between the sense amplifier S / A and the m bit lines BL. The bit line selector BLS is configured to select a specific bit line BL from the m bit lines BL and connect it to the sense amplifier S / A in the data read / write operation. On the other hand, in the refresh operation, the bit line selector BLS can connect all m bit lines BL to the sense amplifier S / A. Thereby, the FBC memory according to the third embodiment can execute the autonomous refresh operation similarly to the first or second embodiment.

  In the third embodiment, since the sense amplifier S / A is provided for every m bit lines, the area of peripheral circuits other than the memory cells can be reduced. That is, the cell occupation ratio with respect to the memory chip is improved. As a result, the chip size of the FBC memory can be reduced.

(Fourth embodiment)
FIG. 14 is a diagram showing an example of the configuration of the FBC memory according to the fourth embodiment of the present invention. In the fourth embodiment, the bit lines are local bit lines LBLLk, i, LBLRk, i (k is 1 to N, i is 1 to M) (hereinafter also simply referred to as LBL), and global bit lines GBLLi, GBLRi ( Hereinafter, this is also simply referred to as GBL). Each local bit line LBL is connected to some of the memory cells MC in a certain column. In FIG. 14, (N + 1) memory cells MC are connected to one local bit line LBL. The global bit line GBL is provided corresponding to a plurality of local bit lines and is connected to the sense amplifier S / A.

  A bit line switch BSW is connected between the local bit line LBL and the global bit line GBL. The global bit line GBL can be selectively connected to a specific local bit line LBL by a bit line switch BSW.

  According to the hierarchical bit line configuration shown in FIG. 14, it is not necessary to provide a sense amplifier S / A for each local bit line LBL, and the number of sense amplifiers S / A can be reduced. For example, in the specific example of FIG. 14, global bit lines GBL are connected to the left and right of the sense amplifier S / A, and each global bit line GBL has four local bit lines LBL (a total of eight local bit lines). It is connected to the. Therefore, the number of sense amplifiers S / A in this embodiment is 1/8 of the number of sense amplifiers S / A provided for each local bit line LBL.

  When the conventional refresh operation is executed in such a hierarchical bit line configuration, the number of memory cells that can be refreshed at one time is reduced to 1/8. As a result, the number of refresh cycles (the number of refresh cycles necessary for refreshing all memory cell cells) increases, and the refresh busy rate increases.

  On the other hand, when the autonomous refresh according to the above embodiment is used, the memory cells in the entire memory cell array can be simultaneously refreshed regardless of the number of sense amplifiers. Therefore, according to the autonomous refresh, all memory cells can be refreshed without increasing the refresh busy rate even in the FBC memory adopting the hierarchical bit line configuration. Furthermore, since the number of sense amplifiers S / As can be reduced by adopting the hierarchical bit line configuration, the size of the entire memory device can be reduced.

  In the above embodiment, the memory cell MC may be a p-type FET. In this case, the memory cell MC stores data by accumulating electrons or emitting electrons. In this case, the polarity of each potential of the word line WL and the bit line BL may be reversed.

In the above embodiment, the source potential is the ground potential, but the source potential may be set to a potential other than the ground potential. In this case, the polarity of each potential of the word line WL and the bit line BL is based on the source potential.

  In the above embodiment, the read and write methods are not particularly limited. Therefore, the autonomous refresh operation according to the present embodiment can be applied to any conventional read and write methods, and any read and write methods that will be proposed.

1 is a diagram showing an example of the configuration of an FBC memory device according to a first embodiment of the present invention. Sectional drawing which shows an example of the structure of the memory cell MC. The experimental result which shows the relationship between the drain current and drain voltage of a certain memory cell MC. The timing diagram which shows the autonomous refresh operation | movement by this embodiment. The timing diagram which shows the autonomous refresh operation | movement by this embodiment. The timing diagram which shows the autonomous refresh operation | movement by this embodiment. The timing diagram which shows the autonomous refresh operation | movement by this embodiment. The timing diagram which shows the autonomous refresh operation | movement by this embodiment. FIG. 4 is a timing chart showing operations of a word line WL and a bit line BL in an active mode and a data holding mode. The graph which shows the relationship between the number of the word lines WL activated simultaneously, and the electric current in data retention mode. The graph which shows the relationship between the number of the word lines WL activated simultaneously, and the refresh busy rate. The timing diagram which shows operation | movement of the FBC memory according to 2nd Embodiment based on this invention. The figure which shows an example of a structure of the FBC memory according to 3rd Embodiment concerning this invention. The figure which shows an example of a structure of the FBC memory according to 4th Embodiment concerning this invention.

Explanation of symbols

MC ... memory cell BL ... bit line WL ... word line SL ... source line 40 ... drain 50 ... body 60 ... source S / A ... sense amplifier MCAL, MCAR ... memory cell array

Claims (5)

A source layer, a drain layer, an electrically floating body region that is provided between the source layer and the drain layer to store or release charges to store logic data; and a gate A plurality of memory cells arranged two-dimensionally, including a gate electrode provided on the body region via an insulating film,
A plurality of bit lines connected to drain layers of the plurality of memory cells;
A plurality of word lines connected to the gate electrodes of the plurality of memory cells or functioning as gate electrodes; and
A sense amplifier connected to the bit line and reading logical data from the memory cell or writing logical data;
When executing a refresh operation for recovering the deterioration of the logic data of the memory cell, the memory cell storing the first logic data indicating a state of a large amount of accumulated charges in the body region has a first current greater than a predetermined current. One or more so as to cause a bipolar action of flowing a second current less than the predetermined current in a memory cell that stores a second logic data indicating a state in which the accumulated charge in the body region is low. A semiconductor memory device, wherein the plurality of memory cells are simultaneously refreshed by simultaneously driving the bit lines and the plurality of word lines.   2. The semiconductor memory device according to claim 1, wherein all the memory cells connected to the plurality of bit lines and the plurality of word lines are simultaneously refreshed.   When performing the refresh operation, the potential of the plurality of word lines is higher than the potential of the plurality of word lines in the data holding state, and the threshold voltage of the memory cell storing the first logic data and the first 2. The semiconductor memory device according to claim 1, wherein the threshold voltage is lower than a threshold voltage of a memory cell storing 2 logic data.   After the sense amplifier reads data to the outside or writes data from the outside, a plurality of the memory cells connected to the bit line to be read or written are utilized using the bipolar action. 4. The semiconductor memory device according to claim 1, wherein refreshing is performed simultaneously.   2. The semiconductor memory device according to claim 1, wherein when the refresh operation is performed, the potentials of the plurality of word lines are substantially equal to the potentials of the plurality of word lines in a data holding state.

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