JP2009176147A - Electronic equipment and method for determining permission of access to memory of electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data-writing device which easily writes data to a nonvolatile memory, which is mounted on a substrate on an electronic device side, while keeping security, a data-writing method, and a data-writing program therefor. <P>SOLUTION: A NOR-type flash memory 204 which is mounted on a substrate of electronic equipment is connected to an external device via a connector which is not illustrated. The state checking part 241 of the flash memory part 221 enables a multiplexer 262 to write on the conditions that data are not written to the NOR-type flash memory 204 and a mode selection signal line 209 designates ROM writing. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electronic device using a non-volatile memory typified by a NOR flash memory and a memory access permission determination method for the electronic device, and more particularly to an electronic device that enables data rewriting related to a non-volatile memory mounted on a substrate. The present invention also relates to a memory access permission determination method for such an electronic device.

  A flash memory is a non-volatile semiconductor memory that is rewritable and retains data even when the power is turned off. In many electronic devices, when the power is turned on, a CPU (Central Processing Unit) arranged therein starts to operate and executes a control program. Such a storage device in the electronic device stores a control program to be executed. In recent years, many embedded system electronic devices have appeared. In embedded system electronic devices, a NOR (Not OR) flash memory is often used for this type of storage device.

  In addition to the NOR type, flash memory also has a NAND (Not AND) type. The NOR type flash memory is characterized in that data can be read and written in units of bytes and random access is fast. In addition, unlike the NAND type, error correction is unnecessary and reliability is high, so that data such as programs is often stored in a semiconductor memory of an electronic device such as a mobile phone or a PDA (Personal Digital Assistants).

  By the way, in the assembly process, the electronic device is mounted as a work for electrically connecting components such as a CPU and a NOR type flash memory to the substrate with solder. After being mounted, the NOR type flash memory has only read and write access from the CPU, and no access from other devices. In other words, the NOR flash memory is always accessed via the CPU while mounted on the substrate.

  This is because the NOR type flash memory is controlled with a set of signal lines, address lines and data lines for controlling the NOR type flash memory. That is, after the NOR flash memory is mounted on the electronic device, the address line and the data line are connected to the CPU in the substrate. Therefore, in a state where the NOR flash memory is mounted on the substrate, there is no means for accessing the NOR flash memory from other than the CPU.

  When power is turned on, the electronic device reads a control program from, for example, a NOR flash memory and starts its operation. In order to enable such startup operation, the NOR flash memory needs to be written with a program necessary for the operation of the electronic device before being mounted on the substrate.

  Conventionally, a program is written into a NOR flash memory before being mounted on a substrate using a device called a ROM (Read Only Memory) writer. As the ROM writer, for example, a product called a device programmer of Minato Electronics Co., Ltd. is used. Conventionally, a technique of mounting a NOR type flash memory, which has been written by a ROM writer, on a substrate has been widely employed.

  FIG. 8 shows a flow of a series of operations until an electronic device is operated using the NOR flash memory in this conventional method. First, using a ROM writer (not shown), data such as a program is written into the NOR type flash memory (ROM writing) (step S101). Next, this NOR type flash memory is mounted on a substrate (step S102). Then, the electronic device in which the substrate is incorporated is activated (step S103).

  As described above, if the ROM writing is normally performed on the NOR type flash memory mounted on the substrate, there is no problem in starting the electronic apparatus. However, when a failure occurs in ROM writing for some reason, it is preferable that ROM writing to the NOR flash memory can be performed after mounting. Further, if ROM writing can be performed after mounting, it is not necessary to complete ROM writing in the NOR type flash memory before mounting.

  Therefore, it has been conventionally performed to write data to a NOR type flash memory mounted on a substrate by previously arranging a connector called a JTAG (Joint Test Action Group) connector on the substrate. When the JTAG connector is used, it is possible not only to write data to the NOR type flash memory but also to read data from the NOR type flash memory.

  However, if the JTAG connector is arranged on the board, a third party can use this JTAG connector to write data into the NOR flash memory or read data in the NOR flash memory. Problems occur.

  Therefore, while a contact IC card is connected to a personal computer, a contact IC card reader / writer is connected to the CPU side of the electronic device, and data from the personal computer side is transferred to the contact IC card reader / writer. It has been proposed as a first related technique of the present invention to rewrite the contents of the memory via the CPU (see, for example, Patent Document 1).

There has also been proposed a second related technique in which a storage medium that is detachable from the electronic device is prepared, and the rewrite prohibition state of the program data on the electronic device side is canceled and rewriting is executed (for example, Patent Document 2).
JP 2000-076395 (paragraph 0010, FIG. 1) JP 2001-188686A (paragraphs 0069 and 0144, FIG. 2)

  In the first related technology described above, when writing data, it is necessary to connect a contact IC card reader / writer to an electronic device in which a NOR flash memory is mounted. Accordingly, ROM writing cannot be performed by an electronic device that is not configured to connect such devices. Further, in the second related technology, it is necessary to store a control program before the addition of functions in the flash ROM on the electronic device side. In other words, the second related technique has a problem that the control program to be corrected must be stored in a normal form in the flash memory on the electronic device side.

  In the above description, the NOR flash memory mounting problem has been described. However, other nonvolatile memories such as the NAND flash memory have the same problem.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic device capable of easily writing data to a nonvolatile memory mounted on a substrate while ensuring security, and a memory access permission determination method for the electronic device.

  In the present invention, (a) a memory that is mounted on a board and is a target for data reading and writing; (b) a CPU that performs predetermined control using the memory; and (c) data stored in the memory from the outside. A connector for performing writing; (d) switch means for selecting one of the CPU and the connector and connecting to the memory; and (e) whether or not data is stored in the memory. Data storage presence / absence determining means for determining; (f) mode determining means for determining whether the CPU is in a normal mode as a mode for accessing the memory; and (g) the mode determining means described above. When it is determined that the mode is not the normal mode, the switch means described above is connected to the connector side described above, and otherwise the switch control means connected to the CPU side is electrically connected. To be provided in the equipment.

  In the present invention, (b) a mode determination step for determining whether or not the CPU is in a mode for accessing the memory mounted on the board; and (b) whether or not data is stored in the memory. And (c) determining that the mode determining step is not the mode accessed by the CPU, and determining that the data storing presence / absence determining step is not storing data in the memory. The memory access permission determining method of the electronic device is provided with an access permission step for permitting external access to the memory only when the memory device has been accessed.

  As described above, according to the present invention, data can be written by connecting the connector to the memory via the switch means in a setting state that is not the mode in which the CPU accesses the memory. Alternatively, data can be written only when it is determined that no data is stored in the memory, so that data is not inadvertently written. Further, only when it is determined that no data is stored in the memory, the memory can be accessed, so that the data in the memory is not inadvertently read out to the outside.

  Next, the present invention will be described together with an embodiment.

  FIG. 1 shows a main part of an electronic device according to an embodiment of the present invention. In the electronic apparatus 201, a CPU 203, a NOR flash memory 204, and a connector 205 are mounted on a built-in board 202. Of these, the connector 205 is connected to a plurality of predetermined terminals of the NOR flash memory 204 via the first signal line group 207. The CPU 203 is connected to the NOR flash memory 204 via the second signal line group 208.

  Here, the first and second signal line groups 207 and 208 are a collection of data lines, address lines, and signal lines, respectively. In addition to this, the NOR flash memory 204 includes a mode selection signal line 209 for selecting whether the mode is a ROM write mode for writing data or a normal mode other than that, and a NOR flash memory. A reset signal line 210 for resetting (initializing) data stored in 204 is connected to a terminal (not shown).

  The second signal line group 208 connecting the CPU 203 and the NOR type flash memory 204 is used in a mode in which the electronic apparatus 201 is normally used, and this mode has existed conventionally. On the other hand, the connector 205 is used when writing data into the NOR flash memory 204 or reading stored data. On the other hand, the connector 205 and the first signal line group 207 that connects the NOR type flash memory 204 and the connector 205 are unique to this embodiment and do not exist in the conventional electronic apparatus.

  FIG. 2 shows a functional configuration of the NOR type flash memory. The NOR type flash memory 204 includes a flash memory unit 221 as an area for storing various data such as programs, and a mode confirmation unit 222 for confirming the current mode.

  Here, a state confirmation unit 241 is arranged in the flash memory unit 221. The state confirmation unit 241 records whether data such as a program is written in the flash memory unit 221 or whether no data is written. When there is a request, the current state of the flash memory unit 221 is sent to the requested mode confirmation unit 222 by a status signal 224.

  FIG. 3 is a diagram for explaining the confirmation principle of the state confirmation unit. The NOR flash memory 204 also shown in FIG. 2 includes a plurality of blocks 251 having a predetermined memory size. For example, the NOR flash memory 204 of the present embodiment has a capacity for storing 64 megabytes of data, and is composed of 1024 blocks 251. In this case, each block 251 has a capacity of 64 kilobytes (KBbytes).

  The status confirmation unit 241 records a signal “0” if even one byte is stored in each block 251, and records a signal “1” when no data is stored. A table 261 is provided. Then, the signal state of each block 251 is scanned and the logical product of these is obtained. When the logical product according to the management table 261 is a signal “1”, it is determined that data is not written in the entire storage area of 64 megabytes. If the logical product is a signal “0”, it is determined that data is written in any of the 64 megabyte storage areas.

  Returning to FIG. 2, the description will be continued. The mode confirmation unit 222 is a mode in which the first signal line group 207 is used by using the state signal 224 from the flash memory unit 221 and the mode selection signal line 209 from the outside of the NOR flash memory 204, or It is determined whether the mode uses the second signal line group 208. Based on the determination result, the multiplexer 262 connects one of the first and second signal line groups 207 and 208 to the third signal line group 225. Here, similarly to the first and second signal line groups 207 and 208, the third signal line group 225 is also a set of data, address, and signal lines (bus structure).

  Now, it is assumed that the mode check unit 222 determines that the first signal line group 207 is to be used by the mode selection signal line 209. In this case, access from the second signal line group 208 to the third signal line group 225 is ignored. On the contrary, it is assumed that the mode check unit 222 determines that the second signal line group 208 is used. In this case, access from the first signal line group 207 to the third signal line group 225 is ignored. The mode selection signal line 209 is electrically set to either the H (high) level or the L (low) level. The enable and disable of the first and second signal line groups 207 and 208 can be determined according to the potential state of the mode selection signal line 209.

  The first and second signal line groups 207 and 208 are connected to one end side of the multiplexer 262, and the third signal line group 225 is connected to the other end side. The mode selection signal line 209 is a control input of the multiplexer 262, and either the first or second signal line group 207, 208 is the third depending on whether the signal level appearing on this signal line is H level or L level. The signal line group 225 is connected.

  FIG. 4 shows an outline of the operation of the electronic device in the present embodiment. This will be described with reference to FIGS. When the electronic device 201 is powered on or the NOR flash memory 204 is initialized by the reset signal line 210, the mode confirmation unit 222 confirms the signal state of the mode selection signal line 209 (step S301). If the mode selection signal line 209 is disabled (NO in step S301), the normal mode is executed (step S304).

  The control as shown in FIG. 4 can be realized by a control program, but can also be incorporated as hardware. In this case, a mode selection signal and a status signal may be input to the 2-input AND gate, and the mode may be switched according to the output.

  FIG. 5 shows the state of data transmission in the NOR flash memory in the normal mode. When the mode selection signal line 209 is disabled, the multiplexer 262 connects the second signal line group 208 to the third signal line group 225. As a result, a signal is transmitted to the flash memory unit 221 via the second signal line group 208. Even if a signal is sent from the first signal line group 207 to the multiplexer 262 at this time, the mode confirmation unit 222 does not send it to the flash memory unit 221.

  Returning to FIG. 4, the description will be continued. When the mode selection signal line 209 is enabled (step S301: Y), the mode confirmation unit 222 checks the current state of the flash memory unit 221 with the state signal 224 output from the state confirmation unit 241 (step S302). As a result, the status signal 224 is the signal “1”, and when it is determined that the data is not written in the storage area of the NOR flash memory 204, that is, it is determined that the data is in the erased state. If (Y), the ROM writing mode is executed (step S303).

  In contrast, although the mode selection signal line 209 is enabled (step S301: Y), the status signal 224 is the signal “0”, and data has already been written in the storage area of the NOR flash memory 204. Suppose that it is determined that the current state has been reached (step S302: N). In this case, if the NOR type flash memory 204 can be accessed from the connector 205 shown in FIG. 1, the program and data already stored in the NOR type flash memory 204 can be read or rewritten from the outside. . In order to prevent the occurrence of such a situation, the normal mode is set for the NOR flash memory except when the status signal 224 is the signal “1” indicating the erased state (step S302: N). It is executed (step S304). Even when it is determined in step S302 that data has been written to the storage area of the NOR flash memory 204 (N), the normal mode is similarly executed (step S304).

  On the other hand, if the status signal is “1” in step S302 and it is determined that data is not written in the storage area of the NOR flash memory 204, that is, it is determined that the data is in the erased state. In this case (Y), there is no fear of reading or rewriting the program or data. Therefore, in this case, the ROM writing mode is executed (step S303).

  FIG. 6 shows the state of data transmission in the NOR type flash memory in the ROM write mode. When the mode selection signal line 209 is enabled, the multiplexer 262 connects the first signal line group 207 to the third signal line group 225. As a result, a signal is transmitted to the flash memory unit 221 via the first signal line group 207. At this time, even if a signal is sent from the second signal line group 208 to the multiplexer 262, the mode confirmation unit 222 does not send it to the flash memory unit 221.

  FIG. 7 shows an outline of processing until the electronic device is first activated in the present embodiment described above. This will be described with reference to FIG.

  The electronic device mounts the NOR flash memory 204 on the substrate 202 (FIG. 1) in the assembly process (step S321), and in this state in which no data is written in the NOR flash memory 204, the connector 205 is used for this. The ROM data is written by connecting the data source of the control program (step S322). Therefore, a conventional ROM writer is not used. It should be noted that some data may remain in the NOR flash memory 204 when writing to the ROM, and writing may not be performed. In such a case, the data remaining in the NOR flash memory 204 may be removed by resetting using the reset signal line 210 before performing ROM writing.

  As described above, after writing the control program necessary for the activation and control of the electronic device in the NOR flash memory 204 in the ROM, the electronic device is activated (step S323).

  As described above, according to the present embodiment, the electronic apparatus 201 can be accessed from an external device via the connector 205 as shown in FIG. Therefore, ROM writing can be performed on the substrate 202 without writing ROM in the flash memory 204 in advance using a ROM writer.

  Moreover, even when the access from the CPU 203 to the NOR flash memory 204 is selected, the status signal 224 indicates that no data is written in the storage area of the NOR flash memory 204. Unless it is, the transition to the ROM writing mode is prohibited. Therefore, data such as a program written in the storage device of the electronic device 201 is not seen by the user via the connector 205, and a situation in which a malicious user alters the data can be avoided.

  In this embodiment, since the reset signal line 210 is connected to the NOR flash memory 204, when data such as a control program is exchanged for the electronic device 201, the previously stored data is easily deleted. There is also an advantage that it can be initialized.

  In the embodiment described above, the example in which the NOR flash memory 204 is used in the electronic device 201 has been described. However, the present invention is not limited to this. For example, the present invention can be similarly applied to the case where another rewritable nonvolatile memory such as a NAND flash memory or a phase change memory is used. That is, the same effect can be obtained even if the flash memory unit 221 shown in FIG. 2 is replaced with such other nonvolatile memory.

It is a block diagram showing the principal part of the electronic device in one embodiment of this invention. 2 is a block diagram showing a functional configuration of a NOR flash memory according to the present embodiment. FIG. It is a principle figure of the management table in the state confirmation part of this Embodiment. It is a flowchart showing the outline | summary of operation | movement of the electronic device in this Embodiment. It is explanatory drawing showing the transmission condition of the data in the NOR type flash memory in a normal mode. It is explanatory drawing showing the transmission condition of the data in the NOR type flash memory in ROM write mode. It is a flowchart showing the outline | summary of the process until an electronic device is first started in this Embodiment. It is the flowchart which showed a series of work until it operates an electronic device using the NOR type flash memory in the conventional method.

Explanation of symbols

201 Electronic Device 202 Substrate 203 CPU
204 NOR type flash memory 205 Connector 209 Mode selection signal line 210 Reset signal line 221 Flash memory unit 224 Status signal 241 Status confirmation unit 262 Multiplexer

Claims (7)

A memory that is mounted on a board and is a target for reading and writing data,
A CPU that performs predetermined control using this memory;
A connector for externally writing data to the memory;
Switch means for selecting any one of the CPU and the connector and connecting to the memory;
Data storage presence / absence determining means for determining whether or not data is stored in the memory;
Mode determining means for determining whether or not the CPU is in a normal mode as a mode for accessing the memory;
An electronic apparatus comprising: switch control means for connecting the switch means to the connector side when the mode discrimination means determines that the mode is not the normal mode, and connecting to the CPU side otherwise.   The electronic device according to claim 1, wherein the connector is attached to the substrate.   The electronic device according to claim 1, wherein the memory is a nonvolatile memory.   The switch control means connects the switch means to the connector side only when it is determined by the data storage presence / absence determining means that no data is stored in the memory. Electronic equipment.   2. The electronic apparatus according to claim 1, further comprising a data erasing unit that collectively erases data stored in the memory. A mode determination step for determining whether or not the CPU is in a mode for accessing the memory mounted on the substrate;
A data storage presence / absence determining step for determining whether data is stored in the memory; and
An access permission step for determining that the mode is not a mode to be accessed by the CPU, and permitting external access to the memory only when the data storage presence / absence determination step determines that no data is stored in the memory; A memory access permission determination method for an electronic device, comprising:   6. The memory access permission determining method according to claim 5, wherein the external access to the memory is an access for writing data.

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