JP2009168952A - Plasma display device - Google Patents

Abstract

An object of the present invention is to provide a plasma display device capable of preventing motion noise.
A plasma display panel (10) in which a plurality of address electrodes are arranged so as to cross a display electrode, and a scan pulse is sequentially supplied to the display electrode in a certain subframe and simultaneously in another subframe. A display electrode drive circuit (20, 30) for supplying scan pulses to the display electrodes, an error diffusion circuit (120) for performing error diffusion processing on display data, and dithering on display data before or after the error diffusion processing Based on the dither processing circuit (130) for inserting a pattern and the display data subjected to the error diffusion processing and the dither pattern insertion processing, among the plurality of display cells corresponding to the scan pulse and constituting the display line Address driving circuit for supplying an address pulse to the address electrode to select a display cell to be lit With a 40) and.
[Selection] Figure 1

Description

  The present invention relates to a plasma display device.

  In recent years, display technology has been further increased in definition and size. The plasma display uses the subframe time division method. In the sub-frame time division method, when one picture is displayed for one frame, the one frame is further divided into sub-frames. The sub-frame emits light during the sustain period by addressing during the address period. A gradation is expressed by selecting a combination to light up the subframe in the address period. In other words, the higher the definition, the greater the number of lines to be addressed, and the longer the address period per subframe. For this reason, it is necessary to reduce the number of subframes and the number of sustains, and there are problems that the number of gradations is insufficient and sufficient luminance cannot be obtained.

  As a driving method for solving the problem, in Patent Document 1 below, since the address time can be shortened by displaying a combination of interlace and progressive, the sustain period is increased to increase the luminance or the number of subframes is increased. Accordingly, there has been proposed a driving method capable of increasing the number of gradations to achieve higher image quality. In addition, a driving method has been proposed in which brightness is increased by causing non-lighted cells to simultaneously emit light with the same data during interlace driving.

JP 2002-182606 A

  However, when the lamp is lit by the above method, the following problems are practically raised. When the input display data is always the same display, if attention is paid to a certain line, there is no difference in display between frames because the error diffusion processing is the same in the progressive drive subframe, but in the interlace drive subframe, Even if the display data is the same line, the data subjected to the error diffusion process is different between the odd-numbered frame and the even-numbered frame, so that the display is different between the frames. Therefore, the difference in error diffusion between frames during interlace driving appears as 30 Hz flicker (motion noise).

  An object of the present invention is to provide a plasma display device capable of preventing motion noise while shortening an address period.

  In the plasma display device of the present invention, one display line is constituted by a display electrode pair composed of two display electrodes, and the display electrode pairs of even display lines and the display electrode pairs of odd display lines are alternately arranged. Each display of the plasma display panel in a plasma display panel in which a plurality of address electrodes are arranged so as to intersect the display electrode and in a subframe among a plurality of subframes weighted in one frame Sequential scan pulses for displaying the lines based on the respective display data are supplied to the display electrodes, and in another subframe, one even display line and one odd number adjacent to the upper and lower sides of the plasma display panel. Simultaneous scan pulse to display based on the same display data as a set of display lines A display electrode driving circuit to be supplied to the display electrode, an error diffusion circuit for performing error diffusion processing on display data, a dither processing circuit for inserting a dither pattern into display data before or after the error diffusion processing, and the error Based on the display data subjected to the diffusion process and the dither pattern insertion process, the address electrode is selected to select a display cell corresponding to the scan pulse and to be lit among a plurality of display cells constituting the display line. And an address driving circuit for supplying an address pulse.

  Since the address period can be shortened by supplying the simultaneous scan pulse, even if the number of display lines is large, one frame can be accommodated within the predetermined period. Further, by inserting a dither pattern, motion noise based on error diffusion processing can be prevented.

(First embodiment)
FIG. 1 is a block diagram showing a configuration example of a plasma display device according to the first embodiment of the present invention. The A / D converter 110 converts the input analog image signal S1 into a digital image signal S2, and outputs a timing signal S3 and a parity signal S4. The error diffusion circuit 120 generates a halftone by error diffusion processing in order to display the input image signal S2 with a lighting pattern having a limited number of bits. For example, the error diffusion circuit 120 performs error diffusion processing on the decimal part of the input image signal S 2 having an integer part and a decimal part, and outputs the result to the dither processing circuit 130. Details of the error diffusion circuit 120 will be described later with reference to FIGS. The dither processing circuit 130 inserts the dither pattern into the integer part and decimal part image signals output from the error diffusion circuit 120 and outputs the integer part to the subframe (SF) conversion circuit 140. Details of the dither processing circuit 130 will be described later with reference to FIGS. The subframe conversion circuit 140 converts the image signal output from the dither processing circuit 130 into a lighting pattern for each subframe. The subframe will be described later with reference to FIGS.

  The drive signal generation circuit 150 generates a drive signal based on the timing signal S3. The selection switch 160 performs a process of shifting one line for sub-frames to be scanned simultaneously according to the parity signal S4, and outputs the result to the Y electrode driver 20. Details thereof will be described later with reference to FIG. The Y electrode driver 20 supplies a voltage to the Y electrode of the plasma display panel 10 according to the drive signal generated by the drive signal generation circuit 150. The X electrode driver 30 supplies a voltage to the X electrode of the plasma display panel 10 according to the drive signal generated by the drive signal generation circuit 150. The address driver 40 supplies a voltage to the address electrode of the plasma display panel 10 according to the lighting pattern converted by the subframe conversion circuit 140. The plasma display panel 10 discharges and emits light according to the voltage of the address electrode, the X electrode, and the Y electrode.

  FIG. 5 is a diagram illustrating a configuration example of the plasma display panel 10, the Y electrode driver 20, the X electrode driver 30, and the address driver 40. The control circuit 50 corresponds to a circuit other than the plasma display panel 10, the Y electrode driver 20, the X electrode driver 30, and the address driver 40 in FIG. 1.

  The Y electrode driver 20 is a circuit that drives Y electrodes (scan electrodes, scan electrodes) Y1, Y2,... Among the display electrodes, and includes a scan circuit (even) 21, a scan circuit (odd) 22, and a sustain circuit 23. Have. In the following, each of the Y electrodes Y1, Y2,... Or their generic name is also referred to as a Y electrode Yi, and i means a subscript.

  The scan circuits 21 and 22 are composed of circuits that generate scan pulses for selecting rows to be displayed by line sequential scanning, and the sustain circuit 23 is a sustain pulse (sustain discharge) for repeating sustain discharge (sustain discharge). Pulse). A predetermined voltage is supplied to the plurality of Y electrodes Yi by the scan circuits 21 and 22 and the sustain circuit 23.

  The scan circuit (even) 21 is provided corresponding to the even-numbered Y electrodes Y2, Y4,... Related to the even-numbered display lines among the display lines, and supplies a drive voltage to the Y electrodes Y2, Y4,. The scan circuit (even) 21 operates so as to sequentially apply the scan pulse to the Y electrodes Y2, Y4,... In the address period, and to apply the sustain pulse from the sustain circuit 23 to the Y electrodes Y2, Y4,. .

  Similarly, the scan circuit (odd) 22 is provided corresponding to the odd-numbered Y electrodes Y1, Y3, Y5,... Related to the odd-numbered display lines, and the drive voltage is applied to the Y electrodes Y1, Y3, Y5,. Supply. The scan circuit (odd) 22 operates so as to sequentially apply the scan pulse to the Y electrodes Y1, Y3,... In the address period, and to apply the sustain pulse from the sustain circuit 23 to the Y electrodes Y1, Y3,. .

  The scan circuit (even) 21 and the sustain circuit 23 are connected, and the scan circuit (odd) 22 and the sustain circuit 23 are connected.

  The X electrode driver 30 is a circuit that drives X electrodes (sustain electrodes) X1, X2,... Among the display electrodes, and includes a sustain circuit 31. Hereinafter, each of the X electrodes X1, X2,... Or their generic name is also referred to as an X electrode Xi, and i means a subscript. The sustain circuit 31 includes a circuit that generates a sustain pulse for repeating sustain discharge (sustain discharge), and supplies a predetermined voltage to the X electrode Xi. One end of the X electrode Xi is commonly connected to the X electrode driver 30.

  The address driver 40 includes a circuit for selecting a column to be displayed, and supplies a predetermined voltage to the plurality of address electrodes A1, A2,. Hereinafter, each of the address electrodes A1, A2,... Or their generic name is also referred to as an address electrode Aj, where j means a subscript.

  The control circuit 50 generates a control signal based on externally input display data, a clock signal, a horizontal synchronization signal, a vertical synchronization signal, and the like. The control circuit 50 supplies the generated control signal to the Y electrode driver 20, the X electrode driver 30, and the address driver 40, and controls these drivers 20, 30, and 40.

  In the plasma display panel 10, the Y electrode Yi and the X electrode Xi constituting the display electrode pair form a row extending in parallel in the horizontal direction, and the address electrode Aj forms a column extending in the vertical direction. The Y electrode Yi and the X electrode Xi are arranged in a predetermined arrangement pattern in the vertical direction and in parallel with each other. The address electrode Aj is arranged in a direction substantially perpendicular to the Y electrode Yi and the X electrode Xi. The Y electrode Yi and the address electrode Aj form a two-dimensional matrix with i rows and j columns.

  Here, in the plasma display panel 10 according to this embodiment, a display electrode pair including two electrodes (a pair of Y electrode Yi and X electrode Xi) is arranged for one display line, and the adjacent display lines are arranged. The display electrode is not shared. That is, with p as a natural number, an odd display line in the display line is configured by a set of Y electrode Y (2p-1) and X electrode X (2p-1), and Y electrode Y (2p) and X electrode X (2p) ) To form an even display line. For example, a first display line is configured by a set of Y electrode Y1 and X electrode X1, and a second display line is configured by a set of Y electrode Y2 and X electrode X2.

  The display cell Cij is formed by the intersection of the Y electrode Yi and the address electrode Aj and the X electrode Xi adjacent thereto corresponding thereto. This display cell Cij corresponds to, for example, red, green, and blue sub-pixels, and one pixel is constituted by these three-color sub-pixels. The panel 10 displays an image by lighting a plurality of pixels arranged two-dimensionally. The scanning circuits 21 and 22 in the Y electrode driver 20 and the address driver 40 determine which display cells are to be lit, and the discharge is repeatedly performed by the sustain circuit 23 in the Y electrode driver 20 and the sustain circuit 31 in the X electrode driver 30. By doing so, a display operation is performed.

  FIG. 6 is an exploded perspective view showing a configuration example of the plasma display panel 10 according to the present embodiment.

  A display electrode (also referred to as a sustain electrode) including a bus electrode (metal electrode) 12 and a transparent electrode 13 is formed on the front glass substrate 11. The display electrodes (12, 13) correspond to the Y electrode Yi and the X electrode Xi shown in FIG. A dielectric layer 14 is provided on the display electrodes (12, 13), and an MgO (magnesium oxide) protective film 15 is further provided thereon. That is, the display electrodes (12, 13) arranged on the front glass substrate 11 are covered with the dielectric layer 14, and the surface thereof is further covered with the MgO protective film 15.

  Address electrodes 17R, 17G, and 17B are formed on the rear glass substrate 16 disposed to face the front glass substrate 11 in a direction orthogonal to the display electrodes (12, 13). Address electrodes 17R, 17G, and 17B correspond to address electrode Aj shown in FIG. A dielectric layer 18 is provided on the address electrodes 17R, 17G, and 17B.

  Furthermore, on the dielectric layer 18, closed barrier ribs (ribs) 19 arranged in a lattice pattern, that is, partitioning the discharge space for each display cell, and red (R) and green (G) for color display. The phosphor layers PR, PG, and PB that emit blue (B) visible light are formed. The phosphor layers PR, PG, and PB are excited by ultraviolet rays generated by surface discharge between the paired display electrodes (12, 13), and each color emits light.

  The barrier ribs 19 include vertical barrier ribs (vertical ribs) formed in the direction in which the address electrodes 17R, 17G, and 17B extend, and horizontal barrier ribs (horizontal ribs) formed in the direction in which the display electrodes (12, 13) extend. That is, the plasma display panel 10 according to the present embodiment has a closed partition structure.

  In the phosphor layers PR, PG, and PB, a phosphor layer PR that emits red light is formed above the address electrode 17R, and a phosphor layer PG that emits green light is formed above the address electrode 17G. A phosphor layer PB that emits blue light is formed above. In other words, the address electrodes 17R, 17G, and 17B are arranged so as to correspond to the red, green, and blue phosphor layers PR, PG, and PB applied to the inner surface of the partition wall 19 corresponding to the display cell.

  In the plasma display panel 10, the front glass substrate 11 and the rear glass substrate 16 are sealed so that the protective film 15 and the partition wall 19 are in contact with each other, and the inside thereof (discharge space between the front glass substrate 11 and the rear glass substrate 16). And a discharge gas such as Ne-Xe is enclosed.

  2A to 2C are diagrams for explaining an example of a driving method of the plasma display panel 10. One frame (odd frame or even frame) is, for example, 16.7 ms and includes a plurality of subframes (SF). 2A to 2C, for the sake of drawing, a configuration in which one frame is composed of five subframes SF1, SF2, SF3, SF4, and SF5 is illustrated. Consists of subframes.

  Each subframe SF1 to SF5 includes a reset period Tr, an address period Ta, and a sustain period Ts. In the reset period Tr, the wall charge state on the electrode is initialized. In the address period Ta, the display cell to be lit by adjusting the wall charge state is selected based on the display data, and the display data is handled in the sustain period Ts. The selected display cell is turned on (the display cell selected according to the display data is discharged to emit light). By selecting which subframes SF1 to SF5 are lit, gradation expression is realized.

  First, the frame in FIG. 2A will be described. In the address period Ta of all the subframes SF1 to SF5, sequential scanning is performed for each line. As a result, the address period Ta is relatively long, and independent data is displayed for each line. Details thereof will be described later with reference to FIGS. Hereinafter, this scanning method is referred to as sequential scanning. In this method, when the number of display lines increases due to high definition, the address period Ta becomes long, and one frame cannot be accommodated within 16.7 ms.

  Next, the frame in FIG. 2C will be described. In the address period Ta of all the subframes SF1 to SF5, the same data is simultaneously scanned every two adjacent lines. As a result, the address period Ta is relatively short (about half of the address period Ta in FIG. 2A), and the two adjacent lines display the same data. Details thereof will be described later with reference to FIGS. Hereinafter, this scanning method is referred to as simultaneous scanning. By halving the address period Ta, one frame can be kept within 16.7 ms. However, since the two adjacent lines are displayed with the same data, the resolution is lowered and the image quality is deteriorated.

  Next, the frame of FIG. 2B according to the present embodiment will be described. Simultaneous scanning is performed in the address period Ta of the subframes SF1 to SF3, and the address period Ta is made relatively short. In the address periods Ta of the subframes SF4 and SF5, scanning is sequentially performed so that the address period Ta is relatively long. As a result, even if the number of display lines increases due to high definition, one frame can be kept within 16.7 ms, and image quality deterioration can be prevented as much as possible.

  At this time, it is preferable to simultaneously scan a predetermined number of subframes SF1 to SF3 having a smaller weight. The weight of the subframe is determined by the length (number of sustain pulses) of the sustain period Ts in the subframe. From the subframe SF1 toward the subframe SF5, the sustain period Ts is sequentially increased and the weight is increased. By selecting whether or not each of the weighted subframes is lit in the address period Ta, gradation expression is possible. When scanning at the same time, the vertical resolution as a still image decreases. Therefore, by simultaneously scanning a predetermined number of subframes SF1 to SF3 having a smaller weight, a decrease in the vertical resolution can be suppressed.

  FIG. 3 is a diagram illustrating an example of an odd frame and an even frame that are sequentially scanned. The sequential scan is performed in the subframes SF1 to SF5 in FIG. 2A and the subframes SF4 and SF5 in FIG. In accordance with the input image signal, the plasma display panel 10 displays the display data D1 to D10 on the lines L1 to L10, respectively, in the odd frames, and the display data E1 to E10 on the lines L1 to L10, respectively, in the even frames. That is, the plasma display panel 10 inputs progressive display data and performs progressive display.

  FIG. 4 is a diagram illustrating an example of an odd frame and an even frame that perform simultaneous scanning. The simultaneous scanning is performed in the subframes SF1 to SF3 in FIG. 2B and the subframes SF1 to SF5 in FIG. The plasma display panel 10 displays the same display data D1 on the lines L1 and L2 and the same display data D3 on the lines L3 and L4 in an odd frame based on the input image signal (progressive display data in FIG. 3). The same display data D5 is displayed on the lines L5 and L6, the same display data D7 is displayed on the lines L7 and L8, and the same display data D9 is displayed on the lines L9 and L10. In the even frame, the display data E1 is displayed on the line L1, the same display data E2 is displayed on the lines L2 and L3, the same display data E4 is displayed on the lines L4 and L5, and the same display data E6 is displayed on the lines L6 and L7. The same display data E8 is displayed on the lines L8 and L9, and the display data D10 is displayed on the line L10.

  As described above, in each frame, the same display data is displayed with a pair of two lines vertically adjacent to each other. Thereby, the length of the address period Ta can be halved. Further, the selection switch 160 in FIG. 1 performs a process for shifting the two-line group of the odd frame and the two-line group of the even frame by one line. Thereby, it is possible to prevent the deterioration of the vertical resolution.

  FIG. 7 is a diagram illustrating an example of a driving waveform for sequential scanning of the plasma display apparatus according to the present embodiment. The sequential scan is performed in the subframes SF1 to SF5 in FIG. 2A and the subframes SF4 and SF5 in FIG. FIG. 7 shows an example of drive waveforms related to the X electrode Xi, the Y electrode Yi, and the address electrode Aj in one subframe among a plurality of subframes constituting one frame. In FIG. 7, A is a voltage waveform applied to the address electrode Aj, X is a voltage waveform applied to the X electrode Xi, Yo is a voltage waveform applied to the Y electrode Yi of the odd display line, and Ye is an even display line. The voltage waveform applied to the Y electrode Yi is shown.

  In the reset period Tr, the display cell Cij is initialized. In the reset period Tr, positive obtuse waves are simultaneously applied to the Y electrodes Yi (Yo and Ye) to form wall charges, and subsequently negative obtuse waves are simultaneously applied to the walls of the display cell Cij. Adjust the amount of charge.

  In the address period Ta, a scan pulse is sequentially applied to the Y electrode Yi, and an address pulse is applied to the address electrode Aj in accordance with the display data in accordance with the scan pulse (by address designation), whereby light emission of each display cell Cij ( A scanning operation is performed to select lighting (on) or non-emission (off). In the sequential scan address period Ta, as shown in FIG. 3, scan pulses are sequentially supplied to all the Y electrodes Yi, and different data is written in the display cells of the Y electrodes Yi.

  In the sustain period Ts, opposite-phase sustain pulses are applied between the X electrode Xi and the Y electrode Yi (Yo and Ye), and the X electrode Xi and Y electrode Yi (Yo and Ye) of the display cell selected in the address period Ta. ) To generate a light emission. In the sustain period Ts, the sustain pulses applied to the Y electrode Yo and the Y electrode Ye are in phase.

  FIG. 8 is a diagram illustrating an example of a driving waveform for simultaneous scanning of the plasma display apparatus according to the present embodiment. The simultaneous scanning is performed in the subframes SF1 to SF3 in FIG. 2B and the subframes SF1 to SF5 in FIG. Hereinafter, the points of FIG. 8 different from FIG. 7 will be described.

  In the address period Ta, two Y electrodes Yi are combined and sequentially applied with a scan pulse, and in response to the scan pulse, an address pulse is applied to the address electrode Aj according to display data (by address designation). A scanning operation for selecting light emission (lighting) or non-light emission (lighting off) of the display cell Cij is performed. Specifically, as shown in FIG. 4, in the address period Ta, in the case of an odd frame, the (2n + 1) th line which is an odd display line and the (2n + 2) th line which is an even display line. Simultaneously, a scan operation is performed, and the same data is written in the corresponding display cell. In the case of an even frame, a scan operation is simultaneously performed on the (2n + 2) th line that is an even display line and the (2n + 3) th line that is an odd display line, and the same data is stored in the corresponding display cell. Write. By the simultaneous scanning, the display cells Cij in the same column can be selected in the odd display lines and the even display lines constituting one set.

  In other words, in the present embodiment, a scan operation is performed with each pair of adjacent odd display lines and even display lines as one set, and the same data is written in the corresponding display cells of the two lines. For example, in an odd frame, data written to the display cell C11 shown in FIG. 5 is also written to the display cell C21, and data written to the display cell C31 is also written to the display cell C41. Similarly, in the even-numbered frame, data written to the display cell C21 shown in FIG. 5 is also written to the display cell C31, and data written to the display cell C41 is also written to the display cell C51. Thereby, the length of the address period Ta can be halved. In the case of an odd frame, the (2n + 1) th line and the (2n) th line are simultaneously scanned, and in the case of an even frame, the (2n + 2) th line and the (2n + 1) th line are scanned. The scanning operation may be performed simultaneously.

  In the sustain period Ts, opposite-phase sustain pulses are applied between the X electrode Xi and the Y electrode Yi (Yo and Ye), and the X electrode Xi and Y electrode Yi (Yo and Ye) of the display cell selected in the address period Ta. ) To generate a light emission.

  The number of sustain pulses in the sustain period Ts in the case of sequential scanning in FIG. 7 is the same as the number of sustain pulses in the sustain period Ts in the case of simultaneous scanning in FIG. It is not necessary to be completely the same.

  In the simultaneous scan, the display operation is performed simultaneously with two lines as one set. Here, assuming that two lines forming a set are regarded as one line, as shown in FIG. 4, the display line positions are shifted in the odd and even frames. Thereby, it is possible to prevent the deterioration of the vertical resolution.

  As described above, according to the present embodiment, the same data is simultaneously scanned in specific subframes SF1 to SF3, with two upper and lower adjacent lines in one frame of the progressive display panel 10 as one set.

  FIG. 9 is a circuit diagram showing a configuration example of the error diffusion circuit 120 of FIG. 1, and FIG. 10 is a diagram showing the error diffusion target pixel PA and its adjacent pixels PB, PC, PD, and PE. The target pixel PA has coordinates (x, y). Here, in the coordinates (X, Y), the X axis indicates the horizontal direction, and the Y axis indicates the vertical direction. The adjacent pixel PB is a pixel on the left of the target pixel PA, and the coordinates are (x-1, y). The adjacent pixel PC is the upper left pixel of the target pixel PA, and the coordinates are (x−1, y−1). The adjacent pixel PD is a pixel above the target pixel PA, and the coordinates are (x, y−1). The adjacent pixel PE is the upper right pixel of the target pixel PA, and the coordinates are (x + 1, y−1). The error diffusion process proceeds from the pixel at the upper left corner of the two-dimensional image in the right horizontal direction, then proceeds from the left end of the horizontal line below to the right horizontal direction, and so on. Do until.

  The separation unit 401 separates the digital pixel data IN of the target pixel PA into upper bit pixel data AB and lower bit pixel data Ea. The pixel data IN is p bits, the upper bit pixel data AB is an m-bit integer part, the lower bit pixel data Ea is an n-bit decimal part, and has a relationship of p = m + n. For example, p is 16 and m and n are 8. The lower bit pixel data Ea is error data of the target pixel PA.

  The one line delay circuit 403 delays the previous transmission error data Ef by one line and outputs the transmission error data Ec of the adjacent pixel PC. That is, the one-line delay circuit 403 stores transmission error data Ef for the past one line. The flip-flop 404 delays the transmission error data Ec by one pixel and outputs the transmission error data Ed of the adjacent pixel PD. The flip-flop 405 delays the transmission error data Ed by one pixel and outputs the transmission error data Ee of the adjacent pixel PE. The flip-flop 406 delays the previous transmission error data Ef by one pixel and outputs the transmission error data Eb of the adjacent pixel PB.

  The multiplication circuit 407 multiplies the transmission error data Ec by, for example, 3/16 as an adjacent pixel weighting coefficient, and outputs weighted transmission error data. The multiplication circuit 408 multiplies the transmission error data Ed by, for example, 5/16 as an adjacent pixel weighting coefficient, and outputs weighted transmission error data. The multiplication circuit 409 multiplies the transmission error data Ee by 1/16 as an adjacent pixel weighting coefficient, for example, and outputs weighted transmission error data. The multiplication circuit 410 multiplies the transmission error data Eb by, for example, 7/16 as an adjacent pixel weighting coefficient, and outputs weighted transmission error data.

  The addition circuit 411 adds the error data Ea and the output data of the multiplication circuits 407 to 410, and outputs an addition value Ef and a carry value CO. The added value Ef becomes transmission error data of the target pixel PA, and is used for error diffusion processing of other pixels. The six error data Ea to Ef are all n bits (for example, 8 bits). The carry value CO is 1 bit, and is 1 when there is a carry, and 0 when there is no carry.

  The adder circuit 402 adds the upper bit pixel data AB and the carry value CO of the target pixel PA, and outputs the output pixel data OUT of the target pixel PA. The output pixel data OUT is m bits (for example, 8 bits), and has the same value as the pixel data AB or a value obtained by adding 1 to the pixel data AB. The error diffusion circuit 120 outputs the integer part pixel data OUT and the fractional part pixel data Ef to the dither processing circuit 130.

  FIGS. 11A to 11C are diagrams showing frames when the interlaced image signal is simultaneously scanned. FIG. 11A shows an input interlaced image signal. In the odd frame, the display data of the first line is D1, and the display data of the third line is D3. In the even frame, the display data of the second line is D2, and the display data of the fourth line is D4. An odd frame and an even frame form one image.

  FIG. 11B is a diagram showing display data when simultaneous scanning is performed in all subframes SF1 to SF3 in an odd-numbered frame. As in FIG. 4, in all the subframes SF1 to SF3, the first line and the second line become the first line display data D1, and the third line and the fourth line become the third line display data D3.

  FIG. 11C is a diagram showing display data when all subframes SF1 to SF3 are scanned simultaneously in an even frame. As in FIG. 4, in all the subframes SF1 to SF3, the second line and the third line become the second line display data D2, and the fourth line and the fifth line become the fourth line display data D4.

  Here, the error diffusion processing in the error diffusion circuit 120 of FIG. 1 will be described. Since the error diffusion processing of the odd-frame display data D1 and the error diffusion processing of the even-frame display data D2 are linked, almost no noise is generated by the error diffusion processing.

  FIGS. 12A to 12E are diagrams showing the frame of FIG. 2B in which the dither processing is not performed. 2B shows an example in which the subframes SF1 to SF3 are simultaneously scanned, but FIGS. 12A to 12E show examples in which the subframes SF1 and SF3 are sequentially scanned to simultaneously scan the subframe SF2. Show.

  FIG. 12A is a diagram illustrating an input progressive image signal. As shown in FIG. 3, in the odd-numbered frame, the display data for the first line is D1, the display data for the second line is D2, the display data for the third line is D3, and the display data for the fourth line is D4. In the even frame, the display data of the first line is E1, the display data of the second line is E2, the display data of the third line is E3, and the display data of the fourth line is E4.

  FIG. 12B is a diagram showing display data when the odd frames are sequentially scanned in the subframes SF1 and SF3 and simultaneously scanned in the subframe SF2. As in FIG. 3, in the subframes SF1 and SF3, the first line becomes the first line display data D1, the second line becomes the second line display data D2, and the third line becomes the third line display data D3. Thus, the fourth line becomes the fourth line display data D4. Similarly to FIG. 4, in the subframe SF2, the first line and the second line become the first line display data D1, and the third line and the fourth line become the third line display data D3.

  FIG. 12C is a diagram showing display data when the even frames are sequentially scanned in the subframes SF1 and SF3 and are simultaneously scanned in the subframe SF2. As in FIG. 3, in the subframes SF1 and SF3, the first line becomes the first line display data E1, the second line becomes the second line display data E2, and the third line becomes the third line display data E3. Thus, the fourth line becomes the fourth line display data E4. Similarly to FIG. 4, in the subframe SF2, the second line and the third line become the second line display data E2, and the fourth line and the fifth line become the fourth line display data E4.

  12D and 12E are diagrams showing display data of each display cell Cij in the sub-frame SF2 of the odd frame and the even frame, and show the display data when the dither processing circuit 130 of FIG. 1 is not provided. In the display cell Cij, red (R), green (G), and blue (B) display cells are repeatedly arranged in the horizontal direction. One display cell Cij corresponds to a sub pixel, and three color display cells Cij constitute one pixel. The image signal S2 in FIG. 1 is separated into signals for red, green, and blue colors, and has different display data for each color.

  FIG. 12D shows display data of each display cell in the subframe SF2 in the odd-numbered frame in FIG. Each display cell of the first line and the second line becomes the first line display data D1, and each display cell of the third line and the fourth line becomes the third line display data D3. Here, it is assumed that the input image signal S2 of all the display cells Cij is the same display data, and the display data is a value between adjacent gradation values. In this case, error diffusion processing is performed by the error diffusion circuit 120 of FIG. 1, for example, the display cell Cij indicated by hatching is not selected in the address period Ta, and the display cell Cij without hatching is selected in the address period Ta. Light.

  FIG. 12E shows display data of each display cell in the subframe SF2 in the even frame in FIG. Each display cell of the second line and the third line becomes the second line display data E2, and each display cell of the fourth line and the fifth line becomes the fourth line display data E4. Here, it is assumed that the input image signal S2 of all the display cells Cij is the same display data, and the display data is a value between adjacent gradation values. In this case, error diffusion processing is performed by the error diffusion circuit 120 of FIG. 1, for example, the display cell Cij indicated by hatching is not selected in the address period Ta, and the display cell Cij without hatching is selected in the address period Ta. Light.

  Since the error diffusion process of the odd frame in FIG. 12B and the error diffusion process of the even frame in FIG. 12C are independent, the lit display cell in the odd frame in FIG. ) Is not related to the lighting display cell in the even frame. Due to the error diffusion process, the lighting display cells are randomly determined between the odd-numbered frame and the even-numbered frame as described above. As a result, the difference in error diffusion between frames appears as 30 Hz flicker (motion noise). In the present embodiment, this motion noise is prevented by the dither processing circuit 130 of FIG.

  13A to 13F are diagrams for explaining the processing of the dither processing circuit 130 according to the present embodiment. FIGS. 13B to 13D are diagrams illustrating the frame of FIG. FIG. 2B shows an example in which the subframes SF1 to SF3 are simultaneously scanned, but FIGS. 13B to 13D show examples in which the subframes SF1 and SF3 are sequentially scanned to simultaneously scan the subframe SF2. Show.

  FIG. 13A is a diagram showing a dither pattern that the dither processing circuit 130 inserts into the input image signal. The dither pattern is added to the display data as a dither pattern of 2 rows × 2 columns (2 × 2) display cells. With the 2 × 2 dither pattern as one block, the two-dimensional display cell is divided into a plurality of blocks, and a dither pattern is inserted into each block. For example, in the 2 × 2 dither pattern, “+ A” is added to the display data of the upper left display cell and the lower right display cell, and “−A” is added to the display data of the upper right display cell and the lower left display cell. Is added. When the difference between adjacent gradation values is 1, “A” is, for example, 0.5. When the difference between adjacent gradation values is 2, “A” is, for example, 1.5.

  FIG. 13B is a diagram showing the progressive image signal after the dither pattern is inserted, and shows the display data of the display cells in the first column of the odd frames and the display cells in the first column of the even frames. The dither processing circuit 130 outputs the image signal of FIG. 13B by inserting the dither pattern of FIG. 13A into the image signal of FIG. As shown in FIG. 13A, the dither processing circuit 130 adds “+ A” to the odd lines and adds “−A” to the even lines in the first column. As a result, in the first column of the odd frame, the display data of the first line is D1 + A, the display data of the second line is D2-A, the display data of the third line is D3 + A, and the display data of the fourth line is D4-A. It is. In the even frame, the display data of the first line is E1 + A, the display data of the second line is E2-A, the display data of the third line is E3 + A, and the display data of the fourth line is E4-A.

  FIG. 13C is a diagram showing display data when the odd frames are sequentially scanned in the subframes SF1 and SF3 and simultaneously scanned in the subframe SF2. Similarly to FIG. 13B, in the subframes SF1 and SF3, the first line is the first line display data D1 + A, the second line is the second line display data D2-A, and the third line is the third line. The line display data becomes D3 + A, and the fourth line becomes the fourth line display data D4-A. In the subframe SF2, the first line and the second line become the first line display data D1 + A, and the third line and the fourth line become the third line display data D3 + A.

  FIG. 13D is a diagram showing display data when the even frames are sequentially scanned in the subframes SF1 and SF3 and are simultaneously scanned in the subframe SF2. As in FIG. 13B, in the subframes SF1 and SF3, the first line is the first line display data E1 + A, the second line is the second line display data E2-A, and the third line is the third line. Line display data E3 + A, and the fourth line becomes fourth line display data E4-A. In the subframe SF2, the second line and the third line become the second line display data E2-A, and the fourth line and the fifth line become the fourth line display data E4-A.

  FIGS. 13E and 13F are diagrams showing display data of the display cells Cij of the subframe SF2 of the odd frame and the even frame. In the display cell Cij, red (R), green (G), and blue (B) display cells are repeatedly arranged in the horizontal direction. One display cell Cij corresponds to a sub pixel, and three color display cells Cij constitute one pixel. The image signal S2 in FIG. 1 is separated into signals for red, green, and blue colors, and has different display data for each color.

  FIG. 13E is a diagram showing display data of each display cell in the subframe SF2 in the odd-numbered frame in FIG. 13C. In the odd-numbered display cells of the first column and the third column, the first line and the second line become the first line display data D1 + A, and the third line and the fourth line are the same as in FIG. 13C. The 3-line display data D3 + A is obtained.

  On the other hand, as shown in FIG. 13A, “−A” is added to the odd-numbered lines and “+ A” is added to the even-numbered lines in the display cells in the second and fourth even-numbered columns. . As a result, by the simultaneous scanning, as shown in FIG. 13E, the first line and the second line become the first line display data D1-A, and the third line and the fourth line become the third line display data D3. -A.

  Here, when the input image signal S2 of all the display cells Cij is the same display data, and the display data is a value between adjacent gradation values, it is indicated by a hatch to which “−A” is added. The display cell to be displayed is turned off without being selected in the address period Ta, and the display cell having no hatch to which “+ A” is added is selected and turned on in the address period Ta. By inserting the dither pattern, it is possible to fix the pattern of the display cell that is lit by the error diffusion process.

  FIG. 13F is a diagram showing display data of each display cell in the subframe SF2 in the even frame in FIG. 13D. In the odd-numbered display cells in the first column and the third column, the second line and the third line become the second line display data E2-A, as in FIG. 13D, and the fourth line and the fifth line. Becomes the fourth line display data E4-A.

  On the other hand, as shown in FIG. 13A, “−A” is added to the odd-numbered lines and “+ A” is added to the even-numbered lines in the display cells in the second and fourth even-numbered columns. . As a result, by the simultaneous scanning, as shown in FIG. 13F, the second line and the third line become the second line display data E2 + A, and the fourth line and the fifth line become the fourth line display data E4 + A. .

  Here, when the input image signal S2 of all the display cells Cij is the same display data, and the display data is a value between adjacent gradation values, it is indicated by a hatch to which “−A” is added. The display cell to be displayed is turned off without being selected in the address period Ta, and the display cell having no hatch to which “+ A” is added is selected and turned on in the address period Ta. By inserting the dither pattern, it is possible to fix the pattern of the display cell that is lit by the error diffusion process.

  As described above, motion noise can be prevented by fixing the pattern of the display cell that is turned on by error diffusion processing, not random, in the odd-numbered frame and the even-numbered frame.

  In FIG. 1, the dither processing circuit 130 inserts the dither pattern of FIG. 13A into the integer part image signal OUT and the fractional part image signal Ef of FIG. 9 output from the error diffusion circuit 120. In the address period Ta, the address driver 40 selectively outputs the address pulses of all the lines sequentially in the sub-frames of the sequential scan according to the image signal. In addition, in the address period Ta, the address driver 40 selectively outputs only the odd-line address pulses in the odd-numbered frame in the simultaneous scan sub-frames sequentially in the address period Ta, and the even-line address pulses in the even-numbered frame. Are output sequentially. As a result, the address period Ta can be reduced to about ½ during simultaneous scanning compared to sequential scanning.

(Second Embodiment)
14A to 14F are diagrams for explaining the processing of the dither processing circuit 130 according to the second embodiment of the present invention. In the present embodiment, the dither pattern in FIG. 14A is different from the dither pattern in FIG. 13A of the first embodiment. Hereinafter, the points of the present embodiment different from the first embodiment will be described. 14B to 14D are diagrams illustrating the frame of FIG. FIGS. 14B to 14D show examples in which the subframes SF1 and SF3 are sequentially scanned and the subframe SF2 is simultaneously scanned.

  FIG. 14A is a diagram showing a dither pattern that the dither processing circuit 130 inserts into the input image signal. In the dither pattern of the 4 rows and 2 columns (4 × 2) display cell, “+ A” is added to the display data of the 1 row, 1 column, 2 rows, 1 column, 3 rows, 2 columns and 4 rows, 2 columns display cell, “−A” is added to the display data of the display cells in the first row, second column, second row, second column, third row, first column, and fourth row, first column. A line indicates a line.

  FIG. 14B is a diagram showing the progressive image signal after the dither pattern is inserted, and shows the display data of the display cells in the first column of the odd frames and the display cells in the first column of the even frames. The dither processing circuit 130 outputs the image signal of FIG. 14B by inserting the dither pattern of FIG. 14A into the image signal of FIG. As shown in FIG. 14A, the dither processing circuit 130 adds “+ A” to the first line and the second line and adds “−A” to the third line and the fourth line in the first column. To do. As a result, in the first column of the odd frame, the display data of the first line is D1 + A, the display data of the second line is D2 + A, the display data of the third line is D3-A, and the display data of the fourth line is D4-A. It is. In the even frame, the display data for the first line is E1 + A, the display data for the second line is E2 + A, the display data for the third line is E3-A, and the display data for the fourth line is E4-A.

  FIG. 14C is a diagram showing display data when the odd frames are sequentially scanned in the subframes SF1 and SF3 and simultaneously scanned in the subframe SF2. As in FIG. 14B, in the subframes SF1 and SF3, the first line is the first line display data D1 + A, the second line is the second line display data D2 + A, and the third line is the third line display. It becomes data D3-A, and the fourth line becomes fourth line display data D4-A. In the subframe SF2, the first line and the second line become the first line display data D1 + A, and the third line and the fourth line become the third line display data D3-A.

  FIG. 14D is a diagram showing display data when the even frames are sequentially scanned in the subframes SF1 and SF3 and are simultaneously scanned in the subframe SF2. As in FIG. 14B, in the subframes SF1 and SF3, the first line is the first line display data E1 + A, the second line is the second line display data E2 + A, and the third line is the third line display. It becomes data E3-A, and the fourth line becomes fourth line display data E4-A. In the subframe SF2, the second line and the third line become the second line display data E2 + A, and the fourth line and the fifth line become the fourth line display data E4-A.

  FIGS. 14E and 14F are diagrams showing display data of each display cell Cij in the sub-frame SF2 of the odd-numbered frame and the even-numbered frame. In the display cell Cij, red (R), green (G), and blue (B) display cells are repeatedly arranged in the horizontal direction.

  FIG. 14E is a diagram showing display data of each display cell in the subframe SF2 in the odd-numbered frame in FIG. 14C. In the odd-numbered display cells of the first column and the third column, the first line and the second line become the first line display data D1 + A, and the third line and the fourth line are the same as in FIG. 13C. It becomes 3-line display data D3-A.

  On the other hand, as shown in FIG. 14A, in the display cells in the even columns of the second column and the fourth column, “−A” is added to the first line and the second line, and the third line and the fourth line are added. “+ A” is added to the 4th line. As a result, by the simultaneous scanning, as shown in FIG. 14E, the first line and the second line become the first line display data D1-A, and the third line and the fourth line become the third line display data D3 + A. become.

  Here, when the input image signal S2 of all the display cells Cij is the same display data, and the display data is a value between adjacent gradation values, it is indicated by a hatch to which “−A” is added. The display cell to be displayed is turned off without being selected in the address period Ta, and the display cell having no hatch to which “+ A” is added is selected and turned on in the address period Ta. By inserting the dither pattern, it is possible to fix the pattern of the display cell that is lit by the error diffusion process.

  FIG. 14F is a diagram showing display data of each display cell in the subframe SF2 in the even frame in FIG. In the odd-numbered display cells of the first column and the third column, the second line and the third line become the second line display data E2 + A, and the fourth line and the fifth line are the same as in FIG. 14D. It becomes the 4-line display data E4-A.

  On the other hand, as shown in FIG. 14A, in the display cells in the even columns of the second column and the fourth column, “−A” is added to the first line and the second line, and the third line and the fourth line are added. “+ A” is added to the 4th line. As a result, by the simultaneous scanning, as shown in FIG. 14F, the second line and the third line become the second line display data E2-A, and the fourth line and the fifth line become the fourth line display data E4 + A. become.

  Here, when the input image signal S2 of all the display cells Cij is the same display data, and the display data is a value between adjacent gradation values, it is indicated by a hatch to which “−A” is added. The display cell to be displayed is turned off without being selected in the address period Ta, and the display cell having no hatch to which “+ A” is added is selected and turned on in the address period Ta. By inserting the dither pattern, it is possible to fix the pattern of the display cell that is lit by the error diffusion process.

  As described above, motion noise can be prevented by fixing the pattern of the display cell that is turned on by error diffusion processing, not random, in the odd-numbered frame and the even-numbered frame.

(Third embodiment)
FIGS. 15A to 15F are diagrams for explaining the processing of the dither processing circuit 130 according to the third embodiment of the present invention. In this embodiment, the dither pattern in FIG. 15A is different from the dither pattern in FIG. 13A of the first embodiment. Hereinafter, the points of the present embodiment different from the first embodiment will be described. FIGS. 15B to 15D are diagrams illustrating the frame of FIG. 15B to 15D show an example in which the subframes SF1 and SF3 are sequentially scanned and the subframe SF2 is simultaneously scanned.

  FIG. 15A is a diagram illustrating a dither pattern that the dither processing circuit 130 inserts into the input image signal. In the dither pattern of 2 rows and 4 columns (2 × 4) display cells, “+ A” is added to the display data of the display cells of 1 row, 1 column, 1 row, 2 columns, 2 rows, 3 columns and 2 rows, 4 columns, “−A” is added to the display data of the display cells in the first row, third column, first row, fourth column, second row, first column, and second row, second column.

  FIG. 15B is a diagram showing the progressive image signal after the dither pattern is inserted, and shows the display data of the display cells in the first column of the odd frames and the display cells in the first column of the even frames. The dither processing circuit 130 outputs the image signal of FIG. 15B by inserting the dither pattern of FIG. 15A into the image signal of FIG. As shown in FIG. 15A, the dither processing circuit 130 adds “+ A” to the first line and adds “−A” to the second line in the first column. As a result, in the first column of the odd frame, the display data of the first line is D1 + A, the display data of the second line is D2-A, the display data of the third line is D3 + A, and the display data of the fourth line is D4-A. It is. In the even frame, the display data of the first line is E1 + A, the display data of the second line is E2-A, the display data of the third line is E3 + A, and the display data of the fourth line is E4-A.

  FIG. 15C is a diagram showing display data when the odd frames are sequentially scanned in the subframes SF1 and SF3 and are simultaneously scanned in the subframe SF2. Similarly to FIG. 15B, in the subframes SF1 and SF3, the first line is the first line display data D1 + A, the second line is the second line display data D2-A, and the third line is the third line. The line display data becomes D3 + A, and the fourth line becomes the fourth line display data D4-A. In the subframe SF2, the first line and the second line become the first line display data D1 + A, and the third line and the fourth line become the third line display data D3 + A.

  FIG. 15D is a diagram showing display data when the even frames are sequentially scanned in the subframes SF1 and SF3 and are simultaneously scanned in the subframe SF2. Similarly to FIG. 15B, in the subframes SF1 and SF3, the first line is the first line display data E1 + A, the second line is the second line display data E2-A, and the third line is the third line. Line display data E3 + A, and the fourth line becomes fourth line display data E4-A. In the subframe SF2, the second line and the third line become the second line display data E2-A, and the fourth line and the fifth line become the fourth line display data E4-A.

  FIGS. 15E and 15F are diagrams showing display data of the display cells Cij of the subframe SF2 of the odd frame and the even frame. In the display cell Cij, red (R), green (G), and blue (B) display cells are repeatedly arranged in the horizontal direction.

  FIG. 15E is a diagram showing display data of each display cell in the subframe SF2 in the odd-numbered frame in FIG. In the display cells in the first column and the second column, as in FIG. 15C, the first line and the second line become the first line display data D1 + A, and the third line and the fourth line display the third line. Data D3 + A.

  On the other hand, in the display cells in the third and fourth columns, as shown in FIG. 15A, “−A” is added to the first line, and “+ A” is added to the second line. As a result, by the simultaneous scanning, as shown in FIG. 15E, the first line and the second line become the first line display data D1-A, and the third line and the fourth line become the third line display data D3. -A.

  Here, when the input image signal S2 of all the display cells Cij is the same display data, and the display data is a value between adjacent gradation values, it is indicated by a hatch to which “−A” is added. The display cell to be displayed is turned off without being selected in the address period Ta, and the display cell having no hatch to which “+ A” is added is selected and turned on in the address period Ta. By inserting the dither pattern, it is possible to fix the pattern of the display cell that is lit by the error diffusion process.

  FIG. 15F is a diagram showing display data of each display cell in the subframe SF2 in the even frame in FIG. In the display cells in the first column and the second column, as in FIG. 15D, the second line and the third line become the second line display data E2-A, and the fourth line and the fifth line are the fourth. It becomes line display data E4-A.

  On the other hand, in the display cells in the third and fourth columns, as shown in FIG. 15A, “−A” is added to the first line, and “+ A” is added to the second line. As a result, by the simultaneous scanning, as shown in FIG. 15F, the second line and the third line become the second line display data E2 + A, and the fourth line and the fifth line become the fourth line display data E4 + A. .

  Here, when the input image signal S2 of all the display cells Cij is the same display data, and the display data is a value between adjacent gradation values, it is indicated by a hatch to which “−A” is added. The display cell to be displayed is turned off without being selected in the address period Ta, and the display cell having no hatch to which “+ A” is added is selected and turned on in the address period Ta. By inserting the dither pattern, it is possible to fix the pattern of the display cell that is lit by the error diffusion process.

  As described above, motion noise can be prevented by fixing the pattern of the display cell that is turned on by error diffusion processing, not random, in the odd-numbered frame and the even-numbered frame.

(Fourth embodiment)
FIG. 16 is a block diagram showing a configuration example of a plasma display device according to the fourth embodiment of the present invention. This embodiment is different from the first embodiment in that the error diffusion circuit 120 and the dither processing circuit 130 are replaced. Hereinafter, the points of the present embodiment different from the first embodiment will be described. The dither processing circuit 130 inserts the dither pattern shown in FIG. 13A into the image signal S 2 output from the A / D converter 110 and outputs it to the error diffusion circuit 120. The error diffusion circuit 120 performs error diffusion processing on the image signal output from the dither processing circuit 130 and outputs the image signal to the subframe conversion circuit 140. In this embodiment, after the dither pattern is inserted by the dither processing circuit 130, the error diffusion circuit 120 performs error diffusion processing. As in the first embodiment, this embodiment can prevent motion noise caused by error diffusion processing.

  As described above, according to the first to fourth embodiments, by shortening the address period Ta by simultaneous scanning, even in a plasma display device with a large number of high-definition lines, one frame can be accommodated within a predetermined period. Can do. Also, by inserting a dither pattern into the image signal, motion noise generated by error diffusion processing can be prevented, and deterioration of image quality can be prevented.

  As shown in FIG. 5, in the plasma display panel 10, one display line is constituted by a display electrode pair composed of two display electrodes Xi and Yi, and the display electrode pairs of even display lines and the display of odd display lines are displayed. The electrode pairs are alternately arranged, and a plurality of address electrodes Aj are arranged so as to intersect the display electrodes. The display electrode driving circuit includes an X electrode driver 30 and a Y electrode driver 20, and in each subframe of a plurality of subframes SF weighted within one frame, for each display line of the plasma display panel 10. In this case, one even display line and one odd display line adjacent to the upper and lower sides of the plasma display panel 10 in another subframe are supplied to the display electrodes. As a set, a simultaneous scan pulse for displaying based on the same display data is supplied to the display electrode. The error diffusion circuit 120 performs error diffusion processing on the display data. The dither processing circuit 130 inserts a dither pattern into the display data before or after the error diffusion process. An address driving circuit (address driver) 40 lights up among a plurality of display cells constituting the display line corresponding to the scan pulse based on the display data subjected to the error diffusion processing and the dither pattern insertion processing. An address pulse is supplied to the address electrode to select a display cell to be operated.

  As shown in FIG. 1, the dither processing circuit 130 inserts a dither pattern into the display data subjected to error diffusion processing by the error diffusion circuit 120.

  Further, as shown in FIG. 16, the error diffusion circuit 120 performs error diffusion processing on the display data in which the dither pattern is inserted by the dither processing circuit 130.

  Further, as shown in FIGS. 13A to 13F, the dither processing circuit 130 inserts a dither pattern of a 2 × 2 display cell.

  Further, as shown in FIGS. 14A to 14F, the dither processing circuit 130 inserts a dither pattern of display cells in 4 rows and 2 columns.

  Further, as shown in FIGS. 15A to 15F, the dither processing circuit 130 inserts a dither pattern of a 2 × 4 display cell.

  Further, as shown in FIG. 4, the combination of the one even display line and the one odd display line is different between the odd frame and the even frame.

  Further, as shown in FIG. 2B, the address period Ta for supplying the simultaneous scan pulse is shorter than the address period Ta for supplying the sequential scan pulse.

  Further, as shown in FIG. 8, the display electrode driving circuit supplies the simultaneous scan pulse in an address period for selecting a display cell to be lit among a plurality of display cells constituting the display line, The display cells in the same column are selected in the even display lines and the odd display lines constituting the one set.

  Since the address period can be shortened by supplying the simultaneous scan pulse, even if the number of display lines is large, one frame can be accommodated within the predetermined period. Further, by inserting a dither pattern, motion noise based on error diffusion processing can be prevented.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

It is a block diagram which shows the structural example of the plasma display apparatus by the 1st Embodiment of this invention. 2A to 2C are diagrams for explaining an example of a driving method of the plasma display panel. It is a figure which shows the example of the odd-numbered frame and even-numbered frame which perform a sequential scan. It is a figure which shows the example of the odd-numbered frame and even-numbered frame which perform simultaneous scanning. It is a figure which shows the structural example of a plasma display panel, a Y electrode driver, an X electrode driver, and an address driver. It is a disassembled perspective view which shows the structural example of a plasma display panel. It is a figure which shows an example of the drive waveform of the sequential scan of a plasma display apparatus. It is a figure which shows an example of the drive waveform of the simultaneous scan of a plasma display apparatus. FIG. 2 is a circuit diagram illustrating a configuration example of an error diffusion circuit in FIG. 1. It is a figure which shows an error diffusion object pixel and its adjacent pixel. FIGS. 11A to 11C are diagrams showing frames when the interlaced image signal is simultaneously scanned. FIGS. 12A to 12E are diagrams showing the frame of FIG. 2B without performing dither processing. FIGS. 13A to 13F are diagrams for explaining the processing of the dither processing circuit according to the first embodiment. 14A to 14F are diagrams for explaining the processing of the dither processing circuit according to the second embodiment of the present invention. FIGS. 15A to 15F are views for explaining the processing of the dither processing circuit according to the third embodiment of the present invention. It is a block diagram which shows the structural example of the plasma display apparatus by the 4th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Plasma display panel 20 Y electrode driver 30 X electrode driver 40 Address driver 110 A / D converter 120 Error diffusion circuit 130 Dither process 140 Sub-frame conversion circuit 150 Drive signal generation circuit 160 Selection switch

Claims (9)

One display line is constituted by a display electrode pair composed of two display electrodes, and the display electrode pairs of even display lines and the display electrode pairs of odd display lines are alternately arranged and intersect the display electrodes. A plasma display panel in which a plurality of address electrodes are arranged,
In one subframe of a plurality of subframes weighted within one frame, a sequential scan pulse for displaying each display line of the plasma display panel based on each display data is supplied to the display electrode. In another subframe, a simultaneous scan pulse for displaying on the basis of the same display data is supplied to the display electrode by combining one even display line and one odd display line adjacent to each other on the upper and lower sides of the plasma display panel. A display electrode driving circuit,
An error diffusion circuit for performing an error diffusion process on display data;
A dither processing circuit for inserting a dither pattern for display data before or after the error diffusion processing;
Based on the display data subjected to the error diffusion process and the dither pattern insertion process, the address for selecting a display cell corresponding to the scan pulse and to be lit among a plurality of display cells constituting the display line. A plasma display device comprising: an address driving circuit for supplying address pulses to the electrodes.   2. The plasma display apparatus according to claim 1, wherein the dither processing circuit inserts a dither pattern into the display data subjected to error diffusion processing by the error diffusion circuit.   The plasma display apparatus according to claim 1, wherein the error diffusion circuit performs error diffusion processing on display data in which a dither pattern is inserted by the dither processing circuit.   4. The plasma display device according to claim 1, wherein the dither processing circuit inserts a dither pattern of a 2 × 2 display cell. 5.   The plasma display apparatus according to any one of claims 1 to 3, wherein the dither processing circuit inserts a dither pattern of display cells in 4 rows and 2 columns.   The plasma display apparatus according to any one of claims 1 to 3, wherein the dither processing circuit inserts a dither pattern of a display cell having 2 rows and 4 columns.   The plasma display device according to claim 1, wherein a combination of the one even display line and the one odd display line is different in an odd frame and an even frame. .   8. The plasma display apparatus according to claim 1, wherein an address period for supplying the simultaneous scan pulse is shorter than an address period for supplying the sequential scan pulse. 9.   The display electrode driving circuit supplies the simultaneous scan pulse in an address period for selecting a display cell to be lit among a plurality of display cells constituting the display line, thereby forming an even number of display lines constituting the set. 9. The plasma display device according to claim 1, wherein display cells in the same column are selected in the odd display lines.

Images