JP2009164440A - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to obtain a silicon carbide semiconductor device capable of suppressing an increase in forward resistance and an initial value of an ON resistance of an element while suppressing an increase in forward resistance over time.
A silicon carbide semiconductor device according to the present invention includes an n-type drift layer 2 formed on a silicon carbide substrate 1, a p-type base region 3 formed in contact with the drift layer 2, A recombination region 7 formed in the drift layer 2 and having recombination centers introduced therein. The recombination region 7 is formed only on a path through which current flows immediately after the start of forward energization in the PN interface, which is a junction interface between the drift layer 2 and the base region 3.
[Selection] Figure 1

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.

  When driving an inverter circuit used to control a motor or the like, a period of several microseconds called a dead time during which both MOSFETs of the upper and lower arms are turned off is provided in order to suppress a short circuit in the upper and lower arms of each phase. ing. During this dead time, in order to flow a current that has been circulated from the MOSFET turned off immediately before to the MOSFET on the opposite arm, in many cases, in the inverter circuit, a feedback diode is connected in antiparallel with each MOSFET. Among them, in devices using Si, in order to reduce cost and size by reducing the number of parts, a current that circulates in the forward direction of a parasitic PN diode called a body diode is connected without connecting a feedback diode. ing. However, in bipolar devices using silicon carbide (SiC), when electrons and holes are recombined at stacking faults near the interface when the PN interface is energized, stacking faults grow due to the released energy. To do. As a result, there is a problem that the lifetime of holes is shortened and the resistance in the forward direction of the PN stack (hereinafter referred to as forward resistance) is increased.

  On the other hand, in Patent Document 1, minority carrier concentrations in these layers are set by setting the layer thicknesses of the P-type layer and the N-type layer of the bipolar device to be larger than the minority carrier diffusion length in the layer. Is reduced to an inherent level. As a result, the stacking fault is prevented from continuing to propagate over the entire device except for a part of the region, and the increase in forward resistance is suppressed.

  Patent Document 2 and Patent Document 3 describe a diode formed in a PN laminated portion. This diode includes a recombination region introduced as a recombination center containing ions such as titanium and vanadium in each layer or any one of the layers. In this recombination region, since electron-hole recombination can be accelerated, recombination of minority carriers existing in the vicinity of the interface is accelerated when switching from forward energization to reverse blocking state.

JP 2005-508086 gazette Special table 2001-502474 gazette JP 2005-276953 A

  However, in the silicon carbide semiconductor device disclosed in Patent Document 1, it is possible to suppress the growth of stacking faults in the device region away from the vicinity of the PN interface, but it is possible to suppress the growth of stacking faults near the PN interface. Can not. For this reason, there has been a problem that an increase in the forward resistance over time cannot be avoided.

  Further, according to the silicon carbide semiconductor devices disclosed in Patent Document 2 and Patent Document 3, recombination is performed without increasing stacking faults by the introduced recombination region. Therefore, recombination in stacking faults or the like is suppressed, and an increase in forward resistance with time can be suppressed. However, an object of the present invention is to expedite recombination of minority carriers existing in the vicinity of the interface when switching from forward energization to reverse blocking. For this reason, although the recombination region itself has a large resistance, the recombination region is introduced over the entire surface of the PN interface, so that the initial value of the forward resistance increases. In addition, when the above-described invention is applied to a device having a PN laminated portion such as a MOSFET, there is a problem that the initial value of the ON resistance is increased in addition to the initial value of the forward resistance.

  The present invention has been made to solve the above-described problems, and it is possible to suppress an increase in forward resistance and the initial value of the ON resistance of the element while suppressing an increase in forward resistance over time. An object is to obtain a silicon carbide semiconductor device.

  A silicon carbide semiconductor device according to the present invention includes a first semiconductor layer having a first conductivity type formed on a silicon carbide substrate, and a second conductivity type formed in contact with the first semiconductor layer. A second semiconductor layer, and a recombination region formed in the first semiconductor layer and / or the second semiconductor layer, into which a recombination center is introduced. The recombination region is formed only on a path through which a current flows immediately after the start of forward energization in a PN interface that is a junction interface between the first semiconductor layer and the second semiconductor layer.

  According to the silicon carbide semiconductor device of the present invention, the recombination region reduces the chance of electron-hole recombination at stacking faults and suppresses the growth of stacking faults over time. Increase can be suppressed. Further, by forming the recombination region only on the path through which current flows immediately after the start of forward energization, it is possible to suppress an increase in the initial value of the forward electrical resistance and the ON resistance of the element.

<Embodiment 1>
In this embodiment, the first conductivity type is assumed to be n-type, and the second conductivity type is assumed to be p-type. FIG. 1 is a cross-sectional view showing a silicon carbide semiconductor device according to the present embodiment. As shown in FIG. 1, the silicon carbide semiconductor device according to the present embodiment includes a drift layer 2 that is a first semiconductor layer, a base region 3 that is a second semiconductor layer, and a third semiconductor layer. A medium-concentration p-type (second conductivity type) region 6 and a recombination region 7 are provided.

  A silicon carbide semiconductor device according to the present embodiment includes an n-channel silicon carbide MOSFET (Metal Oxide Semiconductor Field Effective Transistor), and this n-channel silicon carbide MOSFET has an n-type (first conductivity type) silicon carbide substrate. 1, a drift layer 2 having an n-type (first conductivity type), a base region 3 having a p-type (second conductivity type), a source region 4 having an n-type (first conductivity type), A high-concentration p-type (second conductivity type) region 5, a gate insulating film 8, a gate electrode 9, an interlayer insulating film 10, a source electrode 11, and a drain electrode 12 are provided.

  In this n-channel silicon carbide MOSFET, when a voltage is applied to the gate electrode 9, a channel is formed in the base region 3 near the gate electrode 9. The gist of the present invention is that the recombination region 7 is formed in either or both of the pn junctions of the body diode forward energization start point 22 that can be located at a different position from the energization path 21 shown in FIG. There is in being. It is assumed that the silicon carbide semiconductor device according to the present embodiment includes a plurality of n-channel silicon carbide MOSFETs according to FIG. 1 and is periodically formed on silicon carbide substrate 1.

  Next, the structure and manufacturing process of the silicon carbide semiconductor device according to the present embodiment will be described. First, n-type silicon carbide substrate 1 is prepared. The resistivity of this silicon carbide substrate 1 is preferably 0.1 Ωcm or less, for example.

Drift layer 2 that is the first semiconductor layer has an n-type and is formed on silicon carbide substrate 1. The drift layer 2 is made of n-type silicon carbide and is formed by, for example, an epitaxial crystal growth method. The concentration of the drift layer 2 is preferably, for example, 1 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ¹⁷ cm ⁻³ and the thickness is, for example, 8 to 12 μm.

  After the drift layer 2 is formed by the epitaxial crystal growth method, active ion species are implanted into the n-type drift layer 2 using a resist as a mask to form the recombination region 7. By controlling the implantation energy, impurities can be implanted from the drift layer 2 surface to a desired depth. In the present embodiment, the medium concentration p-type region 6 having an impurity concentration higher than that of the base region 3 is formed on the base region 3 side at the boundary between the p-type base region 3 and the recombination region 7. The recombination region 7 and the medium concentration p-type region 6 will be described in detail later.

The base region 3 that is the second semiconductor layer has a p-type and is formed in contact with the drift layer 2. The p-type base region 3 is formed, for example, by forming a resist on the drift layer 2 and ion-implanting impurities using the resist as a mask. Examples of the p-type impurity include boron (B) and aluminum (Al). The impurity concentration of the p-type base region 3 is preferably 1 × 10 ¹⁸ cm ⁻³ or more, for example, and the thickness is preferably 0.2 to 1 μm, for example.

  Thus, the base region 3 which is the second semiconductor layer has a p-type and is formed in contact with the drift layer 2. In the present embodiment, base regions 3 of adjacent n-channel silicon carbide MOSFETs are formed at portions spaced from each other at a predetermined interval.

  Next, after forming a resist on the p-type base region 3, an impurity is ion-implanted into each base region 3 using the resist as a mask to form an n-type source region 4. Examples of the n-type impurity include phosphorus (P) and nitrogen (N).

Further, a resist is formed on the base region 3 and the source region 4, and p-type impurities are ion-implanted into each source region 4 using the resist as a mask. By this ion implantation, a high concentration p-type region 5 is formed. In the present embodiment, the high concentration p-type region 5 is formed immediately above the recombination region 7. The impurity concentration of the high-concentration p-type region 5 is preferably 1 × 10 ²⁰ cm ⁻³ or more, for example, and the thickness is preferably 0.2 to 0.5 μm, for example. However, the sum of the thicknesses of the high-concentration p-type region 5 and the medium-concentration p-type region 6 must be smaller than the thickness of the base region 3. After the ion implantation of the n-type impurity and the p-type impurity, when the wafer (silicon carbide substrate 1) is annealed at a high temperature by a heat treatment apparatus, the implanted ions are electrically activated.

Next, a gate insulating film 8 made of SiO ₂ is formed on the upper side of the wafer by oxidizing the upper portion of the drift layer 2 by a thermal oxidation method. Note that the range in which the drift layer 2 is oxidized by the thermal oxidation method may be all or part of the wafer in plan view. The film thickness of the gate insulating film 8 formed by oxidizing the drift layer 2 by the thermal oxidation method is about twice as large as the original. After thermal oxidation, the O ₂ atmosphere is switched to an Ar atmosphere or an N ₂ atmosphere and cooled.

  Next, a gate electrode 9 is formed and patterned on the gate insulating film 8. The shape of the gate electrode 9 is formed such that, for example, its end is located on the base region 3 and the source region 4 and its center is located on the drift layer 2 between the adjacent base regions 3. To do.

  Further, after forming the interlayer insulating film 10, the upper part of each source region 4 is removed together with a part of the gate insulating film 8 by lithography and etching techniques. After the removal, the source electrode 11 is formed at a portion where the source region 4 is exposed on the surface and patterned. Thereafter, drain electrode 12 is formed on the back side of silicon carbide substrate 1. Thus, the main part of the element structure as shown in FIG. 1 is completed.

  Next, medium concentration p-type region 6 and recombination region 7 included in the silicon carbide semiconductor device according to the present embodiment will be described.

  First, the recombination region 7 will be described. The recombination region 7 is a region formed in the drift layer 2 and having recombination centers introduced therein. The recombination region 7 according to the present embodiment has a current immediately after the start of forward conduction of the body diode shown in FIG. 2 in the PN interface which is a junction interface between the n-type drift layer 2 and the p-type base region 3. Is formed only on the path 23 through which. In the present embodiment, the path 23 is a path through which holes travel from the base region 3 to the drift layer 2 through the medium concentration p-type region 6. In the present embodiment, the recombination region 7 is formed immediately below the p-type base region 3 and deeper than the base region 3.

In the present embodiment, the recombination region 7 includes a transition metal, which is Sc (scandium), Ti (titanium), V (vanadium), Cr (chromium), Y (yttrium). , Zr (zirconium), Nb (niobium), Mo (molybdenum), Hf (hafnium), Ta (tantalum), and W (tungsten). In the present embodiment, the predetermined impurity concentration in the recombination region 7 is 1 × 10 ¹⁷ cm ⁻³ or more, and the thickness of the recombination region 7 is 0.1 μm or more.

Next, the medium concentration p-type region 6 will be described. The medium concentration p-type region 6 that is the third semiconductor layer is formed in the base region 3 and has a higher impurity concentration than the base region 3. In the present embodiment, the medium concentration p-type region 6 is formed adjacent to the recombination region 7. The impurity concentration of the medium concentration p-type region 6 only needs to be about an order of magnitude higher than the impurity concentration of the peripheral base region 3. In the embodiment shown here, for example, it is 1 × 10 ¹⁹ cm ⁻³ or more. Is preferred. Moreover, it is preferable that thickness is 0.1-0.5 micrometer, for example.

  In the silicon carbide semiconductor device according to the present embodiment configured as described above, recombination region 7 into which a recombination center is introduced is formed. In this recombination region 7, electron-hole recombination is performed without increasing stacking faults. This reduces the chance of electron-hole recombination at stacking faults and suppresses the growth of stacking faults over time. The rise can be suppressed. In the present embodiment, the recombination region 7 is formed only on the path 23 through which the current flows immediately after the start of forward conduction of the body diode shown in FIG. Thus, since the recombination region 7 having a large resistance is not formed on the entire surface of the PN interface between the drift layer 2 and the base region 3, the initial value of the forward resistance and the ON resistance of the element is increased. Can be suppressed.

  In the present embodiment, the medium concentration p-type region 6 is provided adjacent to the recombination region 7. This medium concentration p-type region 6 has a lower resistance than the surrounding region of the same conductivity type. Therefore, the path 23 through which current (minority carriers) flows immediately after the start of forward energization can be a desired path, and the current can be efficiently guided to the recombination region 7.

  In the present embodiment, the recombination region 7 has a transition metal, and the transition metal is at least one of Sc, Ti, V, Cr, Y, Zr, Nb, Mo, Hf, Ta, and W. including. Therefore, minority carriers can be captured more efficiently.

Further, in the present embodiment, the concentration of the predetermined impurity in the recombination region 7 is 1 × 10 ¹⁷ cm ⁻³ or more, and the thickness of the recombination region 7 is 0.1 μm or more. Therefore, it is possible to suppress an increase in the initial value of the forward resistance and the ON resistance of the element, and to efficiently perform electron-hole recombination.

Note that the configuration of the silicon carbide semiconductor device according to the present embodiment is not limited to the configuration of FIG. 1, and may be formed to have a termination structure as shown in FIG. In addition, the structure 14 shown with the dotted line of a figure is the same structure as FIG. 1, This structure 14 may be repeated periodically. Then, a JTE (Junction Termination Extension) portion 13 is formed at the end portion. The JTE unit 13 serves to reduce the electric field concentration at the terminal end. The JTE portion 13 is formed by ion implantation after the formation of the base region 3 described above. The JTE portion 13 preferably has an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 0.2 to 1 μm.

  In the present embodiment, the configuration in which the recombination region 7 is provided in the drift layer 2 as shown in FIG. However, the present invention is not limited to this, and the recombination region 7 may be provided in the base region 3 as shown in FIGS. 4D, 4E, and 4F. h) As shown in (i), the structure provided in both the drift layer 2 and the base region 3 may be sufficient. Even with these configurations, it is possible to suppress the increase in the forward resistance with time and reduce the forward resistance, as described above.

  Further, in the present embodiment, as shown in FIG. 4A, a medium concentration p-type region 6 which is a third semiconductor layer formed in the base region 3 and having an impurity concentration higher than that of the base region 3 is provided. The configuration was explained. Then, the medium concentration p-type region 6 was formed adjacent to the recombination region 7. However, the present invention is not limited to this, and the intermediate concentration p-type region 6 may be formed to overlap the recombination region 7 as shown in FIGS. 4 (d), (e), (g), and (h). Further, instead of the medium concentration p-type region 6, a medium concentration n-type region 24, which is a third semiconductor layer formed in the drift layer 2 and having an impurity concentration higher than that of the drift layer 2, is provided. Then, as shown in FIG. 4 (f), the intermediate concentration n-type region 24 may be formed adjacent to the recombination region 7, or FIG. 4 (b) (c) (h) (i) As shown in FIG. 3, the intermediate concentration n-type region 24 may be formed so as to overlap the recombination region 7. Further, as shown in FIGS. 4B, 4E, and 4H, a configuration in which both the medium concentration p-type region 6 and the medium concentration n-type region 24 are provided may be employed. Even with these configurations, the path 23 through which the current flows immediately after the start of forward energization can be made a desired path, and the current can be efficiently passed through the recombination region 7 as described above.

  In the present embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is not limited to this, and the first conductivity type is p-type, The second conductivity type may be n-type.

<Embodiment 2>
In this embodiment, the first conductivity type is assumed to be n-type, and the second conductivity type is assumed to be p-type. FIG. 5 shows a cross-sectional view of the silicon carbide semiconductor device according to the present embodiment. As shown in FIG. 5, the silicon carbide semiconductor device according to the present embodiment includes a drift layer 2 that is a first semiconductor layer, a guard ring region 15 that is a second semiconductor layer, and a third semiconductor layer. A medium concentration p-type (second conductivity type) region 6 and a recombination region 7 are provided. Hereinafter, of the configuration of the semiconductor device according to the present embodiment, the same configuration as that of the first embodiment is denoted by the same reference numeral, and the configuration not newly described is the same as that of the first embodiment. Shall.

  The silicon carbide semiconductor device according to the present embodiment includes silicon carbide SBD (short barrier diode), and silicon carbide SBD includes silicon carbide substrate 1 having n type (first conductivity type) and n type (first conductivity type). Drift layer 2, medium concentration p-type region 6, recombination region 7, guard ring region 15 having p-type (second conductivity type), and p-type (second conductivity type). JTE region 16 having a mold), a Schottky electrode 17, an anode electrode 18, and a cathode electrode 19.

  Next, the structure and manufacturing process of the silicon carbide semiconductor device according to the present embodiment will be described. First, n-type silicon carbide substrate 1 is prepared. The resistivity of this silicon carbide substrate 1 is preferably 0.1 Ωcm or less, for example.

Drift layer 2 that is the first semiconductor layer has an n-type and is formed on silicon carbide substrate 1. The drift layer 2 is made of n-type silicon carbide and is formed by, for example, an epitaxial crystal growth method. The concentration of the drift layer 2 is preferably, for example, 1 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ¹⁷ cm ⁻³ and the thickness is, for example, 8 to 12 μm.

  After the drift layer 2 is formed by the epitaxial crystal growth method, active ion species are implanted into the n-type drift layer 2 using a resist as a mask to form the recombination region 7. By controlling the implantation energy, impurities can be implanted from the drift layer 2 surface to a desired depth. In the present embodiment, the medium concentration p-type region 6 having an impurity concentration higher than that of the guard ring region 15 is formed on the guard ring region 15 side at the boundary between the p-type guard ring region 15 and the recombination region 7. To do. The recombination region 7 and the medium concentration p-type region 6 will be described in detail later.

The guard ring region 15 as the second semiconductor layer has a p-type and is formed in contact with the drift layer 2. The p-type guard ring region 15 is formed, for example, by forming a resist at a predetermined site on the drift layer 2 and then ion-implanting impurities using the resist as a mask. The p-type JTE region 16 is also formed in the same manner as the guard ring region 15. Examples of the p-type impurity include boron (B) and aluminum (Al). The impurity concentration of the p-type guard ring region 15 is preferably 1 × 10 ¹⁷ cm ⁻³ or more, for example, and the thickness is preferably 0.2 to 1 μm, for example. The impurity concentration of the p-type JTE region 16 is preferably 1 × 10 ¹⁷ cm ⁻³ or more, for example, and the thickness is preferably 0.2 to 1 μm, for example.

  After the ion implantation of the p-type impurity, when the wafer is annealed at a high temperature by a heat treatment apparatus, the implanted ions are electrically activated. Thereafter, the Schottky electrode 17 and the anode electrode 18 are sequentially formed and patterned, and the cathode electrode 19 is formed on the back side of the silicon carbide substrate 1. Thus, the main part of the element structure as shown in FIG. 5 is completed.

  Next, medium concentration p-type region 6 and recombination region 7 included in the silicon carbide semiconductor device according to the present embodiment will be described.

  First, the recombination region 7 will be described. The recombination region 7 is a region formed in the drift layer 2 and having recombination centers introduced therein. The recombination region 7 according to the present embodiment is only on the path through which current flows immediately after the start of forward energization in the PN interface that is the junction interface between the n-type drift layer 2 and the p-type guard ring region 15. It is formed. In the present embodiment, the path is a path that travels from the guard ring region 15 to the drift layer 2 through the medium concentration p-type region 6. In the present embodiment, the recombination region 7 is formed immediately below the p-type guard ring region 15 and deeper than the guard ring region 15.

In the present embodiment, the recombination region 7 includes a transition metal, and the transition metal includes at least one of Sc, Ti, V, Cr, Y, Zr, Nb, Mo, Hf, Ta, and W. Including. In the present embodiment, the predetermined impurity concentration in the recombination region 7 is 1 × 10 ¹⁷ cm ⁻³ or more, and the thickness of the recombination region 7 is 0.1 μm or more.

Next, the medium concentration p-type region 6 will be described. The medium concentration p-type region 6 which is the third semiconductor layer is formed in the guard ring region 15 and has a higher impurity concentration than the guard ring region 15. In the present embodiment, the medium concentration p-type region 6 is formed adjacent to the recombination region 7. The impurity concentration of the medium concentration p-type region 6 only needs to be about an order of magnitude higher than the impurity concentration of the surrounding guard ring region 15. In the embodiment shown here, for example, it is 1 × 10 ¹⁸ cm ⁻³ or more. It is desirable. Moreover, it is preferable that thickness is 0.1-0.5 micrometer, for example.

  In the silicon carbide semiconductor device according to the present embodiment configured as described above, recombination region 7 into which a recombination center is introduced is formed. In this recombination region 7, electron-hole recombination is performed without increasing stacking faults. Therefore, by suppressing the growth of stacking faults over time, it is possible to suppress the increase in forward resistance over time. In the present embodiment, the recombination region 7 is formed only on the path through which current flows immediately after the start of forward energization. Thus, since the recombination region 7 having a large resistance is not formed on the entire surface of the PN interface between the drift layer 2 and the guard ring region 15, the initial value of the forward resistance and the ON resistance of the element is increased. Can be suppressed.

  In the present embodiment, the medium concentration p-type region 6 is provided adjacent to the recombination region 7. Thereby, the path through which the current flows immediately after the start of forward energization can be changed to a desired path, and the current can be efficiently passed through the recombination region 7. In addition, the other effects of the first embodiment can be obtained.

  In the present embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is not limited to this, and the first conductivity type is p-type, The second conductivity type may be n-type.

<Embodiment 3>
In this embodiment, the first conductivity type is assumed to be n-type, and the second conductivity type is assumed to be p-type. FIG. 6 shows a cross-sectional view of the silicon carbide semiconductor device according to the present embodiment. As shown in FIG. 6, the silicon carbide semiconductor device according to the present embodiment includes a drift layer 2 that is a first semiconductor layer, a guard ring region 15 that is a second semiconductor layer, and a p-type (second conductive layer). Type) region 20, medium-concentration p-type (second conductivity type) regions 6, 21 that are third semiconductor layers, and recombination region 7. Hereinafter, among the configurations of the semiconductor device according to the present embodiment, the same reference numerals are given to the same configurations as those in the first embodiment, and the configurations not newly described are the same as those in the second embodiment. Shall.

  The silicon carbide semiconductor device according to the present embodiment includes silicon carbide SBD (short barrier diode), and silicon carbide SBD includes silicon carbide substrate 1 having n type (first conductivity type) and n type (first conductivity type). 1), a high-concentration p-type region 5, medium-concentration p-type regions 6 and 21, a recombination region 7 in which a recombination center is introduced, and a p-type (second conductivity type). A guard ring region 15 having a p-type (second conductivity type), a Schottky electrode 17, an anode electrode 18, a cathode electrode 19, and a p-type region 20.

  Next, the structure and manufacturing process of the silicon carbide semiconductor device according to the present embodiment will be described. First, n-type silicon carbide substrate 1 is prepared. The resistivity of this silicon carbide substrate 1 is preferably 0.1 Ωcm or less, for example.

Drift layer 2 that is the first semiconductor layer has an n-type and is formed on silicon carbide substrate 1. The drift layer 2 is made of n-type silicon carbide and is formed by, for example, an epitaxial crystal growth method. The concentration of the drift layer 2 is preferably, for example, 1 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ¹⁷ cm ⁻³ and the thickness is, for example, 8 to 12 μm.

  After the drift layer 2 is formed by the epitaxial crystal growth method, active ion species are implanted into the n-type drift layer 2 using a resist as a mask to form the recombination region 7. By controlling the implantation energy, impurities can be implanted from the drift layer 2 surface to a desired depth. Further, a medium concentration p-type region 6 having an impurity concentration higher than that of the guard ring region 15 is formed on the guard ring region 15 side at the boundary between the p-type guard ring region 15 and the recombination region 7. In the present embodiment, a medium concentration p-type region 21 having an impurity concentration higher than that of the p-type region 20 is formed on the p-type region 20 side at the boundary between the p-type region 20 and the recombination region 7. The recombination region 7 and the medium concentration p-type regions 6 and 21 will be described in detail later.

The guard ring region 15 and the p-type region 20 which are the second semiconductor layers have a p-type and are formed in contact with the drift layer 2. The p-type guard ring region 15 and the p-type region 20 are formed, for example, by forming a resist at a predetermined site on the drift layer 2 and then ion-implanting impurities using the resist as a mask. The p-type JTE region 16 is formed in the same manner as these. Examples of the p-type impurity include boron (B) and aluminum (Al). The impurity concentration of the p-type guard ring region 15 is preferably 1 × 10 ¹⁷ cm ⁻³ or more, for example, and the thickness is preferably 0.2 to 1 μm, for example. The impurity concentration of the p-type JTE region 16 is preferably 1 × 10 ¹⁷ cm ⁻³ or more, for example, and the thickness is preferably 0.2 to 1 μm, for example. The impurity concentration of the p-type region 20 is preferably 1 × 10 ¹⁸ cm ⁻³ or more and the thickness is preferably 0.2 to 1 μm, for example.

  Further, after a resist is formed at a predetermined site on the drift layer 2, impurities are ion-implanted using the resist as a mask, thereby forming the high-concentration p-type region 5. After the ion implantation of these p-type impurities, if the wafer is annealed at a high temperature by a heat treatment apparatus, the implanted ions are electrically activated. Thereafter, the Schottky electrode 17 and the anode electrode 18 are sequentially formed and patterned, and the cathode electrode 19 is formed on the back side of the silicon carbide substrate 1. Thus, the main part of the element structure as shown in FIG. 6 is completed.

  Next, medium concentration p-type region 6 and recombination region 7 included in the silicon carbide semiconductor device according to the present embodiment will be described.

  First, the recombination region 7 will be described. The recombination region 7 is a region formed in the drift layer 2 and having recombination centers introduced therein. In the present embodiment, the recombination region 7 is only on the path through which current flows immediately after the start of forward energization in the PN interface that is the junction interface between the n-type drift layer 2 and the p-type guard ring region 15. It is formed. The path is a path that travels from the guard ring region 15 to the drift layer 2 through the medium concentration p-type region 6. In the present embodiment, the recombination region 7 is formed immediately below the p-type guard ring region 15 and at a position deeper than the guard ring region 15.

  Further, in the present embodiment, the recombination region 7 is formed only on the path through which current flows immediately after the start of forward energization in the PN interface that is the junction interface between the n-type drift layer 2 and the p-type region 20. The The path is a path that travels from the p-type region 20 to the drift layer 2 through the medium concentration p-type region 6. In the present embodiment, the recombination region 7 is formed at a position deeper than the p-type region 20 immediately below the p-type region 20.

In the present embodiment, the recombination region 7 includes a transition metal, and the transition metal includes at least one of Sc, Ti, V, Cr, Y, Zr, Nb, Mo, Hf, Ta, and W. Including. In the present embodiment, the predetermined impurity concentration in the recombination region 7 is 1 × 10 ¹⁷ cm ⁻³ or more, and the thickness of the recombination region 7 is 0.1 μm or more.

Next, the medium concentration p-type region 6 will be described. The medium concentration p-type region 6 which is the third semiconductor layer is formed in the guard ring region 15 and has a higher impurity concentration than the guard ring region 15. In the present embodiment, the medium concentration p-type region 6 is formed adjacent to the recombination region 7. The impurity concentration of the medium concentration p-type region 6 only needs to be about an order of magnitude higher than the impurity concentration of the surrounding guard ring region 15. In the embodiment shown here, for example, it is 1 × 10 ¹⁸ cm ⁻³ or more. It is preferable. Moreover, it is preferable that thickness is 0.1-0.5 micrometer, for example. The medium concentration p-type region 21 is the same as the medium concentration p-type region 6 except that the guard ring region 15 is changed to the p-type region 20.

  In the silicon carbide semiconductor device according to the present embodiment configured as described above, recombination region 7 into which a recombination center is introduced is formed. In this recombination region 7, electron-hole recombination is performed without increasing stacking faults. Therefore, by suppressing the growth of stacking faults over time, it is possible to suppress the increase in forward resistance over time. In the present embodiment, the recombination region 7 is formed only on the path through which current flows immediately after the start of forward energization. Thus, the recombination region 7 having a large resistance is not formed on the entire PN interface between the drift layer 2 and the guard ring region 15 and between the drift layer 2 and the p-type region 20. In addition, an increase in the initial value of the forward resistance and the ON resistance of the element can be suppressed.

  In the present embodiment, the medium concentration p-type regions 6 and 21 are provided adjacent to the recombination region 7. Thereby, the path through which the current flows immediately after the start of forward energization can be changed to a desired path, and the current can be efficiently passed through the recombination region 7. In addition, the other effects of the first embodiment can be obtained.

  In the present embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is not limited to this, and the first conductivity type is p-type, The second conductivity type may be n-type.

  In the present embodiment, the recombination region 7 is formed on both the guard ring region 15 side and the p-type region 20 side. However, the present invention is not limited to this, and the recombination region 7 may be formed on one side of the guard ring region 15 and the p-type region 20.

1 is a cross sectional view showing a silicon carbide semiconductor device according to a first embodiment. FIG. 3 is a cross sectional view showing an energization path and the like of the silicon carbide semiconductor device according to the first embodiment. 1 is a cross sectional view showing a silicon carbide semiconductor device according to a first embodiment. 1 is a cross sectional view showing a silicon carbide semiconductor device according to a first embodiment. FIG. 6 is a cross sectional view showing a silicon carbide semiconductor device according to a second embodiment. FIG. 6 is a cross sectional view showing a silicon carbide semiconductor device according to a third embodiment.

Explanation of symbols

  1 silicon carbide substrate, 2 drift layer, 3 base region, 4 source region, 5 high concentration p-type region, 6,21 medium concentration p-type region, 7 recombination region, 8 gate insulating film, 9 gate electrode, 10 interlayer insulation Membrane, 11 source electrode, 12 drain electrode, 13 JTE section, 14 structure, 15 guard ring region, 16 JTE region, 17 Schottky electrode, 18 anode electrode, 19 cathode electrode, 20 p-type region, 21 energization path when ON , 22 Body diode forward energization start point, 23 Current flow path immediately after body diode forward energization start, 24 Medium density n-type region.

Claims (10)

A first semiconductor layer having a first conductivity type formed on a silicon carbide substrate;
A second semiconductor layer having a second conductivity type formed in contact with the first semiconductor layer;
A recombination region formed in the first semiconductor layer and / or the second semiconductor layer and introduced with a recombination center;
The recombination region is
Of the PN interface, which is the junction interface between the first semiconductor layer and the second semiconductor layer, formed only on the path through which current flows immediately after the start of forward energization,
Silicon carbide semiconductor device. A third semiconductor layer formed on the first semiconductor layer and / or the second semiconductor layer and having a higher impurity concentration than the semiconductor layer;
The third semiconductor layer is formed adjacent to the recombination region;
The silicon carbide semiconductor device according to claim 1. A third semiconductor layer formed on the first semiconductor layer and / or the second semiconductor layer and having a higher impurity concentration than the semiconductor layer;
The third semiconductor layer is formed to overlap the recombination region;
The silicon carbide semiconductor device according to claim 1. The impurity concentration of the third semiconductor layer is 1 × 10 ¹⁹ cm ⁻³ or more;
The silicon carbide semiconductor device according to claim 2 or claim 3. The third semiconductor layer has a thickness of 0.1 to 0.5 μm.
The silicon carbide semiconductor device according to claim 2. The recombination region is
Comprising a transition metal,
The silicon carbide semiconductor device according to any one of claims 1 to 5. The transition metal is
Including at least one of Sc, Ti, V, Cr, Y, Zr, Nb, Mo, Hf, Ta, W,
The silicon carbide semiconductor device according to claim 6. A concentration of the transition metal in the recombination region is 1 × 10 ¹⁷ cm ⁻³ or more;
A silicon carbide semiconductor device according to claim 6 or 7. The recombination region has a thickness of 0.1 μm or more.
The silicon carbide semiconductor device according to claim 6. (A) forming a first semiconductor layer having a first conductivity type on a silicon carbide substrate;
(B) forming a second semiconductor layer having a second conductivity type in contact with the first semiconductor layer;
(C) forming a recombination region into which a recombination center is introduced in the first semiconductor layer and / or the second semiconductor layer,
The recombination region in step (c) is
Of the PN interface, which is the junction interface between the first semiconductor layer and the second semiconductor layer, formed only on the path through which current flows immediately after the start of forward energization,
A method for manufacturing a silicon carbide semiconductor device.

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