JP2009152488A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily manufacture a semiconductor device including a TFT in which an unexpected increase in off current is suppressed.
A method of manufacturing a semiconductor device according to the present invention includes a step of forming a photoresist layer (P), a first region (GH), and a first region (GH) in a conductive layer (G). Forming a thinner second region (GL), and removing the photoresist layer (P) so as not to remove a part of the photoresist layer (P) and the remaining part of the photoresist layer (P). A step of partially etching, a step of forming a gate electrode (130) using a portion (PA ′) of the photoresist layer (P) that has not been removed as a mask, and a first region (G) of the conductive layer (G) GH) and forming the first region (120H) and the second region (120L) of the insulating layer (120) corresponding to the second region (GL).
[Selection] Figure 3

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, a technique for manufacturing a semiconductor layer having a crystal structure (hereinafter referred to as a crystalline semiconductor layer) by crystallizing an amorphous semiconductor layer formed over an insulating substrate such as a glass substrate has been widely studied. . The crystalline semiconductor layer is, for example, a polycrystalline semiconductor layer or a microcrystalline semiconductor layer. A thin film transistor (TFT) manufactured using a crystalline semiconductor layer has much higher carrier mobility than a TFT manufactured using an amorphous semiconductor layer. Accordingly, the pixel TFTs in the display region and the driver circuit TFTs in the peripheral region in the driver-integrated active matrix substrate suitably used for a display device (for example, a liquid crystal display device) are manufactured using a crystalline semiconductor layer. Yes.

  As a method for crystallizing an amorphous semiconductor layer, a CGS (Continuous Grain Silicon) method is known in which a catalytic element (for example, nickel) is added to the amorphous semiconductor layer and heat treatment is performed. According to this method, a good crystalline semiconductor layer with uniform crystal orientation can be formed by low-temperature and short-time heat treatment. However, in the case where a crystalline semiconductor layer is manufactured by the CGS method, if a catalytic element remains in a channel region provided in the semiconductor layer, the off current of the TFT may increase suddenly. For this reason, it is known that a gettering region for gettering the catalytic element is provided in the semiconductor layer to suppress a sudden increase in off-current in the TFT (see, for example, Patent Document 1).

  FIG. 10 is a schematic cross-sectional view of a semiconductor device 700 disclosed in Patent Document 1.

  The semiconductor device 700 includes a glass substrate 702, a base coat layer 704 supported by the glass substrate 702, semiconductor layers 710n and 710p provided over the base coat layer 704, an insulating layer 720 covering the semiconductor layers 710n and 710p, Gate electrodes 730 n and 730 p facing the semiconductor layers 710 n and 710 p with the layer 720 interposed therebetween are provided. The semiconductor device 700 is provided with an N-channel thin film transistor (TFT) 810 and a P-channel TFT 820. Further, an interlayer insulating film 740 covering the gate electrodes 730n and 730p is provided, and source electrodes 830ns and 830ps and drain electrodes 830nd and 830pd are provided in contact holes formed in the interlayer insulating film 740.

  In the N-channel TFT 810, the semiconductor layer 710n includes a source region 710ns, a channel region 710nc, a drain region 710nd, an LDD (Lightly Doped Drain) region 710nL, and a gettering region 710ng. In the semiconductor layer 710n, the source region 710ns, the drain region 710nd, the LDD region 710nL, and the gettering region 710ng are doped with phosphorus imparting n-type conductivity. The impurity concentration of the gettering region 710ng is higher than that of the source region 710ns and the drain region 710nd, and the impurity concentration of the LDD region 710nL is lower than that of the source region 710ns and the drain region 710nd. The gettering region 710 ng is also doped with boron.

  In the P-channel TFT 820, the semiconductor layer 710p includes a source region 710ps, a channel region 710pc, a drain region 710pd, and a gettering region 710pg. Of the semiconductor layer 710p, the source region 710ps, the drain region 710pd, and the gettering region 710pg are doped with boron. The gettering region 710pg is also doped with phosphorus.

  Hereinafter, a method for manufacturing the semiconductor device 700 disclosed in Patent Document 1 will be described with reference to FIGS. The process proceeds in the order of FIGS. 11 (a) to 11 (g) and FIGS. 12 (a) to 12 (e).

  As shown in FIG. 11A, a base coat layer 704 is formed on a glass substrate 702. The base coat layer 704 includes a first base film 706 made of a silicon oxynitride film and a second base film 708 made of a silicon oxide film. Thereafter, an a-Si film 710 is formed on the base coat layer 704, and a small amount of nickel 712 is added to the surface of the a-Si film 710.

  As shown in FIG. 11B, heat treatment is performed to crystallize the a-Si film 710 to obtain a crystalline silicon film 710a. In this crystallization process, nickel 712 added to the a-Si film 710 functions as a catalyst and promotes crystallization.

  As shown in FIG. 11C, the laser beam L is irradiated. Thereby, a crystalline silicon film 710b with improved crystallinity is obtained.

  As shown in FIG. 11D, island-like crystalline silicon layers 710n and 710p are formed. The crystalline silicon layers 710n and 710p later become semiconductor layers of the N-channel TFT 810 and the P-channel TFT 820.

  As shown in FIG. 11E, an insulating layer 720 covering the crystalline silicon layers 710n and 710p is formed. Subsequently, a lower conductive film GA and an upper conductive film GB made of a refractory metal are formed by sputtering. The lower conductive film GA is a tantalum nitride (TaN) film, and the upper conductive film GB is a tungsten (W) film. Thereafter, photoresist layers 910n and 910p are formed on the upper conductive film GB.

  Next, a first etching process is performed to form upper conductive layers GBn and GBp having tapered end portions. Subsequently, a second etching process is performed to form lower conductive layers GAn and GAp. As a result, as shown in FIG. 11F, upper conductive layers GBn and GBp having a trapezoidal cross section and lower conductive layers GAn and GAp having substantially the same width as the lower portions of the upper conductive layers GBn and GBp are obtained. It is done.

  As shown in FIG. 11G, a part of the upper conductive layers GBn and GBp is removed by performing the third etching process. By this etching, only the upper conductive layers GBn and GBp are selectively removed in the lateral direction.

  As shown in FIG. 12A, the photoresist layers 910n and 910p are ashed, and then a photoresist layer 920 covering the gate electrode 730n is formed. The photoresist layer 920 is disposed so as to overlap the central portion of the semiconductor layer 710n but not the end portion.

  Thereafter, boron is implanted into the semiconductor layers 710n and 710p by ion doping using the photoresist layer 920 and the upper conductive layer GBp as a mask. Boron is implanted through the insulating layer 720 into a region of the semiconductor layer 710n that does not overlap with the photoresist layer 920. Boron is implanted through the insulating layer 720 or both the insulating layer 720 and the lower conductive layer GAp into a region of the semiconductor layer 710p that does not overlap with the upper conductive layer GBp. Since the atomic weight of boron is smaller than that of phosphorus, it has a high penetration capability and can penetrate both the insulating layer 720 and the lower conductive layer GAp even with a relatively low acceleration voltage.

  As shown in FIG. 12B, a fourth etching process for removing a part of the lower conductive layer GAp and a thinning of the insulating layer 720 are performed. In the fourth etching process, the lower conductive layer GAp is selectively etched using the upper conductive layer GBp as a mask. As a result, the widths of the upper conductive layer GBp and the lower conductive layer GAp are substantially equal, and the gate electrode 730p has a different shape from the gate electrode 730n.

  Further, the insulating layer 720 is thinned by etching the insulating layer 720 using the photoresist layer 920 and the lower conductive layer GAp as a mask. Accordingly, a region of the insulating layer 720 that does not overlap with the photoresist layer 920 and the lower conductive layer GAp is thinner than a region that overlaps with the photoresist layer 920 and the lower conductive layer GAp, and a region having a different thickness is formed in the insulating layer 720. Is done. After the etching, the photoresist layer 920 is removed.

  Note that either the fourth etching treatment or the etching for thinning the insulating layer 720 may be performed first. Further, these two etchings and the removal of the photoresist layer 920 may be continuously performed in the same etching apparatus. Furthermore, some or all of these three steps may be simultaneously processed as the same step. In the case of simultaneous processing, for example, the step of thinning the insulating layer 720 and the step of removing the photoresist layer 920 may be performed simultaneously.

  As shown in FIG. 12C, a photoresist layer 930 is formed. The photoresist layer 930 covers the gate electrode 730p, and is disposed so as to overlap with the central portion of the semiconductor layer 710p and not with the end portion.

  Thereafter, phosphorus is implanted into the semiconductor layers 710n and 710p by ion doping using the upper conductive layer GBn and the photoresist layer 930 as a mask. Phosphorus penetrates both the insulating layer 720 or both the insulating layer 720 and the lower conductive layer GAn, and is implanted into a region of the semiconductor layers 710n and 710p that does not overlap with the upper conductive layer GBn and the photoresist layer 930.

  Specifically, phosphorus is implanted into an end portion of the semiconductor layer 710p that does not overlap with the photoresist layer 930. In this manner, the region into which phosphorus is implanted in the semiconductor layer 710p becomes the gettering region 710pg. Note that the gettering region 710 pg is also doped with boron. In addition, since the semiconductor layer 710p overlaps with the photoresist layer 930, regions doped only with boron and not doped with phosphorus become a source region 710ps and a drain region 710pd. Note that in the semiconductor layer 710p, a region in which neither phosphorus nor boron is doped becomes a channel region 710pc.

  Phosphorus is also implanted into a region of the semiconductor layer 710n that does not overlap with the upper conductive layer GBn. The concentration of phosphorus varies depending on the presence of the lower conductive layer GAn overlapping the region. The phosphorus concentration in the region of the semiconductor layer 710n that overlaps with the lower conductive layer GAn is lower than the phosphorus concentration of the region of the semiconductor layer 710n that does not overlap with the lower conductive layer GAn. Thus, in the semiconductor layer 710n, a region of the semiconductor layer 710n that overlaps with the lower conductive layer GAn but does not overlap with the upper conductive layer GBn is an LDD region 710nL.

  Further, the concentration of phosphorus differs depending on the thickness of the insulating layer 720 existing on the region. Of the semiconductor layer 710n, the phosphorus concentration in the region below the thin region of the insulating layer 720 is higher than the phosphorus concentration in the region below the thick region of the insulating layer 720. Thus, in the semiconductor layer 710n, a region below the thin region of the insulating layer 720 is a gettering region 710ng, and a region below the thick region of the insulating layer 720 is a source region 710ns and a drain region 710nd. A region of the gate electrode 730n that overlaps with the lower conductive layer GAn and is not implanted with phosphorus is a channel region 710nc. Note that since the insulating layer 720 on the gettering region 710 ng is thinner than the insulating layer 720 on the source region 710 ns and the drain region 710 nd, the gettering region 710 ng receives larger impact energy. Further, the gettering region 710 ng is also doped with boron and is made amorphous.

  As shown in FIG. 12D, the catalyst element is gettered by performing a heat treatment step. The gettering regions 710 ng and 710 pg are doped with high concentration of phosphorus, and the solid solubility of nickel in the gettering regions 710 ng and 710 pg is high. The gettering regions 710 ng and 710 pg are amorphized, and crystal defects and dangling bonds (dangling bonds) function as nickel segregation sites. Therefore, the gettering effects of the gettering regions 710 ng and 710 pg are synergistically increased. For this reason, nickel existing in the channel region 710nc, the LDD region 710nL, the source region 710ns, and the drain region 710nd in the semiconductor layer 710n of the N-channel TFT by the heat treatment step is a direction indicated by an arrow toward the gettering region 710ng. Move to. Similarly, in the semiconductor layer 710p of the P-channel TFT, nickel existing in the source region 710ps, the channel region 710pc, and the drain region 710pd moves to the gettering region 710pg in the direction indicated by the arrow.

As shown in FIG. 12E, an interlayer insulating film 740 covering the gate electrodes 730n and 730p is formed. The interlayer insulating film 740 has a two-layer structure including a silicon nitride film 742 and a silicon oxide film 744. Next, contact holes are formed in the interlayer insulating film 740 to form source electrodes 830 ns and 830 ps and drain electrodes 830 nd and 830 pd composed of a two-layer film of titanium nitride and aluminum.
JP 2005-251794 A

  In the manufacturing method disclosed in Patent Document 1, photoresist layers 910n and 910p for forming gate electrodes and a photoresist for preventing boron implantation are used to form P-channel TFTs and N-channel TFTs. A layer 920 and a photoresist layer 930 for preventing phosphorus implantation are formed. In general, a photoresist layer is formed by depositing a photoresist material and performing exposure using a photomask having a light transmission region and a light shielding region for each photolithography process. In the manufacturing method disclosed in Patent Document 1, it is necessary to perform the photolithography process at least three times in order to form the three photoresist layers, and the semiconductor device cannot be easily manufactured.

  In the manufacturing method disclosed in Patent Document 1, the photoresist layer 920 is used to reduce the thickness of the insulating layer 720. For this reason, even when a semiconductor device including only an N-channel TFT is manufactured, it is necessary to provide the photoresist layer 920, and the semiconductor device cannot be easily manufactured.

  Further, when the removal of the photoresist layer 920 and the thinning of the insulating film 720 are performed at the same time, the insulating film 720 cannot be made sufficiently thin, and it is difficult to control the thickness of the insulating film 720. For this reason, the concentration of phosphorus in the gettering regions 720 ng and 720 pg becomes insufficient, so that sufficient gettering cannot be performed, the off-current in the TFTs 810 and 820 increases suddenly, and point defects occur. is there.

  The present invention has been made in view of the above problems, and an object thereof is to provide a simple manufacturing method of a semiconductor device including a TFT in which an unexpected increase in off current is suppressed.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including an N-channel thin film transistor, the step of preparing a semiconductor layer containing a catalytic element for promoting crystallization, and the crystal of the semiconductor layer A step of forming an insulating layer, a step of forming an insulating layer covering the semiconductor layer, a step of forming a conductive layer on the insulating layer, a first region in the insulating layer, and thinner than the first region A step of forming a second region, and implanting an impurity element belonging to Group B of the periodic table into the semiconductor layer through the insulating layer, thereby corresponding to the first region and the second region of the insulating layer And forming a source region or a drain region and a gettering region in the semiconductor layer, wherein the impurity element concentration in the gettering region of the semiconductor layer is changed to the source region or drain of the semiconductor layer. Including a step of increasing the impurity element concentration in the region and a step of moving the catalyst element in the semiconductor layer to the gettering region, and after the step of forming the conductive layer and in the insulating layer Before the step of forming the first region and the second region, a photoresist layer covering a part of the conductive layer, which overlaps with a portion to be a source region or a drain region of the semiconductor layer, Forming a photoresist layer that does not overlap with a portion to be a gettering region, and thinning a portion of the conductive layer that is not covered with the photoresist layer, thereby forming a first region in the conductive layer; and Forming a second region thinner than the first region, and removing the photoresist layer so as not to remove a portion of the photoresist layer and remove the remaining portion of the photoresist layer. A step of partially ashing, and a step of forming the gate electrode of the N-channel type thin film transistor by etching the conductive layer using a portion of the photoresist layer that has not been removed as a mask. The first and second regions of the insulating layer are formed corresponding to the first and second regions of the conductive layer.

  In one embodiment, the method further includes forming a first region and a second region thinner than the first region in the photoresist layer, and partially ashing the photoresist layer. A portion corresponding to the second region of the photoresist layer is removed, and a part of the portion corresponding to the first region of the photoresist layer is not removed.

  In one embodiment, forming the first and second regions in the photoresist layer includes using a halftone mask having three regions having different light transmittances.

  In one embodiment, the semiconductor device further includes a P-channel thin film transistor, and the semiconductor layer for the P-channel thin film transistor is changed from the semiconductor layer for the N-channel thin film transistor in the crystallized semiconductor layer. Separating the layers, placing the photoresist layer so as not to overlap the gettering region of the semiconductor layer for the N-channel thin film transistor, and implanting an impurity element belonging to Group B of the periodic table; Is included.

  According to the present invention, it is possible to easily manufacture a semiconductor device including a TFT in which an unexpected increase in off current is suppressed.

  Hereinafter, embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings. In addition, this invention is not limited to the following embodiment.

(Embodiment 1)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described.

  FIG. 1 shows a schematic cross-sectional view of a semiconductor device 100 of the present embodiment. The semiconductor device 100 includes an insulating substrate 102, a base coat layer 104 supported by the insulating substrate 102, a semiconductor layer 110 provided on the base coat layer 104, an insulating layer 120 covering the semiconductor layer 110, and the insulating layer 120. The semiconductor layer 110 and the conductive layer 130 facing each other are provided. The semiconductor device 100 is provided with an N-channel thin film transistor 200. The conductive layer 130 functions as a gate electrode of the TFT 200, and the insulating layer 120 located between the gate electrode 130 and the semiconductor layer 110 functions as a gate insulating film. In FIG. 1, the source electrode and the drain electrode of the TFT 200 are not shown.

The semiconductor layer 110 includes a source region 110s, a channel region 110c, a drain region 110d, and a gettering region 110g. The source region 110s, the drain region 110d, and the gettering region 110g are doped with an impurity element (eg, phosphorus) belonging to Group B of the periodic table that imparts n-type conductivity. The phosphorus element concentration in the source region 110s and the drain region 110d is, for example, 5 to 8 × 10 ¹⁴ atoms / cm ³ , and the phosphorus element concentration in the gettering region 110g is, for example, 8 × 10 ^{14 to} 1.2 × 10 ¹⁵ atoms. / Cm ³ . Thus, the phosphorus element concentration in the gettering region 110g is higher than that in the source region 110s and the drain region 110d.

The semiconductor layer 110 is manufactured by a CGS method, and the semiconductor layer 110 contains nickel as a catalyst element. The catalyst element concentration of the source region 110s, the channel region 110c, and the drain region 110d is, for example, 1 to 3 × 10 ¹⁶ atoms / cm ³ , and the catalyst element concentration of the gettering region 110g is, for example, 1 × 10 ¹⁹ to 1 × 10. ²⁰ atoms / cm ³ . As described above, the concentration of the catalytic element in the channel region 110c is low, thereby suppressing an unexpected increase in off-current in the TFT 200.

  The insulating layer 120 is provided with regions having different thicknesses. In the following description, a thicker region is referred to as a thick region (first region) 120H, and a thinner region is referred to as a thin region (second region) 120L. In the insulating layer 120, the thickness of the thick region 120H is, for example, 70 to 100 nm, and the thickness of the thin region 120L is, for example, 30 to 50 nm. The thin region 120L of the insulating layer 120 only needs to be thinner than the thick region 120H, and the thin region 120L may be completely removed (that is, the thickness of the thin region (second region) 120L is substantially zero. May be). In the semiconductor device 100, the source region 110s, the channel region 110c, and the drain region 110d of the semiconductor layer 110 correspond to the thick region 120H of the insulating layer 120, and the gettering region 110g of the semiconductor layer 110 corresponds to the thin region 120L of the insulating layer 120. It corresponds to.

  Hereinafter, a method of manufacturing the semiconductor device 100 will be described with reference to FIGS.

As shown in FIG. 2A, a base coat layer 104 is formed on the insulating substrate 102. The insulating substrate 102 is a glass substrate, for example. The base coat layer 104 is made of an insulating material and may have a two-layer structure. Thereafter, an amorphous semiconductor layer Sa is formed on the base coat layer 104. The amorphous semiconductor layer Sa is, for example, an amorphous silicon layer. Thereafter, a trace amount of the catalyst element 112 is added to the surface of the amorphous semiconductor layer Sa. The catalyst element 112 is, for example, nickel, and the addition amount is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ atoms / cm ² .

  As shown in FIG. 2B, heat treatment is performed to crystallize the amorphous semiconductor layer Sa to form a crystalline semiconductor layer Sb. Since nickel 112 is added as a catalyst to the amorphous semiconductor layer Sa, crystallization is promoted in this crystallization step.

  As shown in FIG. 2C, the laser beam L is irradiated. Thereby, the crystallinity of the crystalline semiconductor layer Sb is improved.

  Thereafter, unnecessary portions of the crystalline semiconductor layer Sb are removed, and an island-shaped semiconductor layer 110 is formed as shown in FIG. Here, for the purpose of controlling the threshold voltage, an impurity element imparting p-type conductivity (such as B) may be added to the entire surface of the semiconductor layer 110 at a low concentration.

As shown in FIG. 2E, an insulating layer 120 covering the semiconductor layer 110 is deposited. The insulating layer 120 is made of, for example, SiO ₂ and has a thickness of 70 to 100 nm. Next, the conductive layer G is deposited by sputtering. For example, the conductive layer G may have a two-layer structure. The conductive layer G has, for example, a laminated structure of tungsten (W) having a thickness of 300 to 400 nm and TaN having a thickness of 20 to 60 nm.

  As shown in FIG. 2F, a photoresist layer P is deposited. Here, the photoresist layer P is a positive type. Thereafter, exposure is performed by aligning the halftone mask HM with respect to the photoresist layer P. The halftone mask HM has three regions MA, MB, and MC having different light transmittances. The exposure is performed using light having a wavelength of 365 nm (i-line) and / or 405 nm / 436 nm (g-h line). The regions of the halftone mask HM are arranged in the order of the regions MC, MB, MA, MB, and MC along the direction in which the semiconductor layer 110 extends. The light transmittance of the region MC of the halftone mask HM is higher than that of the regions MA and MB, and the light transmittance of the region MB is higher than that of the region MA. For example, the region MA is formed from a light shielding film, and the region MB is formed from a semi-transmissive film. The light transmittance of the region MB is, for example, 30 to 70%. By this exposure, the portion corresponding to the region MA of the halftone mask HM in the photoresist layer P hardly changes, while the portion corresponding to the region MC changes greatly.

  As shown in FIG. 2G, the portion corresponding to the region MC of the halftone mask HM in the photoresist layer P is removed by development. The portions corresponding to the areas MA and MB of the halftone mask HM remain. This is because the solubility in the developer increased due to the change in the photoresist layer P caused by exposure. However, since the light transmittance of the region MB is higher than that of the region MA, the portion PB corresponding to the region MB of the halftone mask HM in the photoresist layer P is more than the portion PA corresponding to the region MA of the halftone mask HM. thin. In this way, a thick region (first region) PA and a thin region (second region) PB are formed in the photoresist layer P by development. For example, the thickness of the thick region PA of the photoresist layer P is 1.0 to 2.0 μm, and the thickness of the thin region PB is 0.1 to 1.0 μm. As shown in FIG. 2G, the width of the photoresist layer P is shorter than that of the semiconductor layer 110 when viewed in the extending direction of the semiconductor layer 110, and the photoresist layer P overlaps with the central portion of the semiconductor layer 110. Are arranged so as not to overlap with the end portion of the semiconductor layer 110.

As shown in FIG. 3A, a portion of the conductive layer G that is not covered with the photoresist layer P is etched. Etching is performed, for example, in an atmosphere of CF ₄ / O ₂ gas for 50 seconds. Thereby, regions having different thicknesses corresponding to the presence or absence of the photoresist layer P are formed in the conductive layer G. In the following description, the thick region of the conductive layer G is called a thick region (first region) GH, and the thin region is called a thin region (second region) GL. The thickness of the thick region GH is, for example, 300 to 400 nm, and the thickness of the thin region GL is, for example, 200 to 300 nm. The overlapping portion of the thin region GL and the semiconductor layer 110 corresponds to the gettering region 110 g of the semiconductor layer 110. The thin region GL of the conductive layer G only needs to be thinner than the thick region GH, and the thin region GL may be completely removed (that is, the thickness of the thin region (second region) GL is substantially zero). May be).

As shown in FIG. 3B, the photoresist layer P is partially ashed. Ashing is performed in an O ₂ gas atmosphere for 50 seconds. By isotropically removing the photoresist layer P, a portion corresponding to the thin region PB of the photoresist layer P is removed, and only a portion corresponding to the thick region PA remains, and a photoresist layer PA ′ is formed. The

As shown in FIG. 3C, an etching process is performed, whereby the conductive layer G not covered with the photoresist layer PA ′ is removed to form the conductive layer 130 and a part of the insulating layer 120 is removed. Thus, a thick region (first region) 120H and a thin region (second region) 120L are formed in the insulating layer 120. Etching is performed, for example, in a CF ₄ / O ₂ gas atmosphere for 150 seconds. In this etching, the etching rate of the conductive layer G is about 2 to 3 nm / second, and the etching rate of the insulating layer 120 is about 0.2 to 0.5 nm / second. The thick region 120H and the thin region 120L of the insulating layer 120 correspond to the thick region GH and the thin region GL of the conductive layer G before performing the etching process. The thickness of the thick region 120H is, for example, 70 to 100 nm, and the thickness of the thin region 120L is, for example, 30 to 50 nm. Note that the thickness (pattern) of the insulating layer 120 can be measured using a scanning electron microscope (SEM).

  As shown in FIG. 3D, the photoresist layer PA 'is ashed. As a result, the conductive layer 130 is exposed. Note that the conductive layer 130 functions as a gate electrode of the TFT 200.

As shown in FIG. 3E, the semiconductor layer 110 is doped with phosphorus. Phosphorus doping is performed by, for example, an ion doping method, and phosphine is used as a doping gas, for example. Phosphorus is doped through the insulating layer 120 in a portion of the semiconductor layer 110 that does not overlap with the gate electrode 130. The phosphorus concentration in the semiconductor layer 110 varies depending on the thickness of the insulating layer 120. Of the semiconductor layer 110, the phosphorus concentration in the region below the thin region 120L of the insulating layer 120 is higher than the phosphorus concentration in the region below the thick region 120H. As described above, the region below the thin region 120L of the insulating layer 120 in the semiconductor layer 110 becomes the gettering region 110g, and the region below the thick region 120H of the insulating layer 120 becomes the source region 110s and the drain region 110d. . The phosphorus concentration in the gettering region 110g is, for example, 8 × 10 ^{14 to} 1.2 × 10 ¹⁵ atoms / cm ³ , and the phosphorus concentration in the source region 110s and the drain region 110d is, for example, 5 to 8 × 10 ¹⁴ atoms / cm ^3. It is. The phosphorus concentration in the semiconductor layer 110 can be measured using, for example, a scanning capacitance microscope (SCM).

  Further, since the thin region 120L corresponding to the gettering region 110g is thin, phosphorus ions are implanted into the gettering region 110g with a relatively high acceleration voltage as compared with the source region 110s and the drain region 110d. For this reason, the impact energy received by the gettering region 110g is large, and the crystallinity is further broken. On the other hand, since phosphorus ions are implanted into the source region 110s and the drain region 110d through the relatively thick region 120H, the impact energy of the ions at the time of implantation is relaxed, and a good crystal state is maintained. The

  As shown in FIG. 3F, heat treatment is performed in an inert atmosphere (for example, in a nitrogen atmosphere). In the heat treatment step, nickel existing in the channel region 110c, the source region 110s, and the drain region 110d of the semiconductor layer 110 is indicated by arrows from the channel region 110c to the source region 110s, the drain region 110d, and the gettering region 110g. Move in the direction

Strictly speaking, since the source region 110s and the drain region 110d also contain phosphorus, the source region 110s and the drain region 110d also have a gettering effect. However, the gettering region 110g contains more phosphorus than the source region 110s and the drain region 110d, and the solid solubility of the catalytic element (nickel) in the gettering region 110g is a solid solution in the source region 110s and the drain region 110d. Higher than degree. In addition, the gettering region 110g is thin in the thin region 120L positioned thereon and has a large impact energy upon doping. Therefore, the gettering region 110g becomes amorphous, causing crystal defects and dangling bonds (dangling bonds). Will increase. The free energy of nickel in the gettering region 110g is lowered, and as a result, the gettering region 110g functions as a nickel segregation site. Therefore, the gettering effect of the gettering region 110g is higher than that of the source region 110s and the drain region 110d, and the catalytic element in the semiconductor layer 110 is gettered to the gettering region 110g. After the gettering treatment, the catalyst element concentration in the gettering region 110g is 1 to 3 × 10 ¹⁹ atoms / cm ³ or more, and the catalyst element concentration in the channel region of the semiconductor layer 110 is 1 to 3 × 10 ¹⁶ atoms / cm ³ or less. Become.

  As shown in FIG. 3G, the semiconductor device 100 including the N-channel TFT 200 is manufactured. Since the concentration of the catalytic element in the channel region 110c is reduced, a sudden increase in off-current in the N-channel TFT 200 is suppressed. Note that an interlayer insulating film that covers the insulating layer 120 and the gate electrode 130 may be formed as needed. Further, an LDD region may be formed in the semiconductor layer 110 as necessary. Further, after the gettering step, the gettering region 110g may be removed as necessary.

  In the manufacturing method of this embodiment, the photoresist layer P is used not only for forming the gate electrode 130 but also for forming the thick region 120H and the thin region 120L in the insulating film 120. For this reason, the number of photolithography processes can be reduced. In addition, since the number of photolithography processes can be reduced, defects due to particles related to the photolithography process can be suppressed and yield can be improved.

  In the above description, nickel is exemplified as the catalyst element, but the present invention is not limited to this. As the catalytic element, one or more elements selected from Ni, Co, Sn, Pb, Pd, Fe, and Cu may be used.

  In the above description, phosphorus is exemplified as the impurity belonging to Group B of the periodic table, but the present invention is not limited to this. As the impurities, other elements belonging to Group B of the periodic table B may be used, or a plurality of elements belonging to Group B of the periodic table may be used.

  In the above description, the photoresist layer P having regions with different thicknesses is provided and the photoresist layer P is partially ashed to form the mask of the gate electrode 130. However, the present invention is not limited to this. . The mask of the gate electrode 130 may be formed by anisotropically ashing the photoresist layer P having the same thickness.

  Further, after the insulating layer 120 shown in FIG. 3A is thinned, an impurity element belonging to Group B of the periodic table (for example, boron) may be implanted. Thereby, the region to be the gettering region 110g in the semiconductor layer 110 is further amorphized, and the gettering effect can be further increased.

(Embodiment 2)
Hereinafter, a second embodiment of the semiconductor device according to the present invention will be described.

  FIG. 4 is a schematic diagram of an active matrix substrate 300 including the semiconductor device 100 of the present embodiment. 4A is a schematic plan view of the active matrix substrate 300, and FIG. 4B is a schematic cross-sectional view taken along the line A-A 'of FIG. 4A.

  As shown in FIG. 4, an active matrix substrate 300 includes a semiconductor device provided with a thin film transistor element (hereinafter also referred to as “TFT element”) 210 having a first thin film transistor (TFT) 220 and a second thin film transistor (TFT) 230. 100, a source bus line 310, a gate bus line 320, and a pixel electrode 330. The TFTs 220 and 230 are both N-channel thin film transistors. Two TFTs 220 and 230 of the TFT element 210 are arranged in series. The TFTs 220 and 230 are arranged in the order of the TFTs 220 and 230 from the source contact part 110t1 to the drain contact part 110t2. As described above, the plurality of TFTs are arranged in series, so that the off-current of the TFT element 210 is suppressed.

  The gate bus line 320 includes a main body part 320a extending in the x direction and a branch part 320b extending from the main body part 320a in the y direction. Part of the gate bus line 320 functions as the gate electrodes 130 a and 130 b of the TFTs 220 and 230.

  The source region 110 s 1, the channel region 110 c 1 and the drain region 110 d 1 of the TFT 220, and the source region 110 s 2, the channel region 110 c 2 and the drain region 110 d 2 of the TFT 230 are provided in the semiconductor layer 110. The source region 110 s 1 of the TFT 220 is provided with a source contact portion 110 t 1 in contact with the source electrode 222 electrically connected to the source bus line 310, and the drain region 110 d 2 of the TFT 230 is electrically connected to the pixel electrode 330. A drain contact portion 110t2 is provided in contact with the drain electrode 232 formed. The drain region 110d1 of the TFT 220 and the source region 110s2 of the TFT 230 are continuous.

  The semiconductor layer 110 is manufactured by a CGS method using nickel as a catalyst element. The semiconductor layer 110 has a first gettering region 110g1, a second gettering region 110g2, and a third gettering region 110g3 for removing the catalyst element. The gettering region 110g1 is adjacent to the source region 110s1 of the TFT 220, and the gettering region 110g2 is adjacent to the drain region 110d2 of the TFT 230.

  The semiconductor layer 110 includes three portions, that is, a first end portion 110x, a second end portion 110y, and a central portion 110z located between the first and second end portions 110x and 110y. In the first end portion 110x, a part of the source region 110s1 including the source contact portion 110t1 and the first gettering region 110g1 are provided. In the second end portion 110y, a part of the drain region 110d2 including the drain contact portion 110t2 and the second gettering region 110g2 are provided. Further, in the central portion 110z, a part of the source region 110s1 of the TFT 220, a channel region 110c1 and a drain region 110d1, a part of the drain region 110d2 of the TFT 230, a channel region 110c2 and a source region 110s2, and a third gettering region 110g3 are provided. It has been. Thus, in the semiconductor device 100, not only the first and second gettering regions 110g1 and 110g2 are provided at the end portions 110x and 110y of the semiconductor layer 110, but the third getter is provided at the central portion 110z of the semiconductor layer 110. A ring region 110g3 is provided. The third gettering region 110g3 is provided near the channel region 110c2. As a result, the catalytic element remaining in the channel region 110c2 can be sufficiently gettered, and the sudden increase in off-current in the TFT 230 is suppressed.

  Hereinafter, a method of manufacturing the active matrix substrate 300 will be described with reference to FIGS.

  As shown in FIG. 5A, a base coat layer 104 is formed on the glass substrate 102. The base coat layer 104 is made of an insulating material and may have a two-layer structure. An amorphous semiconductor layer Sa is formed on the base coat layer 104. The amorphous semiconductor layer Sa is, for example, an amorphous silicon layer. Thereafter, a trace amount of the catalyst element 112 is added to the surface of the amorphous semiconductor layer Sa. The catalyst element 112 is, for example, nickel.

  As shown in FIG. 5B, heat treatment is performed to crystallize the amorphous semiconductor layer Sa to form a crystalline semiconductor layer Sb. Since nickel 112 is added as a catalyst element to the amorphous semiconductor layer Sa, crystallization is promoted.

  As shown in FIG.5 (c), the laser beam L is irradiated. Thereby, the crystallinity of the crystalline semiconductor layer Sb is improved.

  Next, unnecessary portions of the crystalline semiconductor layer Sb are removed, and an island-shaped semiconductor layer 110 is formed as shown in FIG. Here, an impurity element imparting a low concentration of p-type (such as B) may be added to the entire surface of the semiconductor layer 110 for the purpose of controlling the threshold voltage.

  As shown in FIG. 5E, an insulating layer 120 covering the semiconductor layer 110 is deposited. Next, the conductive layer G is deposited by sputtering. For example, the conductive layer G may have a two-layer structure.

  As shown in FIG. 5F, a photoresist layer P is deposited. Thereafter, exposure is performed by aligning the halftone mask HM with respect to the photoresist layer P. The halftone mask HM has three regions MA, MB, and MC having different light transmittances. The regions of the halftone mask HM are arranged in the order of the regions MC, MB, MA, MB, MA, MB, and MC along the direction in which the semiconductor layers 110n and 110g extend. The light transmittance of the region MC of the halftone mask HM is higher than the regions MA and MB, and the light transmittance of the region MB is higher than that of the region MA. For example, the region MA is formed from a light shielding film, and the region MB is formed from a semi-transmissive film.

  As shown in FIG. 5G, development is performed to remove a portion of the photoresist layer P corresponding to the region MC of the halftone mask HM. Thereby, the thick region PA and the thin region PB are formed in the photoresist layer P.

  As shown in FIG. 6A, a portion of the conductive layer G that is not covered with the photoresist layer P is etched. Thereby, the thick region GH and the thin region GL are formed in the conductive layer G. A portion of the semiconductor layer 110 that overlaps the thin region GL becomes a gettering region 110g.

  As shown in FIG. 6B, a part of the photoresist layer P is ashed. As a result, the portion corresponding to the thin region PB of the photoresist layer P is removed, and only the portion corresponding to the thick region PA remains, so that the photoresist layer PA 'is formed.

  As shown in FIG. 6C, an etching process is performed, whereby the conductive layer G not covered with the photoresist layer PA ′ is removed to form the conductive layers 130a and 130b and the insulating layer 120 has a thick region. 120H and thin region 120L are formed. The region 120H and the thin region 120L of the insulating layer 120 correspond to the thick region GH and the thin region GL of the conductive layer G.

  As shown in FIG. 6D, the photoresist layer PA 'is ashed. Thereby, the conductive layers 130a and 130b are exposed. The conductive layers 130a and 130b function as gate electrodes of the TFTs 220 and 230.

As shown in FIG. 6E, phosphorus is doped. Phosphorus is doped through the insulating layer 120 in portions of the semiconductor layer 110 that do not overlap with the conductive layers 130a and 130b. The phosphorus concentration in the semiconductor layer 110 varies depending on the thickness of the insulating layer 120. Of the semiconductor layer 110, the phosphorus concentration in the region below the thin region 120L of the insulating layer 120 is higher than the phosphorus concentration in the region below the thick region 120H. Therefore, as shown in FIG. 4, the regions under the thin region 120L of the insulating layer 120 in the semiconductor layer 110 become gettering regions 110g1, 110g2, and 110g3, and the regions under the thick region 120H of the insulating layer 120. Becomes source regions 110s1, 110s2 and drain regions 110d1, 110d2. The phosphorus concentrations of the source regions 110s1, 110s2 and the drain regions 110d1, 110d2 are, for example, 5 to 8 × 10 ¹⁴ atoms / cm ³ , and the phosphorus concentrations of the gettering regions 110g1, 110g2, 110g3 are, for example, 8 × 10 ¹⁴ to 1. 2 × 10 ¹⁵ atoms / cm ³ . As described above, the phosphorous concentrations of the gettering regions 110g1, 110g2, and 110g3 in the semiconductor layer 110 are higher than the phosphorous concentrations of the source regions 110s1 and 110s2 and the drain regions 110d1 and 110d2.

  Further, since the thin regions 120L corresponding to the gettering regions 110g1, 110g2, and 110g3 are thin, the gettering regions 110g1, 110g2, and 110g3 are relatively higher than the source regions 110s1, 110s2 and the drain regions 110d1, 110d2. Phosphorus ions are implanted at an acceleration voltage. For this reason, the impact energy received by the gettering regions 110g1, 110g2, and 110g3 is large, and the crystallinity is further broken. In contrast, since phosphorus ions are implanted into the source regions 110s1 and 110s2 and the drain regions 110d1 and 110d2 through the relatively thick region 120H, the impact energy of ions during implantation is mitigated, and good crystallinity is achieved. State is maintained.

  As shown in FIG. 6F, heat treatment is performed in an inert atmosphere (for example, in a nitrogen atmosphere). In the heat treatment step, nickel existing in the channel regions 110c1 and 110c2, the source regions 110s1 and 110s2 and the drain regions 110d1 and 110d2 of the semiconductor layer 110 moves to the gettering regions 110g1, 110g2, and 110g3.

  Strictly speaking, since the source regions 110s1 and 110s2 and the drain regions 110d1 and 110d2 also contain phosphorus, the source regions 110s1 and 110s2 and the drain regions 110d1 and 110d2 also have a gettering effect. However, since the gettering regions 110g1, 110g2, and 110g3 contain more phosphorus than the source regions 110s1 and 110s2 and the drain regions 110d1 and 110d2, the solid solubility of the catalytic element (nickel) in the gettering region 110g is the source. It is higher than the solid solubility in the region 110s and the drain region 110d. In addition, the gettering region 110g is thin in the thin region 120L positioned thereon, and the collision energy received during doping is large. Therefore, the gettering region 110g becomes amorphous, causing crystal defects and dangling bonds (dangling bonds). Will increase. The free energy of nickel in the gettering region 110g is lowered, and as a result, the gettering region 110g functions as a nickel segregation site. Accordingly, the gettering effect of the gettering regions 110g1, 110g2, and 110g3 is higher than that of the source regions 110s1 and 110s2 and the drain regions 110d1 and 110d2.

  As shown in FIG. 6G, an interlayer insulating film 140 covering the insulating layer 120 and the gate electrodes 130a and 130b is formed. Contact holes are formed in the interlayer insulating film 140, and the source electrode 222, the drain electrode 232, the source bus line 310, and the pixel electrode 330 are formed. As described above, the active matrix substrate 300 provided with the N-channel TFTs 220 and 230 is formed.

  In the manufacturing method described above, the photoresist layer P is used not only for forming the gate electrodes 130a and 130b but also for forming the thick region 120H and the thin region 120L in the insulating film 120. For this reason, the frequency | count of a photolithography process can be suppressed.

  Further, as shown in FIG. 6A, after the insulating layer 120 is thinned, an impurity element (for example, boron) belonging to Group 3 B of the periodic table may be implanted. As a result, the regions that become the gettering regions 110g1, 110g2, and 110g3 in the semiconductor layer 110 are further amorphized, and the gettering effect can be further increased.

(Embodiment 3)
Hereinafter, a third embodiment of the semiconductor device according to the present invention will be described.

  FIG. 7 is a schematic diagram of an active matrix substrate 300 including the semiconductor device 100 of the present embodiment. FIG. 7A is a schematic cross-sectional view in the display area of the active matrix substrate 300, and FIG. 7B is a schematic cross-sectional view in the peripheral area of the active matrix substrate 300.

  As shown in FIG. 7A, a TFT element 210 is provided in the display area of the active matrix substrate 300, and in the peripheral area arranged around the display area, as shown in FIG. 7B. TFTs 200n and 200p are provided. The TFTs 200n and 200p are used as drivers. The TFTs 200 and 200n are N-channel TFTs, and the TFT 200p is a P-channel TFT.

  The TFT element 210 has the same configuration as the TFT element described in the second embodiment with reference to FIG. The TFT 200n has the same configuration as the TFT 200 described in Embodiment 1 with reference to FIG. Therefore, redundant description is omitted to avoid redundancy.

  In the TFT element 210, as described with reference to FIG. 4, the semiconductor layer 110 includes the source regions 110s1, 110s2, the channel regions 110c1, 110c2, the drain regions 110d1, 110d2, and the gettering regions 110g1, 110g2, 110g3. Have. In the TFT 200n, the semiconductor layer 110n has a source region 110ns, a channel region 110nc, a drain region 110nd, and a gettering region 110ng. Similarly, in the TFT 200p, the semiconductor layer 110p has a source region 110ps, a channel region 110pc, a drain region 110pd, and a gettering region 110pg.

  Hereinafter, a method for manufacturing the active matrix substrate 300 will be described with reference to FIGS. 4 and 7 to 9. 8 and 9, the manufacturing process of the TFT 200 provided in the display area on the left side of the paper surface is shown, and the manufacturing process of TFTs 200n and 200p provided in the peripheral area on the right side of the paper surface is shown.

  As shown in FIG. 8A, a base coat layer 104 is formed on the glass substrate 102. The base coat layer 104 is made of an insulating material and may have a two-layer structure. An amorphous semiconductor layer Sa is formed on the base coat layer 104. Thereafter, a trace amount of the catalyst element 112 is added to the surface of the amorphous semiconductor layer Sa. The catalyst element 112 is, for example, nickel.

  As shown in FIG. 8B, heat treatment is performed to crystallize the amorphous semiconductor layer Sa to form a crystalline semiconductor layer Sb. Nickel 112 is added as a catalytic element to the amorphous semiconductor layer Sa, thereby promoting crystallization.

  As shown in FIG. 8C, the laser beam L is irradiated. Thereby, the crystallinity of the crystalline semiconductor layer Sb is improved.

  Next, unnecessary portions of the crystalline semiconductor layer Sb are removed and element isolation is performed to form island-shaped semiconductor layers 110, 110n, and 110p as shown in FIG. 8D. Here, for the purpose of controlling the threshold voltage, an impurity element that imparts a low-concentration p-type to the entire surface of the semiconductor layers 110, 110n, and 110p or to the semiconductor layers 110 and 110n for the N-channel TFT. B etc.) may be added.

  As shown in FIG. 8E, an insulating layer 120 covering the semiconductor layers 110, 110n, and 110p is deposited. Next, the conductive layer G is deposited by sputtering.

  As shown in FIG. 8F, a photoresist layer P is deposited. Thereafter, exposure is performed by aligning the halftone mask HM with respect to the photoresist layer P. The halftone mask HM has three regions MA, MB, and MC having different light transmittances. The areas of the halftone mask HM are arranged in the order of areas MC, MB, MA, MB, MA, MB, and MC along the direction in which the semiconductor layer 110 extends in the display area. Further, the regions MC, MB, MA, MB, and MC are arranged in the order of the regions MC, MB, MA, MB, and MC in the peripheral region, and the regions MC, MA, and MC are arranged in the P-channel TFT formation portion of the peripheral region. Is arranged. The light transmittance of the region MC of the halftone mask HM is higher than that of the regions MB and MA, and the light transmittance of the region MB is higher than that of the region MA.

  As shown in FIG. 8G, the portions corresponding to the region MC of the halftone mask HM in the photoresist layer P are removed by development, and photoresist layers Pa, Pb, and Pc are formed. The photoresist layers Pa, Pb, Pc have a thick area PA and a thin area PB. In the photoresist layer Pa formed in the display area, areas PB, PA, PB, PA, and PB are arranged in this order. In addition, regions PB, PA, and PB are arranged in this order in Pb formed in the peripheral region, and a region PA is arranged in the photoresist layer Pc. The photoresist layers Pa, Pb, and Pc are arranged so as to overlap with the central portions of the semiconductor layers 110, 110n, and 110p and not with the end portions.

  As shown in FIG. 9A1, portions of the conductive layer G that are not covered with the photoresist layers Pa, Pb, and Pc are etched. Thereby, the thick region GH and the thin region GL are formed in the conductive layer G.

As shown in FIG. 9A2, boron is implanted into the semiconductor layers 110, 110n, and 110p. Thereby, boron is implanted into the regions of the semiconductor layers 110, 110n, and 110p that do not overlap with the photoresist layers Pa, Pb, and Pc through the conductive layer G and the insulating layer 120. The concentration of boron implanted into the semiconductor layers 110, 110n, and 110p is, for example, 1 × 10 ¹³ to 1 × 10 ¹⁴ atoms / cm ³ .

  As shown in FIG. 9B, a part of the photoresist layer P is ashed. As a result, the portion corresponding to the thin region PB of the photoresist layer P is removed, and only the portion corresponding to the thick region PA remains, so that the photoresist layer PA 'is formed.

  As shown in FIG. 9C, an etching process is performed. Thus, the conductive layer G not covered with the photoresist layer PA ′ is removed to form the conductive layers 130a, 130b, 130n, and 130p, and a part of the insulating layer 120 is removed to form the thick region 120H in the insulating layer 120. And the thin region 120L is formed. The insulating layer 120 has a thick region 120H and a thin region 120L corresponding to the thick region GH and the thin region GL of the conductive layer G.

  As shown in FIG. 9D1, the photoresist layer PA 'is ashed. As a result, the conductive layers 130a, 130b, 130n, and 130p are exposed. The conductive layers 130a, 130b, 130n, and 130p function as gate electrodes of the TFTs 220, 230, 230n, and 230p.

  As shown in FIG. 9 (d2), a photoresist layer P1 is formed. The photoresist layer P1 is provided so as to correspond to the TFT 200p, and is disposed so as to overlap with the central portion of the semiconductor layer 110p and not with the end portion.

As shown in FIG. 9E, phosphorus is doped. Phosphorus is doped through the insulating layer 120 in portions of the semiconductor layers 110, 110n, and 110p that do not overlap with the gate electrodes 130a, 130b, and 130n and the photoresist layer P1. Depending on the thickness of the insulating layer 120, the phosphorus concentration in the semiconductor layers 110, 110n, and 110p varies. Of the semiconductor layers 110 and 110n, the phosphorus concentration in the region below the thin region 120L of the insulating layer 120 is higher than the phosphorus concentration in the region below the thick region 120H. For this reason, as shown in FIGS. 4 and 7, the regions below the thin region 120L of the insulating layer 120 in the semiconductor layers 110, 110n, and 110p become gettering regions 110g1, 110g2, 110g3, 110ng, and 110pg. The regions below the thick region 120H of the layer 120 are the source regions 110s1, 110s2, 110ns, 110ps and the drain regions 110d1, 110d2, 110nd, 110pd. The phosphorus concentration of the source regions 110s1, 110s2, 110ns, 110ps and the drain regions 110d1, 110d2, 110nd, 110pd is, for example, 5-8 × 10 ¹⁴ atoms / cm ³ , and the gettering regions 110g1, 110g2, 110g3, 110ng, 110pg The phosphorus concentration of is, for example, 8 × 10 ^{14 to} 1.2 × 10 ¹⁵ atoms / cm ³ . As described above, the phosphorous concentrations in the gettering regions 110g1, 110g2, 110g3, 110ng, and 110pg in the semiconductor layer 110 are higher than the phosphorous concentrations in the source regions 110s1, 110s2, 110ns, and 110ps and the drain regions 110d1, 110d2, 110nd, and 110pd. .

  Further, since the thin regions 120L corresponding to the gettering regions 110g1, 110g2, 110g3, 110ng, and 110pg are thin, the gettering regions 110g1, 110g2 are compared with the source regions 110s1, 110s2, and 110ns and the drain regions 110d1, 110d2, and 110nd. , 110g3, 110ng, and 110pg are implanted with phosphorus ions at a relatively high acceleration voltage. For this reason, the impact energy received by the gettering regions 110g1, 110g2, 110g3, 110ng, and 110pg is large, and the crystallinity is further broken. In contrast, phosphorus ions are implanted into the source regions 110s1, 110s2, and 110ns and the drain regions 110d1, 110d2, and 110nd through the relatively thick region 120H. Crystal state is maintained.

  As shown in FIG. 9F, after ashing the photoresist layer P1, heat treatment is performed in an inert atmosphere (for example, in a nitrogen atmosphere). In the heat treatment step, nickel existing in the channel regions 110c1, 110c2, 110nc, 110pc, the source regions 110s1, 110s2, 110ns, 110ps and the drain regions 110d1, 110d2, 110nd, 110pd of the semiconductor layers 110, 110n, 110p is gettered. Move to areas 110g1, 110g2, 110g3, 110ng, and 110pg. In addition, since the impurity elements in the channel regions 110nc and 110pc of the semiconductor layers 110n and 110p are reduced in this way, a sudden increase in off-current in the TFT used for the driver is suppressed, resulting in a line defect Is suppressed.

  As shown in FIG. 9G, an interlayer insulating film 140 covering the insulating layer 120 and the gate electrodes 130a, 130b, 130n, and 130p is formed. Contact holes are formed in the interlayer insulating film 140, and a source electrode 222, a drain electrode 232, a source bus line 310, source electrodes 310ns and 310ps, drain electrodes 310nd and 310pd, and a pixel electrode 330 are formed. As described above, the active matrix substrate 300 is formed.

  In the semiconductor device 100 of this embodiment, the photoresist layer P is used not only for forming the gate electrodes 130a, 130b, 130n, and 130p but also for forming the thick region 120H and the thin region 120L in the insulating film 120. Further, the photoresist layer P prevents an impurity element (for example, boron) belonging to Group B of the periodic table from being implanted into a part of the semiconductor layers 110 and 110n of the N-channel TFTs 200 and 200n.

  Although the TFT 200n and the TFT 200p are separately provided in the peripheral region here, the present invention is not limited to this. The TFT 200n and the TFT 200p may constitute a complementary TFT.

  In the above description, boron is exemplified as the impurity belonging to Group 3 B of the periodic table, but the present invention is not limited to this. As the impurity, another element belonging to Group B of the periodic table B may be used, or a plurality of elements belonging to Group B of the periodic table B may be used.

  According to the present invention, a high-quality semiconductor device can be easily manufactured. This semiconductor device is suitably used for an active matrix substrate of a liquid crystal display device, for example.

1 is a schematic cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. (A)-(g) is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device of 1st Embodiment, respectively. (A)-(g) is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device of 1st Embodiment, respectively. It is a schematic diagram which shows an active matrix substrate provided with 2nd Embodiment of the semiconductor device by this invention, (a) is a schematic top view of an active matrix substrate, (b) is AA of (a). It is sectional drawing along a line. (A)-(g) is typical sectional drawing for demonstrating the manufacturing method of the active-matrix board | substrate of FIG. 4, respectively. (A)-(g) is typical sectional drawing for demonstrating the manufacturing method of the active-matrix board | substrate of FIG. 4, respectively. It is typical sectional drawing which shows an active matrix substrate provided with 3rd Embodiment of the semiconductor device by this invention. (A)-(g) is typical sectional drawing for demonstrating the manufacturing method of the active-matrix board | substrate of FIG. 7, respectively. (A1)-(g) is typical sectional drawing for demonstrating the manufacturing method of the active-matrix board | substrate of FIG. 7, respectively. It is typical sectional drawing of the conventional semiconductor device. (A)-(g) is typical sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device, respectively. (A)-(e) is typical sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device, respectively.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 102 Insulating substrate 104 Base coat layer 110 Semiconductor layer 110s Source region 110c Channel region 110d Drain region 110g Gettering region 120 Insulating layer 120H Thick region 120L Thin region 130 Gate electrode 200 TFT

Claims (4)

A method of manufacturing a semiconductor device comprising an N-channel thin film transistor,
Preparing a semiconductor layer containing a catalytic element for promoting crystallization;
Crystallization of the semiconductor layer;
Forming an insulating layer covering the semiconductor layer;
Forming a conductive layer on the insulating layer;
Forming a first region and a second region thinner than the first region in the insulating layer;
By implanting an impurity element belonging to Group B of the periodic table into the semiconductor layer through the insulating layer, a source region is formed in the semiconductor layer corresponding to the first region and the second region of the insulating layer. Or a step of forming a drain region and a gettering region, wherein the impurity element concentration in the gettering region of the semiconductor layer is higher than the impurity element concentration in the source region or drain region of the semiconductor layer;
Moving the catalytic element in the semiconductor layer to the gettering region,
After the step of forming the conductive layer and before the step of forming the first region and the second region in the insulating layer,
Forming a photoresist layer covering a part of the conductive layer, the photoresist layer overlapping a portion that becomes a source region or a drain region of the semiconductor layer and not a portion that becomes a gettering region of the semiconductor layer; When,
Forming a first region and a second region thinner than the first region in the conductive layer by thinning a portion of the conductive layer that is not covered with the photoresist layer;
Partially ashing the photoresist layer so as to remove a portion of the photoresist layer and not remove the remaining portion of the photoresist layer;
Forming a gate electrode of the N-channel thin film transistor by etching the conductive layer using a portion of the photoresist layer that has not been removed as a mask.
The method of manufacturing a semiconductor device, wherein the first and second regions of the insulating layer are formed corresponding to the first and second regions of the conductive layer. Further comprising forming a first region and a second region thinner than the first region in the photoresist layer;
The step of partially ashing the photoresist layer removes a portion corresponding to the second region of the photoresist layer and does not remove a part of the portion corresponding to the first region of the photoresist layer. Item 14. A method for manufacturing a semiconductor device according to Item 1.   The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the first and second regions in the photoresist layer includes a step of using a halftone mask having three regions having different light transmittances. The semiconductor device further includes a P-channel thin film transistor,
Separating the semiconductor layer for the P-channel thin film transistor from the semiconductor layer for the N-channel thin film transistor in the crystallized semiconductor layer;
2. The step of disposing the photoresist layer so as not to overlap the gettering region of the semiconductor layer for the N-channel thin film transistor and injecting an impurity element belonging to Group B of the periodic table is included. 4. A method for manufacturing a semiconductor device according to any one of items 1 to 3.

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