JP2009141459A - Piezoelectric oscillator - Google Patents

Abstract

を満たすように構成した。
【選択図】図１A piezoelectric oscillator that effectively utilizes a region in which the capacitance value of a MOS varactor of an oscillation circuit changes linearly.
In a VCXO1 configured to apply a reference voltage Vref to the gates of varactors D1 and D2 and to apply an output voltage of a resistance switching unit 7 to back gates of the varactors D1 and D2, the varactors D1 and D2 Has a CV characteristic having a region in which the capacitance value is substantially constant with respect to a change in the inter-terminal voltage VBG and a region in which the capacitance value changes, with the inter-terminal voltage VBG being approximately 0 V as a boundary. At the same time, the first reference voltage Vref1 is

It was configured to satisfy.
[Selection] Figure 1

Description

  The present invention relates to a piezoelectric oscillator having a frequency voltage control function.

A conventional crystal oscillator (hereinafter referred to as “VCXO”) having a frequency voltage control function adjusts the voltage between terminals of a variable capacitance diode or a MOS type variable capacitance element by a control voltage applied from the outside, and makes these variable A desired oscillation frequency is obtained by controlling the capacitance value between terminals of the capacitive element (varactor).
By the way, the VCXO as described above is affected by variations in electrical characteristics of a crystal resonator, a variable capacitance element, and other amplifier circuits, and the frequency change amount (frequency sensitivity) with respect to the voltage change between terminals between individuals. There are variations. For this reason, in order to reduce the variation between individuals, the voltage between terminals is adjusted according to the variation. In order to adjust such variation, it is conceivable to provide a gain control unit in the VCXO. The gain control unit generates a desired inter-terminal voltage using the voltage gain of the control voltage, and is composed of, for example, an operational amplifier.

FIG. 14 is a diagram showing a circuit configuration of a conventional VCXO disclosed in Patent Document 1. In FIG.
A conventional VCXO 50 shown in FIG. 14 includes a quartz crystal resonator 51 excited at a predetermined frequency, an oscillation amplifier 52 for exciting the quartz crystal resonator 51 by passing a current, a voltage-controlled variable capacitance element D1, D2, a feedback resistor Rf that feeds back a signal by connecting the output terminal and the input terminal of the oscillation amplifier 52, a gain control unit 53 that controls the gain of the external control voltage VC, and a gain control that is output from the gain control unit 53 High resistance elements RA and RB that apply voltage VAFC to variable capacitance elements D1 and D2, capacitors CB1, CB2, and CB3 that function as capacitance elements, resistance elements RC and RD that divide control voltage VAFC, and an oscillation signal externally And an output buffer unit 54 for outputting.
In such a VCXO 50, MOS type variable capacitance elements D1 and D2 are arranged, the gate G1 of the variable capacitance element D1 is connected to the input side of the oscillation amplifier 52 via the capacitor CB1, and the variable capacitance element D2 The gate G2 is connected to the output side of the oscillation amplifier 52 via the capacitor CB2. Further, the back gate B1 of the variable capacitance element D1 and the back gate B2 of the variable capacitance element D2 are connected and grounded via the capacitor CB3. The control voltage VAFC of the gain control unit 53 is applied to the gate side G1 of the variable capacitance element D1 through the high resistance element RA and is applied to the gate G2 of the variable capacitance element D2 through the high resistance element RB. The Furthermore, one terminal of the circuit in which the voltage dividing resistor elements RC and RD are connected in series is grounded, and the control voltage VAFC of the gain control unit 53 is applied to the other terminal. A connection point between the voltage dividing resistor elements RC and RD is connected to a connection point between the back gate B1 of the variable capacitance element D1 and the back gate B2 of the variable capacitance element D2.
JP 2006-33092 A

However, in the conventional VCXO 50 shown in FIG. 14, since an active element such as an operational amplifier constituting the gain control unit 53 that is a voltage generation circuit generates noise, the phase of the VCXO 50 is generated by the voltage generated by the gain control unit 53. There was a problem of deteriorating noise characteristics. Further, since the active element consumes electric power and requires an area for arrangement, the gain control unit 53 has a problem that current consumption is large and miniaturization is difficult.
Therefore, the present applicant has proposed a voltage generation circuit capable of preventing the occurrence of noise caused by active elements as a prior art (Japanese Patent Application No. 2006-275293). FIG. 15 is a diagram showing a configuration of a voltage generation circuit proposed by the present applicant.
The voltage generation circuit GEN illustrated in FIG. 15 includes a resistance switching unit RSW and a current supply unit CSP, and defines a slope in the relationship between the reference voltage Vref, the external control voltage VC, and the external control voltage VC and the control voltage VAFC. Slope signals SL1 to SL3, offset voltage signals OF1 to OF2 for setting an offset current Ioff for defining the offset voltage Voff in the relationship between the external control voltage VC and the control voltage VAFC, and the offset current Ioff and the slope signal. A control voltage VAFC is generated based on SL1 to SL3 and the external control voltage VC. The control voltage VAFC generated by the voltage generation circuit is applied to a varactor of an oscillation circuit (not shown) so as to vary the oscillation frequency.

However, in the voltage generation circuit shown in FIG. 15, since the reference voltage Vref is applied to the reference voltage Vref terminal, the external control voltage VC applied to the external control voltage VC terminal is higher than the reference voltage Vref. When VC> Vref, since the control voltage VAFC is higher than the reference voltage Vref, a negative voltage is applied between the gate and the back gate (GB) of the MOS varactor provided in the oscillation circuit. There is a possibility that the region where the capacitance value of the MOS varactor changes linearly cannot be used effectively.
Also, if the reference voltage Vref is set higher than usual and the voltage levels of the control voltage VAFC and the reference voltage Vref are not equal, the center voltage of the external control voltage VC will also increase. The balance between the external control voltage VC and the center voltage may be deteriorated, and the matching with the specifications (for example, voltage range, center voltage, etc.) of the external control voltage VC on the set side on which the oscillator is mounted may be deteriorated.
The present invention has been made in view of these points, and an object of the present invention is to provide a piezoelectric oscillator that can effectively utilize a region in which the capacitance value of a MOS varactor of an oscillation circuit changes linearly. It is another object of the present invention to provide a piezoelectric oscillator capable of improving the linearity of frequency control characteristics without impairing matching with the specification on the set side.

を満たすことを特徴とする。
本発明によれば、外部制御電圧ＶＣを可変した場合でも第１の可変容量素子のゲート−バックゲート間電圧が負の電圧になることがないので、第１の可変容量素子の容量変化が直線となる領域の中心を基準にして直線的に変化する範囲内に収まるので、第１の可変容量素子の容量値が直線的に変化する領域を有効活用することが可能になる。
また、制御電圧ＶＡＦＣと基準電圧Ｖｒｅｆとが等しくなることがないので、基準電圧Ｖｒｅｆを通常より高めに設定する必要が無い。従って、従来のように、電源電圧と外部制御電圧ＶＣのセンター電圧とのバランスが悪くなり、発振器が搭載されるセット側の外部制御電圧ＶＣの仕様とのマッチングが悪化することもない。 In order to achieve the above object, a piezoelectric oscillator according to the present invention includes a piezoelectric vibrator, an oscillation amplifier for exciting the piezoelectric vibrator, and a gate provided on at least one of an input side and an output side of the oscillation amplifier. A variable capacitance circuit having a first variable capacitance element connected and having a back gate grounded via the first capacitance element; and a first reference voltage that is lower than the reference voltage is input. A first terminal to be applied, a second terminal to which the external control voltage is applied, a plurality of resistors and input resistors connected in series between the first terminal and the second terminal, A switching circuit configured by a plurality of switches for selecting one connection point of a series circuit of a plurality of resistors and outputting a control voltage; and a current for supplying a current to the plurality of resistors And a supply unit A piezoelectric generator configured to apply the reference voltage to a gate of the first variable capacitance element and to apply the control voltage to a back gate of the first variable capacitance element. The first variable capacitance element is configured such that when the gate-back gate voltage is approximately 0 V, the capacitance value of the first variable capacitance element increases from a substantially constant capacitance value with a predetermined slope. The reference voltage is Vref, the first reference voltage is Vref1, the external control voltage is VC, the resistance values of the resistors are R, the resistance values of the input resistors are Rin, and the resistors are The first reference voltage is represented by the following equation: m is the number of resistors selected by the plurality of switches is n, and the set value of the constant current is Ioff.

It is characterized by satisfying.
According to the present invention, even when the external control voltage VC is varied, the voltage between the gate and the back gate of the first variable capacitor does not become a negative voltage, so that the capacitance change of the first variable capacitor is linear. Therefore, it is possible to effectively use the region where the capacitance value of the first variable capacitance element changes linearly.
Further, since the control voltage VAFC and the reference voltage Vref do not become equal, it is not necessary to set the reference voltage Vref higher than usual. Therefore, unlike the conventional case, the balance between the power supply voltage and the center voltage of the external control voltage VC is not deteriorated, and the matching with the specification of the external control voltage VC on the set side on which the oscillator is mounted is not deteriorated.

In the piezoelectric oscillator of the present invention, the variable capacitance circuit includes a second variable capacitance circuit having a gate connected to at least one of an input side and an output side of the oscillation amplifier and a back gate grounded through the first capacitance element. A capacitor element is provided, and a reference voltage is applied to the gate of the second variable capacitor element, and a control voltage is applied to the back gate of the second variable capacitor element.
According to the present invention, even when the external control voltage VC is varied, the voltage between the gate and the back gate of the first and second variable capacitance elements does not become a negative voltage. Since the capacitance change of the element falls within a linearly changing range with reference to the center of the linear region, the region where the capacitance values of the first and second variable capacitance elements change linearly is effectively utilized. Is possible.
Further, since the external control voltage VC and the reference voltage Vref do not become equal, it is not necessary to set the reference voltage Vref higher than usual. Therefore, unlike the conventional case, the balance between the power supply voltage and the center voltage of the external control voltage VC is not deteriorated, and the matching with the specification of the external control voltage VC on the set side on which the oscillator is mounted is not deteriorated.

The piezoelectric oscillator of the present invention includes a voltage dividing resistor circuit that generates a first reference voltage from a reference voltage. According to the present invention, there is an advantage that only one power source for supplying the reference voltage is required.
The piezoelectric oscillator of the present invention is characterized in that the resistance value of the voltage dividing resistor circuit is variable. According to the present invention, it is possible to easily adjust the variation of the variable capacitance element in the manufacturing process.

  The piezoelectric oscillator of the present invention is a voltage-controlled piezoelectric oscillator in which the oscillation circuit is frequency-controlled by voltage control input from the outside of the oscillator circuit, and the control voltage is a voltage based on the external control voltage. . According to the present invention, since no active element is used in the voltage generation circuit as in the prior art, noise caused by the active element can be suppressed, and the phase noise characteristics of the piezoelectric oscillator can be improved. In addition, it is possible to reduce the power consumption and the size of the IC chip.

Hereinafter, embodiments of the piezoelectric oscillator of the present invention will be described.
FIG. 1 is a diagram showing a circuit configuration of a VCXO according to an embodiment of the present invention.
The VCXO 1 shown in FIG. 1 includes an oscillation circuit 2 and a voltage generation circuit 3.
The oscillation circuit 2 includes a crystal resonator X, an oscillation amplifier 4, an output buffer 5, variable capacitance elements (hereinafter simply referred to as “varactors”) D1 and D2, a resistance Rf, a high resistance RA, and RB. , Capacitors CB1, CB2, and CB3, which are capacitive elements, and an input resistor RC.
The oscillation amplifier 4 is an oscillation amplifier for exciting the crystal resonator X, and a resistor Rf that feeds back the output of the oscillation amplifier 4 to the input side is connected between its input terminal and output terminal. An output buffer 5 is connected to the output terminal of the oscillation amplifier 4. The output side of the output buffer 5 is connected to the output terminal t1. Further, one terminal of capacitors CB1 and CB2 is connected to the input terminal and output terminal of the oscillation amplifier 4, respectively, and the crystal resonator X is connected between the other terminals of these capacitors CB1 and CB2. Therefore, the oscillation amplifier 4 is connected in parallel to the crystal resonator X.
Furthermore, high resistances RA and RB for AC blocking connected in series are connected in parallel to the crystal unit X. A reference voltage Vref is applied to the connection point of the high resistances RA and RB via the voltage generation circuit 3. The reference voltage Vref is applied as a gate voltage to the gates G1 and G2 of the varactors D1 and D2 via the high resistances RA and RB. The gate G1 of the varactor D1 is connected to the input side of the oscillation amplifier 4 via the capacitor CB1, and the gate G2 of the varactor D2 is connected to the output side of the oscillation amplifier 4 via the capacitor CB2.
The varactors D1 and D2 are composed of MOS varactors. The back gates B1 and B2 of the varactors D1 and D2 are connected to the ground potential GND through the capacitor CB3. The control voltage VAFC is applied to the back gates B1 and B2 from the voltage generation circuit 3 through the input resistor RC.

The voltage generation circuit 3 includes a current supply circuit 6, a resistance switching unit 7, and a voltage dividing resistor circuit 9.
The voltage generation circuit 3 receives a reference voltage Vref through an input terminal t2 and an external control voltage VC from an external device (not shown) through an input terminal t3. Further, offset signals D0 and D1 are input from an external device (not shown) via input terminals t4 and t5. The offset signals D0 and D1 are signals for controlling an offset current Ioff flowing into the current supply circuit 6 from a resistance switching unit 7 described later.
The first reference voltage Vref1 obtained by dividing the reference voltage Vref by the voltage dividing resistor circuit 9 is input to the input terminal t21 of the resistance switching unit 7, and the external control voltage VC is input to the input terminal t22 via the input terminal t3. Is entered.
The voltage dividing resistor circuit 9 is constituted by a series circuit of a variable resistor VR1 and a resistor VR2, and divides and outputs the reference voltage Vref by the resistors VR1 and VR2.
Further, as will be described later, gradient signals SL1 to SL3 that define the gradient in the relationship between the input external control voltage VC and the output control voltage VAFC are input to the resistance switching unit 7, and these offset signals are input. A control voltage VAFC corresponding to D0, D1, inclination signals SL1 to SL3, and external control voltage VC is generated and output.

  The current supply circuit 6 includes, for example, a current mirror circuit composed of NMOS transistors S3, S4, S5, PMOS transistors S6, S7, switches S3a, S3b, S4a, S4b composed of open / close switches, two inverters IN1, IN2, and a current source. 8. The NMOS transistors S3 and S4 are configured so that, for example, the gate width or gate length of a semiconductor element constituting the transistor is different from that of the NMOS transistor S5, whereby the current i1 flowing through the NMOS transistor S3 and the NMOS transistor S4 The current value of the current i2 flowing through the NMOS transistor S5 is set to a certain ratio with respect to the drain current flowing through the NMOS transistor S5. For example, the current value of the current i2 flowing through the NMOS transistor S4 is twice the drain current of the NMOS transistor S5, and the current value of the current i1 flowing through the NMOS transistor S3 is set to be equal to the drain current of the NMOS transistor S5. ing.

The drain of the NMOS transistor S3 is connected to the resistance switching unit 7, and the source thereof is grounded to GND. Further, one terminals of switches S3a and S3b are connected to the gate of the NMOS transistor S3. The other terminal of the switch S3b is grounded to GND. The gate of the NMOS transistor S5 is connected to the other terminal of the switch S3a.
Further, the drain of the PMOS transistor S7 constituting the current mirror circuit is connected to the drain of the NMOS transistor S5.
Thus, when the switch S3a is turned on and the switch S3b is turned off, the PMOS transistor S6, the PMOS transistor S7 and the current source 8 cause a drain current having a value equal to the drain current of the NMOS transistor S5 to flow through the NMOS transistor S3.
The switch S3a is turned on / off by an inverted signal obtained by inverting the offset signal D0 by the inverter IN1. The switch S3b is controlled to be turned on / off by the offset signal D0. Therefore, for example, when the offset signal D0 is “0”, the switch S3a is turned on, the switch S3b is turned off, the NMOS transistor S3 is turned on, and the current i1 flows. On the other hand, when the offset signal D0 is “1”, the switch S3a is turned off, the switch S3b is turned on, the NMOS transistor S3 is turned off, and the current i1 does not flow.

On the other hand, the NMOS transistor S4 has its drain connected to the resistance switching unit 7 and its source grounded to GND. Further, one terminals of switches S4a and S4b are connected to the gate of the NMOS transistor S4. The other terminal of the switch S4a is connected to the gate of the NMOS transistor S5. The other terminal of the switch S4b is grounded to GND. As a result, when the switch S4a is turned on and the switch S4b is turned off, the PMOS transistor S6, the PMOS transistor S7 and the current source 8 cause the drain current having a value twice the drain current of the NMOS transistor 5 to the NMOS transistor S4. Flowing.
The switch S4a is turned on / off by an inverted signal obtained by inverting the offset signal D1 by the inverter IN2. The switch S4b is controlled to be turned on / off by the offset signal D1. Therefore, for example, when the offset signal D1 is “0”, the switch S4a is turned on, the switch S4b is turned off, the NMOS transistor S4 is turned on, and the current i2 flows. On the other hand, when the offset signal D1 is “1”, the switch S4a is turned off, the switch S4b is turned on, the NMOS transistor S4 is turned off, and the current i2 does not flow.
Therefore, when the current supply circuit 6 is configured in this way, for example, when the offset signal D0 is “0” and the offset signal D1 is “1”, the offset current Ioff is determined by the current i1 flowing through the NMOS transistor S3. . On the other hand, when the offset signals D0 and D1 are both “0”, the offset current Ioff is determined by the current i1 flowing through the NMOS transistor S3 and the current i2 flowing through the NMOS transistor S4.

FIG. 2 is a diagram showing a circuit configuration of the resistance switching unit 7 shown in FIG.
The resistance switching unit 7 is a resistance string type D / A conversion unit, and includes an input resistor RIN, resistors R1 to R7, switches SWA0 to SWA7, switches SWB0 to SWB3, switches SWC0 and SWC1, and inverters INA, INB and INC. .
A first reference voltage Vref1 obtained by dividing the reference voltage Vref by voltage dividing resistors VR1 and VR2 (see FIG. 1) is input to the input terminal t21, and an external control voltage VC is input to the input terminal t22 as 0 to 0, for example. A voltage of 2.5V is input. The second reference voltage Vref2 is output from the output terminal t23, and the control voltage VAFC is output from the output terminal t24.
In addition, 3-bit gradient signals SL1, SL2, and SL3 are input to input terminals t25, t26, and t27 from an external device (not shown).
The resistors R1 to R7 are connected in series between the input terminal t21 and the output terminal t23 (a connection point between the input resistor RIN and the resistor R1). The resistance values of the resistors R1 to R7 are the same.
The input resistance RIN is provided between the input terminal t22 and the output terminal t23, and its resistance value is larger than the resistance values of the resistances R1 to R7.

The switches SWA0 to SWA7 are composed of NMOS transistors. For example, the drain of the switch SWA0 is connected to one terminal of the resistor R1, and the drain of the switch SWA1 is connected to the other terminal of the resistor R1 (connection side to the resistor R2). The source of the switch SWA0 and the source of the switch SWA1 are connected at the connection point CP1.
Similarly, the drain of the switch SWA2 is connected to the other terminal of the resistor R2 (the connection side with the resistor R3), and the drain of the switch SWA3 is connected to the other terminal of the resistor R3 (the connection side with the resistor R4). The sources are connected at the connection point CP2. The drain of the switch SWA4 is connected to the other terminal of the resistor R4 (the connection side with the resistor R5), and the drain of the switch SWA5 is connected to the other terminal of the resistor R5 (the connection side with the resistor R5). The sources of the switches SWA4 and SWA5 They are connected to each other at the connection point CP3. Further, the drain of the switch SWA6 is connected to the other terminal of the resistor R6 (the connection side with the resistor R7), the drain of the switch SWA7 is connected to the other terminal of the resistor R7, and the sources of these switches SWA6 and SWA7 are connected to each other at the connection point CP4. ing.
The slope signal SL1 is applied to the gates of the switches SWA0, SWA2, SWA4, and SWA6 via the input terminal t25, and the gates of the switches SWA1, SWA3, SWA5, and SWA7 are inverted by the inverter INA. The inverted tilt signal SL11 is applied.

The switches SWB0 to SWB3 are also composed of NMOS transistors. For example, the drain of the switch SWB0 is connected to the connection point CP1, the drain of the switch SWB1 is connected to the connection point CP2, and the sources of the switches SWB0 and SWB1 are connected to each other at the connection point CP5. ing. The drain of the switch SWB2 is connected to the connection point CP3, the drain of the switch SWB3 is connected to the connection point CP4, and the sources of the switches SWB2 and SWB3 are connected to each other at the connection point CP6. Further, the slope signal SL2 is applied to the gates of the switches SWB0 and SWB2 via the input terminal t26, and the inverted slope signal SL21 inverted by the inverter INB is applied to the gates of the switches SWB1 and SWB3. .
The switches SWC0 and SWC1 are also NMOS transistors, the drain of the switch SWC0 is connected to the connection point CP5, the drain of the switch SWC1 is connected to the connection point CP6, and the sources of the switches SWC0 and SWC1 are connected to the connection point CP7, that is, the control voltage VAFC. Is connected to an output terminal t24. The slope signal SL3 is applied to the gate of the switch SWC0 via the input terminal t27, and the inverted slope signal SL31 inverted by the inverter INC is applied to the gate of the switch SWC1.

The resistance switching unit 7 configured as described above can select a desired resistance from among the resistances R1 to R7 by the inclination signals SL1, SL2, and SL3. For example, when the inclination signal SL1 = “1”, the inclination signal SL2 = “0”, and the inclination signal SL3 = “1”, the switches SWA0, SWA2, SWA4, and SWA6 are turned on (conductive) by the inclination signal SL1 = “1”. ), When the slope signal SL2 = “0”, the switches SWB1 and SWB3 are turned on (conductive), and when the slope signal SL3 = “1”, the switch SWC0 is turned on (conductive). In this case, the point P2 is selected.
The resistors R1 to R7 of the resistance switching unit 7 equally divide the difference voltage [Vref1-VP0] between the first reference voltage Vref1 and the voltage at the point P0 (hereinafter referred to as “voltage VP0”) into seven equal parts. Here, the first reference voltage Vref1 is a fixed voltage, whereas the voltage VP0 is variable because it is determined by the variable external control voltage VC and the variable offset current Ioff by the superposition theorem. Voltage.
Further, when the resistance value R of the resistors R1 to R7 is R, the combined resistance value of the resistors R1 to R7 is 7R, and the resistance value of the input resistor RIN is Rin, the external control voltage VC is drawn or swept from the first reference voltage Vref1. The current value of the output current is ((Vref1-VC) / (7R + Rin)).
Assuming that n resistors among the resistors R1 to R7 are selected by the inclination signals SL1 to SL3, a voltage (first voltage) at a point P7-n (hereinafter referred to as voltage VP (7n)) is: It is given by the following formula 1.
(Vref1 + n × R × (VC−Vref1) / (6R + Rin)) (Equation 1)
Further, the offset voltage Voff (second voltage) in the voltage VP (7-n) with the first reference voltage Vref1 as a reference is the total resistance value (n × R) of n resistors and the current supply circuit. 6 is multiplied by the current value of the offset current Ioff, which is a constant current from 6.
(−n × R × Ioff) (2)

In Equation 2, since a current is drawn from the first reference voltage Vref1 by the current supply circuit 6, a minus sign is attached.
As a result, the voltage VP (7-n) is a voltage obtained by adding the first voltage and the second voltage.
Further, as described above, it is assumed that the inclination signal SL1 = “1”, the inclination signal SL2 = “0”, the inclination signal SL3 = “1”, and the resistors R3 to R7 are selected from the resistors R1 to R7. The resistance switching unit 7 has a third voltage as
(Vref1 + 5 × R × (VC−Vref1) / (7R + Rin)) + (Vref1 + (− 5 × R × Ioff)) is output from the output terminal t24 as the control voltage VAFC.

As can be seen from the above description, the voltage generation circuit 3 changes the relationship between the input external control voltage VC and the output control voltage VAFC by the slope signals SL1, SL2, and SL3 and the offset signals D0 and D1. Can do. That is, a desired resistor is selected from the resistors R1 to R7 based on the gradient signals SL1, SL2, and SL3, and as a result, the “gradient” in the relationship between the external control voltage VC and the control voltage VAFC is changed as shown in FIG. be able to.
Further, by changing the magnitude of the offset current Ioff by the offset signals D0 and D1, the magnitude of the offset voltage Voff in the relationship between the external control voltage VC and the control voltage VAFC can be changed as shown in FIG. That is, the voltage generation circuit 3 can change the relationship between the external control voltage VC and the control voltage VAFC as shown in FIG. 5 by changing the slope signals SL1, SL2, and SL3 and the offset signals D0 and D1.
With this configuration, the “slope” and “offset voltage” in the relationship between the external control voltage VC and the control voltage VAFC can be changed without using an active element such as an operational amplifier in the voltage generation circuit 3. Such deterioration of the phase noise characteristics of the oscillation circuit 2 can be avoided. In addition, since an operational amplifier with relatively high power consumption is not required, power consumption can be reduced. Further, the transistor elements for operational amplifiers and the capacitors for phase compensation are not necessary, so that the IC chip can be miniaturized.

FIG. 6 is a diagram illustrating the CV characteristics of the MOS varactor when the first reference voltage Vref1 is input to the resistance switching unit 7 of the VCXO1 of the present embodiment. The vertical axis indicates the capacitance value (C), The applied voltage value (V) of the gate-back gate terminal voltage (hereinafter referred to as terminal voltage) VGB is shown on the horizontal axis.
When the inter-terminal voltage VGB is changed linearly, the capacitance value (CM) of the MOS varactor changes as shown in FIG. That is, in the MOS type varactor, when the voltage VGB between the terminals becomes approximately 0 V, the capacitance value (CM) changes from a predetermined potential to a substantially constant capacitance when the voltage VGB is approximately 0 V, and the capacitance change hardly occurs with respect to the voltage change. . On the other hand, when the inter-terminal voltage VGB becomes a predetermined positive potential, the capacitance value (CM) increases as the potential rises. After that, when the inter-terminal voltage VGB reaches the predetermined potential, it becomes a substantially constant capacity again and the voltage changes. Therefore, it has a CV characteristic in which the capacitance change is almost eliminated.
Here, the MOS type varactors D1 and D2 are within the voltage VGB (VGB1-VGB2) region (linear region E) between the terminals of the MOS type varactors D1 and D2 when the capacitance value (CM) linearly changes (increases). When the inter-terminal voltage VGB is controlled, the capacitance value (CM) greatly changes linearly, so that the frequency change can be increased linearly.
Therefore, in the VCXO1 of the present embodiment, the resistance switching unit 7 so that the inter-terminal voltage VGB0 of the MOS varactor at the center voltage Vcen of the external control voltage VC is near the center of the linear region E of the CV characteristics of the varactors D1 and D2. The first reference voltage Vref1 input to the voltage Vx1 is made lower than the reference voltage Vref of the VCXO1 by about 0.6V, for example. The center voltage Vcen of the external control voltage VC is always the control voltage VAFC = the first reference voltage Vref1 (for example, 1.2 V) when the external control voltage VC is changed by changing the slope of the control voltage VAFC. Is an external control voltage. When the offset current Ioff = I0 (0 A), Vcen = Vref1, and when the offset current Ioff = I3, Vcen> Vref1.

FIG. 7 is a diagram illustrating a relationship between the external control voltage VC and the control voltage VAFC when the first reference voltage Vref1 is input to the resistance switching unit 7 of the VCXO1 of the present embodiment.
Here, the power supply voltage VDD = 2.5V of the VCXO1, the reference voltage Vref = 1.8V, the first reference voltage Vref1 = 1.2V, the external control voltage VC = 0 to 2.5V, the offset current Ioff = I0 (0A ), When I3, the resistance switching unit 7 outputs the control voltage VAFC as shown in FIG. 7, and the voltage level of the control voltage VAFC is within the range of the external control voltage VC = 0 to 2.5V. It becomes lower than (1.8V). That is, even when the external control voltage VC is varied within a variable range (for example, 0 V to 2.5 V), the inter-terminal voltage VGB of the varactors D1 and D2 does not become a negative voltage.
Therefore, the capacitance values of the MOS varactors D1 and D2 are within the linear area E of the varactors D1 and D2 with reference to the center (for example, 0.6V) of the linear area E where the capacitance changes of the varactors D1 and D2 are linear. It is possible to effectively use a region that changes linearly.
Further, since the control voltage VAFC is lower than the reference voltage Vref, for example, it is not necessary to set the reference voltage Vref higher than usual. Therefore, unlike the conventional case, the balance between the power supply voltage and the center voltage of the external control voltage VC is not deteriorated, and the matching with the specification of the external control voltage VC on the set side on which the oscillator is mounted is not deteriorated.

On the other hand, as a comparative example with the present invention, FIG. 9 shows the relationship between the external control voltage VC and the control voltage CAFC when the reference voltage Vref is input to the resistance switching unit 7 of the VCXO 1 of the present embodiment. In the case of the offset current Ioff = I0 (0A), the center voltage Vcen of the external control voltage VC and the reference voltage Vref are both equal to 1.8 V, and therefore, as shown in FIG. When the reference voltage Vref is input, the inter-terminal voltage VGB0 of the MOS varactor at the center voltage Vcen of the external control voltage VC is approximately 0V.
Therefore, when the external control voltage VC is varied within the variable range, the voltage VGB between the terminals of the varactors D1 and D2 becomes a negative voltage, and the linear region E in which the capacitance values of the MOS varactors D1 and D2 change linearly is obtained. It turns out that it cannot be used effectively.

Further, in the VCXO1 of this embodiment, in order to be able to adjust the first reference voltage Vref1 input to the resistance switching unit 7, the voltage dividing resistors VR1 and VR2 that can change the voltage dividing resistor circuit 9 are connected in series. I made it up. It should be noted that at least one of the voltage dividing resistors VR1 and VR2 may be a variable that can be varied.
For example, when the main circuit of the VCXO 1 is manufactured by an IC, the thickness of the oxide film of the MOS varactors D1 and D2 varies due to variations in the manufacturing process and the threshold voltage of the MOS varactors D1 and D2 varies. In this case, for example, as shown in FIG. 10, the CV characteristics of the MOS varactors D1 and D2 shift in the voltage axis (horizontal axis) direction, but the voltage dividing resistor circuit 9 can be configured as in this embodiment. For example, since one or both of the resistor VR1 and the resistor VR2 of the voltage dividing resistor circuit 9 can be varied and the first reference voltage Vref1 input to the resistor switching unit 7 can be changed, as shown in FIG. In addition, Vref1 can be adjusted so as to cancel out the voltage shift due to film thickness variation, and the linearity of the frequency control characteristics of the VCXO due to variations in the IC manufacturing process is easy. It can be adjusted. For example, when the oxide film pressure of the IC is finished thicker, the threshold voltage is increased, and the CV characteristic of the MOS varactor is shifted by -0.1 V in the voltage axis direction, Vref1 is erased so that the shift amount is erased. May be set higher by + 0.1V.

一方、制御電圧ＶＡＦＣは、下記の式４により求めることができる。

ここで、ＶＧＢ＝Ｖｒｅｆ−ＶＡＦＣであるから、ＶＡＦＣ＝Ｖｒｅｆ−ＶＧＢを上記式４に代入して変形すると、

と表すことができる。 Hereinafter, the VCXO 1 of this embodiment will be specifically described.
Here, the voltage dividing resistors are VR1, VR2, the reference voltage is Vref, the first reference voltage is Vref1, the external control voltage is VC, the control voltage is VAFC, the resistance values of a plurality of resistors are R, and the resistance values of the input resistors are Rin, m is the number of resistors, n is the number of resistors selected by the switches, Ioff is the constant current setting value, and VGB is the gate-back gate voltage (terminal voltage).
In this case, the first reference voltage Vref1 can be obtained by the following Equation 3.

On the other hand, the control voltage VAFC can be obtained by the following equation 4.

Here, since VGB = Vref−VAFC, when VAFC = Vref−VGB is substituted into Equation 4 and transformed,

It can be expressed as.

となる。
そして、上記式７を変形すると、電圧Ｖｒｅｆ１を下記の式８のよう示すことができる。

Next, in Equation 6 above, the resistance values of Vref1 and R1 to R7 are selected so as to satisfy VGB ≧ 0.
That is,

It becomes.
Then, by transforming Equation 7 above, the voltage Vref1 can be expressed as Equation 8 below.

  Note that when the inter-terminal voltage VGB at the center of the linear region E of the capacitance change of the varactors D1 and D2 is VGB0, it is preferable that Vref1 = Vref−VGB0. That is, Vref−Vref1 in the above expression 6 represents the bias point VGB0 at the center of the linear region E of the capacitance change of the varactors D1 and D2.

As an example, Vdd = 2.5V, Vref = 1.8V, VR1 = 60kΩ, VR2 = 120kΩ, first reference voltage Vref1 = 1.2V, VC = 0-2.5V, and the number of resistance switching bits is 3 bits. Consider a case where the total number of resistors R is m = 6, the resistance values of resistors R1 to R7 are R = 30 kΩ, and Ioff = 0A.
In this case, the characteristic of each part with respect to the external control voltage VC of VCXO1 is as shown in FIG. That is, FIG. 12A shows the external input current I_VC with respect to the external control voltage VC, FIG. 12B shows the control voltage VAFC with respect to the external control voltage VC, and FIG. 12C shows the inter-terminal voltage VGB with respect to the external control voltage VC. It becomes like this.

Also, mR = 180 kΩ, and when the number n of selective resistors is maximized, n = 6 and nR = 180 kΩ.
The terminal voltage VGB of the varactors D1 and D2 when the external input control voltage VC = 0V can be calculated as the following expression 9 using the above expression 6.
Further, the inter-terminal voltage VGB of the varactors D1 and D2 when the external input control voltage VC = 2.5V can be calculated using the above equation 6 as the following equation 10.

As described above, the VCXO 1 according to this embodiment includes the crystal resonator X, the oscillation amplifier 4 for exciting the crystal resonator X, and the gate connected to at least one of the input side and the output side of the oscillation amplifier 4. And an oscillation circuit 2 having a variable capacitance circuit having varactors D1 and D2 whose back gate is grounded via a capacitor CB3. The input terminal t2 to which the reference voltage Vref is input, the input terminal t3 to which the external control voltage VC is applied, a plurality of resistors R1 to R7 and an input resistor connected in series between the input terminal t2 and the input terminal t3. A resistance switching unit 7 having RIN and a switch network composed of a plurality of switches for selecting one connection point of a series circuit of the plurality of resistors R1 to R7 and outputting the control voltage VAFC, and an input terminal a voltage dividing resistor circuit 8 that divides the reference voltage Vref input at t3 and inputs the first reference voltage Vref1 to the resistance switching unit 7, a current supply unit 6 that supplies current to the resistors R1 to R7, The voltage generation circuit 3 having The reference voltage Vref is applied to the gates of the varactors D1 and D2, and the output voltage of the resistance switching unit 7 is applied to the back gates of the varactors D1 and D2.
In addition, the varactors D1 and D2 have a region in which the capacitance value is substantially constant with respect to the change in the inter-terminal voltage VBG and a region in which the capacitance value changes, with the inter-terminal voltage VBG being substantially 0V. In addition to having CV characteristics, the first reference voltage is set such that Vref1 satisfies the above equation (8).

With this configuration, even when the external control voltage VC is varied, the voltage VBG between the terminals of the varactors D1 and D2 does not become a negative voltage. Therefore, the center of the region where the capacitance changes of the varactors D1 and D2 are linear. Therefore, it is possible to effectively utilize the region where the capacitance values of the varactors D1 and D2 change linearly.
Further, since the control voltage VAFC and the reference voltage Vref do not become equal, it is not necessary to set the reference voltage Vref higher than usual. Therefore, unlike the conventional case, the balance between the power supply voltage and the center voltage of the external control voltage VC is not deteriorated, and the matching with the specification of the external control voltage VC on the set side on which the oscillator is mounted is not deteriorated.

  Further, in the VCXO1, since the first reference voltage Vref1 input to the resistance switching unit 7 can be arbitrarily adjusted, the voltage dividing resistor circuit 8 is configured by variable voltage dividing resistors VR1 and VR2. Variations in characteristics in the manufacturing process of D1 and D2 can be easily adjusted. Furthermore, the VCXO1 has the advantage that the voltage dividing resistor circuit 9 that generates the first reference voltage Vref1 from the reference voltage Vref is provided, so that only one power source for supplying the reference voltage is required.

  In the present embodiment, the reference voltage Vref is divided by the voltage dividing resistors VR1 and VR2 to generate the first reference voltage Vref1, but this is only an example, and the first reference voltage Vref1 is You may comprise so that it may input from the outside.

Further, in the present embodiment described so far, the CMOS oscillation circuit has been described as an example of the oscillation circuit 2, but this is only an example, and the oscillation circuit 2 can be configured as follows.
FIG. 13 is a diagram showing another circuit configuration of an oscillation circuit applicable to the piezoelectric oscillator of this embodiment, where (a) is a Colpitts type oscillation circuit and (b) is a circuit configuration of a Pierce type oscillation circuit. FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.
In the Colpitts type oscillation circuit shown in FIG. 13A, one terminal of the crystal unit X is connected to the base of a transistor Q11 that is an oscillation amplifier, and a base bias circuit including resistors R11 and R12 is connected. Furthermore, a series circuit of capacitors C11 and C12 that bear a part of the load capacitance is connected between the base and the ground. The connection midpoint of this series circuit is connected to the connection point between the emitter of the transistor Q11 and the resistor R13. The collector of the transistor Q11 is connected to the power supply Vcc via the collector resistor R14.
A reference voltage Vref is applied to the other terminal of the crystal unit X. The variable capacitance circuit includes a varactor D1, and the gate G1 of the varactor D1 is connected to the input side (base) of the transistor Q11 via the crystal unit X. The back gate B1 of the varactor D1 is connected to the ground potential GND through the capacitor CB3. The first control voltage VAFC is input to the back gate B1 of the varactor D1.

In the Pierce type oscillation circuit shown in FIG. 13B, one terminal of the crystal unit X is connected to the base of the transistor Q11 which is an oscillation amplifier, and a base bias circuit including resistors R11 and R12 is connected. Further, a capacitor C14 that bears a part of the load capacity is connected between the base and the ground. The collector of the transistor Q11 is connected to the power supply Vcc via the collector resistor R14. Further, a capacitor C14 is connected between the other terminal of the crystal unit X and the collector of the transistor Q11. The gate G1 of the varactor D1 is connected to the input side (base) of the transistor Q11 via the crystal resonator X and is connected to the output side (collector) of the transistor Q11 via the capacitor C14. The other configuration on the other terminal side of the crystal unit X is the same as that shown in FIG.
In the embodiment shown in FIG. 13, a configuration in which the second varactor is connected in parallel with the varactor D1 as the variable capacitance circuit may be applied.

The figure which showed the circuit structure of the oscillation circuit of VCXO which concerns on embodiment of this invention. The figure which showed the circuit structure of the voltage generation circuit 3 shown in FIG. The figure which showed the relationship between the external control voltage of a voltage generation circuit, and a control voltage. The figure which showed the relationship between the external control voltage of a voltage generation circuit, and a control voltage. The figure which showed the relationship between the external control voltage of a voltage generation circuit, and a control voltage. The figure which showed the CV characteristic of the MOS type | mold varactor when the 1st reference voltage is input into the resistance switching part of VCXO of this embodiment. The figure which showed the relationship between the external control voltage at the time of inputting a 1st reference voltage into the resistance switching part of VCXO of this embodiment, and a control voltage. The figure which showed the CV characteristic of the MOS type | mold varactor when a reference voltage is input into the resistance switching part of VCXO of this embodiment. The figure which showed the relationship between the external control voltage at the time of inputting a reference voltage into the resistance switching part of VCXO of this embodiment, and a control voltage. The figure which showed the relationship between the film thickness of the oxide film of MOS varactor, and a CV characteristic. The figure which showed the relationship between the external control voltage at the time of changing the film thickness of the oxide film of MOS varactor, and a control voltage. The figure which showed the characteristic of each part with respect to the external input voltage of VCXO of a present Example. The figure which showed the other circuit structure of the oscillation circuit applicable to the piezoelectric oscillator of this embodiment. The figure which showed the circuit structure of the conventional VCXO. The figure which showed the structure of the voltage generation circuit which the present applicant has proposed.

Explanation of symbols

  1 VCXO, 2 oscillation circuit, 3 voltage generation circuit, 4 oscillation amplifier, 5 output buffer, 6 current supply unit, 7 resistance switching unit, 8 current source, 9 voltage dividing resistor circuit, VR1, VR2 voltage dividing resistor, R1 R7 resistance, RIN input resistance, SWA0 to SWA7, SWB0 to SWB3, SWC0, SWC1 switch, IN1, IN2, INA, INB, INC, IND inverter

Claims (5)

An oscillation circuit and a voltage generation circuit;
The oscillation circuit includes a piezoelectric vibrator, an oscillation amplifier for exciting the piezoelectric vibrator, a variable capacitance circuit having a MOS type first variable capacitance element, and one terminal of the variable capacitance element as a reference. A configuration in which a voltage is applied, and a configuration in which a gate of the first variable capacitance element is connected to at least one of an input side or an output side of the oscillation amplifier and a back gate is grounded through the first capacitance element; With
The voltage generation circuit includes: a first terminal to which a first reference voltage that is lower than the reference voltage is input; a second terminal to which the external control voltage is applied; the first terminal; A plurality of resistors and input resistors connected in series with the second terminal, and a switch composed of a plurality of switches for selecting one connection point of the series circuit of the plurality of resistors and outputting a control voltage A resistance switching unit having a network,
The first variable capacitance element includes a region in which a capacitance value is substantially constant with respect to a change in the gate-back gate voltage when the gate-back gate voltage is approximately 0 V, and a capacitance value Having a CV characteristic with a region where
The reference voltage is Vref, the first reference voltage is Vref1, the external control voltage is VC, the resistance value of the plurality of resistors is R, the resistance value of the input resistor is Rin, the number of the plurality of resistors is m, the plurality of the plurality of resistors When the selection number of the plurality of resistors selected by the switch is n and the set value of the constant current is Ioff,
The first reference voltage is

A piezoelectric oscillator characterized by satisfying   The variable capacitance circuit includes a second variable capacitance element having a gate connected to at least one of an input side and an output side of the oscillation amplifier and a back gate grounded via the first capacitance element, 2. The piezoelectric oscillator according to claim 1, wherein the reference voltage is applied to a gate of the second variable capacitance element, and the control voltage is applied to a back gate of the second variable capacitance element.   The piezoelectric oscillator according to claim 1, further comprising a voltage dividing resistor circuit that generates the first reference voltage from the reference voltage.   The piezoelectric oscillator according to claim 3, wherein the voltage dividing resistor circuit is configured to be variable in resistance value.   The oscillation circuit is a voltage-controlled piezoelectric oscillator whose frequency is controlled by voltage control input from the outside of the oscillator circuit, and the control voltage is a voltage based on the external control voltage. The piezoelectric oscillator according to any one of the above.

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