JP2009140963A - Schottky barrier diode and manufacturing method thereof - Google Patents

Abstract

Provided is a Schottky barrier diode that has low reverse leakage current and can be driven at low voltage with low power consumption.
A semiconductor substrate having a first conductivity type semiconductor layer on its surface and a second conductivity type constituting a composite rectification region provided at a predetermined depth from the surface of the first conductivity type semiconductor layer. A Schottky barrier diode comprising a first semiconductor layer 7 and a metal layer 20 disposed in contact with the first conductive type semiconductor layer and the second conductive type semiconductor layer. The surface of the mold semiconductor layer constitutes a {110} plane.
[Selection] Figure 1

Description

  The present invention relates to a Schottky barrier diode and a method for manufacturing the same, and more particularly to reduction of reverse leakage current.

  A Schottky junction formed by contact between a semiconductor (layer) and a metal (layer) having different work functions is widely used as a Schottky barrier diode because it has a rectifying action due to its barrier, and this Schottky barrier diode. Is widely used as a rectifier for switching power supplies because of its low forward voltage drop and excellent high-speed response characteristics. In a switching power supply, the forward voltage drop and leakage current of the Schottky barrier diode that performs rectification are the major factors that determine the power supply efficiency, and the forward voltage drop and leakage current must be minimized. Is desired.

  However, there is a reciprocal relationship between the forward voltage and the reverse leakage current, a material with a small leakage current has a high forward voltage, and a material with a low forward voltage has a large reverse leakage current, Both the leakage current and the forward voltage cannot be lowered.

Therefore, as a structure for reducing the reverse leakage current of a Schottky barrier semiconductor device, a p ⁺ type semiconductor region provided in an island shape or a strip shape on the surface of an n ⁻ type semiconductor layer as an operation layer, A structure has been proposed in which a depletion layer formed on the layer 2 side reduces the leakage current in the reverse direction (Patent Document 1).

However, in order to reduce the leakage current in the reverse direction, when a semiconductor region having a conductivity type different from that of the semiconductor layer (for example, a p ⁺ type semiconductor region with respect to the n-type semiconductor layer) is formed on the surface of the semiconductor layer serving as the operation layer described above Since the p ⁺ type semiconductor region does not become an operation region, the area of the operation region of the semiconductor layer is reduced. When the area is reduced, there is a problem in that the series resistance between the metal layer and the electrode provided on the back surface of the semiconductor substrate increases, and eventually the forward voltage increases.
Under these circumstances, along with the recent trend toward lighter and thinner electronic devices and power-saving and low-voltage driving, both forward voltage drop and reverse leakage current are further increased without increasing the chip area. There is a demand for a Schottky barrier semiconductor device that is reduced and has high performance.

  In such a situation, in order to reduce the reverse leakage current and reduce the forward voltage drop, it is necessary to increase the depth and width of the second conductivity type semiconductor region. .

Japanese Patent Publication No.59-35183

Thus, in order to realize a significant reduction in leakage current, it is necessary to form a P ⁺ type semiconductor region deeply. However, in order to deeply form a P ⁺ type semiconductor region by ion implantation, it is necessary to increase the implantation energy. To increase the implantation energy, an oxide film mask or resist mask used as an implantation mask is made thick. There is a need to. For this reason, it is necessary to form a pattern with a high aspect ratio, and it is difficult to form an implantation mask having a fine opening. Since the P ⁺ type semiconductor region is hardly utilized when energized in the forward direction, it is desirable to narrow the opening width of the implantation mask and to form the narrow P ⁺ type semiconductor region. Thus, when the implantation mask is made thick, there is a problem that a fine opening cannot be formed.
The present invention has been made in view of the above circumstances, and provides a Schottky barrier diode capable of reducing the reverse leakage current without increasing the forward voltage drop and saving power and driving at a low voltage. Objective.

  Therefore, the Schottky barrier diode of the present invention includes a semiconductor substrate having a first conductivity type semiconductor layer on the surface, and a second conductivity type semiconductor provided at a predetermined depth from the surface of the first conductivity type semiconductor layer. A Schottky barrier diode comprising: a layer; and a metal layer disposed in contact with the first conductive type semiconductor layer and the second conductive type semiconductor layer, wherein the Schottky barrier diode includes: The surface is a {110} plane.

Since the projection range in the <110> direction by ion implantation from the {110} plane is larger than the other planes, it is customary for the purpose of forming a shallow impurity diffusion region and controlling the diffusion depth with high accuracy. The {111} plane is used in the manufacture of the semiconductor device. On the other hand, in the Schottky barrier diode of the present invention, it is desired to form a P ⁺ -type region having a deep and small lateral extension, so that the {110} plane is ideal as the element formation surface. Since the projection range of ion implantation in the <110> direction is larger than that of other surfaces, a deep P-type region can be formed even with relatively low implantation energy. If the implantation energy can be lowered, the implantation mask may be thinned, so that a fine opening can be provided in the implantation mask, and therefore, a P ⁺ type region having a narrow width and a deep profile can be formed. Is possible. For the above reason, a Schottky barrier diode having a composite rectifying region including a rectifying unit by a PN junction and a rectifying unit by a Schottky junction with the {110} plane as an element formation surface does not increase the forward voltage drop. This makes it possible to reduce the reverse leakage current.

  In the present invention, the Schottky barrier diode includes a guard ring made of an annular second conductive type semiconductor layer extending from the surface of the semiconductor layer into the layer so as to surround the second conductive type semiconductor layer. Including

In the present invention, the Schottky barrier diode includes a semiconductor layer having an annular insulating film that covers a part of the guard ring on the surface of the semiconductor layer.
Note that when the annular insulating film contains, for example, phosphorus or the like, it is possible to prevent adverse effects of movable ions such as sodium ions and potassium ions on semiconductor characteristics.

  In the present invention, in the Schottky barrier diode, the guard ring is integrated at a predetermined depth from the surface in the vicinity of the outer edge of at least the region where the metal layer is in contact with the first and second conductivity type semiconductor layers. First guard ring region, and a second guard ring having a super junction structure comprising a first conductive ring and a second conductivity type semiconductor layer that is further divided into a plurality of portions and extends to a predetermined depth from the first guard ring region Area.

  According to this configuration, since the guard ring has a super junction structure, the depletion layer easily spreads when a reverse bias is applied, the electric field of the PN junction can be relaxed, and a high breakdown voltage can be achieved. Become. In this configuration, since the first guard ring region is integrally formed at a predetermined depth from the surface, high-precision positioning for obtaining a structure in which the inner end of the insulating film is in contact with the guard ring region Therefore, manufacturing is easy.

  Also, in the present invention, in the Schottky barrier diode, the guard ring is divided into a plurality of portions up to a predetermined depth in the vicinity of an outer edge of a region where the metal layer is in contact with the first and second conductivity type semiconductor layers. This includes a super junction structure composed of a semiconductor layer of the second conductivity type that extends.

  According to this configuration, since the guard ring has a super junction structure, the depletion layer is likely to expand when a reverse bias is applied, the electric field at the PN junction can be relaxed, and a high breakdown voltage can be achieved. Become. In this configuration, since the guard ring is divided into a plurality of parts from the surface, it is necessary to perform highly accurate positioning to obtain a structure in which the inner end of the insulating film is in contact with the guard ring region.

According to the present invention, in the Schottky barrier diode, the guard ring includes a guard layer formed in the same step as a second conductivity type semiconductor layer forming a composite rectification region inside the guard ring.
With this configuration, the second conductivity type semiconductor layer that forms the guard ring and the junction barrier is formed in the same process, so that the manufacturing is easy.

  Further, in the present invention, the depletion layer extending from the second conductive type semiconductor layers adjacent to each other forming the composite rectifying region to the first conductive type semiconductor layer is connected when the reverse voltage is applied. Including the first conductivity type semiconductor layer and the second conductivity type semiconductor layer in which the impurity concentration and width are set.

  According to the present invention, in the Schottky barrier diode, the impurity constituting the second conductivity type semiconductor layer includes boron.

  In the present invention, in the Schottky barrier diode, the metal layer includes a Schottky metal layer including any one of nickel, molybdenum, and titanium and an electrode layer including aluminum.

In the present invention, in the Schottky barrier diode, the second conductivity type semiconductor layer constituting the super junction structure includes a semiconductor layer having a width of 2 μm or less.
According to this configuration, a depletion layer is likely to spread when a reverse bias is applied to the junction between the second conductivity type semiconductor layer forming the guard ring and the first conductivity type semiconductor layer, and the electric field at the junction is reduced. Thus, a high breakdown voltage can be achieved. The width of the second conductive type semiconductor layer forming the guard ring for the highest breakdown voltage depends on the impurity concentration and width of the first conductive type semiconductor layer, but is as narrow as about 1 μm. Is desirable.

  Also, the method for manufacturing a Schottky barrier diode of the present invention provides a semiconductor substrate having a first conductivity type semiconductor layer on a surface, and a main surface of the first conductivity type semiconductor layer constituting a {110} plane. A step of forming a second conductivity type semiconductor layer so as to have a predetermined depth from the surface of the first conductivity type semiconductor layer by introducing a second conductivity type impurity; and Forming a metal layer so as to be in contact with the conductive type semiconductor layer and the second conductive type semiconductor layer.

  According to the present invention, in the method for manufacturing a Schottky barrier diode, the second conductive type is formed so as to surround the second conductive type semiconductor layer formed from the surface of the first conductive type semiconductor layer to a predetermined depth. A step of forming a guard ring made of an annular second conductivity type semiconductor layer extending from the surface of the semiconductor layer into the layer by introducing a type impurity;

  In the present invention, the Schottky barrier diode manufacturing method includes a step of forming an annular insulating film on the surface of the first conductivity type semiconductor layer so as to cover a part of the guard ring.

  According to the present invention, in the method for manufacturing the Schottky barrier diode, the step of forming the guard ring includes forming a ring shape having a first width at least near the outer edge of the region where the metal layer is in contact with the semiconductor layer. As described above, the first ion implantation step for implanting ions of the second conductivity type to the first depth and the peripheral region including at least the region implanted in the first ion implantation step are implanted. A second ion implantation step of ion-implanting a second conductivity type impurity to a second depth with a second width that is half or less of the first width so as to divide the region into a plurality of regions. A first guard ring region integrally formed at a predetermined depth from the surface, and a second conductivity type semiconductor layer further divided into a plurality of portions extending from the first guard ring region and extending to a predetermined depth Na Forming a component guard ring second guard ring region of the super junction structure.

  According to the present invention, in the manufacturing method of the Schottky barrier diode, the step of forming the guard ring ionizes impurities of the second conductivity type at least near the outer edge of the region where the metal layer is in contact with the semiconductor layer. This is a step of forming a guard ring having a super junction structure made of a second conductivity type semiconductor layer that is implanted and divided into a plurality of portions and extends to a predetermined depth.

  According to the present invention, in the method for manufacturing a Schottky barrier diode, the step of forming the guard ring is formed in the same step as the second conductivity type semiconductor layer constituting the composite rectification region inside the guard ring. The

  Further, in the present invention, the depletion layer extending from the second conductive type semiconductor layers adjacent to each other forming the composite rectifying region to the first conductive type semiconductor layer is connected when the reverse voltage is applied. The impurity concentration and width of the first conductive type semiconductor layer and the second conductive type semiconductor layer are set.

  In the present invention, boron is used as an impurity constituting the second conductivity type semiconductor layer in the Schottky barrier diode manufacturing method.

  According to the present invention, in the method for manufacturing a Schottky barrier diode, the step of forming the metal layer includes a step of forming a Schottky metal layer containing any of nickel, molybdenum, and titanium, and an electrode layer containing aluminum. Forming the step.

According to the present invention, in the above-described Schottky barrier diode manufacturing method, the second conductivity type semiconductor layer constituting the super junction structure includes one formed by ion implantation so as to have a width of 2 μm or less.
Although it is difficult to form a semiconductor region of the second conductivity type having a width of 2 μm or less, according to this configuration, by using implantation into the {110} plane, it is possible to easily suppress lateral expansion and easily It becomes possible to form a deep second conductivity type semiconductor region. It is desirable to form with a width of about 1 μm. Alternatively, the second conductivity type semiconductor layer having a desired depth can be formed even with a width of 1 μm or less.

  According to the above configuration, since the {110} plane is used, it is possible to suppress lateral diffusion and realize deep implantation with a very small width, thereby reducing the Schottky junction area and increasing the series resistance. It is possible to provide a Schottky barrier diode that can be suppressed and that can reduce the reverse leakage current without increasing the forward voltage drop.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
1A and 1B are diagrams showing a Schottky barrier diode according to an embodiment of the present invention, where FIG. 1A shows a cross-sectional view, and FIG. 1B shows an AA plane of FIG. It is a top view. Moreover, Fig.1 (a) is BB sectional drawing of FIG.1 (b). In the Schottky barrier diode of this embodiment, a silicon wafer (N ⁺ type silicon substrate) having a {110} plane as a main surface is prepared, and a low-concentration N layer is formed on the surface as a first conductivity type semiconductor layer by epitaxial growth. ^Using the N ⁺ type semiconductor substrate 1 on which the ⁻ type semiconductor layer 2 is formed as a starting material, the P type semiconductor layer 7 constituting the composite rectifying region 20 composed of a Schottky junction and a PN junction is formed in a narrow and deep shape. Therefore, the <110> direction has a large projection range for ion implantation. The Schottky barrier diode is a Schottky barrier diode having a chip size of 2.2 mm ² formed using the N ⁺ type semiconductor substrate 1 as a starting material, and has a first conductivity type by epitaxial growth on the {110} surface. An N ⁺ type semiconductor substrate 1 on which an N ⁻ type semiconductor layer 2 having a low concentration is formed as a semiconductor layer, and a composite rectification region provided at a predetermined depth from the surface of the N ⁻ type semiconductor layer 2 and inside the guard ring And a plurality of P-type semiconductor layers 7 as second conductivity type semiconductor layers constituting the N ^- type semiconductor layer 2 and a plurality of P-type semiconductor layers 7 constituting a composite rectification region on the surface of the N ⁻ type semiconductor layer 2 The guard ring 6 made of the formed P-type semiconductor layer and the plurality of P-type semiconductor layers 7 constituting the composite rectification region inside the N ⁻ -type semiconductor layer 2 and the guard ring are in contact with each other. A Schottky metal 4 provided and a metal layer as an electrode layer 5 formed thereon are provided.

In the present embodiment, the N ⁻ type semiconductor layer 2 formed by epitaxial growth on the silicon wafer surface having the {110} plane as the main surface has a specific resistance of 2.0Ω and a thickness of 9.0 μm. Here, the width of the guard ring is 30 μm, the width of the plurality of P-type semiconductor layers 7 constituting the composite rectification region formed in stripes inside the guard ring is 0.5 μm, and the distance between the P-type semiconductor layers is 2. The thickness was 5 μm. At this time, the depth of the plurality of P-type semiconductor layers 7 constituting the composite rectifying region was 1.1 μm.

Here, an oxide film 3 having an opening is formed on the N ⁻ type semiconductor layer 2 formed on the surface of the N ⁺ type semiconductor substrate 1 so that the surface of the N ⁻ type semiconductor layer 2 is exposed from the opening, A Schottky metal 4 made of molybdenum (Mo) is deposited on the exposed surface of the N ⁻ type semiconductor layer 2 to form a Schottky contact state. A guard ring 6, which is a high-concentration P-type semiconductor layer formed by implanting boron by ion implantation, is formed in a ring shape on the surface of the N ⁻ -type semiconductor layer 2, and an electrode 5 made of aluminum is used as a Schottky metal. 4 is covered. Further, an ohmic-connected electrode 8 made of gold is formed on the side of the N ⁺ type semiconductor substrate 1 facing the N ⁻ type semiconductor layer 2.
The Schottky barrier diode of the present embodiment is formed in the same manner as the conventional example except that the crystal plane of the semiconductor substrate used is different.

Next, a method for manufacturing this Schottky barrier diode will be described.
2 to 4 are diagrams showing the manufacturing process of this Schottky barrier diode. In the present embodiment, the P-type semiconductor layer constituting the guard ring 6 and the plurality of P-type semiconductor layers 7 constituting the composite rectification region are formed in separate ion implantation steps.
First, as shown in FIG. 2A, a silicon wafer (N ⁺ type silicon substrate) having a {110} plane as a main surface is prepared.
Then, as shown in FIG. 2B, an N ⁻ type semiconductor layer 2 having a specific resistance of 2.0Ω and a thickness of 9.0 μm is formed on the surface of the N ⁺ type semiconductor substrate 1 by an epitaxial growth method.
Thereafter, as shown in FIG. 2C, an oxide film (insulating film 3) is formed by thermal oxidation.

  Then, as shown in FIG. 3A, a resist is applied to the upper layer, a resist pattern is formed by photolithography, and the oxide film is patterned so as to form an opening h1 in the guard ring formation region.

Thereafter, as shown in FIG. 3B, ion implantation for forming the guard ring 6 is performed using the oxide film 3 as a mask. At this time, boron was used as the ion species, the implantation energy was 50 keV, and the dose amount was 2e13 cm ⁻² . Then, drive-in diffusion is performed at 1100 ° C. for 30 minutes to obtain a desired diffusion length.

  Then, as shown in FIG. 3C, a resist is applied to the upper layer, a resist pattern R1 is formed by photolithography, and an opening h2 is formed in the P-type semiconductor layer forming region constituting the composite rectifying region. Using this resist pattern as a mask, the oxide film 3 is patterned.

Thereafter, as shown in FIG. 3D, ion implantation for forming a plurality of P-type semiconductor layers 7 constituting the composite rectification region inside the guard ring using the oxide film 3 and the resist pattern R1 as a mask. I do. FIG. 5 shows an enlarged cross-sectional view of the main part of the substrate surface at this time. At this time, boron is used as the ion species, the first ion implantation is performed with an implantation energy of 80 keV and a dose amount of 5e12 cm ⁻² , and then the second ion implantation with an implantation energy of 20 keV and a dose amount of 1e13 cm ⁻² . Do. Here, the second ion implantation is performed in order to enhance the ohmic contact between the P-type semiconductor layer constituting the composite rectification region and the Schottky metal 4 by performing ion implantation at a relatively low energy and high concentration. It is. Then, RTA (high-speed annealing) is performed at 1025 ° C. for 20 seconds to activate boron. In this way, through the annealing process for activation, the guard ring 6 and the plurality of P-type semiconductor layers 7 constituting the composite rectification region inside the guard ring 6 are formed. Here, the plurality of P-type semiconductor layers 7 constituting the composite rectifying region have a width of 0.5 μm, a depth of 1.1 μm, an impurity concentration of 1 × 10 ¹⁶ / cm ^{3 to} 3 × 10 ¹⁷ / cm ³ , and a high concentration of P-type silicon. The guard ring 6 as a layer has a width of 30 μm and a depth of 1.4 μm, and an impurity concentration of 1 × 10 ¹⁶ / cm ³ to 2 × 10 ¹⁷ / cm ³ .

Further, as shown in FIG. 4A, an oxide film 3S is formed on the surface by a CVD method and patterned by photolithography, and an opening is formed as shown in FIG. A Schottky metal 4 and an electrode 5 are formed so as to contact the N ⁻ type semiconductor layer 2 in which a plurality of P type semiconductor layers 7 constituting the region are formed (FIG. 4C) and patterned (FIG. 4 ( d)). Then, a protective film (not shown) was formed as necessary to complete the Schottky barrier diode.

  With respect to the depth direction when the P-type semiconductor layer 7 constituting the composite rectification region is formed on the silicon wafer having the {111} plane as the main surface and the silicon wafer having the {110} plane as the main surface by the above-described process. The impurity profile is shown in FIG. The curve a showing the impurity profile of the P-type semiconductor layer 7 constituting the composite rectification region of the Schottky barrier diode having the {110} plane as the main surface in the present embodiment and the {111} plane as a conventional example as the main surface As is apparent from comparison with the curve b indicating the impurity profile of the Schottky barrier diode, the P type constituting the composite rectification region of the Schottky barrier diode of the present embodiment in which the implantation depth direction is the <110> direction. It can be seen that the semiconductor layer 7 is formed deeper than the P-type semiconductor layer 7 constituting the conventional composite rectification region in which the implantation depth direction is the <111> direction. Thus, according to the present invention, a Schottky barrier diode having a narrow and deep P-type semiconductor layer can be obtained.

FIG. 7 shows the result of measuring the electrical characteristics obtained by the Schottky barrier diode. FIG. 7A is a diagram showing the results of measuring the forward electrical characteristics. The Schottky barrier diode according to the present embodiment in which the injection depth direction is the <110> direction also has the injection depth direction of <111>. As for the conventional Schottky barrier diode in the direction, the voltage drop of the forward voltage at 10 A is 0.92 V and 0.93 V, respectively, and the characteristics of the Schottky barrier diode of this embodiment are slightly degraded. It is almost the same.
On the other hand, FIG. 7B is a diagram showing the results of measuring the reverse electrical characteristics, and the leakage current when 100 V is applied to the Schottky barrier diode of the present embodiment in which the injection depth direction is the <110> direction is , 8.3 μA, and the leakage current when applying 100 V of the conventional Schottky barrier diode with <111> direction as the injection depth direction is 13.6 μA, and the Schottky barrier diode of this embodiment is It can be seen that the reverse direction characteristics are improved.

  In the above embodiment, the P-type semiconductor layer 7 constituting the composite rectifying region is formed in a plurality of stripes, but a plurality of circles having a predetermined width and a predetermined interval, or a predetermined width and You may form so that it may become the spiral shape which makes a predetermined space | interval, or a square-shaped spiral shape.

  In the above-described embodiment, the method of separately forming the P-type semiconductor layer and the guard ring constituting the composite rectifying region has been described. However, the junction barrier and the guard ring may be formed simultaneously. Thereby, the man-hour can be reduced.

Next, as a modification of the first embodiment, a second conductivity type semiconductor layer (P type region) constituting the composite rectification region and a second conductivity type semiconductor layer (P type region) constituting the guard ring are provided. A method for simultaneous formation will be described.
The point of using a silicon wafer having the {110} plane as the main surface is similar to the method of the above embodiment.

A silicon wafer (N ⁺ type silicon substrate) having a {110} plane as a main surface is prepared, and an N ⁻ type semiconductor layer 2 having a specific resistance of 2.0Ω and a thickness of 9.0 μm is formed by an epitaxial growth method. Since the process up to the formation of the oxide film (insulating film 3) by thermal oxidation is the same as that in FIG.
Next, as shown in FIG. 8 (a), a resist is applied to the {110} surface, which is the main surface of the N ⁻ type semiconductor layer 2 on which the oxide film 3 is formed, and a resist pattern R2 is formed by photolithography. The oxide film is patterned so that the opening h is formed in the ring formation region and the P-type semiconductor layer formation region that forms the composite rectification region inside the guard ring formation region.

Thereafter, as shown in FIG. 8B, ion implantation for forming the P-type semiconductor layer 7 and the guard ring 6 constituting the composite rectification region is performed using the oxide film 3 as a mask. Boron is used as the ion species, and the first ion implantation is performed with an implantation energy of 80 keV and a dose amount of 5e12 cm ⁻² , and then a second ion implantation is performed with an implantation energy of 20 keV and a dose amount of 1e13 cm ⁻² . Here again, the second ion implantation is performed in order to increase the ohmic contact between the P-type semiconductor layer and the Schottky metal 4 by relatively high energy ion implantation at a relatively low energy. Then, RTA (high-speed annealing) is performed at 1025 ° C. for 20 seconds to activate boron. In this manner, the guard ring 6 and the P-type semiconductor layer 7 constituting the composite rectification region are formed inside the guard ring 6 through an annealing process for activation. The widths of impurity concentrations of the P-type semiconductor layer 7 and the guard ring constituting the composite rectification region are 0.5 μm and 30 μm, respectively, the depth is 1.1 μm, and the impurity concentration is 1 × 10 ¹⁶ / cm. ^{3 to} 3 × 10 ¹⁷ / cm ³ .

Further, as shown in FIG. 8C, a silicon oxide film 3S is formed on the surface by the CVD method, and this is patterned by photolithography. As shown in FIG. Then, the Schottky metal 4 and the electrode 5 are formed so as to contact the N ⁻ type semiconductor layer 2 in which the P type semiconductor layer 7 constituting the composite rectifying region is formed inside the guard ring (FIG. 9B). ) Patterning is performed (FIG. 9C). Then, a protective film (not shown) was formed as necessary to complete the Schottky barrier diode.

  According to this method, since the guard ring and the p-type silicon layer forming the junction barrier can be formed in the same process, the manufacturing is easy.

  In the above embodiment, molybdenum is used as the Schottky metal layer. In addition, various metals such as titanium, nickel, vanadium, chromium, tungsten, palladium, and platinum can be selected. A method such as vacuum deposition or sputtering is applicable.

  In the above-described embodiment, the two-layer structure of the Schottky metal 4 and the electrode 5 is used. However, if a material having a low resistance and an optimal work function can be selected by selecting a material, a single layer may be used. It is also possible to configure with a structure.

(Embodiment 2)
FIG. 10 is a diagram showing a main part of the Schottky barrier diode according to the second embodiment of the present invention. For the Schottky barrier diode of this embodiment, a silicon wafer (N ⁺ type silicon substrate) having a {110} plane as a main surface is prepared as in the first embodiment, and the first conductivity type is formed on this surface by epitaxial growth. An N ⁺ type semiconductor substrate 1 on which an N ⁻ type semiconductor layer 2 having a low concentration is formed as a semiconductor layer is used as a starting material, and an ion implantation direction is set to a <110> direction having a large projection range. However, the guard ring 6 is formed as a second conductive body integrally formed at a predetermined depth from the surface in the vicinity of the outer edge of the region where the molybdenum (metal layer) 4 is in contact with the N ⁻ type semiconductor layer 2. First guard ring region 6a made of a P-type semiconductor layer as a type semiconductor layer, and a second guard ring that is further divided into a plurality of portions from first guard ring region 6a and extends to a predetermined depth It is characterized in that is constituted by a band 6b. The guard ring 6 is the same as the Schottky barrier diode of the first embodiment except that a super junction structure is used. A floating ring (auxiliary guard ring) 6F made of a p-type silicon layer having a super junction structure is formed on the outer periphery of the guard ring 6.

The Schottky barrier diode of the present embodiment is also a Schottky barrier diode having a chip size of 2.2 mm ² using the N ⁺ type semiconductor substrate 1 as a starting material, as in the first embodiment, and the {110} surface An N ⁺ type semiconductor substrate 1 on which a low concentration N ⁻ type semiconductor layer 2 is formed as a first conductivity type semiconductor layer by epitaxial growth, and a predetermined depth from the surface of the N ⁻ type semiconductor layer 2 is provided. A P-type semiconductor layer 7 constituting a composite rectification region and a P-type semiconductor layer 7 constituting the composite rectification region on the surface of the N ⁻ -type semiconductor layer 2 are formed in an annular shape, and the lower portion has a super junction structure. a guard ring 6 made of P-type semiconductor layer, the N ^- arranged so as to be in contact with the P-type semiconductor layer 7 constituting the type semiconductor layer 2 and the composite rectified areas are Schottky meta 4 and are provided with a metal layer as an electrode layer 5 formed on the upper layer.

Also in the present embodiment, the N ⁻ type semiconductor layer 2 formed by epitaxial growth on the silicon wafer surface having the {110} plane as the main surface has a specific resistance of 2.0Ω and a thickness of 9.0 μm. Here, the width of the entire guard ring region is 30 μm, the depth of the first guard ring region is 0.5 μm, the width of the plurality of second guard ring regions formed in stripes is 0.5 μm, and the depth is 1. The distance between the 1 μm and second guard ring regions was 2.5 μm. At this time, the depth of the P-type semiconductor layer constituting the composite rectifying region was 1.1 μm.

Also here, an oxide film 3 having an opening is formed on the N ⁻ type semiconductor layer 2 formed on the surface of the N ⁺ type semiconductor substrate 1 so that the surface of the N ⁻ type semiconductor layer 2 is exposed from the opening, A Schottky metal 4 made of molybdenum (Mo) is deposited on the exposed n ^- silicon layer 2 surface to form a Schottky contact state. A guard ring 6, which is a high-concentration P-type semiconductor layer formed by implanting boron by ion implantation, is formed in a ring shape on the surface of the N ⁻ -type semiconductor layer 2, and an electrode 5 made of aluminum is used as a Schottky metal. 4 is covered. Further, an ohmic-connected electrode 8 made of gold is formed on the side of the N ⁺ type semiconductor substrate 1 facing the N ⁻ type semiconductor layer 2.

  According to this configuration, since the guard ring has a super junction structure, the depletion layer is likely to expand when a reverse bias is applied, the electric field at the PN junction can be relaxed, and a high breakdown voltage can be achieved. Become. In this configuration, since the first guard ring region is integrally formed at a predetermined depth from the surface, high-precision positioning for obtaining a structure in which the inner end of the oxide film is in contact with the guard ring region Therefore, manufacturing is easy. Further, by forming the auxiliary guard ring 6F in an electrically floating state, when a reverse bias is applied, a depletion layer extends from the auxiliary guard ring 6F, thereby suppressing breakdown and increasing the breakdown voltage. .

Next, a method for manufacturing this Schottky barrier diode will be described.
10 to 11 are diagrams showing the manufacturing process of this Schottky barrier diode. It is to be noted that the method using the silicon wafer having the {110} plane as the main surface is the same as the method of the above embodiment.

That is, a silicon wafer (N ⁺ silicon substrate) having a {110} plane as a main surface is prepared, and an N ⁻ type semiconductor layer 2 having a specific resistance of 2.0Ω and a thickness of 9.0 μm is formed by an epitaxial growth method. The steps up to the step of forming the oxide film (insulating film 3) by thermal oxidation are the same as those in FIG.
Next, as shown in FIG. 11A, a resist is applied to the {110} surface, which is the main surface of the N ⁻ type semiconductor layer 2 on which the oxide film 3 is formed, and a resist pattern is formed by photolithography. The oxide film 3 is patterned so as to form the opening h1 in the formation region.

Thereafter, as shown in FIG. 11B, ion implantation for forming the first guard ring region 6a is performed using the oxide film 3 as a mask. At this time, boron was used as the ion species, the implantation energy was 20 keV, and the dose amount was 5e12 cm ⁻² . Then, RTA (high-speed annealing) is performed at 1025 ° C. for 20 seconds to obtain a desired diffusion length. This heat treatment may be performed simultaneously with the heat treatment for forming the junction barrier.

  Then, as shown in FIG. 11C, a resist is applied to the upper layer, and an opening h2 is formed in the P-type semiconductor layer forming region and the second guard ring forming region constituting the composite rectifying region by photolithography. Next, a resist pattern R3 is formed.

Thereafter, using this resist pattern as a mask, as shown in FIG. 11D, the oxide film 3 is patterned. Using this oxide film 3 and the resist pattern R3 as a mask, the second guard ring formation region 6b, the second Ion implantation is performed to form the P-type semiconductor layer 7 constituting the composite rectification region inside the guard ring formation region 6b. An enlarged cross-sectional view of the main part of the substrate surface at this time is as shown in FIG. At this time, boron is used as the ion species, the first ion implantation is performed with an implantation energy of 80 keV and a dose amount of 5e12 cm ⁻² , and then the second ion implantation with an implantation energy of 20 keV and a dose amount of 1e13 cm ⁻² . Do. Here, the second ion implantation is performed in order to enhance the ohmic contact between the P-type semiconductor layer constituting the composite rectification region and the Schottky metal 4 by performing ion implantation at a relatively low energy and high concentration. It is. Then, RTA (high-speed annealing) is performed at 1025 ° C. for 20 seconds to activate boron. In this way, through the annealing process for activation, the guard ring 6 and the P-type semiconductor layer 7 constituting the composite rectification region are formed inside the guard ring 6. Here, the P-type semiconductor layer 7 constituting the composite rectifying region has a width of 0.5 μm and a depth of 1.1 μm, an impurity concentration of 1 × 10 ¹⁶ / cm ^{3 to} 3 × 10 ¹⁷ / cm ³ , and the first guard ring region 6 a The second guard ring region having a width of 30 μm and a depth of 0.5 μm, and a plurality of stripes formed in a stripe shape has a width of 0.5 μm and a depth of 1.1 μm, and the interval between the second guard ring regions is 2.5 μm.

Further, as shown in FIG. 12A, a silicon oxide film 3S is formed on the surface by the CVD method and patterned by photolithography. As shown in FIG. 12B, an opening is formed and the guard ring 6 and the guard ring 6 are guarded. A Schottky metal 4 and an electrode 5 are formed so as to contact the N ⁻ type semiconductor layer 2 in which the P type semiconductor layer 7 constituting the composite rectifying region is formed inside the ring 6 (FIG. 12C). (FIG. 12D). Then, a protective film (not shown) was formed as necessary to complete the Schottky barrier diode.

(Embodiment 3)
FIG. 13 is a diagram showing a main part of the Schottky barrier diode according to the third embodiment of the present invention. In the Schottky barrier diode of this embodiment, a silicon wafer (N ⁺ silicon substrate) having a {110} plane as a main surface is prepared as in the first and second embodiments, and the first conductive layer is epitaxially grown on this surface. The N ⁺ type semiconductor substrate 1 on which the low concentration N ⁻ type semiconductor layer 2 is formed as the type semiconductor layer is used as a starting material, and the ion implantation direction is set to the <110> direction having a large projection range. As a feature, the guard ring 6 is composed of an aggregate of ultra-fine guard ring regions 6S having a so-called super junction structure that is divided into a plurality of portions and extends to a predetermined depth. The guard ring 6 is the same as the Schottky barrier diode of the first and second embodiments except that a super junction structure is used.

The Schottky barrier diode of this embodiment is also a Schottky barrier diode having a chip size of 2.2 mm ² using the N ⁺ type semiconductor substrate 1 as a starting material, as in the first and second embodiments, and {110 An N ⁺ type semiconductor substrate 1 having a low concentration N ⁻ type semiconductor layer 2 formed as a first conductivity type semiconductor layer by epitaxial growth on the surface, and a predetermined depth from the surface of the N ⁻ type semiconductor layer 2 P of the super junction structure formed in an annular shape so as to surround the P-type semiconductor layer 7 constituting the composite rectification region and the P-type semiconductor layer 7 constituting the composite rectification region on the surface of the N ⁻ type semiconductor layer 2. type guard ring 6 made of a semiconductor layer, wherein the N ^- type arranged in contact with the semiconductor layer 2 and the P-type semiconductor layer 7 of the composite rectified areas are Schottky metal And it is provided with a metal layer as an electrode layer 5 formed on the upper layer.

Also in the present embodiment, the N ⁻ type semiconductor layer 2 formed by epitaxial growth on the silicon wafer surface having the {110} plane as the main surface has a specific resistance of 2.0Ω and a thickness of 9.0 μm. Here, the width of the entire guard ring was 30 μm, the width of the ultra-fine guard ring region formed in a plurality of super junction structure stripes was 0.5 μm, the interval was 2.5 μm, and the depth was 1.1 μm. At this time, the depth of the P-type semiconductor layer constituting the composite rectifying region was 1.1 μm.

Also here, an oxide film 3 having an opening is formed on the N ⁻ type semiconductor layer 2 formed on the surface of the N ⁺ type semiconductor substrate 1 so that the surface of the N ⁻ type semiconductor layer 2 is exposed from the opening, A Schottky metal 4 made of molybdenum (Mo) is deposited on the exposed surface of the N ⁻ type semiconductor layer 2 to form a Schottky contact state. A guard ring 6, which is a high-concentration P-type semiconductor layer formed by implanting boron by ion implantation, is formed in a ring shape on the surface of the N ⁻ -type semiconductor layer 2, and an electrode 5 made of aluminum is used as a Schottky metal. 4 is covered. Further, an ohmic-connected electrode 8 made of gold is formed on the side of the N ⁺ type semiconductor substrate 1 facing the N ⁻ type semiconductor layer 2.

  According to this configuration, since the guard ring has a super junction structure, the depletion layer easily spreads when a reverse bias is applied, the electric field can be relaxed, and a high breakdown voltage can be achieved. In this configuration, since the guard ring is composed of an ultra-fine guard ring, it is necessary to perform highly accurate positioning to obtain a structure in which the inner end of the oxide film is in contact with the guard ring region.

Next, a method for manufacturing this Schottky barrier diode will be described.
14 to 15 are diagrams showing the manufacturing process of this Schottky barrier diode. It is to be noted that the method using the silicon wafer having the {110} plane as the main surface is the same as the method of the above embodiment.

That is, a silicon wafer (N silicon substrate) having a {110} plane as a main surface is prepared, and an N ⁻ type semiconductor layer 2 having a specific resistance of 2.0Ω and a thickness of 9.0 μm is formed by an epitaxial growth method. Since the process up to the formation of the oxide film (insulating film 3) by thermal oxidation is the same as that in FIG.
Next, as shown in FIG. 14 (a), a resist is applied to the {110} plane which is the main surface of the N ⁻ type semiconductor layer 2 on which the oxide film 3 is formed, and a resist pattern R4 is formed by photolithography. The oxide film 3 is patterned so as to form the opening h in the P-type semiconductor layer forming region and the guard ring forming region constituting the rectifying region.

Thereafter, as shown in FIG. 14B, with the oxide film 3 as a mask, the guard ring 6 composed of the ultrafine guard ring 6S and the P-type semiconductor layer 7 constituting the composite rectification region inside the guard ring are formed. Ion implantation for forming is performed. At this time, boron is used as the ion species, the first ion implantation is performed with an implantation energy of 80 keV and a dose amount of 5e12 cm ⁻² , and then the second ion implantation with an implantation energy of 20 keV and a dose amount of 1e13 cm ⁻² . Do. Again, the second ion implantation is performed in order to improve the ohmic contact between the P-type semiconductor layer constituting the composite rectification region and the Schottky metal 4 by performing ion implantation at a relatively low energy and high concentration. It is. Then, RTA (high-speed annealing) is performed at 1025 ° C. for 20 seconds to activate boron. In this manner, the guard ring 6 and the P-type semiconductor layer 7 constituting the composite rectification region are formed through an annealing process for activation. Here, each of the ultrafine guard ring 6S and the P-type semiconductor layer 7 constituting the composite rectifying region has a width of 0.5 μm and a depth of 1.1 μm, and an impurity concentration of 1 × 10 ¹⁶ / cm ^{3 to} 3 × 10 ¹⁷ / cm ^3. It is said.

Further, an oxide film 3S is formed on the surface by the CVD method, and this is patterned by photolithography. As shown in FIG. 15A, an opening is formed and a composite rectification region is formed inside the guard ring 6 and the guard ring 6. A Schottky metal 4 and an electrode 5 are formed so as to contact the N ⁻ type semiconductor layer 2 on which the P type semiconductor layer 7 to be formed is formed (FIG. 15B) and patterned (FIG. 15C). Then, a protective film (not shown) was formed as necessary to complete the Schottky barrier diode.

  According to this method, the P-type semiconductor layer constituting the super junction structure guard ring and the P-type semiconductor layer constituting the composite rectification region can be realized in the same ion implantation step, and therefore can be manufactured very easily. .

  As mentioned above, although the Example of this invention was shown, Embodiment of this invention is not limited to drawing and description which were mentioned above.

  The present invention is useful as a Schottky barrier diode that can reduce reverse leakage current.

The figure which shows the structure of the Schottky barrier diode which concerns on Embodiment 1 of this invention. Sectional drawing which shows the manufacturing process of the Schottky barrier diode which concerns on Embodiment 1 of this invention Sectional drawing which shows the manufacturing process of the Schottky barrier diode which concerns on Embodiment 1 of this invention Sectional drawing which shows the manufacturing process of the Schottky barrier diode which concerns on Embodiment 1 of this invention Explanatory drawing of the principal part of the Schottky barrier diode according to the first embodiment of the present invention Comparison diagram showing impurity profiles of a Schottky barrier diode according to an embodiment of the present invention and a conventional Schottky barrier diode Comparison diagram showing electrical characteristics of a Schottky barrier diode according to an embodiment of the present invention and a conventional Schottky barrier diode Sectional drawing which shows the modification of the manufacturing process of the Schottky barrier diode which concerns on Embodiment 1 of this invention. Sectional drawing which shows the modification of the manufacturing process of the Schottky barrier diode which concerns on Embodiment 1 of this invention. The figure which shows the structure of the Schottky barrier diode which concerns on Embodiment 2 of this invention. Sectional drawing which shows the manufacturing process of the Schottky barrier diode which concerns on Embodiment 2 of this invention. Sectional drawing which shows the manufacturing process of the Schottky barrier diode which concerns on Embodiment 2 of this invention. The figure which shows the structure of the Schottky barrier diode which concerns on Embodiment 3 of this invention. Sectional drawing which shows the manufacturing process of the Schottky barrier diode which concerns on Embodiment 3 of this invention. Sectional drawing which shows the manufacturing process of the Schottky barrier diode which concerns on Embodiment 3 of this invention.

Explanation of symbols

1 N ⁺ type semiconductor substrate 2 N ⁻ type semiconductor layer 3 Oxide film 4 Schottky metal 5 Electrode 6 Guard ring 6 a First guard ring region 6 b Second guard ring region 6 S Ultra fine guard ring region 7 Composite rectification region Constructing P-type semiconductor layer 8 Electrode 20 Composite rectification region

Claims (20)

A semiconductor substrate having a first conductivity type semiconductor layer on a surface;
A second conductivity type semiconductor layer provided at a predetermined depth from the surface of the first conductivity type semiconductor layer;
A Schottky barrier diode comprising a semiconductor layer of the first conductivity type and a metal layer disposed in contact with the semiconductor layer of the second conductivity type,
A Schottky barrier diode in which the surface of the first conductivity type semiconductor layer forms a {110} plane. The Schottky barrier diode according to claim 1,
Surrounding the semiconductor layer of the second conductivity type that forms the composite rectification region,
A Schottky barrier diode comprising a guard ring made of an annular second conductivity type semiconductor layer extending from the surface of the first conductivity type semiconductor layer into the layer. The Schottky barrier diode according to claim 2,
A Schottky barrier diode in which an annular insulating film is formed on a surface of the first conductivity type semiconductor layer so as to cover a part of the guard ring to a periphery of the first conductivity type semiconductor layer. The Schottky barrier diode according to claim 2 or 3,
The guard ring is a first guard integrally formed at a predetermined depth from the surface in the vicinity of an outer edge of a region where at least the metal layer contacts the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. A Schottky barrier diode including a ring region and a second guard ring region having a super junction structure made of a semiconductor layer of a second conductivity type, which is further divided into a plurality of portions from the first guard ring region and extends to a predetermined depth. The Schottky barrier diode according to claim 2 or 3,
The guard ring is a second conductivity type semiconductor that is divided into a plurality of portions and extends to a predetermined depth in the vicinity of an outer edge of a region where at least the metal layer is in contact with the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. A Schottky barrier diode with a super junction structure consisting of layers. A Schottky barrier diode according to any one of claims 2 to 5,
The guard ring is a Schottky barrier diode formed in the same process as a semiconductor layer of a second conductivity type that forms the composite rectification region inside. The Schottky barrier diode according to any one of claims 1 to 6,
The first conductive semiconductor layer and the first conductive semiconductor layer and the depletion layer extending from the second conductive semiconductor layer forming the composite rectifying region adjacent to each other to the first conductive semiconductor layer are connected when a reverse voltage is applied. A Schottky barrier diode in which the impurity concentration and width of the second conductivity type semiconductor layer are set. The Schottky barrier diode according to any one of claims 1 to 7,
The Schottky barrier diode, wherein the impurity constituting the second conductivity type semiconductor layer is boron. A Schottky barrier diode according to any one of claims 1 to 8,
The metal layer is a Schottky barrier diode including a Schottky metal layer containing any of nickel, molybdenum, and titanium and an electrode layer containing aluminum. A Schottky barrier diode according to any one of claims 4 to 9,
The second conductivity type semiconductor layer constituting the super junction structure is a Schottky barrier diode having a width of 2 μm or less. Providing a semiconductor substrate having a semiconductor layer of a first conductivity type on the surface, wherein a main surface of the first conductivity type semiconductor layer forms a {110} plane;
Forming a second conductivity type semiconductor layer so as to have a predetermined depth from the surface of the first conductivity type semiconductor layer by introducing a second conductivity type impurity;
Forming a metal layer so as to be in contact with the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. A method of manufacturing a Schottky barrier diode according to claim 11,
Surrounding the second conductivity type semiconductor layer formed on the surface of the first conductivity type semiconductor layer,
A method for manufacturing a Schottky barrier diode, comprising introducing a second conductivity type impurity to form a guard ring made of an annular second conductivity type semiconductor layer extending from the surface of the semiconductor layer into the layer. A method for manufacturing a Schottky barrier diode according to claim 12,
A method for manufacturing a Schottky barrier diode, comprising a step of forming an annular insulating film on a surface of the semiconductor layer of the first conductivity type so as to cover a part of the guard ring. A method for manufacturing a Schottky barrier diode according to claim 12 or 13,
Forming the guard ring comprises:
The second conductive layer is formed to a first depth so that at least the metal layer forms a ring having a first width in the vicinity of the outer edge of the region in contact with the first conductive type semiconductor layer and the second conductive type semiconductor layer. A first ion implantation step of ion-implanting a type impurity;
At least a peripheral region including a region implanted in the first ion implantation step is divided into a plurality of regions from the implanted region, and the second width is less than or equal to one-half of the first width. A second ion implantation step of ion-implanting a second conductivity type impurity to a depth of 2;
A supermarket comprising a first guard ring region integrally formed at a predetermined depth from the surface, and a second conductive type semiconductor layer further divided into a plurality of portions extending from the first guard ring region and extending to a predetermined depth. A method of manufacturing a Schottky barrier diode that forms a guard ring including a second guard ring region having a junction structure. A method for manufacturing a Schottky barrier diode according to claim 12 or 13,
Forming the guard ring comprises:
At least the metal layer is ion-implanted with a second conductivity type impurity in the vicinity of the outer edge of the region where the metal layer contacts the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and is divided into a plurality of portions and extended to a predetermined depth. A method of manufacturing a Schottky barrier diode, which is a step of forming a guard ring having a super junction structure made of a second conductivity type semiconductor layer. A method for manufacturing a Schottky barrier diode according to any one of claims 12 to 15,
The step of forming the guard ring is a method for manufacturing a Schottky barrier diode formed in the same step as the semiconductor layer of the second conductivity type that forms a composite rectification region inside the guard ring. A method for manufacturing a Schottky barrier diode according to any one of claims 11 to 16,
The first conductivity type semiconductor layer is formed so that a depletion layer extending from adjacent second conductivity type semiconductor layers forming the composite rectification region to the first conductivity type semiconductor layer is connected when a reverse voltage is applied. And a Schottky barrier diode manufacturing method for setting an impurity concentration and a width of the semiconductor layer of the second conductivity type. A method for manufacturing a Schottky barrier diode according to any one of claims 11 to 17,
A method for manufacturing a Schottky barrier diode, wherein boron is used as an impurity constituting the second conductivity type semiconductor layer. A method for manufacturing a Schottky barrier diode according to any one of claims 11 to 18,
The step of forming the metal layer includes a step of forming a Schottky metal layer including any of nickel, molybdenum, and titanium and a step of forming an electrode layer including aluminum. A method for manufacturing a Schottky barrier diode according to any one of claims 14 to 19,
A method of manufacturing a Schottky barrier diode, wherein the second conductivity type semiconductor layer constituting the super junction structure is formed by ion implantation so as to have a width of 2 μm or less.

Images