JP2009135660A - Signal transfer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal transfer circuit capable of accurately outputting an output signal, while driving a transformer at a power saving mode without saturating the transformer. <P>SOLUTION: The signal transfer circuit 1 comprises a transformer 53 having a primary-side coil and a secondary-side coil, a drive portion 56 for causing the primary-side coil to generate a first pulse voltage at a rise timing of an input signal while causing the primary-side coil to generate a second pulse voltage at a fall timing of the input signal, a secondary-side circuit 52 for raising an output signal when a pulse voltage corresponding to the first pulse voltage occurs at the secondary-side coil and falling the output signal when a pulse voltage corresponding to the second pulse voltage occurs at the secondary-side coil, a driving circuit 3 for causing the primary-side coil to generate a third pulse voltage with a fixed period, a resistor 68 for changing current flowing to the secondary-side coil if a fault occurs at an output destination of the secondary-side circuit 52, and a MOSFET 73. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a signal transmission circuit that transmits a signal from an input side to an output side in a state where the input side and the output side are electrically insulated.

Some signal transmission circuits use a photocoupler in a portion where the input side and the output side are electrically insulated.
However, since the photocoupler has a large transmission delay between input and output, the signal transmission circuit described above has a problem that the signal transmission delay becomes large. Further, since the photocoupler cannot be used in an environment of 100 ° C. or higher, there is a problem that the above-described signal transmission circuit cannot be used in an environment of 100 ° C. or higher.

In order to solve these problems, for example, it is conceivable to use a transformer instead of a photocoupler in a portion where the input side and the output side are electrically insulated.
FIG. 5 is a diagram illustrating a signal transmission circuit using a transformer as a portion that electrically isolates the input side and the output side.

  A signal transmission circuit 50 shown in FIG. 5 includes a primary side circuit 51 to which a signal (input signal) is input, a secondary side circuit 52 that outputs a signal (output signal), and a secondary side from the primary side circuit 51. And a transformer 53 that electrically insulates and transmits a signal to the circuit 52.

The transformer 53 includes a primary side coil and a secondary side coil.
The primary side circuit 51 includes power supply units 54 and 55, a drive unit 56, and an abnormal signal output circuit 57.

  Each of the power supply units 54 and 55 includes an npn bipolar transistor 58, N-channel MOSFETs 59 and 60, a diode 61, a constant current source 62, a comparator 63, a resistor 64, and a constant voltage source 65. It is configured.

  That is, the collector terminal of the npn bipolar transistor 58 is connected to the power supply of the voltage VDD and the cathode terminal of the diode 61 and is connected to the drain terminal of the MOSFET 60 and the base terminal of the npn bipolar transistor 58 via the constant current source 62. The emitter terminal of the bipolar transistor 58 is connected to the drain terminal of the MOSFET 59 and the anode terminal of the diode 61. The gate terminals of the MOSFETs 59 and 60 are connected to each other, and the source terminal of the MOSFET 59 is connected to the positive input terminal of the comparator 63 and connected to the ground via the resistor 64. The source terminal of the MOSFET 60 and the negative terminal of the constant voltage source 65 are each connected to the ground. The negative input terminal of the comparator 63 is connected to the positive terminal of the constant voltage source 65. In the power supply unit 54, the connection point between the npn bipolar transistor 58 and the MOSFET 59 is connected to one end of the primary side coil of the transformer 53, and in the power supply unit 55, the connection point between the npn bipolar transistor 58 and the MOSFET 59 is the primary side of the transformer 53. Connected to the other end of the coil.

  Note that one end of the primary coil of the transformer 53 (point connected to the power supply unit 54) is point A, and the other end of the primary coil of the transformer 53 (point connected to the power supply unit 55) is point B. And In the power supply unit 54, a connection point between the source terminal of the MOSFET 59 and the resistor 64 is a C point, and in the power supply unit 55, a connection point between the source terminal of the MOSFET 59 and the resistor 64 is a D point.

  The secondary circuit 52 includes resistors 66 to 68, diodes 69 to 72, an N-channel MOSFET 73, comparators (hysteresis comparators) 74 and 75, and an RS flip-flop circuit 76. Yes.

  That is, the positive input terminal of the comparator 74 is connected to one end of the secondary coil of the transformer 53, one end of the resistor 66, and the negative input terminal of the comparator 75. The output terminal of the comparator 74 is connected to the flip-flop circuit 76. It is connected to the set terminal (S). The positive input terminal of the comparator 75 is connected to the other end of the secondary coil of the transformer 53, the other end of the resistor 66, and the negative input terminal of the comparator 74. The output terminal of the comparator 75 is the reset terminal of the flip-flop circuit 76. Connected to (R). The anode terminal of the diode 69 is connected to the positive input terminal of the comparator 74 and the cathode terminal of the diode 70, the cathode terminal of the diode 69 is connected to the cathode terminal of the diode 71 and one end of the resistor 67, and the anode terminal of the diode 71 is The positive input terminal of the comparator 75 and the cathode terminal of the diode 72 are connected. The anode terminal of the diode 72 is connected to the anode terminal of the diode 70, the other end of the resistor 67, and the ground. One end of the resistor 68 is connected to one end of the resistor 67, and the other end of the resistor 68 is connected to the drain terminal of the MOSFET 73. The source terminal of the MOSFET 73 is connected to the other end of the resistor 67.

  It is assumed that the resistance value of the resistor 67 is larger than the resistance value of the resistor 68. Further, one end of the secondary side coil of the transformer 53 (a point connected to the positive input terminal of the comparator 74) is designated as point E, and the other end of the secondary side coil of the transformer 53 (to the positive input terminal of the comparator 75). The point to be connected) is F point.

The drive unit 56 includes drive circuits 77 and 78 and an inverter 79.
FIG. 6 is a timing chart of signals output from each circuit in the signal transmission circuit 50. In FIG. 6, during the high level period and low level period of the input signal, the drive signal M2 for driving the MOSFETs 59 and 60 of the power supply unit 54 and the drive signal M1 for driving the MOSFETs 59 and 60 of the power supply unit 55 are displayed. It is assumed that it is sufficiently longer than each high level pulse width. Further, the base-emitter voltage of the npn bipolar transistor 58 is Vbe, and the threshold voltage when the diode 61 operates is VF.

At the rising timing of the input signal, the drive signal M1 changes from the low level to the high level. At this time, the drive signal M2 is at a low level.
Then, the npn bipolar transistor 58 of the power supply unit 54 and the MOSFET 59 of the power supply unit 55 are turned on, the MOSFET 59 of the power supply unit 54 and the npn bipolar transistor 58 of the power supply unit 55 are turned off, and the point B of the primary side circuit 51 is set to the ground. The point A of the primary side circuit 51 becomes a voltage (VDD−Vbe) corresponding to the drop of the voltage Vbe from the power supply voltage VDD. Therefore, a positive polarity voltage (VDD−Vbe) is generated between the points A and B of the primary side circuit 51, and the voltage between the points E and F of the secondary side circuit 52 through the transformer 53 is changed to the point A− A positive polarity voltage corresponding to the positive polarity voltage generated between points B is generated. The positive polarity voltage is equal to or higher than a threshold value (first threshold value) set by the comparator 74, and when input to the comparator 74, a high level voltage is output from the comparator 74.

  When a high level voltage is output from the comparator 74 to the set terminal (S) of the flip-flop circuit 76, the voltage (output signal) output from the output terminal (Q) of the flip-flop circuit 76 rises.

  Thereafter, when the drive signal M1 changes from the high level to the low level (at this time, the drive signal M2 is also at the low level), the npn bipolar transistors 58 of the power supply units 54 and 55 are turned on, and the power supply units 54 and 55 are turned on. The MOSFET 59 is turned off, and the positive polarity voltage generated between the points A and B of the primary circuit 51 falls to a negative polarity voltage (− (Vbe + VF)), and the point E of the secondary circuit 52 − The voltage generated between points F also falls. As a result, the first pulse voltage of the drive signal M1 is transmitted from the primary side circuit 51 to the secondary side circuit 52.

  Furthermore, when the drive signal M1 changes from the low level to the high level again (at this time, the drive signal M2 is at the low level), as described above, the npn bipolar transistor 58 of the power supply unit 54 and the MOSFET 59 of the power supply unit 55 are connected. The MOSFET 59 of the power supply unit 54 and the npn bipolar transistor 58 of the power supply unit 55 are turned off, a positive polarity voltage (VDD-Vbe) is generated between the points A and B of the primary side circuit 51, and the transformer 53 is As a result, a positive polarity voltage corresponding to a positive polarity voltage generated between the points A and B is generated in the voltage between the points E and F of the secondary circuit 52.

  Thereafter, when the drive signal M1 changes from the high level to the low level (at this time, the drive signal M2 is also at the low level), as described above, the npn bipolar transistors 58 of the power supply units 54 and 55 are turned on, and the power supply unit 54 55, the MOSFET 59 is turned off, and the positive polarity voltage generated between the points A and B of the primary side circuit 51 falls to a negative polarity voltage (-(Vbe + VF)), and the secondary side circuit The voltage generated between point E and point F of 52 also falls. As a result, the second pulse voltage of the drive signal M1 is transmitted from the primary side circuit 51 to the secondary side circuit 52. On the other hand, the drive signal M2 changes from the low level to the high level at the falling timing of the input signal. At this time, the drive signal M1 is at a low level.

  Then, the MOSFET 59 of the power supply unit 54 and the npn bipolar transistor 58 of the power supply unit 55 are turned on, the npn bipolar transistor 58 of the power supply unit 54 and the MOSFET 59 of the power supply unit 55 are turned off, and the point A of the primary side circuit 51 is grounded. The point B of the primary side circuit 51 becomes a voltage (VDD−Vbe) corresponding to the drop of the voltage Vbe from the power supply voltage VDD. Therefore, a negative polarity voltage (− (VDD−Vbe)) is generated between the points A and B of the primary circuit 51, and a negative polarity voltage is generated between the points E and F via the transformer 53. . The negative polarity voltage is equal to or higher than a threshold value (second threshold value) set by the comparator 75, and when the voltage is input to the comparator 75, a high level voltage is output from the comparator 75.

  When a high level voltage is output from the comparator 75 to the reset terminal (R) of the flip-flop circuit 76, the voltage output from the output terminal (Q) of the flip-flop circuit 76 falls.

  Thereafter, when the drive signal M2 changes from the high level to the low level (at this time, the drive signal M1 is also at the low level), the npn bipolar transistors 58 of the power supply units 54 and 55 are turned on and the power supply units 54 and 55 are turned on. The MOSFET 59 is turned off, and the negative polarity voltage generated between the points A and B of the primary side circuit 51 rises to the positive polarity voltage (Vbe + VF), and between the points E and F of the secondary side circuit 52. The generated voltage also rises. As a result, the first pulse voltage of the drive signal M <b> 2 is transmitted from the primary side circuit 51 to the secondary side circuit 52.

  Furthermore, when the drive signal M2 changes from the low level to the high level again (at this time, the drive signal M2 is at the low level), as described above, the MOSFET 59 of the power supply unit 54 and the npn bipolar transistor 58 of the power supply unit 55 are connected. On, the npn bipolar transistor 58 of the power supply unit 54 and the MOSFET 59 of the power supply unit 55 are turned off, and a negative polarity voltage (− (VDD−Vbe)) is generated between the points A and B of the primary side circuit 51. A negative polarity voltage corresponding to a negative polarity voltage generated between the points A and B is generated in the voltage between the points E and F of the secondary circuit 52 via the transformer 53.

  Thereafter, when the drive signal M2 changes from the high level to the low level (at this time, the drive signal M1 is also at the low level), as described above, the npn bipolar transistors 58 of the power supply units 54 and 55 are turned on, and the power supply unit 54 55, the MOSFET 59 is turned off, and the negative polarity voltage generated between the points A and B of the primary side circuit 51 rises to the positive polarity voltage (Vbe + VF), and the E point of the secondary side circuit 52 The voltage generated between the points -F also rises. As a result, the second pulse voltage of the drive signal M2 is transmitted from the primary side circuit 51 to the secondary side circuit 52. Note that the comparator 74 generates a voltage generated between the point E and the point F when the voltage between the point A and the point B is (VDD−Vbe), and a point E−F when the voltage between the point A and the point B is (Vbe + VF). It is assumed that a threshold is set between the voltage generated between the points. Further, the comparator 75 has a voltage generated between the point E and the point F when the voltage between the point A and the point B is (-(VDD-Vbe)), and a voltage between the point A and the point B (-(Vbe + VF)). It is assumed that a threshold value is set between the voltage generated between point E and point F. However, (VDD−Vbe)> (Vbe + VF).

  Further, in the signal transmission circuit 50 shown in FIG. 5, as shown in FIG. 6, two pulse voltages (drive signals M1 and M2) that are continuous at the rising timing and falling timing of the input signal are input. The second pulse voltage of the two pulse voltages to be used is when the first pulse voltage is not transmitted to the secondary side circuit 52 for some reason and the output signal does not rise or fall However, it is input in order to make the output signal rise or fall reliably with the second pulse voltage.

As described above, the signal transmission circuit 50 illustrated in FIG. 5 outputs the output signal having the same rising timing and falling timing as the input signal via the transformer 53.
The signal transmission circuit 50 shown in FIG. 5 outputs an output signal to the gate terminal of the N-channel MOSFET 80, for example, and the voltage applied to the resistor 81 provided between the source terminal of the MOSFET 80 and the ground is positive. It is assumed that a voltage output from the comparator 82, which is input to the input terminal and is input to the negative input terminal, is input to the gate terminal of the MOSFET 73.

The abnormal signal output circuit 57 includes OR circuits 83 and 84, an inverter 85, AND circuits 86 and 87, and an RS flip-flop circuit 88.
FIG. 7 is a timing chart of signals output from each circuit in the abnormal signal output circuit 57.

  For example, when the MOSFET 80 is destroyed for some reason and a voltage higher than the reference voltage V1 is applied to the resistor 81, and the voltage output from the comparator 82 becomes high level, the MOSFET 73 is turned on. Thereafter, when the input signal falls and a voltage is generated between the point A and the point B and between the point E and the point F, the current flowing in the secondary side circuit 52 increases due to the resistor 68 being effective, so that the transformer 53 The current flowing through the primary side coil also increases, and the voltage at the point C of the primary side circuit 51 becomes larger than when the voltage is normal (when the low level voltage is output from the comparator 82). Therefore, a high-level pulse voltage (output signal S5) is output from the comparator 63 of the power supply unit 54, and a high-level pulse voltage is output from the AND circuit 86. For this reason, the voltage (abnormal signal A1) output from the flip-flop circuit 88 changes from the low level to the high level.

  After that, when the voltage output from the comparator 82 becomes low level, such as when a large voltage is not applied to the resistor 81, the MOSFET 73 is turned off and the resistor 68 is disabled. After that, when the input signal rises once and then falls further, the voltage at the point C of the primary circuit 51 returns to normal, and the voltage (output signal S5) output from the comparator 63 of the power supply unit 54 is low. The level and the voltage output from the inverter 85 become high level, and the AND circuit 87 outputs a high level pulse voltage. Therefore, the voltage (abnormal signal A1) output from the flip-flop circuit 88 changes from the high level to the low level.

  In this way, in the signal transmission circuit 50 shown in FIG. 5, when an abnormality occurs in the output signal output destination circuit and the MOSFET 73 is turned on, the abnormal signal output circuit 57 outputs the high-level abnormality signal A1.

  However, in the signal transmission circuit 50, a pulse voltage is generated in the primary side coil only for a fixed time from the rising edge of the input signal or for a fixed time from the falling edge of the input signal. Therefore, as shown in FIG. If the output of the comparator 82 becomes high level after a certain time has elapsed from the rise of the signal, current does not flow through the primary side coil and the secondary side coil even if the MOSFET 73 of the secondary side circuit 52 is turned on. There is a problem in that it is impossible to transmit from the secondary side circuit 52 to the primary side circuit 51 that an abnormality has occurred in the MOSFET 80 until the input signal falls.

Therefore, as an existing signal transmission circuit, a pulse voltage of a fixed period is applied to the primary coil of the transformer in the primary circuit, and the pulse voltage applied to the primary coil is lowered during the high level period of the input signal. In the secondary side circuit, there is a signal transmission circuit that sets the output signal to a high level during the period in which the pulse voltage applied to the secondary coil of the transformer is reduced (see, for example, Patent Document 1). In this signal transmission circuit, like the signal transmission circuit 50, when the output destination of the secondary side circuit is abnormal, the impedance of the secondary side circuit is lowered and the currents flowing in the primary side circuit and the secondary side circuit are respectively reduced. Increasing. By detecting that the current has increased in the primary side circuit, an abnormality in the output destination of the secondary side circuit is transmitted from the secondary side circuit to the primary side circuit. According to this signal transmission circuit, a pulse voltage having a constant period is always applied to the transformer. Therefore, even if an abnormality occurs in the output destination of the secondary circuit at any timing during the high level period of the input signal, The abnormality can be transmitted from the secondary side circuit to the primary side circuit by the pulse voltage applied to the transformer at a constant period in the high level period.
JP 2006-280100 A

  However, as described above, in a signal transmission circuit that constantly applies a pulse voltage to a transformer at a constant period, if the period of the pulse voltage applied to the transformer is increased in order to save power, the rise / fall of the output signal is changed to the input signal. On the other hand, there is a problem that it is greatly delayed.

  Therefore, in the present invention, when an abnormality in the output destination of the secondary side circuit is transmitted from the secondary side circuit to the primary side circuit via the transformer, the output signal synchronized with the input signal is driven while saving power. It is an object to provide a signal transmission circuit capable of outputting.

In order to solve the above problems, the present invention adopts the following configuration.
That is, the signal transmission circuit of the present invention generates a first pulse voltage in the primary coil at the rising timing of the input signal, and a transformer including a primary coil and a secondary coil. A first drive circuit for generating a second pulse voltage in the primary side coil at a fall timing, and an output signal rising when a pulse voltage corresponding to the first pulse voltage is generated in the secondary side coil And a secondary circuit that causes the output signal to fall when a pulse voltage corresponding to the second pulse voltage is generated in the secondary coil, and a current fluctuation that varies a current flowing through the secondary coil. In order to transmit from the secondary coil to the primary coil that the current flowing through the circuit and the secondary coil has fluctuated, And a second driving circuit for generating a third pulse voltage.

  In the signal transmission circuit of the present invention, the first pulse voltage is generated at the rising timing of the input signal and the second pulse voltage is input even if the period of the third pulse voltage is increased in order to drive with power saving. Since it occurs at the falling timing of the signal, an output signal synchronized with the input signal can be output.

The first driving circuit may be configured to generate two or more of the first pulse voltage or the second pulse voltage.
Thereby, an input signal can be more reliably transmitted from a primary side circuit to a secondary side circuit.

  The second driving circuit generates the first pulse voltage from the first driving circuit, then generates the third pulse voltage, and generates the third pulse voltage from the first driving circuit. After detecting that the pulse voltage has been generated, the third pulse voltage is generated.

The pulse width of the third pulse voltage may be adjusted based on a leakage inductance of the transformer.
As a result, it is possible to suppress the fact that the fluctuation of the current flowing in the secondary coil due to the transmission delay of the third pulse voltage due to the leakage inductance of the transformer makes it difficult to transmit from the secondary coil to the primary coil. it can.

  The signal transmission circuit is configured to include an abnormality determination circuit that determines that an abnormality has occurred in the output destination of the secondary side circuit when detecting that the current flowing through the primary side circuit has changed. Also good.

Accordingly, when an abnormality occurs in the output destination of the secondary circuit, the abnormality determination circuit can be configured to stop the first drive circuit or the second drive circuit.
The secondary side circuit raises the output signal when the pulse voltage corresponding to the first pulse voltage equal to or higher than the first threshold value is generated in the secondary side coil, and causes the secondary side coil to When a pulse voltage corresponding to the second pulse voltage equal to or greater than a threshold value of 2 is generated, the output signal falls, and the first drive circuit generates the first pulse voltage in the primary coil. After that, the pulse voltage generated in the secondary coil in the primary coil is less than the second threshold value, and the second pulse voltage is generated in the primary coil. The pulse voltage generated in the secondary coil may be generated in the primary coil so that the pulse voltage is less than the first threshold value.

  As a result, even if the coupling coefficient of the transformer is poor, LC oscillation due to the leakage inductance of the transformer and the capacitance component of the circuit can be suppressed after the rising or falling timing of the input signal, and malfunction of the circuit can be prevented. In addition, the transformer is automatically reset after inserting a pulse into the transformer, so that saturation of the transformer can be prevented.

  According to the present invention, in a signal transmission circuit that transmits a digital signal from the input side to the output side in a state where the input side and the output side are electrically insulated, the output synchronized with the input signal while being driven with power saving A signal can be output.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating a signal transmission circuit according to an embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure as the structure shown in FIG. 5, and the description is abbreviate | omitted.

A signal transmission circuit 1 shown in FIG. 1 includes a primary circuit 2, a secondary circuit 52, and a transformer 53.
The primary side circuit 2 includes pulse count units 3 and 4, OR circuits 5 to 7, an oscillator 8, a pulse generation circuit 9, AND circuits 10 and 11, power supply units 54 and 55, and a drive unit 56. And an abnormal signal output circuit 57.

  Each of the pulse count units 3 and 4 includes an inverter 12 and T-type flip-flop circuits 13 and 14. In the flip-flop circuits 13 and 14, signals input to the T terminal are processed with positive logic, and signals input to the T_ terminal and R_ terminal are processed with negative logic.

The pulse generation circuit 9 includes a rising delay circuit 15, an inverter 16, a buffer 17, and an AND circuit 18.
In addition, the 1st drive circuit in a claim shall be comprised by the drive part 56 etc. in the primary side circuit 2, etc., for example. Further, the second drive circuit in the scope of claims is constituted by, for example, an oscillator 8 and a pulse generation circuit 9 in the primary side circuit 2. Further, the current fluctuation circuit in the claims is constituted by, for example, the resistor 68 and the MOSFET 73 in the secondary side circuit 52. In addition, the abnormality determination circuit in the claims includes, for example, a comparator 63 in the power supply units 54 and 55, a resistor 64, a constant voltage source 65, an abnormality signal output circuit 57, and the like.

FIG. 2 is a diagram illustrating a timing chart of signals output from each circuit of the signal transmission circuit 1 of the present embodiment.
First, the transmission operation of the input signal from the primary side circuit 2 to the secondary side circuit 52 in the signal transmission circuit 1 of the present embodiment will be described.

  In the signal transmission circuit 1 of the present embodiment, when the input signal rises, two continuous high-level pulse voltages from the drive circuit 78 are output to the power supply unit 55 via the OR circuit 7 as the drive signal M1. At this time, a low-level drive signal M 2 is output from the drive circuit 77 to the power supply unit 54 via the OR circuit 6.

  When two continuous high-level pulse voltages are output to the power supply unit 55 via the OR circuit 7, as described above, the two continuous high-level pulse voltages between the points A and B of the primary circuit 51. Positive-polarity pulse voltages are generated, and positive-polarity pulse voltages corresponding to these pulse voltages are continuously generated between points E and F of the secondary circuit 52.

  When the input signal falls, two continuous high-level pulse voltages are output from the drive circuit 77 to the power supply unit 54 via the OR circuit 6 as the drive signal M2. At this time, a low-level drive signal M 1 is output from the drive circuit 78 to the power supply unit 55 via the OR circuit 7.

  Then, when two continuous high-level pulse voltages are output to the power supply unit 54 via the OR circuit 6, as described above, the two continuous high-level pulse voltages between the points A and B of the primary side circuit 51. Negative polarity pulse voltages are generated, and negative polarity pulse voltages respectively corresponding to these pulse voltages are continuously generated between points E and F of the secondary circuit 52.

  Therefore, similarly to the signal transmission circuit 50 shown in FIG. 5, the signal transmission circuit 1 of the present embodiment can output output signals having the same rising timing and falling timing as the input signal. The operations of the power supply units 54 and 55 and the secondary circuit 52 in the signal transmission circuit 1 of the present embodiment are the same as the operations of the power supply units 54 and 55 and the secondary circuit 52 in the signal transmission circuit 50 shown in FIG. Therefore, the description is omitted.

Next, the operation of the signal transmission circuit 1 of the present embodiment other than the rising timing and falling timing of the input signal will be described.
During the period when the input signal is high level, a low level signal obtained by inverting the input signal (high level) by the inverter 79 is input to each reset release terminal R_ of the flip-flop circuits 13 and 14 in the pulse count unit 3. Therefore, the signals output from the respective output terminals Q of the flip-flop circuits 13 and 14 in the pulse count unit 3 are at low level, and the flip-flop circuits 13 and 14 in the pulse count unit 4 are in a period during which the input signal is at low level. Since a low level signal is input to each reset release terminal R_, a signal output from each output terminal Q of the flip-flop circuits 13 and 14 in the pulse count unit 4 is at a low level. .

  The period of the pulse signal output from the oscillator 8 can be adjusted. When setting longer than the interval between two continuous pulse voltages of the drive signal M1 and the drive signal M2, power saving can be achieved as compared with a case where a pulse voltage with a constant period is applied to the transformer.

  Further, each pulse width of the pulse voltage having a constant period output from the pulse generation circuit 9 may be adjusted based on the leakage inductance of the transformer 53. In the example shown in FIG. 2, it is set to be the same as the high level period of each pulse voltage of the drive signal M1 and the drive signal M2.

  First, when the input signal rises, at the timing, the first pulse voltage is output from the drive circuit 78 and input to the input terminal T of the flip-flop circuit 13 in the pulse count unit 4. Then, the signal output from the output terminal Q_ of the flip-flop circuit 13 to the input terminal T of the flip-flop circuit 14 changes from high level to low level, and the signal output from the output terminal Q of the flip-flop circuit 14 is low level. It remains.

  Next, the second pulse voltage is output from the drive circuit 78 and input to the input terminal T of the flip-flop circuit 13 in the pulse count unit 4. Then, the signal input from the output terminal Q_ of the flip-flop circuit 13 to the input terminal T of the flip-flop circuit 14 changes from low level to high level, and the signal output from the output terminal Q of the flip-flop circuit 14 changes from low level. Change to high level.

  In the pulse count unit 4, when a high level signal is output from the flip-flop circuit 14 to the oscillator 8 via the OR circuit 5, a pulse signal having a fixed period is output from the oscillator 8 to the pulse generation circuit 9.

  The pulse signal input to the pulse generation circuit 9 is delayed by the rising delay circuit 15 and then inverted by the inverter 16 and input to one input terminal of the AND circuit 18 and through the buffer 17. To the other input terminal of the AND circuit 18. The AND circuit 18 inputs a pulse signal having the same cycle as the pulse signal output from the oscillator 8 and having the same high level period as the delay time of the rising delay circuit 15 to one input terminal of the AND circuit 11. At this time, a high-level input signal is input to the other input terminal of the AND circuit 11. Therefore, the signal output from the AND circuit 11 is the same as the pulse signal output from the pulse generation circuit 9, and the pulse signal is output to the power supply unit 55 via the OR circuit 7.

At this time, since the signal output from the AND circuit 10 is at a low level, the signal input from the OR circuit 6 to the power supply unit 54 is at a low level.
Thereby, in the high level period of the input signal, after two positive pulse voltages (first pulse voltage) generated between the points A and B of the primary side circuit 2, that is, the transformer 53 are generated, A positive-polarity pulse voltage (third pulse voltage) having a certain period is generated.

  On the other hand, when the input signal falls, at the timing, the first pulse voltage is output from the drive circuit 77 and input to the input terminal T of the flip-flop circuit 13 in the pulse count unit 3. Then, the signal output from the output terminal Q_ of the flip-flop circuit 13 to the input terminal T of the flip-flop circuit 14 changes from high level to low level, and the signal output from the output terminal Q of the flip-flop circuit 14 is low level. It remains.

  Next, a second pulse voltage is output from the drive circuit 78 and input to the input terminal T of the flip-flop circuit 13 in the pulse count unit 3. Then, the signal input from the output terminal Q_ of the flip-flop circuit 13 to the input terminal T of the flip-flop circuit 14 changes from low level to high level, and the signal output from the output terminal Q of the flip-flop circuit 14 changes from low level. Change to high level.

  In the pulse count unit 3, when a high level signal is output from the flip-flop circuit 14 to the oscillator 8 via the OR circuit 5, a pulse signal having a fixed period is output from the oscillator 8 to the pulse generation circuit 9.

  The pulse signal input to the pulse generation circuit 9 is delayed by the rising delay circuit 15 and then inverted by the inverter 16 and input to one input terminal of the AND circuit 18 and through the buffer 17. To the other input terminal of the AND circuit 18. The AND circuit 18 inputs a pulse signal having the same cycle as the pulse signal output from the oscillator 8 and having the same high level period as the delay time of the rising delay circuit 15 to one input terminal of the AND circuit 10. At this time, a high-level input signal is input to the other input terminal of the AND circuit 10. Therefore, the signal output from the AND circuit 10 is the same as the pulse signal output from the pulse generation circuit 9, and the pulse signal is output to the power supply unit 54 via the OR circuit 6.

At this time, since the signal output from the AND circuit 11 is at a low level, the signal input from the OR circuit 7 to the power supply unit 55 is at a low level.
Thereby, in the low level period of the input signal, after two negative pulse voltages (second pulse voltages) generated between the points A and B of the primary circuit 2, that is, the transformer 53 are generated, A negative polarity pulse voltage (third pulse voltage) is generated in a certain cycle.

  As described above, in the signal transmission circuit 1 of the present embodiment, in the high level period of the input signal, after two positive-polarity pulse voltages continuous to the transformer 53 are generated, a positive-polarity pulse voltage having a constant cycle is generated. At the same time, in the low level period of the input signal, after two negative polarity pulse voltages continuous to the transformer 53 are generated, a negative polarity pulse voltage having a constant cycle is generated. Is generated, the impedance of the secondary circuit 52 is lowered and the secondary circuit 52 (secondary coil of the transformer 53) or the primary circuit 2 (primary coil of the transformer 53) is turned on. An increase in the flowing current can be detected by the comparator 63 and the resistor 64 of the primary side circuit 2.

  For example, when the MOSFET 80 is destroyed for some reason and a voltage higher than the reference voltage V1 is applied to the resistor 81, and the voltage output from the comparator 82 becomes high level, the MOSFET 73 is turned on. Thereafter, when the input signal rises (or falls) and a voltage is generated between point A and point B and between point E and point F, it flows to the secondary side circuit 52 because the resistor 68 becomes effective. Since the current increases, the current flowing through the primary side coil of the transformer 53 also increases, and the voltage at the point D (or the voltage at the point C) of the primary side circuit 51 is normal (a low level voltage is output from the comparator 82). Is larger than when) Therefore, a high-level pulse voltage (output signal S6 (or output signal S5)) is output from the comparator 63 of the power supply unit 55 (or the comparator 63 of the power supply unit 54), and a high-level pulse voltage is output from the AND circuit 86. The For this reason, the voltage (abnormal signal A1) output from the flip-flop circuit 88 changes from the low level to the high level.

  After that, when the voltage output from the comparator 82 becomes low level, such as when a large voltage is not applied to the resistor 81, the MOSFET 73 is turned off and the resistor 68 is disabled. Thereafter, when the input signal falls (or rises), the voltage at the point D (or the voltage at the point C) of the primary side circuit 51 returns to normal, and the comparator 63 of the power supply unit 55 (or the comparator 63 of the power supply unit 54). ) (The output signal S6 (or output signal S5)) is at a low level, the voltage output from the inverter 85 is at a high level, and a high level pulse voltage is output from the AND circuit 87. Therefore, the voltage (abnormal signal A1) output from the flip-flop circuit 88 changes from the high level to the low level.

  As described above, in the signal transmission circuit 1 of the present embodiment, when an abnormality occurs in the output signal output destination circuit and the MOSFET 73 is turned on, the abnormal signal output circuit 57 outputs the high-level abnormality signal A1.

  For example, the driving unit 56 may be configured to stop the MOSFETs 59 and 60 of the power supply units 54 and 55 when the abnormal signal output circuit 57 outputs a high level abnormal signal A1 to the driving unit 56. Good.

  Further, in the signal transmission circuit 1 of the present embodiment, even if the period of the pal signal output from the oscillator 8 is increased in order to drive with power saving, a double pulse is generated from the drive circuit 78 at the rising timing of the input signal. Since the drive circuit 77 generates a double pulse at the falling timing of the input signal, the rising timing and falling timing of the output signal can be prevented from being delayed with respect to the rising timing and falling timing of the input signal. An output signal synchronized with the input signal can be output.

  Further, in the signal transmission circuit 1 of the present embodiment, by adjusting the delay time of the rise delay circuit 15 of the pulse generation circuit 9, a pulse having a constant cycle generated in the transformer 53 during the high level period or low level period of the input signal. Each pulse width of the voltage can be varied. For example, when the leakage inductance of the transformer 53 is large and the current rise is slow, the currents of the primary side coil and the secondary side coil of the transformer 53 are increased by increasing the pulse width of the pulse voltage of the constant period accordingly. It can be increased sufficiently, and an abnormal signal can be easily transmitted from the secondary side coil of the transformer 53 to the primary side coil.

  Next, a positive polarity pulse voltage generated between the points A and B (one of the two consecutive positive polarity pulse voltages generated after the rising timing of the input signal, or the two consecutive The operation of the signal transmission circuit 1 after the fall of one pulse voltage of a positive polarity pulse voltage having a certain period after the generation of the positive polarity pulse voltage will be described.

  In the signal transmission circuit 1 of the present embodiment, when a positive polarity pulse voltage generated between point A and point B falls, one end (point A) of the primary side coil of the transformer 53 is connected to the npn bipolar transistor of the power supply unit 54. 58, and the other end (point B) of the primary coil is connected to the power supply (VDD) of the power supply section 55 via the diode 61 of the power supply section 55. , A negative polarity voltage (− (VF + Vbe)) is generated between the points A and B, the power supply (VDD) of the power supply unit 54, the npn bipolar transistor 58 of the power supply unit 54, the primary coil of the transformer 53, the power supply The current flowing in the order of the MOSFET 59 of the unit 55 and the ground of the power unit 55 is the power source (VDD) of the power unit 54, the npn bipolar transistor 58 of the power unit 54, the transformer 5 Of the primary coil, the diode 61 of the power supply unit 55, in this order of the power supply unit 55 (VDD), the energy accumulated in the primary side coil is reset. When the energy stored in the transformer 53 is reset, the current flowing through the transformer 53 becomes zero, and the voltages at the points A and B become the power supply voltage VDD.

  At this time, the pulse voltage generated in the secondary coil corresponding to the negative polarity voltage (− (VF + Vbe)) generated between the points A and B has such a magnitude that a high level voltage is not output from the comparator 75. Voltage. That is, the absolute value of the pulse voltage generated in the secondary coil is set to a voltage less than the second threshold value.

  Next, a negative polarity pulse voltage generated between the points A and B (one of the two consecutive negative polarity pulse voltages generated after the falling timing of the input signal, or the continuous 2 The operation of the signal transmission circuit 1 after the rise of one pulse voltage of a negative polarity pulse voltage having a fixed period after the generation of two negative polarity pulse voltages will be described.

  In the signal transmission circuit 1 of the present embodiment, when a negative polarity pulse voltage generated between the points A and B rises, one end (point A) of the primary side coil of the transformer 53 causes the diode 61 of the power supply unit 54 to be connected. The other end (point B) of the primary coil is connected to the power supply (VDD) of the power supply section 55 via the npn bipolar transistor 58 of the power supply section 55. , A positive polarity voltage (VF + Vbe) is generated between the points A and B, the power supply (VDD) of the power supply unit 55, the npn bipolar transistor 58 of the power supply unit 55, the primary coil of the transformer 53, and the power supply unit 54 The current that flows in the order of the MOSFET 59 and the ground of the power supply unit 54 is the power supply (VDD) of the power supply unit 55, the npn bipolar transistor 58 of the power supply unit 55, and the primary side of the transformer 53. Yl, diode 61 of the power supply unit 54, in this order of the power supply unit 54 (VDD), the energy accumulated in the primary side coil of the transformer 53 is reset. When the energy stored in the transformer 53 is reset, the current flowing through the transformer 53 becomes zero, and the voltages at the points A and B become the power supply voltage VDD.

  At this time, the pulse voltage generated in the secondary coil corresponding to the positive polarity voltage (VF + Vbe) generated between the point A and the point B is a voltage with which the high level voltage is not output from the comparator 74. . That is, the pulse voltage generated in the secondary coil is set to a voltage lower than the first threshold value.

  Therefore, the signal transmission circuit 1 of the present embodiment has the leakage inductance of the transformer 53 and the capacitances at points E and F after generating a pulse in the primary side coil of the transformer 53 even if the coupling coefficient of the transformer 53 is poor. LC oscillation due to the components can be suppressed, and the flip-flop circuit 76 can be prevented from malfunctioning. Further, since the transformer is automatically reset when a pulse is inserted into the transformer 53, saturation of the transformer can be prevented.

Next, the configuration of the drive circuits 77 and 78 will be described.
FIG. 3A is a diagram illustrating the drive circuit 78, and FIG. 3B is a diagram illustrating the drive circuit 77.

  The drive circuits 77 and 78 include inverters 89 and 90, rising delay circuits 91 to 93, buffers 94 and 95, AND circuits 96 and 97, and an OR circuit 98, respectively.

  4A is a timing chart of signals output from each circuit in the drive circuit 78, and FIG. 4B is a timing chart of signals output from each circuit in the drive circuit 77. FIG. Note that the delay times of the rise delay circuits 91 and 93 of the drive circuits 77 and 78 and the rise delay circuits 91 and 93 of the drive circuit 78 are the same, and the rise delay circuit 92 of the drive circuit 77 and the rise delay of the drive circuit 78 are the same. The delay times of the circuits 92 are the same. In the drive circuits 77 and 78, the delay time of the rising delay circuit 91: the delay time of the rising delay circuit 92 = (VF + Vbe) :( VDD−Vbe) is used as a guide.

  As shown in FIG. 4A, when the input signal rises, a high level signal is inputted to the drive circuit 78 via the buffer 94 to one input terminal of the AND circuit 96 and the rise delay circuit 91. . The high level signal input to the rising delay circuit 91 is delayed for a predetermined time, and then inverted by the inverter 89 to become a low level signal, which is input to the other input terminal of the AND circuit 96. Therefore, a high level signal is input to the other input terminal of the AND circuit 96 until a high level signal is output from the rising delay circuit 91.

  Therefore, during a period when high level signals are input to both input terminals of the AND circuit 96, a high level pulse voltage is input from the AND circuit 96 to the OR circuit 98, and a high level signal (driving) is output from the OR circuit 98. Signal M1) is output.

  Thereafter, when a high level signal is output from the rising delay circuit 91, a low level signal is input to the other input terminal of the AND circuit 96, and thus a low level signal is output from the AND circuit 96. The

  When the input signal rises, a high level signal is delayed in the drive circuit 78 by the rise delay circuits 91 and 92 for a predetermined time, and one input terminal of the AND circuit 97 and the rise delay circuit 93 are passed through the buffer 95. Is input. The high level signal input to the rising delay circuit 93 is delayed for a predetermined time, and then inverted by the inverter 90 to become a low level signal, which is input to the other input terminal of the AND circuit 97. Therefore, a high level signal is input to the other input terminal of the AND circuit 97 until a high level signal is output from the rising delay circuit 93.

  Therefore, during a period when a high level signal is input to both input terminals of the AND circuit 97, a high level pulse voltage is input from the AND circuit 97 to the OR circuit 98, and a high level signal (driving) is output from the OR circuit 98. Signal M1) is output.

Therefore, when the input signal rises, the drive circuit 78 outputs two continuous pulse voltages.
As shown in FIG. 4B, when the input signal falls, the drive circuit 77 causes the high-level signal inverted by the inverter 79 to rise through the buffer 94 to one input terminal of the AND circuit 96. Input to the delay circuit 91. The high level signal input to the rising delay circuit 91 is delayed for a predetermined time, and then inverted by the inverter 89 to become a low level, and input to the other input terminal of the AND circuit 96. Therefore, a high level signal is input to the other input terminal of the AND circuit 96 until a high level signal is output from the rising delay circuit 91.

  Therefore, during a period when high level signals are input to both input terminals of the AND circuit 96, a high level pulse voltage is input from the AND circuit 96 to the OR circuit 98, and a high level signal (driving) is output from the OR circuit 98. Signal M2) is output.

  Thereafter, when a high level signal is output from the rising delay circuit 91, a low level signal is input to the other input terminal of the AND circuit 96, and thus a low level signal is output from the AND circuit 96. The

  When the input signal falls, the drive circuit 77 causes the high-level signal inverted by the inverter 79 to be delayed for a predetermined time by the rise delay circuits 91 and 92, and one input terminal of the AND circuit 97 through the buffer 95. And is input to the rising delay circuit 93. The high level signal input to the rising delay circuit 93 is delayed for a predetermined time, and then inverted by the inverter 90 to become a low level signal, which is input to the other input terminal of the AND circuit 97. Therefore, a high level signal is input to the other input terminal of the AND circuit 97 until a high level signal is output from the rising delay circuit 93.

  Therefore, during a period when a high level signal is input to both input terminals of the AND circuit 97, a high level pulse voltage is input from the AND circuit 97 to the OR circuit 98, and a high level signal (driving) is output from the OR circuit 98. Signal M2) is output.

  Therefore, when the input signal falls, the drive circuit 77 outputs two continuous pulse voltages.

It is a figure which shows the signal transmission circuit of embodiment of this invention. It is a figure which shows the timing chart of the signal output from each circuit in the signal transmission circuit of this embodiment. It is a figure which shows a drive circuit. It is a figure which shows the timing chart of the signal output from each circuit in a drive part. It is a figure which shows the conventional signal transmission circuit. It is a figure which shows the timing chart of the signal output from each circuit in the conventional signal transmission circuit. It is a figure which shows the timing chart of the signal output from each circuit in an abnormal signal output circuit. It is a figure which shows the timing chart of the signal output from each circuit in a signal transmission circuit in case an abnormal signal is not transmitted from a secondary side circuit to a primary side circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Signal transmission circuit 2 Primary side circuit 3, 4 Pulse count part 5-7 OR circuit 8 Oscillator 9 Pulse generation circuit 10, 11 AND circuit 12 Inverter 13, 14 Flip-flop circuit 15 Rise delay circuit 16 Inverter 17 Buffer 18 AND circuit DESCRIPTION OF SYMBOLS 50 Signal transmission circuit 51 Primary side circuit 52 Secondary side circuit 53 Transformer 54, 55 Power supply part 56 Drive part 57 Abnormal signal output circuit 58 npn bipolar transistor 59, 60 MOSFET
61 Diode 62 Constant current source 63 Comparator 64 Resistor 65 Constant voltage source 66-68 Resistor 69-72 Diode 73 MOSFET
74, 75 Comparator 76 Flip-flop circuit 77, 78 Drive circuit 79 Inverter 80 MOSFET
81 resistor 82 comparator 83, 84 OR circuit 85 inverter 86, 87 AND circuit 88 flip-flop circuit 89, 90 inverter 91-93 rising delay circuit 94, 95 buffer 96, 97 AND circuit 98 OR circuit

Claims (6)

A transformer comprising a primary coil and a secondary coil;
A first drive circuit for generating a first pulse voltage in the primary coil at the rising timing of the input signal and generating a second pulse voltage in the primary coil at the falling timing of the input signal; ,
When a pulse voltage corresponding to the first pulse voltage is generated in the secondary side coil, an output signal is raised, and when a pulse voltage corresponding to the second pulse voltage is generated in the secondary side coil, the output signal is raised. A secondary circuit that causes the output signal to fall;
A current fluctuation circuit that fluctuates the current flowing through the secondary coil;
A second pulse voltage is generated in the primary coil at a constant period in order to transmit from the secondary coil to the primary coil that the current flowing in the secondary coil has fluctuated. A drive circuit;
A signal transmission circuit comprising: The signal transmission circuit according to claim 1,
The signal transmission circuit, wherein the first driving circuit generates two or more of the first pulse voltage or the second pulse voltage. The signal transmission circuit according to claim 1 or 2,
The second driving circuit generates the third pulse voltage after the first pulse voltage is generated from the first driving circuit,
The signal transmission circuit, wherein the second driving circuit generates the third pulse voltage after the second pulse voltage is generated from the first driving circuit. The signal transmission circuit according to any one of claims 1 to 3,
The signal transmission circuit, wherein a pulse width of the third pulse voltage is adjusted based on a leakage inductance of the transformer. The signal transmission circuit according to any one of claims 1 to 4,
A signal transmission circuit comprising: an abnormality determination circuit that determines that an abnormality has occurred in the output destination of the secondary side circuit when detecting that the current flowing through the primary side coil has changed. A signal transmission circuit according to any one of claims 1 to 5,
When the pulse voltage corresponding to the first pulse voltage equal to or higher than the first threshold value is generated in the secondary side coil, the secondary side circuit causes the output signal to rise and causes the secondary side coil to generate a second voltage. When a pulse voltage corresponding to the second pulse voltage equal to or higher than a threshold is generated, the output signal is caused to fall,
The first drive circuit generates the first pulse voltage in the primary coil, and then the pulse voltage generated in the secondary coil in the primary coil is less than the second threshold value. After generating a pulse voltage and generating the second pulse voltage in the primary coil, the pulse voltage generated in the secondary coil in the primary coil is less than the first threshold value. Generating,
A signal transmission circuit characterized by that.