JP2009130016A - Semiconductor device manufacturing method and electronic apparatus - Google Patents

Abstract

As a manufacturing technique of a TFT for forming an LDD simultaneously with a source and a drain, a technique of performing ion implantation using a tapered photoresist layer as a mask immediately above a semiconductor layer, or a mask having a tapered gate electrode shape Although the technique for performing ion implantation is known, the former technique has a problem that damage due to the photoresist peeling is accumulated in the semiconductor layer, and the performance and reliability of the TFT are lowered. In the latter technique, since the cross-sectional shape of the gate electrode is processed into a special shape, there is a problem that it becomes a concern for lowering the reliability of the TFT.
A tapered photoresist layer is disposed on a gate insulating layer, and ion implantation is performed using this layer as a mask. Since it is not necessary to process the gate electrode into a special shape and damage accumulation on the surface of the semiconductor layer is suppressed, it is possible to suppress degradation of the performance and reliability of the TFT.
[Selection] Figure 5

Description

  The present invention relates to a method for manufacturing a semiconductor device and an electronic apparatus.

  As an electro-optical device such as a liquid crystal device, an organic electroluminescence (EL) device, or a plasma display, each dot is provided with a thin film transistor (TFT) as a semiconductor device in order to drive a large number of dots arranged in a matrix. Active matrix electro-optical devices are widely used. The TFT generally uses amorphous silicon or polycrystalline silicon as a channel region. In particular, a polycrystalline silicon TFT manufactured using a laser annealing method is widely used in electro-optical devices such as the above-described liquid crystal devices and organic EL devices because electrons and holes have a large electric field mobility.

  As a TFT (semiconductor device), a TFT having an LDD (Lightly Doped Drain) structure and a TFT having a GOLD (Gate-drain Overlapped LDD) structure are widely known. A TFT having an LDD structure has a structure in which a low concentration impurity region is formed in a polycrystalline silicon layer located outside a gate electrode in plan view, and a high concentration impurity region serving as a source region and a drain region is formed in the outer region. I am doing. A TFT having an LDD structure has an effect of suppressing an off-current value. In addition, since there is little overlap between the gate electrode and the LDD portion in plan view, the parasitic capacitance is reduced, and the structure is suitable for high-speed operation. On the other hand, a TFT having a GOLD structure has a structure in which the low-concentration impurity region of the LDD structure is formed so as to overlap with a polycrystalline silicon layer located in the gate electrode in plan view. There is an inhibitory effect. Furthermore, the above effect can be further enhanced by providing a concentration gradient in the low concentration impurity region.

As a method of forming a TFT having the LDD and GOLD structure, a photoresist pattern having a thin region at the end from the center is formed on the surface of the semiconductor layer forming the channel, and this photoresist pattern is used as a mask. A method for forming a TFT having an LDD structure by injecting impurities into a semiconductor layer is disclosed (for example, Patent Document 1).
Further, a photoresist pattern having a region with a thinner layer at the end than the center is formed using a diffraction grating pattern or a photomask having a pattern whose transmittance is controlled to be halftone. Then, the conductive layer is etched using this photoresist pattern. Using such a process, a gate electrode having a thin region at the end from the center is formed, and by using this gate electrode as a mask, an impurity is implanted into the semiconductor layer, so that a low concentration impurity region has a concentration gradient. A method for forming a TFT having an LDD structure is disclosed (for example, Patent Document 2).

JP 2006-54424 A JP 2002-151523 A

In the TFT forming method disclosed in Patent Document 1, a photoresist pattern is formed directly on the surface of the semiconductor layer. Since the ashing process using oxygen plasma is usually used to remove the photoresist pattern, damage is accumulated on the surface of the semiconductor layer by the oxygen plasma. Therefore, there is a problem that the performance and reliability of the TFT are lowered.
Even when the wet stripping process is used, organic contaminants derived from the photoresist may adhere to the semiconductor surface and remain, and there is a concern that the performance and reliability of the TFT may be lowered.

  Further, in the TFT forming method having the LDD and GOLD structure disclosed in Patent Document 2, the remaining layer thickness at the both ends of the gate electrode is 5 to 30% of the initial layer thickness using the photoresist pattern as a mask. A low concentration impurity region is formed in the semiconductor layer using the gate electrode as a mask.

  However, in the TFT forming method having the LDD and GOLD structure, the gate electrode layer thickness is controlled to a predetermined thickness, so that the dry etching selection ratio must be taken into account, and the processing of the gate electrode is complicated. There is a problem of becoming. Further, when dry etching is performed, the etching is performed in consideration of the selection ratio in order to control the layer thickness of the gate electrode as described above. In order to obtain this desired selection ratio, the material constituting the gate electrode, There is a problem that restrictions are imposed on the selection of the etching solution and the like. Further, since the cross-sectional shape of the gate electrode is processed into a special shape, there is a problem that it becomes a concern for lowering the reliability of the TFT.

  In this specification, “upper” is defined as a direction normal to the substrate and from the substrate toward the semiconductor layer. The “channel region” is defined as a region in the semiconductor layer that is a shadow of the gate electrode in plan view from above.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 A manufacturing method of a semiconductor device according to this application example is a manufacturing method of a semiconductor device having a source region, a drain region, a channel region, and a gate electrode, and at least the surface is insulative. Forming an insulating layer on a semiconductor layer disposed on the substrate having; a first photoresist portion disposed on the insulating layer and disposed on a region including at least a part of the channel region; A second photoresist portion located on an insulating layer and disposed on a region including the source region and the drain region and having a thickness (including zero) formed thinner than the first photoresist portion; It is sandwiched between the first photoresist portion and the second photoresist portion in plan view, and is thinner than the layer thickness of the first photoresist portion and thicker than the layer thickness of the second photoresist portion. And a step of forming a photoresist portion, and when ions are implanted into the semiconductor layer through the insulating layer, the impurity concentration in the semiconductor layer has a peak, or the impurity concentration peak is shallower than the semiconductor layer. An ion implantation process performed at an acceleration energy at which the impurity concentration monotonously decreases according to the thickness of the second photoresist portion disposed on the insulating layer, and the ion implantation process ends. And a step of performing at least one of ashing and wet peeling.

  According to this, the insulating layer is formed after the patterning of the semiconductor layer. A photoresist layer is formed on the insulating layer as an ion implantation mask, and an ashing process for removing the photoresist layer is performed after the ion implantation process. Therefore, damage caused by the ashing process does not reach the surface of the semiconductor layer, so that it is possible to provide a technique for manufacturing a semiconductor device having excellent performance and reliability. In addition, even when a wet stripping process is used, it is possible to prevent adhesion and residue of organic contaminants derived from photoresist on the semiconductor layer, so that a technology for manufacturing a semiconductor device having excellent performance and reliability can be provided. It becomes possible. In addition, the impurity concentration has a peak in the semiconductor layer, or the impurity concentration peak is formed at a position shallower than the semiconductor layer, so that the second photoresist portion disposed on the insulating layer has a thickness. Ion implantation can be performed with acceleration energy at which the impurity concentration monotonously decreases, and the impurity concentration can be controlled by the thickness of the second photoresist portion.

  Application Example 2 In the method of manufacturing a semiconductor device according to the application example, the third photoresist portion has a uniform thickness.

  According to the application example described above, a region having a uniform impurity concentration is formed in a region sandwiching the channel region. This region is covered with a third photoresist portion that is thicker than the second photoresist portion covering the source region and the drain region and thinner than the first photoresist portion covering the channel region. When an ion implantation process is performed on this structure, an electric field relaxation region having a lower concentration than the source region and the drain region and a higher concentration than the channel region is formed at the same time. That is, the source region, the drain region, and the electric field relaxation region can be formed by one ion implantation. Furthermore, since it has a uniform impurity distribution, it is easy to determine the conditions for the ion implantation process, and the ion implantation conditions can be obtained with a small number of trial steps.

  Application Example 3 In the method of manufacturing a semiconductor device according to the application example, the third photoresist portion includes a step having a thickness of one step or more.

  According to the application example described above, the semiconductor layer covered with the third photoresist portion functions as an electric field relaxation region. The third photoresist portion includes a step. Therefore, a distribution can be given to the impurity concentration in the electric field relaxation region, and the electric field strength distribution in the electric field relaxation region can be adjusted. Therefore, since it is possible to give a distribution to the electric field strength, it is possible to provide a manufacturing process of a semiconductor device capable of optimizing the withstand voltage design.

  Application Example 4 In the method of manufacturing a semiconductor device according to the application example, the third photoresist portion includes a tapered shape in thickness.

  According to the application example described above, the semiconductor layer covered with the third photoresist portion functions as an electric field relaxation region. A tapered impurity distribution is formed in the electric field relaxation region corresponding to the shape of the third photoresist portion. Therefore, the electric field distribution in the electric field relaxation region can be continuously changed, and local electric field concentration can be avoided. Therefore, it becomes possible to manufacture a semiconductor device with a high breakdown voltage.

  Application Example 5 In the method of manufacturing a semiconductor device according to the application example, the gate electrode is positioned below the third photoresist portion at both ends of the gate electrode with respect to the length direction of the channel region. It is formed so as to overlap with at least a part of the semiconductor layer in a plan view.

  According to the application example described above, the semiconductor layer covered with the third photoresist portion functions as an electric field relaxation region. When the electric field relaxation region and the gate electrode partially overlap in plan view, a state in which the electric field relaxation region and the channel region located under the gate electrode are continuous is formed. Therefore, electric field concentration that occurs when the channel region and the electric field relaxation region are separated can be avoided, and a semiconductor device with high breakdown voltage can be formed.

  Application Example 6 In the method of manufacturing a semiconductor device according to the application example described above, it includes an ion implantation process that is performed again using the gate electrode as a mask after the ion implantation process is completed.

  According to the application example described above, in addition to the semiconductor layer covered with the third photoresist portion functioning as the electric field relaxation region, the step of performing ion implantation again using the gate electrode as a mask is included. Therefore, the electric field relaxation region and the channel region under the gate electrode are connected in a self-aligned manner. That is, it becomes possible to manufacture a semiconductor device in which an electric field relaxation region and a channel region are formed while suppressing performance degradation due to mask misalignment.

  Application Example 7 In the semiconductor device manufacturing method according to the application example, the semiconductor device manufacturing method according to claim 1, wherein the gate electrode is a length of the channel region. Both ends of the gate electrode with respect to the direction are located under the third photoresist portion, and the semiconductor layer that has been ion-implanted by passing through the third photoresist portion is formed under the gate electrode. It is formed so as to be separated from the semiconductor layer in plan view, and includes an ion implantation step in which the ion implantation step is completed and then performed again using the gate electrode as a mask.

  According to the application example described above, an LDD structure can be formed. In the LDD structure, a region having a higher impurity concentration than the LDD region and a lower impurity concentration than the source region and the drain region is formed between the LDD region and the source region and the drain region with respect to the length direction of the channel region. A semiconductor device having a higher breakdown voltage can be manufactured by cooperating with the LDD region.

  Application Example 8 In the method for manufacturing a semiconductor device according to the application example, the substrate has a light-transmitting property.

  According to the application example described above, the semiconductor device can be used for a device that transmits light and forms a light intensity distribution.

  Application Example 9 An electronic apparatus according to this application example includes a semiconductor device formed by using the semiconductor device manufacturing method described above.

  According to this, it is possible to provide an electronic device including a semiconductor device that requires a high breakdown voltage.

(First Embodiment: Application Example of Semiconductor Device (TFT))
An application example of the semiconductor device of this embodiment will be described with reference to FIGS. In this embodiment, an active matrix transmissive liquid crystal device using a TFT as a semiconductor device will be described as an example.

  FIG. 1 is an equivalent circuit diagram of switching elements, signal lines and the like in a plurality of dots arranged in a matrix constituting the image display area of the liquid crystal device of this embodiment, and FIG. 2 is a diagram of data lines, scanning lines, pixel electrodes and the like. FIG. 3 is a cross-sectional view showing the structure of the liquid crystal device of the present embodiment, and is a cross-sectional view taken along the line AA ′ of FIG. Note that FIG. 3 illustrates the case where the upper side in the drawing is the light incident side and the lower side in the drawing is the viewing side (observer side). Moreover, in each figure, in order to make each layer and each member the size which can be recognized on drawing, the scale is varied for every layer and each member.

  In the liquid crystal device according to the present embodiment, as shown in FIG. 1, a plurality of dots arranged in a matrix that forms an image display area are pixel electrodes 9 and switching elements for controlling the pixel electrodes 9. Each TFT (semiconductor device) 90 is formed, and a data line 6 a to which an image signal is supplied is electrically connected to the source of the TFT 90. Image signals S1, S2,..., Sn to be written to the data line 6a are supplied line-sequentially in this order, or are supplied for each group to a plurality of adjacent data lines 6a.

  The scanning line 3a is electrically connected to the gate of the TFT 90, and scanning signals G1, G2,..., Gm are applied to the plurality of scanning lines 3a in a pulse-sequential manner at a predetermined timing. The pixel electrode 9 is electrically connected to the drain of the TFT 90. By turning on the TFT 90, which is a switching element, for a predetermined period, the image signals S1, S2,... Sn supplied from the data line 6a are predetermined. Write at the timing.

  A predetermined level of image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9 is held for a certain period with the common electrode described later. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. Here, in order to prevent the held image signal from leaking, a storage capacitor 98 (see FIG. 2) is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 and the common electrode.

  As shown in FIG. 3, the liquid crystal device according to the present embodiment has a TFT array substrate 100 on which a TFT 90 and pixel electrodes 9 are formed, and a counter substrate on which a common electrode 108 is formed. 104 and is schematically configured.

Hereinafter, the planar structure of the TFT array substrate 100 will be described with reference to FIG.
A plurality of rectangular pixel electrodes 9 are provided in a matrix on the TFT array substrate 100. As shown in FIG. 2, data lines 6a and scanning lines 3a are arranged along the vertical and horizontal boundaries of each pixel electrode 9. The capacitor line 3b is provided. In the present embodiment, each pixel electrode 9 and a region where the data line 6a, the scanning line 3a, and the like arranged so as to surround each pixel electrode 9 are formed are one dot.

  The data line 6a is electrically connected to the source region 18 through the contact hole 92 in the polycrystalline semiconductor layer 14a (see FIG. 3) constituting the TFT 90, and the pixel electrode 9 is connected to the polycrystalline semiconductor layer 14a. Among them, the drain region 19 is electrically connected through a contact hole 96, a source line 6 b and a contact hole 94. A part of the scanning line 3a is widened so as to face the channel region 20 in the polycrystalline semiconductor layer 14a, and the widened part of the scanning line 3a functions as the gate electrode 24a. The polycrystalline semiconductor layer 14a constituting the TFT 90 extends to a portion facing the capacitor line 3b. The storage capacitor (storage capacitor) having the extended portion 1f as a lower electrode and the capacitor line 3b as an upper electrode. Element) 98 is formed.

Next, a cross-sectional structure of the liquid crystal device of the present embodiment will be described based on FIG.
The TFT array substrate 100 is mainly composed of a substrate 10 made of a light-transmitting material such as glass, a pixel electrode 9, a TFT 90, and an alignment layer 11 formed on the liquid crystal layer 102 side, and the counter substrate 104 is made of glass or the like. The substrate 104 </ b> A made of a translucent material, the common electrode 108 formed on the surface of the liquid crystal layer 102, and the alignment layer 110 are mainly configured.

  Specifically, in the TFT array substrate 100, a base protective layer (buffer layer) 12 made of a silicon oxide layer or the like is formed immediately above the substrate 10. In addition, a pixel electrode 9 made of a transparent conductive material such as indium tin oxide (ITO) is provided on the liquid crystal layer 102 side of the substrate 10, and each pixel electrode 9 is subjected to switching control at a position adjacent to each pixel electrode 9. A pixel switching TFT 90 is provided.

  A polycrystalline semiconductor layer 14a made of polycrystalline silicon is formed in a predetermined pattern on the base protective layer 12, and a gate insulating layer 22 made of a silicon oxide layer or the like is formed on the polycrystalline semiconductor layer 14a. A gate electrode 24 a is formed on the gate insulating layer 22. In the polycrystalline semiconductor layer 14a, a region facing the gate electrode 24a through the gate insulating layer 22 is a channel region 20 in which a channel is formed by an electric field from the gate electrode 24a. In the polycrystalline semiconductor layer 14a, a source region 18 is formed on one side (the left side in the drawing) of the channel region 20, and a drain region 19 is formed on the other side (the right side in the drawing). A pixel switching TFT 90 is configured by the gate electrode 24a, the gate insulating layer 22, the data line 6a, the source line 6b, the source region 18, the channel region 20, the drain region 19 and the like of the polycrystalline semiconductor layer 14a.

  In this embodiment, the pixel switching TFT 90 has an LDD structure, and has a source region 18 and a drain region 19 having a relatively high impurity concentration, and a source side low concentration as a relatively low concentration region. A region 26 and a drain side low concentration region 27 (LDD region) are formed.

  A first interlayer insulating layer 4 made of a silicon oxide layer or the like is formed on the substrate 10 on which the gate electrode 24a is formed. On the first interlayer insulating layer 4, a data line 6a and a source line 6b are formed. Is formed. The data line 6a is electrically connected to the source region 18 of the polycrystalline semiconductor layer 14a through a contact hole 92 formed in the first interlayer insulating layer 4, and the source line 6b is connected to the first interlayer insulating layer. 4 is electrically connected to the drain region 19 of the polycrystalline semiconductor layer 14a through a contact hole 94 formed in the contact hole 94.

  Further, a second interlayer insulating layer 5 made of a silicon nitride layer or the like is formed on the first interlayer insulating layer 4 on which the data line 6a and the source line 6b are formed, and on the second interlayer insulating layer 5, A pixel electrode 9 is formed. The pixel electrode 9 is electrically connected to the source line 6 b through a contact hole 96 formed in the second interlayer insulating layer 5. An alignment layer 11 for controlling the alignment of liquid crystal molecules in the liquid crystal layer 102 is formed on the outermost surface of the TFT array substrate 100 on the liquid crystal layer 102 side.

  On the other hand, in the counter substrate 104, light incident on the liquid crystal device on the surface of the substrate 104A on the liquid crystal layer 102 side is at least the channel region 20, the source side low concentration region 26, and the drain side low concentration region of the polycrystalline semiconductor layer 14a. A light shielding layer 106 for preventing light incident on the light 27 is formed. A common electrode 108 made of ITO or the like is formed on almost the entire surface of the substrate 104A on which the light shielding layer 106 is formed.

(Semiconductor Device Manufacturing Method-1: LDD Structure)
The TFT (semiconductor device) having the LDD structure according to the present embodiment will be described below. FIGS. 4A to 4C and FIGS. 5A to 5C are schematic cross-sectional views showing a method of manufacturing an n-channel TFT having an LDD structure in this embodiment in the order of steps.
First, as step 1, a light-transmitting substrate such as a glass substrate cleaned by ultrasonic cleaning or the like is prepared as the substrate 10.

Next, as step 2, under the condition that the surface temperature of the substrate 10 is 150 to 450 ° C., a base protective layer (buffer layer) 12 made of a silicon oxide layer or the like is formed on the entire surface of the substrate 10 by a plasma CVD method or the like. Stratified to a thickness of 500 nm. As the source gas used in this step, a mixed gas of monosilane and dinitrogen monoxide, a mixed gas of TEOS (tetraethoxysilane, Si (OC ₂ H ₅ ) ₄ ) and oxygen, or the like is preferable.

  Next, as step 3, an amorphous semiconductor layer 14 made of amorphous silicon is deposited on the entire surface of the base protective layer 12 to a thickness of 30 to 100 nm by plasma CVD or the like. As the source gas used in this step, disilane or monosilane is suitable.

  Next, as step 4, the amorphous semiconductor layer 14 is polycrystallized by laser annealing or the like to form a polycrystal semiconductor layer 14a.

  Next, as step 5, a protective layer 17 of the polycrystalline semiconductor layer 14a made of a silicon oxide layer is formed using a CVD method or the like.

  Next, as step 6, a photoresist 16 is formed on the protective layer 17, and the photoresist 16 is patterned into a predetermined shape by a photolithography method, and etching is performed to separate elements of the polycrystalline semiconductor layer 14a. FIG. 4A shows a state where the steps so far are performed.

  Next, as step 7, the photoresist 16 is removed by ashing, and the protective layer 17 is removed by wet etching. By performing element isolation in such a process, the polycrystalline semiconductor layer 14a can be protected from damage due to ashing performed when the photoresist 16 is removed. Even when a wet stripping process is used, contamination of the semiconductor surface from organic contaminants derived from photoresist can be prevented. FIG. 4B shows a state where the steps so far are performed.

  Next, as step 8, the gate insulating layer 22 is formed. The gate insulating layer 22 is preferably a silicon oxide layer using, for example, a CVD method.

  Next, as Step 9, after applying the photoresist 150, exposure is performed using a halftone mask. The shape of the photoresist 150 is such that the layer thickness in the second photoresist portion 150c corresponding to the source region 18 and the drain region 19 of the polycrystalline semiconductor layer 14a is the layer thickness of the first photoresist portion 150b corresponding to the channel region 20a. It is formed to be thinner.

  This condition is that when high-concentration impurity ions are implanted into the polycrystalline semiconductor layer 14a, the irradiated high-concentration impurity ions are blocked by the photoresist 150 in the channel region 20a, and the source region 18 and the drain region 19 This means that the layer thickness is such that it is implanted into the polycrystalline semiconductor layer 14a. The layer thickness of the second photoresist portion 150c in the regions corresponding to the source region 18 and the drain region 19 is preferably, for example, 0 nm (no layer) or more and 200 nm or less. In this embodiment, the condition of 0 nm (no layer) is used.

  On the other hand, the layer thickness of the first photoresist portion 150b corresponding to the channel region 20a of the polycrystalline semiconductor layer 14a is such that the high-concentration impurity ions implanted into the polycrystalline semiconductor layer 14a are irradiated with a high concentration. The layer thickness is such that the impurity ions are blocked in the first photoresist portion 150b and the impurity ions do not reach the polycrystalline semiconductor layer 14a. The layer thickness of the first photoresist portion 150b corresponding to the channel region 20a is preferably 200 nm or more, for example. In this embodiment, a condition of 400 nm is used.

  The upper limit of the layer thickness of the first photoresist portion 150b corresponding to the channel region 20a is not particularly limited, but when the thickness of the first photoresist portion 150b exceeds 2 μm, for example, the source-side low concentration region 26 and the drain Since it becomes difficult to control the layer thickness of the third photoresist portion 150a corresponding to the low-concentration side region 27, a layer thickness of about 2 μm or less is preferable. Note that the layer thickness of the third photoresist portion 150a exceeds 2 μm when a process capable of controlling a desired layer thickness in a region where the source side low concentration region 26 and the drain side low concentration region 27 are located is used. The layer thickness may be selected.

The thickness of the third photoresist portion 150a corresponding to the source-side low-concentration region 26 and the drain-side low-concentration region 27 connecting the source region 18 and drain region 19 and the channel region 20a is determined by high-concentration impurity ion implantation. When performed, the layer thickness is preferably such that impurity ions of a predetermined concentration reach the polycrystalline semiconductor layer 14a. As a standard of the layer thickness, it is thicker than the second photoresist portion 150c, has a uniform layer thickness in the range of 200 nm or less, and is highly ion-implanted (for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm). ² ), the drain-side low-concentration region 27 is controlled to have an impurity concentration (for example, about 1 × 10 ¹⁶ to 1 × 10 ²⁰ / cm ³ ) that functions as an electric field relaxation region. Is preferred. FIG. 4C shows a state where the steps so far are performed.

Next, as step 10, with the photoresist 150 as a mask, a high concentration of impurity ions (phosphorus ions) is applied to the polycrystalline semiconductor layer 14a, for example, at a dose of about 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ^2. Inject with. As a result, for the second resist portion where the photoresist 150 is thin, the high-concentration impurity ions pass through the second photoresist portion 150c (here, no layer) in a high-concentration state, and the polycrystalline semiconductor layer 14a. In this manner, the source region 18 and the drain region 19 can be formed in the polycrystalline semiconductor layer 14a using the second photoresist portion 150c (here, no layer) as a mask.
On the other hand, in the first photoresist portion 150b where the layer thickness of the photoresist 150 is thick, the high-concentration impurity ions are blocked in the first photoresist portion 150b. Therefore, a region where impurity ions do not reach is formed in the region of the polycrystalline semiconductor layer 14a. This region becomes a part of the channel region 20a.
In the third photoresist portion 150a, when high concentration ion implantation (for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ² ) is performed, the source side low concentration region 26 and the drain side low concentration region 27 are formed. Is thicker than the second photoresist portion 150c and within a range of 200 nm or less so that the impurity concentration is controlled so as to function as an electric field relaxation region (for example, about 1 × 10 ¹⁶ to 1 × 10 ²⁰ / cm ³ ). A uniform layer thickness. FIG. 5A shows a state where the steps so far are performed.

  Next, as step 11, the photoresist 150 formed on the gate insulating layer 22 is peeled off.

  Next, as step 12, a conductive layer 24 to be a gate electrode 24a described later is formed on the entire surface of the gate insulating layer 22.

  Next, as step 13, a photoresist 30 is deposited on the entire surface of the conductive layer 24, and the photoresist 30 is exposed and developed by photolithography to be patterned into a predetermined shape.

  Next, as step 14, the conductive layer 24 is etched using the photoresist 30 patterned in the predetermined shape as a mask to form a gate electrode 24a. FIG. 5B shows a state where the steps so far are performed.

  Next, as step 15, the photoresist 30 is etched to form a TFT 90a. FIG. 5C shows the state after the steps so far.

  In the step of forming the gate electrode 24a, misalignment may occur. When the source-side low concentration region 26, the drain-side low concentration region 27, and the channel region 20a are separated from each other, a region having an abnormally high electric resistance is generated, and the current that can flow through the channel region 20a is reduced. Further, a high electric field is generated beside the channel region 20a, and the reliability is lowered. Therefore, the channel region 20a may be overlapped so as to include the source side low concentration region 26 and the drain side low concentration region 27 as part of the channel region 20a.

  In this manner, the TFT 90a having the LDD structure in which the source-side low concentration region 26 and the drain-side low concentration region 27 are disposed at both ends of the channel region 20a of the polycrystalline semiconductor layer 14a region is formed. When this step is used, the source region 18, the drain region 19, the source side low concentration region 26, and the drain side low concentration region 27 can be formed at the same time, so that the manufacturing process can be shortened.

  Further, since the photoresists 16 and 150 do not directly contact the polycrystalline semiconductor layer 14a, contamination caused by the contact of the polycrystalline semiconductor layer 14a with the photoresists 16 and 150 can be prevented. In addition, since the polycrystalline semiconductor layer 14a can be protected from damage caused by oxygen plasma or the like in the ashing process for removing the photoresists 16 and 150, deterioration of the electrical characteristics of the TFT 90a can be suppressed. In addition, even when a wet stripping process is used, it is possible to prevent the organic contaminants derived from the photoresist from adhering to or remaining on the polycrystalline semiconductor layer 14a, and thus a technique for manufacturing a TFT 90a having excellent performance and reliability is provided. It becomes possible.

(Semiconductor Device Manufacturing Method-1: Modification)
In the above, a modification is introduced about the manufacturing method of the semiconductor device (TFT) which has LDD structure.

  As the method for manufacturing this semiconductor device, an n-channel type has been described, but in this case, a p-channel type TFT can be formed by using, for example, boron ions instead of phosphorus ions in step 10. Further, a CMOS structure in which an n-channel type and a p-channel type are formed on the same substrate may be manufactured.

  In this method for manufacturing a semiconductor device, the conductive layer 24 for forming the gate electrode 24a is formed as the step 12 on the gate insulating layer 22 that has been processed up to the step 11. The gate insulating layer 22 may be peeled off, a new gate insulating layer may be disposed again, and the process 12 and subsequent steps may be performed. In this case, since the gate insulating layer 22 that has been damaged in processes such as ion implantation and ashing is replaced, it is possible to provide a higher quality TFT.

  Further, although an example in which a step shape is given to the photoresist 150 formed in step 9 using a halftone mask has been described, this may be formed using a plurality of photolithographic steps. For example, first, a second photoresist portion 150c (can be omitted in the case of 0 nm) is formed using a thin photoresist. Next, the third photoresist portion 150a is formed in the same manner. In this case, the photoresist layer thickness is preferably a value obtained by subtracting the layer thickness of the second photoresist portion 150c from the desired thickness of the third photoresist portion 150a. Next, a first photoresist portion 150b is formed. In this case, the layer thickness of the photoresist is preferably a value obtained by subtracting the layer thickness of the third photoresist portion 150a from the desired thickness of the first photoresist portion 150b. By forming in this way, a photoresist pattern with high layer thickness accuracy can be obtained.

  Further, instead of the halftone mask, a mask that continuously changes the exposure amount by forming a narrow pattern having an exposure resolution or less may be used.

  Further, as an example of the shape of the photoresist 150 formed in step 9, the third photoresist portion 150a has been described as using a flat pattern, but this is a stepped shape, a tapered shape, a bowl-shaped shape, A trumpet shape and a combination thereof may be used. When these techniques are used, it is possible to control the concentration distribution of the source-side low concentration region 26 and the drain-side low concentration region 27, and a TFT with higher breakdown voltage can be provided.

  In this method of manufacturing a semiconductor device, the case where the polycrystalline semiconductor layer 14a made of polycrystalline silicon obtained by crystallizing the amorphous semiconductor layer 14 is used as the semiconductor layer has been described. May be used as it is, and in this case, the annealing process by laser irradiation having a long processing time can be omitted, so that the time required for production can be shortened. Alternatively, the layers may be formed under the conditions for forming a polycrystalline semiconductor from the beginning.

  For example, a single crystal semiconductor layer may be formed over the light-transmitting substrate 10 by using a bonding technique. In this case, since a semiconductor layer having high mobility is used, a TFT operating at an extremely high speed can be provided.

Further, instead of the light-transmitting substrate 10, a light-shielding substrate may be used. In this case, the present invention can be applied to a reflection type optical device. Furthermore, it is not necessary to be limited to the application to the optical related field, and it is possible to deal with the field in which the withstand voltage design is particularly important.
In the TFT 90a, the example in which the source region 18, the drain region 19, the source side low concentration region 26, and the drain side low concentration region 27 are symmetric with respect to the channel region 20a has been described. For example, the impurity concentration of the source side low concentration region 26 may be made higher than that of the drain side low concentration region 27. By applying a voltage to the TFT 90 a, a stronger electric field is applied to the drain side low concentration region 27 than to the source side low concentration region 26. For this reason, the drain side lightly doped region 27 gives priority to electric field relaxation, and the source side lightly doped region 26 gives priority to conductivity, so that the withstand voltage and drive capability can be optimized.

(Semiconductor Device Manufacturing Method-2: GOLD Structure)
A TFT 90b having an n-channel GOLD structure can be manufactured by partially changing the manufacturing method for creating the LDD structure. Note that the GOLD structure disclosed in this embodiment means a structure in which at least a part of the low concentration region overlaps the gate electrode 24a. Specifically, the layer thickness of the third photoresist portion 150a is reduced, and the source-side low-concentration region 26 and the drain introduced in the ion implantation step performed in step 10 of (Semiconductor device manufacturing method-1) described above. The concentration of the side low concentration region 27 is increased, and the length of the first photoresist portion 150b is decreased. When this condition is used, the channel region 20a located under the gate electrode 24a is divided into a region where ion implantation is blocked by the first photoresist portion 150b, and a channel low concentration region 20b for relaxing the electric field (see FIG. 6 (b).). When this configuration is used, the electric field is relaxed by the channel low concentration region 20b, so that generation of hot carriers can be suppressed. Hereinafter, the manufacturing process of the GOLD structure will be described with reference to the drawings. 6A and 6B are schematic cross-sectional views showing a method of manufacturing an n-channel TFT having a GOLD structure in this embodiment in the order of steps.

From Step 1 to Step 8, the same steps as in (Semiconductor Device Manufacturing Method-1) are performed.
Then, in step 9a, after applying the photoresist 150, a halftone mask having a mask pattern different from the halftone mask in step 9 is used. Specifically, a halftone mask configured to reduce the layer thickness of the third photoresist portion 150a and reduce the length of the first photoresist portion 150b is used.

Next, the same process as the process 10 is performed. FIG. 6A shows a state where the steps so far are performed. Since the pattern shape of the photoresist 150 is different, the impurity distribution of the polycrystalline semiconductor layer 14a is changed. The channel region 20a includes a region where ion implantation is blocked by the first photoresist portion 150b and a channel low concentration region 20b for relaxing the electric field. Then, as Step 11 to Step 15, the same steps as in (Semiconductor Device Manufacturing Method-1) are performed, and a TFT 90b having a GOLD structure is obtained. FIG. 6B shows a state where the steps so far are performed. By performing the above steps, the TFT 90b having a GOLD structure can be manufactured without increasing the number of steps. Also in this case, a modification similar to (Semiconductor Device Manufacturing Method-1: Modification) can be used.
Further, after that, ion implantation is performed on the GOLD structure shown in FIG. 8A using the gate electrode 24a as a mask, and the source-side intermediate concentration region 26a and the drain-side intermediate concentration having different impurity concentrations from the channel low concentration region 20b. The region 27a may be formed to form the structure shown in FIG. Also in this case, a modification similar to (Semiconductor Device Manufacturing Method-1: Modification) can be used.

(Semiconductor Device Manufacturing Method-3: Self-Aligned LDD Structure)
Hereinafter, a TFT having an n-channel self-aligned LDD structure according to the present embodiment will be described. 7A to 7C are schematic cross-sectional views showing a method of manufacturing an n-channel TFT having a self-aligned LDD structure in this embodiment in the order of steps.
First, steps similar to those in steps 1 to 12 (semiconductor device manufacturing method-1) are performed.

  Next, as step 13a, exposure and development processes with different photomask patterns are performed. Specifically, the photoresist 30 is formed so that the source-side low concentration region 26, the drain-side low concentration region 27, and the photoresist 30 are separated from each other in plan view. FIG. 7A shows the structure after the steps so far are completed.

  Next, Step 14 and Step 15 are performed in the same manner as (Semiconductor Device Manufacturing Method-1). FIG. 7B shows the structure after the steps so far are completed.

  Next, in step 16, phosphorus ions are implanted in a self-aligning manner using the gate electrode 24a as a mask. By this step, the source side low concentration region 26 and the drain side low concentration region 27 become the source side intermediate concentration region 26a and the drain side intermediate concentration region 27a, and the source side intermediate concentration region 26a, the drain side intermediate concentration region 27a, and the gate electrode 24a. A source-side lightly doped region 26b and a drain-side lightly doped region 27b are formed in between. FIG. 7C shows the structure after the steps so far are completed.

  When manufactured using this process, the source-side lightly doped region 26b and the drain-side lightly doped region 27b can be formed in a self-aligned manner, so that performance degradation due to misalignment can be suppressed. Further, since the parasitic capacitance between the gate electrode 24a and the source-side lightly doped region 26b and the drain-side lightly doped region 27b can be suppressed, a TFT 90c that operates at high speed and with low power consumption can be provided. Even when the pattern of the third photoresist portion 150a uses a structure that can be easily manufactured and has a uniform thickness, there are two levels between the source region 18 and the drain region 19 and the channel region 20a. It is possible to provide a manufacturing method of the TFT 90c having an impurity distribution and facilitating electric field relaxation. Further, since the source side low concentration region 26b and the drain side low concentration region 27b are formed between the source region 18 and the source side intermediate concentration region 26a and between the drain region 19 and the drain side intermediate concentration region 27a, The electrical resistance can be kept low, and a manufacturing method of the TFT 90c with higher driving capability can be applied. Also in this case, a modification similar to (Semiconductor Device Manufacturing Method-1: Modification) can be used.

[Electronics]
Hereinafter, specific examples of the electronic apparatus including the liquid crystal display device according to the embodiment of the present invention will be described. FIG. 9 is a perspective view showing an example of the liquid crystal display television 200. In FIG. 9, a liquid crystal display television 200 shows a television main body 202 and a speaker 203, and includes a display unit 201 using the display device. Note that the above-described liquid crystal display television 200 can be applied to various other electronic devices.
For example, projector, multimedia compatible personal computer (PC) and engineering workstation (EWS), pager, word processor, viewfinder type or monitor direct view type video recorder, electronic notebook, electronic desk calculator, car navigation device, POS terminal It can be applied to an electronic device such as a device provided with a touch panel. In the present embodiment, the liquid crystal display device has been described in detail as an example. However, this can be applied to a self-luminous organic EL display device, a line head using an organic EL as a light source, a recording device, or the like. Is possible.

FIG. 3 is an equivalent circuit diagram of switching elements, signal lines, and the like arranged in a matrix that forms an image display area of the liquid crystal device. The top view which expands and shows 1 dot of a TFT array substrate. Sectional drawing which shows the structure of a liquid crystal device. (A)-(c) is a 1st schematic sectional drawing which shows the manufacturing method of the n channel type TFT which has LDD structure in order of a process. (A)-(c) is the 2nd schematic sectional drawing which shows the manufacturing method of the n channel type TFT which has LDD structure in order of a process. (A), (b) is a schematic sectional drawing which shows the manufacturing method of the n channel type TFT which has a GOLD structure in order of a process. (A)-(c) is a schematic sectional drawing which shows the manufacturing method of n channel type TFT which has a self alignment type LDD structure in order of a process. (A), (b) is a schematic sectional drawing which shows the manufacturing method of the n channel type TFT which has the self alignment type GOLD structure in this embodiment in order of a process. The perspective view which showed an example of the liquid crystal display television.

Explanation of symbols

  1f ... extended portion, 3a ... scanning line, 3b ... capacitor line, 4 ... first interlayer insulating layer, 5 ... second interlayer insulating layer, 6a ... data line, 6b ... source line, 9 ... pixel electrode, 10 ... substrate , 11 ... orientation layer, 12 ... base protective layer, 14 ... amorphous semiconductor layer, 14a ... polycrystalline semiconductor layer, 16 ... photoresist, 17 ... protective layer, 18 ... source region, 19 ... drain region, 20 ... channel 20a ... channel region, 20b ... channel low concentration region, 22 ... gate insulating layer, 24 ... conductive layer, 24a ... gate electrode, 26 ... source side low concentration region, 26a ... source side medium concentration region, 26b ... source side Low concentration region, 27 ... Drain side low concentration region, 27a ... Drain side medium concentration region, 27b ... Drain side low concentration region, 30 ... Photoresist, 90 ... TFT, 90a ... TFT, 90b ... TFT, 90c ... T T, 90d ... TFT, 92 ... contact hole, 94 ... contact hole, 96 ... contact hole, 98 ... storage capacitor, 100 ... TFT array substrate, 102 ... liquid crystal layer, 104 ... counter substrate, 104A ... substrate, 106 ... light shielding layer , 108 ... common electrode, 110 ... orientation layer, 150 ... photoresist, 150a ... third photoresist part, 150b ... first photoresist part, 150c ... second photoresist part, 200 ... liquid crystal display television, 201 ... display Part 202, television body 203, speaker.

Claims (9)

A method for manufacturing a semiconductor device having a source region, a drain region, a channel region, and a gate electrode,
Forming an insulating layer on a semiconductor layer disposed on a substrate having at least an insulating surface; and
A first photoresist portion located on the insulating layer and disposed on a region including at least a part of the channel region;
A second photoresist portion disposed on the insulating layer and disposed on a region including the source region and the drain region and having a thickness smaller than that of the first photoresist portion (including zero); ,
The first photoresist part and the second photoresist part are sandwiched between the first photoresist part and the second photoresist part, and are thinner than the first photoresist part and thicker than the second photoresist part. 3 photoresist portions, and a step of forming
When ions are implanted into the semiconductor layer through the insulating layer, the impurity concentration shows a peak in the semiconductor layer, or the impurity concentration peak is formed at a position shallower than the semiconductor layer. An ion implantation step that is performed with acceleration energy in which the impurity concentration monotonously decreases according to the thickness of the second photoresist portion disposed in
A step of performing at least one of ashing or wet peeling after the ion implantation step is completed;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the third photoresist portion has a uniform thickness.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the third photoresist portion includes a step having a thickness of one step or more.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the third photoresist portion includes a tapered shape in thickness. 3.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the gate electrode has the third photoresist portion at both ends of the gate electrode with respect to a length direction of the channel region. A method of manufacturing a semiconductor device, wherein the semiconductor layer is formed so as to overlap with at least a part of the semiconductor layer located underneath in plan view.   6. The method of manufacturing a semiconductor device according to claim 1, further comprising an ion implantation step that is performed again using the gate electrode as a mask after the ion implantation step is completed. Device manufacturing method. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the gate electrode has the third photoresist portion at both ends of the gate electrode with respect to a length direction of the channel region. The semiconductor layer that is ion-implanted by passing through the third photoresist portion is formed to be separated from the semiconductor layer under the gate electrode in plan view,
A method of manufacturing a semiconductor device, comprising: an ion implantation step in which the gate electrode is used again as a mask after the ion implantation step is completed.   8. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate has translucency.   An electronic apparatus comprising a semiconductor device formed using the method for manufacturing a semiconductor device according to claim 1.

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