JP2009127981A - Clean room, film forming method, and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clean room reduced in the characteristic dispersion of a semiconductor device to be manufactured. <P>SOLUTION: A vacuum chamber is set in a room filled with gas having no unfavorable effect on a semiconductor film so as to prevent an oxygen gas or a nitrogen gas of an atmospheric component from entering a vacuum chamber from the outside of the vacuum chamber. The gas having no unfavorable effect on the semiconductor film is a rare gas or hydrogen. According to such a clean room structure, an oxygen concentration, a nitrogen concentration and a moisture concentration around a manufacturing device in the room can be minimized as much as possible. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a clean room used as an environment for manufacturing a semiconductor device. The present invention also relates to a method for manufacturing a semiconductor device having a circuit including thin film transistors (hereinafter referred to as TFTs). For example, the present invention relates to an electronic apparatus in which an electro-optical device typified by a liquid crystal display panel or a light-emitting display device having an organic light-emitting element is mounted as a component.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

A production line for producing semiconductor devices is installed in a clean room in which the interior is maintained at a desired cleanliness in order to prevent yield reduction due to dust.

The production line consists of various production equipment, and depending on the type of equipment, there are equipment that is sensitive to dust and equipment that is likely to generate dust. Strict dust management is performed by partitioning the cleanliness area. Patent Document 1 discloses a clean room in which an apparatus installation area, a process area, and an operation area are partitioned and air conditioning is performed independently.

Further, Patent Document 2 discloses a clean room that forms an air curtain that surrounds the apparatus in order to prevent dust from entering the apparatus during maintenance of the apparatus installed in the clean room.
JP 2002-147811 A JP 2004-308964 A

In order to manufacture a semiconductor device having electric characteristics superior to those of conventional ones or to improve the product yield, it is required to increase and maintain the cleanliness of the clean room as much as possible.

In addition to the particulate dust, there are concerns about the influence on the manufacturing process due to contamination by gaseous contaminants, so-called molecular contamination.

In the clean room, the air taken in from the outside air taking-in duct is adjusted to a predetermined temperature and humidity, and the air purified by the fan filter unit is supplied. Therefore, workers can freely come and go in the clean room. On the other hand, since the clean room is filled with air, nitrogen and oxygen contained in the air exist, and when processing an object (for example, silicon wafer) sensitive to nitrogen or oxygen, the object to be processed For things, the air in the clean room itself can be called a pollutant.

Also, depending on the manufacturing process, characteristic variations may occur due to the time that is exposed to the air in the clean room while being transferred from one apparatus to the next apparatus being different for each substrate or lot.

For example, oxygen or nitrogen is an element that makes a part of an amorphous semiconductor layer n-type, and these elements increase the defect density in the amorphous semiconductor layer and reduce field effect mobility. Become. Furthermore, oxygen and nitrogen contained in the film may be one of the factors that cause variations in TFT electrical characteristics.

In particular, in the case of a film formation process performed under film formation conditions having a long film formation time, the amount of oxygen or nitrogen that enters the chamber also increases. For example, in the case of forming a microcrystalline silicon film, silane is formed by diluting with hydrogen to more than 100 times and 2,000 times or less, so the film formation speed is slow and it takes a long time to obtain a desired film thickness. . Oxygen is an impurity to be reduced particularly when a microcrystalline silicon film is formed because oxygen inhibits crystallization and may act as a donor when taken into the microcrystalline silicon film.

Therefore, it is necessary to highly purify the semiconductor film constituting the thin film transistor. The semiconductor film is formed in a vacuum chamber. At this time, unless the atmospheric component gases such as oxygen and nitrogen remaining in the vacuum chamber are reduced as much as possible, the residual gases are simultaneously taken in during the formation of the semiconductor film, so that it cannot be highly purified. The semiconductor for high purification of membrane, 1 × ¹⁰ -10 Torr the ultimate vacuum in the vacuum chamber from the ultra-high vacuum region (1 × ¹⁰ -7 Torr (about 1 × ¹⁰ -5 Pa or more 1 × 10 ^- It is conceivable to evacuate to the range of ⁸ Pa). For this purpose, the leakage of the vacuum chamber must be reduced as much as possible. Specifically, it is necessary to use a vacuum pump with a high exhaust speed by polishing the flange joint surface of the vacuum chamber with high accuracy and performing a process such as joining using a metal gasket.

However, as the size of the substrate increases, such as a large-area glass substrate for mass production of liquid crystal display devices, the vacuum chamber for depositing the semiconductor film also increases in size, corresponding to the ultra-high vacuum range. Manufacturing the vacuum chamber itself becomes difficult. Further, when the vacuum apparatus is maintained on the production line, the vacuum chamber must be inspected for leaks every time, and workability is deteriorated.

An object of the present invention is to provide a clean room in which variation in characteristics of a semiconductor device to be manufactured is reduced.

The material gas used for the amorphous semiconductor film and the microcrystalline semiconductor film is a special material gas having high reactivity. For example, silane gas is a dangerous gas that reacts with oxygen even if there is no ignition source. Another issue is a clean room configuration that improves the safety of a manufacturing apparatus that uses such a highly reactive special material gas.

Another object is to provide a method for forming a semiconductor film in which the oxygen concentration and the nitrogen concentration in the film are reduced.

Another object is to provide a method for manufacturing a semiconductor device using a semiconductor film with reduced oxygen concentration and nitrogen concentration.

Therefore, the vacuum chamber is installed in a room filled with a gas that does not adversely affect the semiconductor film so that oxygen gas and nitrogen gas as atmospheric components do not enter the vacuum chamber from the outside of the vacuum chamber.

Specifically, a first area surrounding the manufacturing apparatus and a second area surrounding the first area are separated by partitions in the clean room. And in order to reduce oxygen and nitrogen contained in the first area surrounding the manufacturing apparatus as much as possible, by filling with high-purity rare gas or hydrogen, the oxygen concentration and nitrogen concentration in the atmosphere are less than 1/100, preferably The inside of the manufacturing apparatus in which the object to be processed is arranged is kept clean even less than one thousandth.

In the structure of the invention disclosed in this specification, a manufacturing apparatus having a vacuum chamber is arranged, a first area surrounded by a first partition, and a rare gas or a hydrogen gas is supplied to the first area for circulation. A clean room having a gas circulation means, a second area surrounding the first area and surrounded by the second partition, and an air conditioning means for supplying and circulating air to the second area.

The present invention solves at least one of the above problems.

Examples of the rare gas include helium, neon, argon, xenon, and krypton. Among them, it is preferable to use argon, which is inexpensive. Argon gas is cheaper than other rare gases, but high-purity argon gas is expensive. Therefore, the maintenance cost is reduced by circulating the gas inside.

The first area and the second area circulate gas independently. In the first area, a high-purity rare gas or hydrogen is circulated. In the first area, a manufacturing apparatus sensitive to oxygen or nitrogen or a manufacturing apparatus used for a process sensitive to oxygen or nitrogen is installed. When the film forming chamber, the transfer chamber, the load chamber, the unload chamber, etc. of the manufacturing apparatus installed in the first area are opened to the atmosphere, the cleanliness in the first area is maintained using noble gas instead of nitrogen. By using the manufacturing apparatus installed in the first area that hardly contains oxygen or nitrogen, a clean room in which the characteristic variation of the semiconductor device to be manufactured is reduced can be realized.

In addition, by installing a manufacturing apparatus that handles highly reactive special material gas in the first area, the seal portion of the manufacturing apparatus deteriorates, and silane gas or the like flows out to the first area, or the first area is placed in the silane gas cylinder. Even if the gas flows backward, it will ignite and no fire will occur. Therefore, it is possible to realize a clean room that enhances the safety of a manufacturing apparatus that uses a highly reactive special material gas.

In the above configuration, the gas circulation means for supplying and circulating the rare gas or the hydrogen gas to the first area includes at least a rare gas cylinder or a hydrogen cylinder or a gas supply unit having a gas purifier and an exhaust unit. The oxygen concentration, nitrogen concentration, and water concentration in the first area are all 30 ppm or less, preferably 30 ppb or less. More preferably, the oxygen concentration, nitrogen concentration, and moisture concentration around the manufacturing apparatus in the first area are all less than about 1 ppt. The gas supplied into the first area can be measured by an oxygen analyzer for measuring the oxygen concentration and a nitrogen analyzer for measuring the nitrogen concentration.

For example, if a compressed gas cylinder of ultra high purity argon is used, a high purity gas of 99.9995 or more can be supplied to the first area. Further, if an ultra-high purity hydrogen purifier is used, 9N (99.9999999%) high-purity gas can be supplied to the first area. The oxygen concentration, nitrogen concentration, and water concentration around the manufacturing apparatus in the first area depend on the flow rate supplied to the first area, the gas purification method, the airtightness of the first partition, etc., but as much as possible. Use a clean room configuration that reduces the number of clean rooms.

The manufacturing apparatus having the vacuum chamber arranged in the first area includes a plasma CVD apparatus. When a plasma CVD apparatus preferably having a double chamber structure is used, the oxygen concentration and the nitrogen concentration in the semiconductor film to be formed can be effectively reduced. The double chamber structure refers to a structure having a second chamber that further surrounds the outside of the first chamber in which the substrate is disposed. In the second chamber, the atmosphere outside the first chamber is reduced in pressure. There are provided exhausting means for supplying rare gas or hydrogen gas to the atmosphere outside the first chamber.

The first area also includes a transport area from the end of processing at a certain device until the next device is loaded. By transporting in the first area that contains almost no oxygen or nitrogen, variation in characteristics is reduced even if the time exposed to the clean room during transport from one device to the next varies from substrate to substrate or from lot to lot. it can.

In the second area, clean air is circulated. Preferably, a clean room structure in which atmospheric components in the second area are partitioned by a material partition that does not enter the first area is adopted. For example, as the surface material of the partition, a steel plate, an aluminum plate, a stainless steel plate or the like is used, and it is used for a wall or ceiling surrounding the first area. In the above configuration, the first area is preferably divided by the first partition, and the first area is preferably adjusted to a positive pressure by the gas circulation means as compared with the second area. Furthermore, the second area is preferably divided into second partitions, and the first area is preferably adjusted to a positive pressure rather than an atmospheric pressure by air conditioning means.

A substrate to be processed is transported from outside the clean room, and the substrate is first loaded into the second area and mounted on an automatic transport device that moves within the second area. Move and transport to the load chamber of the manufacturing apparatus in the first area.

When rare gas diffuses from the first area to the second area through the gap, the oxygen concentration in the first area decreases, and the worker entering the second area may cause oxygen deficiency. Installs multiple oxygen concentration meters or nitrogen concentration meters that can confirm an oxygen concentration of 19% or more. In particular, if there is no sufficient seal structure near the door connecting the first area and the second area, specifically, the gap between the door and the wall, there is a risk that the rare gas will diffuse from the first area to the second area. is there.

When performing maintenance, the operator performs maintenance after exhausting the rare gas in the first area and replacing the inside of the first area with clean air. Alternatively, the worker wears a compressed oxygen circulation respirator and enters the first area to perform maintenance work and the like. The compressed oxygen circulation respirator is constructed so that after supplying oxygen to the wearer, the carbon dioxide in the exhaled breath is absorbed into a clean can, and the oxygen is returned to the breathing bag for reuse. Does not release oxygen, carbon dioxide or nitrogen.

In the above configuration, the air conditioning means for supplying and circulating air to the second area has at least a fan filter unit and an exhaust unit for exhausting the atmosphere to the outside. As a filter used for the fan filter unit, a high efficiency particulate air (HEPA) filter, an ultra low penetration air (ULPA) filter, or the like is used.

The cleanliness of the first area or the second area is defined by the number of fine particles having a size of 0.5 μm or more in 1 ft ³ (28.3 L) of air, and is class 1000 or less, preferably class 100 or less. To do. The cleanliness can be measured with a light scattering type automatic particle measuring instrument, a so-called particle counter.

Note that when plasma is generated in a vacuum chamber in which film formation is performed, the pressure in the vacuum chamber is preferably at least 2 × 10 ⁻² Torr (2.666 Pa) to 1 Torr (133.3 Pa). In addition, in order to reduce the residual oxygen, nitrogen, H ₂ O and other atmospheric component gases in the true chamber (reaction vessel) as much as possible before film formation, a high purity argon gas is allowed to flow around the chamber, A high-purity material gas is allowed to flow, and the substrate temperature during film formation is set to a range of 100 ° C. or higher and lower than 300 ° C.

Further, a film forming method is one of the inventions disclosed in this specification, and the invention includes a second area surrounding the first area by circulating a rare gas or a hydrogen gas in the first area where the plasma CVD apparatus is disposed. The substrate is transferred to the plasma CVD apparatus by an automatic transfer device that circulates the air that has passed through the fan filter unit and moves in the second area, and the substrate is placed in the vacuum chamber of the plasma CVD device. In this film forming method, plasma is generated by introducing a material gas to form a semiconductor film on a substrate.

In the film forming method, the first area in which the rare gas or the hydrogen gas is circulated is a positive pressure whose pressure is higher than the atmospheric pressure. In the film forming method, the oxygen concentration and the nitrogen concentration contained in the rare gas or the hydrogen gas are 30 ppm or less. Oxygen and nitrogen are elements that make part of the amorphous semiconductor layer n-type, and these elements increase the defect density in the amorphous semiconductor layer and cause a reduction in field-effect mobility. Furthermore, oxygen and nitrogen contained in the film may be one of the factors that cause variations in TFT electrical characteristics. For example, in the case of forming a microcrystalline silicon film, since the silane gas is formed by diluting with hydrogen to more than 100 times and 2,000 times or less, the film formation speed is slow and it takes a long time to obtain a desired film thickness. . Oxygen is an impurity to be reduced particularly when a microcrystalline silicon film is formed because oxygen inhibits crystallization and may act as a donor when taken into the microcrystalline silicon film. The above film formation method is particularly effective for a microcrystalline semiconductor film in which oxygen and nitrogen are easily incorporated into the film because the film formation rate is low and the time required to obtain a desired film thickness is long.

Note that in this specification, a microcrystalline semiconductor film is a film including a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). This semiconductor is a semiconductor having a third state which is stable in terms of free energy, and is a crystalline one having a short-range order and having a lattice strain, and has a columnar or needle shape with a particle size of 0.5 to 20 nm. Crystals grow in the normal direction with respect to the substrate surface. In addition, a microcrystalline semiconductor and a non-single-crystal semiconductor are mixed. Microcrystalline silicon which is a typical example of a microcrystalline semiconductor has its Raman spectrum shifted to a lower frequency side than 520.5 cm ⁻¹ indicating single crystal silicon. That is, the peak of the Raman spectrum of microcrystalline silicon is between 520.5 cm ⁻¹ representing single crystal silicon and 480 cm ⁻¹ representing amorphous silicon. In addition, at least 1 atomic% or more of hydrogen or halogen is contained to terminate dangling bonds (dangling bonds).

Note that the film quality of a semiconductor film such as an amorphous semiconductor film, a polycrystalline semiconductor film, or a compound semiconductor film can be significantly improved without being limited to the microcrystalline semiconductor film. For example, even when the time required to obtain a desired film thickness when the film thickness of the semiconductor film is increased, the film formation method can provide uniform film quality.

In this specification, a partition is a partition, for example, refers to a partition that inhibits contact between two different atmospheres and prevents gas from entering each atmosphere.

Conventionally, a vacuum chamber such as a film forming chamber and a transfer chamber connected to the film forming chamber is filled with nitrogen except when it is necessary to evacuate, but in the present invention, a noble gas or Vacuum replace with hydrogen. Vacuum replacement is one of the methods for maintaining cleanliness in a chamber into which gas is introduced after the chamber is evacuated.

Also, using a portable and sealable substrate transport container such as FOUP (Front Opening Unified Pod), the substrate is stored in the substrate transport container while maintaining a local clean space by the substrate transport container. By combining this method with the present invention, the oxygen concentration and nitrogen concentration in the chamber of the plasma CVD apparatus can be further reduced. The high-purity gas that is airtight in the substrate transfer container is not nitrogen but rare gas or hydrogen gas.

Further, a method for manufacturing a semiconductor device is one of the inventions disclosed in this specification, in which the gate electrode is formed over a substrate having an insulating surface, the insulating film is formed over the gate electrode, and the outside air is formed. A first area in which rare gas or hydrogen gas is circulated between the outer wall and the vacuum chamber outer wall is provided in contact with the outer wall of the vacuum chamber, and the first area is surrounded by the first partition to isolate the vacuum chamber and the second area. Further, the second area and the first area are surrounded by the second partition to isolate the outside air and the second area, a substrate provided with an insulating film is installed in the vacuum chamber, and a material gas is introduced into the vacuum chamber. Then, plasma is generated to form a microcrystalline semiconductor film over the insulating film, a buffer layer is formed over the microcrystalline semiconductor film, and the microcrystalline semiconductor film is formed by the first step near the interface with the buffer layer. Insulating area Than the second region near the interface of a method for manufacturing a semiconductor device for stepwise or continuously changing the deposition conditions such deposition speed increases.

Since the microcrystalline semiconductor film is oxidized when exposed to an atmosphere containing oxygen, it is preferable to prevent oxidation by stacking a buffer layer without opening to the atmosphere. Even when the microcrystalline semiconductor film and the buffer layer are formed in two chambers, respectively, if the two chambers are arranged in the first area, the oxygen concentration and the nitrogen concentration in the formed film are reduced. can do. A microcrystalline semiconductor film and a buffer layer can be sequentially stacked by adjusting a material gas in one chamber. For example, in the case where a microcrystalline silicon film is formed as the microcrystalline semiconductor film and an amorphous silicon film is formed as the buffer layer, the microcrystalline semiconductor film can be stacked by adjusting a flow ratio of silane gas and hydrogen gas. In the case of stacking in one chamber, the interface between the microcrystalline semiconductor film and the buffer layer can be extremely cleaned.

In addition to the above method for manufacturing a semiconductor device, a semiconductor film containing an n-type impurity element is formed over the buffer layer, a source electrode or a drain electrode is formed over the semiconductor film containing the n-type impurity element, and an n-type impurity is formed. A channel film type bottom gate is formed by etching a semiconductor film containing an element to form a source region and a drain region, leaving a region overlapping with the source region and the drain region, and removing a part of the buffer layer by etching. A thin film transistor is manufactured. These steps are also preferably performed in the first area.

By installing the vacuum chamber in a room filled with hydrogen or a rare gas so that gas of atmospheric components does not enter the vacuum chamber from the outside of the vacuum chamber, impurities in the semiconductor film (oxygen, which is an atmospheric component, Nitrogen) concentration can be reduced.

When the microcrystalline semiconductor film is formed, an atmospheric component gas such as oxygen or nitrogen does not act by isolating the vacuum chamber from the atmosphere, so that a microcrystalline semiconductor film with good crystallinity can be formed.

Further, even if the ultimate vacuum in the vacuum chamber is not set to the ultrahigh vacuum region, the characteristic variation of the semiconductor device to be manufactured is reduced by installing the first area filled with hydrogen or a rare gas in the clean room.

  Embodiments of the present invention will be described below.

(Embodiment 1) FIG. 1 is a sectional view showing an example of the configuration of a clean room of the present invention.

The first area 102 refers to a region surrounded by the first partition 101 and is filled with a rare gas supplied from the gas supply unit 105, here argon gas.

In the first area 102, a manufacturing apparatus, here, a plasma CVD apparatus 103 is installed on the grating floor 107a. The plasma CVD apparatus 103 is connected to the load chamber 106 via a gate valve.

The argon gas supplied from the gas supply unit 105 is blown by the first fan filter unit 104. The first fan filter unit 104 is installed in a separately provided partition. Argon gas is sent by the first fan filter unit 104 in the direction indicated by the dotted arrow in FIG. 1, passes through an opening provided in the grating floor 107 a, is sent downward, and then pushed upward. Then, it passes through the opening provided in the grating floor 107b, is sent along the side wall of the first partition 101, and passes through the first fan filter unit 104 again.

Further, in order to effectively use the argon gas, an exhaust unit 108 is provided outside the first area 102, and the introduced argon gas is circulated by supplying it to the gas supply unit 105.

By setting it as such a clean room structure, the cleanliness in the 1st area 102 is maintained. Note that the worker is prohibited from entering the first area where the oxygen concentration is low.

The first area 102 is further surrounded by a second partition 109. Between the second partition 109 and the first partition 101 is the second area 110, and clean air is blown. As shown in FIG. 1, the first area 102 is surrounded by the second area 110 in the horizontal direction. The first area 102 is also surrounded by the second area 110 in the vertical direction.

The second area 110 and the first area are circulated independently. In the second area 110, the air taken in from the outside of the second partition 109 is supplied to the second area 110 as clean air by the air conditioner 112 and is blown by the second fan filter unit 113. The clean air is sent in the direction indicated by the solid line arrow in FIG. 1 by the second fan filter unit 113, passes through the opening provided in the grating floor 107 c, is sent downward, and then pushed upward. Then, it passes through the opening provided in the grating floor 107d, is sent along the side wall of the second partition 109, and passes through the second fan filter unit 113 again. In addition, a path for supplying the air in the second area 110 to the air conditioner 112 is also provided and can be circulated.

By setting it as such a clean room structure, the cleanliness in the 2nd area 110 is maintained. Since the second area 110 is an atmospheric atmosphere, the worker can enter the second area 110.

The second area 110 is a space where an automatic transfer device 111 such as an AGV can move to transfer the substrate before and after processing. The automatic transfer device 111 in the second area 110 is designed so that the substrate can be transferred to the load chamber 106 in the first area 102.

A plastic case called FOUP may be used in place of the cassette so that the substrate is not exposed to the atmosphere when it is transported from one device to another. In the case of using FOUP, if a FOUP containing a plurality of substrates is filled with a rare gas or hydrogen and a FOUP opener mechanism is provided in the load chamber 106, a mechanism that automatically opens and is transported to a film forming chamber by a transfer robot; Become.

FIG. 2A illustrates an example of a top view of the clean room. Although FIG. 1 illustrates an example in which one first area is illustrated in the second area, when a semiconductor device is manufactured, a plurality of manufacturing apparatuses are arranged, and thus, as illustrated in FIG. A plurality of first areas are provided in the second area.

In this way, the first area 102 is made an argon atmosphere and the second area 110 is made a clean air atmosphere so that a film that is sensitive to oxygen, nitrogen, etc. contained in the air is arranged in the first area 102. Can be done with the device.

Further, when performing maintenance of the plasma CVD apparatus 103, the argon gas in the first area 102 is exhausted to the outside air by the exhaust unit 108 so that the worker enters the first area, and clean air from the air conditioner 112 is introduced. To do. Although not shown, a clean room configuration that can supply clean air from the air conditioner 112 to the first area is adopted. Note that the supply of argon gas from the gas supply unit 105 is stopped when performing maintenance.

Although not shown here, the auxiliary device is provided outside the first area or the second area. This auxiliary device refers to a device that assists the operation of the device installed in the first area or the second area. For example, when a device installed in the first area or the second area requires vacuum, an exhaust unit that performs vacuum exhaust from the device through a pipe, and when cooling is required, cools the device through a reciprocating pipe. When a heat exchange unit or device that circulates water discharges harmful substances to the human body, it takes in the harmful substances from the device through piping, changes them into harmless items, and discharges them outside the clean room. Examples include a waste liquid treatment facility for storing waste liquid.

Further, when a double chamber CVD apparatus is used as the plasma CVD apparatus, the oxygen concentration and the nitrogen concentration in the semiconductor film to be further formed can be effectively reduced.

FIG. 2B shows a top view of an example in which a double chamber CVD apparatus is disposed in the first area 102. FIG. 3 is a perspective view of a CVD apparatus having a double chamber structure.

The film formation apparatus shown in FIGS. 2 and 3 includes a film formation chamber and a transfer chamber, a transfer chamber 202b is disposed between the film formation chambers 204a and 204b, and the transfer chambers 202a and 202b are disposed adjacent to each other. It has a structure. Each film forming chamber is provided with ten chambers 208a and 208b arranged in the vertical direction, and each of the chambers 208a and 208b is supplied with a supply system 206a and 206b for supplying a film forming gas, and exhaust gas is exhausted. Exhaust systems 207a and 207b and power supplies 205a and 205b are provided.

  The film forming apparatus shown in FIGS. 2 and 3 is characterized in that in each of the film forming chambers 204a and 204b, all the supply systems of the plurality of chambers 208a and 208b are connected to one supply source. Similarly, all the exhaust systems of the plurality of chambers 208a and 208b are connected to one exhaust port. Due to this feature, in the film forming apparatus shown in FIGS. 2 and 3, the supply systems 206a and 206b and the exhaust systems 207a and 207b are simplified even though a plurality of chambers 208a and 208b are vertically stacked. Can be arranged. The film formation chambers 204a and 204b are provided with an exhaust system (not shown) for reducing the pressure in each film formation chamber. By controlling the pressure in the chamber and the pressure in the film formation chamber, film formation and cleaning in the chamber can be performed alternately, and film formation can be performed efficiently.

In film formation, plasma is generated in a state where the pressure in the chamber is lower than that in the film formation chamber. A small amount of the material gas supplied into the chamber flows outside the chamber. That is, it can be said that the chamber has a double structure. In the case of this double-structured chamber, the inner chamber has no seal portion and the outer wall of the outer film forming chamber has a seal portion for maintenance because the chamber 208a, 208b is sealed simply by contacting a metal plate. There is. Here, a bag body 209 is provided so as to cover the outside of all the film formation chambers, and separates the film formation chambers from the atmosphere. A rare gas or hydrogen gas containing almost no oxygen or nitrogen is supplied to the space 210 in the bag body 209.

  A material gas such as monosilane, disilane, or trisilane and a hydrogen gas are introduced as a source gas, and plasma is generated so that a microcrystalline semiconductor film can be directly formed over the substrate to be processed.

  In FIG. 2, a substrate having an insulating surface such as a glass substrate of a desired size is set in the load chamber 201a. 2 and 3 adopt horizontal transport as the substrate transport method. However, when using a meter angle substrate of the fifth generation or later, the substrate is vertically moved for the purpose of reducing the area occupied by the transporter. You may perform the vertical conveyance set.

  Each of the transfer chambers 202a and 202b is provided with transfer mechanisms (such as robot arms) 203a and 203b. The substrate set in the load chamber 201a is transferred to the film forming chambers 204a and 204b by the transfer mechanism. Then, in the chambers 208a and 208b of the film formation chambers 204a and 204b, predetermined processing is performed on the processing target surface of the transferred substrate. 2 and 3, a plurality of transfer chambers are provided, but one may be provided. The substrate after film formation is transferred to the unload chamber 201b.

  As shown in FIGS. 2 and 3, by forming a film with a film forming apparatus having a plurality of chambers, films formed under the same conditions on a large number of substrates can be formed at the same time. For this reason, it becomes possible to reduce the variation between substrates, and to improve a yield. In addition, throughput can be improved.

Further, by arranging a plurality of chambers in an argon atmosphere having a low oxygen concentration and a low nitrogen concentration formed by the first partition 101 and isolating them from the atmosphere, the chambers 208a and 208b have a long period of time. An increase in the concentration of atmospheric components can be prevented. Therefore, the plasma CVD apparatus arranged in the first area 102 shown in FIG. 2B can provide a uniform film formation over a long period of time compared to the conventional case.

2 and 3 show an example of a batch type plasma CVD apparatus, but the invention is not particularly limited, and the effects of the present invention can also be obtained as a single wafer type CVD apparatus that forms a substrate one by one.

(Embodiment 2)
In this embodiment, a manufacturing process of a thin film transistor used for a liquid crystal display device will be described with reference to FIGS. 4 to 6 are cross-sectional views illustrating a manufacturing process of a thin film transistor, and FIG. 7 is a top view of a connection region between a thin film transistor and a pixel electrode in one pixel. FIG. 8 is a timing chart showing a method for forming a microcrystalline silicon film.

A thin film transistor including a microcrystalline semiconductor film is more suitable for use in a driver circuit because an n-type thin film transistor has higher mobility than a p-type. In order to reduce the number of steps, it is desirable that all thin film transistors formed over the same substrate have the same polarity. Here, description is made using an n-channel thin film transistor.

  As shown in FIG. 4A, a gate electrode 51 is formed over the substrate 50. As the substrate 50, an alkali-free glass substrate manufactured by a fusion method or a float method such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass can be used. When the substrate 50 is mother glass, the size of the substrate is the first generation (320 mm × 400 mm), the second generation (400 mm × 500 mm), the third generation (550 mm × 650 mm), the fourth generation (680 mm × 880 mm, or 730mm x 920mm), 5th generation (1000mm x 1200mm or 1100mm x 1250mm), 6th generation 1500mm x 1800mm), 7th generation (1900mm x 2200mm), 8th generation (2160mm x 2460mm), 9th generation (2400mm x 2800 mm, 2450 mm × 3050 mm), 10th generation (2950 mm × 3400 mm), or the like can be used.

The gate electrode 51 is formed using a metal material such as titanium, molybdenum, chromium, tantalum, tungsten, or aluminum, or an alloy material thereof. The gate electrode 51 is formed by forming a conductive film on the substrate 50 by a sputtering method or a vacuum evaporation method, forming a mask on the conductive film by a photolithography technique or an inkjet method, and etching the conductive film using the mask. Can be formed. Alternatively, the gate electrode 51 can be formed by discharging and baking the conductive nanopaste of silver, gold, copper, or the like by an inkjet method. Note that a nitride film of the above metal material may be provided between the substrate 50 and the gate electrode 51 as a barrier metal that prevents adhesion to the gate electrode 51 and diffusion to the base. Here, the conductive film formed over the substrate 50 is etched using the resist mask formed using the first photomask to form the gate electrode.

As a specific example of the gate electrode structure, a molybdenum film may be stacked on an aluminum film to prevent a hillock or electromigration peculiar to aluminum. Alternatively, a three-layer structure in which an aluminum film is sandwiched between molybdenum films may be used. As another example of the gate electrode structure, a molybdenum film is laminated on a copper film, a titanium nitride film is laminated on the copper film, and a tantalum nitride film is laminated on the copper film.

  Note that since a semiconductor film or a wiring is formed over the gate electrode 51, it is desirable that the end portion be tapered so as to prevent disconnection. Although not shown, a wiring connected to the gate electrode can be formed at the same time in this step.

  Next, gate insulating films 52 a, 52 b, and 52 c are sequentially formed on the gate electrode 51. A cross-sectional view after the steps up to here corresponds to FIG.

Each of the gate insulating films 52a, 52b, and 52c can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film by a CVD method, a sputtering method, or the like. In order to prevent an interlayer short circuit due to a pinhole or the like formed in the gate insulating film, it is preferable to use multiple different insulating layers. Here, a mode in which a silicon nitride film, a silicon oxynitride film, and a silicon nitride film are stacked in this order as the gate insulating films 52a, 52b, and 52c is shown.

Here, the silicon oxynitride film has a composition that contains more oxygen than nitrogen and has a concentration range of 55 to 65 atomic%, 1 to 20 atomic%, and 25 Si. -35 atomic%, and hydrogen is contained in the range of 0.1-10 atomic%. The silicon nitride oxide film has a composition containing more nitrogen than oxygen, and the concentration ranges of oxygen are 15 to 30 atomic%, nitrogen is 20 to 35 atomic%, and Si is 25 to 25%. 35 atomic% and hydrogen are included in the range of 15 to 25 atomic%.

The film thicknesses of the first and second layers of the gate insulating film are both greater than 50 nm. The first layer of the gate insulating film is preferably a silicon nitride film or a silicon nitride oxide film in order to prevent diffusion of impurities (for example, alkali metal) from the substrate. The first layer of the gate insulating film can prevent hillocks when aluminum is used for the gate electrode, in addition to preventing oxidation of the gate electrode. The third layer of the gate insulating film in contact with the microcrystalline semiconductor film is thicker than 0 nm and 5 nm or less, preferably about 1 nm. The third layer of the gate insulating film is provided to improve adhesion with the microcrystalline semiconductor film. Further, when the third layer of the gate insulating film is a silicon nitride film, the microcrystalline semiconductor film can be prevented from being oxidized by heat treatment performed later. For example, when heat treatment is performed in a state where an insulating film containing a large amount of oxygen is in contact with a microcrystalline semiconductor film, the microcrystalline semiconductor film may be oxidized.

Furthermore, it is preferable to form the gate insulating film using a microwave plasma CVD apparatus having a frequency of 1 GHz. A silicon oxynitride film and a silicon nitride oxide film formed with a microwave plasma CVD apparatus have high withstand voltage and can improve the reliability of the thin film transistor.

Here, the gate insulating film has a three-layer structure, but when used as a switching element of a liquid crystal display device, only a single layer of a silicon nitride film may be used for AC driving.

Next, after the gate insulating film is formed, the substrate is transported without exposure to the air, and the microcrystalline semiconductor film 53 is preferably formed in a vacuum chamber different from the vacuum chamber in which the gate insulating film is formed.

In this embodiment mode, the microcrystalline semiconductor film 53 is formed using the film formation apparatus disposed in the first area of the clean room illustrated in FIG. By installing the film forming apparatus in a room filled with argon gas, the low oxygen concentration and the low nitrogen concentration in the film forming apparatus are maintained.

Hereinafter, a procedure for forming the microcrystalline semiconductor film 53 will be described with reference to FIG. The description of FIG. 8 is shown from the stage where the vacuum chamber is evacuated 1200 from the atmospheric pressure. The pre-coating 1201, substrate carry-in 1202, base pretreatment 1203, film formation treatment 1204, substrate carry-out 1205, and cleaning 1206 performed thereafter Each process is shown in time series. However, it is not limited to evacuating from atmospheric pressure, and it is preferable to keep the vacuum chamber at a certain degree of vacuum at all times for mass production, or for reducing the ultimate vacuum in a short time.

In the present embodiment, vacuum evacuation is performed in which the degree of vacuum in the vacuum chamber before carrying the substrate is in the range of 2 × 10 ⁻² Torr (2.666 Pa) to 1 Torr (133.3 Pa). This stage corresponds to the evacuation 1200 of FIG. In addition, the heater for heating the substrate is also operated to stabilize the temperature. The heating temperature of the substrate is 100 ° C to 300 ° C, preferably 120 ° C to 220 ° C.

Next, pre-coating 1201 is performed before the substrate is carried in, and a silicon film is formed as an inner wall coating film. As pre-coat 1201, after introducing hydrogen or a rare gas to generate plasma and removing gas (atmospheric components such as oxygen and nitrogen, or etching gas used for cleaning the vacuum chamber) attached to the inner wall of the vacuum chamber, Silane gas is introduced to generate plasma. Since silane gas reacts with oxygen, moisture, and the like, oxygen and moisture in the vacuum chamber can be removed by flowing silane gas and generating silane plasma. In addition, by performing the pre-coating 1201, it is possible to prevent the metal element of the member constituting the vacuum chamber from being taken into the microcrystalline silicon film as an impurity. That is, by covering the inside of the vacuum chamber with silicon, the inside of the vacuum chamber can be prevented from being etched by plasma, and the concentration of impurities contained in the microcrystalline silicon film to be formed later can be reduced. Can do. The precoat 1201 includes a process of coating the inner wall of the vacuum chamber with a film of the same type as the film to be deposited on the substrate.

Substrate carry-in 1202 is performed after the precoat 1201. Since the substrate on which the microcrystalline silicon film is to be deposited is stored in the evacuated load chamber, the degree of vacuum in the vacuum chamber does not deteriorate significantly even if the substrate is loaded.

Next, a base pretreatment 1203 is performed. The base pretreatment 1203 is preferably a particularly effective treatment in the case of forming a microcrystalline silicon film. That is, when a microcrystalline silicon film is formed by plasma CVD on the surface of a glass substrate, the surface of an insulating film or the surface of amorphous silicon, it is amorphous in the initial stage of deposition due to factors such as impurities and lattice mismatch. There is a risk that a quality layer will be formed. In order to reduce the thickness of the amorphous layer as much as possible and to eliminate it if possible, it is preferable to perform the base pretreatment 1203. The base pretreatment is preferably performed by rare gas plasma treatment, hydrogen plasma treatment, or a combination of both. As the rare gas plasma treatment, a rare gas element having a large mass number such as argon, krypton, or xenon is preferably used. This is because impurities such as oxygen, moisture, organic matter, and metal elements attached to the surface are removed by the sputtering effect. The hydrogen plasma treatment is effective for removing the impurities adsorbed on the surface by hydrogen radicals and forming a clean deposition surface by an etching action on the insulating film or the amorphous silicon film. In addition, the combination of rare gas plasma treatment and hydrogen plasma treatment promotes the promotion of microcrystal nucleation.

In terms of promoting the generation of microcrystalline nuclei, it is effective to continue supplying a rare gas such as argon at the initial stage of forming the microcrystalline silicon film, as indicated by a broken line 1207 in FIG.

Next, a film formation process 1204 for forming a microcrystalline silicon film is performed following the base pretreatment 1203. In this embodiment, a film in the vicinity of the gate insulating film interface is formed under a first film formation condition with a low film formation speed but good quality, and then changed to a second film formation condition with a high film formation speed. To deposit.

There is no particular limitation as long as the deposition rate under the second deposition condition is higher than the deposition rate under the first deposition condition. Therefore, it is formed by a high-frequency plasma CVD method having a frequency of several tens to several hundreds of MHz, or a microwave plasma CVD apparatus having a frequency of 1 GHz or more. Typically, silicon hydride such as SiH ₄ or Si ₂ H ₆ is used. A film can be formed by generating plasma by diluting with hydrogen. In addition to silicon hydride and hydrogen, the microcrystalline semiconductor film can be formed by dilution with one or more kinds of rare gas elements selected from helium, argon, krypton, and neon. The flow rate ratio of hydrogen to silicon hydride at these times is 12 to 1000 times, preferably 50 to 200 times, and more preferably 100 times. Note that SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like can be used instead of silicon hydride.

In addition, when helium is added to the material gas, helium has the highest ionization energy of all gases at 24.5 eV, and has a metastable state at a level of about 20 eV, which is slightly lower than the ionization energy. During the discharge duration, the difference requires only about 4 eV for ionization. Therefore, the discharge start voltage also shows the lowest value among all gases. From such characteristics, helium can maintain the plasma stably. In addition, since uniform plasma can be formed, the plasma density can be made uniform even when the area of the substrate on which the microcrystalline silicon film is deposited is increased.

In addition, carbon hydride such as CH ₄ and C ₂ H ₆ , germanium hydride such as GeH ₄ and GeF ₄ , and germanium fluoride are mixed in a gas such as silane, and the energy bandwidth is 1.5-2. It may be adjusted to .4 eV, or 0.9 to 1.1 eV. When carbon or germanium is added to silicon, the temperature characteristics of the TFT can be changed.

Here, the first film formation condition is that silane is diluted with hydrogen and / or rare gas to more than 100 times and less than 2000 times, and the heating temperature of the substrate is 100 ° C. to 300 ° C., preferably 120 ° C. to 220 ° C. To do. In order to inactivate the growth surface of the microcrystalline silicon film with hydrogen and promote the growth of the microcrystalline silicon, the film formation is preferably performed at 120 ° C. to 220 ° C.

FIG. 4B shows a cross-sectional view at the stage where the first film formation conditions are completed. On the gate insulating film 52c, a microcrystalline semiconductor film 23 having a low film formation speed but high quality is formed. Since the quality of the microcrystalline semiconductor film 23 obtained under the first film formation conditions contributes to an increase in on-current and field effect mobility of a TFT to be formed later, the clean room configuration shown in FIG. It is important to sufficiently reduce the oxygen concentration so that the oxygen concentration becomes 1 × 10 ¹⁷ / cm or less. In addition, since the concentration of not only oxygen but also nitrogen and carbon in the microcrystalline semiconductor film can be reduced by the clean room structure, the microcrystalline semiconductor film is prevented from becoming n-type. be able to.

Next, the microcrystalline semiconductor film 53 is formed by changing the second deposition condition to increase the deposition rate. A cross-sectional view at this stage corresponds to FIG. The thickness of the microcrystalline semiconductor film 53 may be 50 nm to 500 nm (preferably 100 nm to 250 nm). Note that in this embodiment, the film formation time of the microcrystalline semiconductor film 53 is formed in the first film formation period in which film formation is performed under the first film formation condition and in the second film formation condition. A second film formation period.

Here, the second film formation condition is that silane is diluted 12 to 100 times with hydrogen and / or rare gas, and the heating temperature of the substrate is 100 ° C. to 300 ° C., preferably 120 ° C. to 220 ° C. . A capacitively coupled (parallel plate type) CVD apparatus was used, the gap (distance between the electrode surface and the substrate surface) was 20 mm, the degree of vacuum in the vacuum chamber was 100 Pa, the substrate temperature was 300 ° C., and high frequency power of 60 MHz was applied. 20 W is added and silane gas (flow rate 8 sccm) is diluted 50 times with hydrogen (flow rate 400 sccm) to form a microcrystalline silicon film. Further, when the microcrystalline silicon film is formed by changing only the flow rate of the silane gas to 4 sccm and diluting 100 times under the above film forming conditions, the film forming speed is slowed down. The film formation rate is increased by fixing the hydrogen flow rate and increasing the silane flow rate. The crystallinity is improved by reducing the deposition rate.

In this embodiment, a capacitive coupling type (parallel plate type) CVD apparatus is used, the gap (distance between the electrode surface and the substrate surface) is set to 20 mm, the first film formation condition is set to a vacuum degree of 100 Pa in the vacuum chamber, Second deposition conditions for increasing the deposition rate by changing the gas flow rate, with a substrate temperature of 100 ° C., 30 W of high frequency power of 60 MHz applied, and silane gas (flow rate 2 sccm) diluted 200 times with hydrogen (flow rate 400 sccm) The film formation is performed under the condition of diluting 4 sccm of silane gas 100 times with hydrogen (flow rate 400 sccm).

Next, after film formation of microcrystalline silicon under the second film formation condition is completed, supply of a material gas such as silane and hydrogen and high-frequency power is stopped, and substrate unloading 1205 is performed. When the film formation process is subsequently performed on the next substrate, the process returns to the substrate carry-in 1202 and the same process is performed. Cleaning 1206 is performed in order to remove the film and powder attached to the vacuum chamber.

The cleaning 1206 performs plasma etching by introducing an etching gas typified by NF ₃ and SF ₆ . Further, the etching is performed by introducing a gas such as ClF ₃ that can be etched without using plasma. The cleaning 1206 is preferably performed by turning off the heater for heating the substrate and lowering the temperature. This is to suppress generation of reaction by-products due to etching. After the cleaning 1206 is completed, the process returns to the precoat 1201 and the same processing as described above may be performed on the next substrate. Since NF ₃ contains nitrogen in its composition, it is desirable to sufficiently reduce the nitrogen concentration by pre-coating in order to reduce the nitrogen concentration in the film formation chamber.

Next, after the microcrystalline semiconductor film 53 is formed, the buffer layer 54 is preferably formed in a vacuum chamber different from the vacuum chamber in which the microcrystalline semiconductor film 53 is formed by transporting the substrate without exposure to the air. . By separating the buffer layer 54 from the vacuum chamber, impurity contamination can be suppressed as much as possible. In addition, by using separate vacuum chambers, the frequency of the high-frequency power can be varied according to the film quality to be obtained.

The buffer layer 54 is formed using an amorphous semiconductor film containing hydrogen or halogen. An amorphous semiconductor film containing hydrogen can be formed using hydrogen at a flow rate of 1 to 10 times, more preferably 1 to 5 times the flow rate of silicon hydride. Further, by using the silicon hydride and a gas containing fluorine, chlorine, bromine, or iodine (F ₂ , Cl ₂ , Br ₂ , I ₂ , HF, HCl, HBr, HI, or the like), fluorine, chlorine, An amorphous semiconductor film containing bromine or iodine can be formed. Note that SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like can be used instead of silicon hydride.

The buffer layer 54 can be formed using an amorphous semiconductor as a target by sputtering with hydrogen or a rare gas to form an amorphous semiconductor film. In addition, by containing a gas containing fluorine, chlorine, bromine, or iodine (F ₂ , Cl ₂ , Br ₂ , I ₂ , HF, HCl, HBr, HI, etc.) in the atmosphere, fluorine, chlorine, bromine, Alternatively, an amorphous semiconductor film containing iodine can be formed.

The buffer layer 54 is preferably formed using an amorphous semiconductor film that does not include crystal grains. For this reason, when forming by a high frequency plasma CVD method or a microwave plasma CVD method with a frequency of several tens to several hundreds of MHz, the film formation conditions are controlled so that the amorphous semiconductor film does not contain crystal grains. It is preferable to do.

The buffer layer 54 is partially etched in a later formation process of the source region and the drain region. At that time, it is preferable to form the buffer layer 54 so that part of the buffer layer 54 remains so that the microcrystalline semiconductor film 53 is not exposed. Typically, it is preferably formed with a thickness of 100 nm to 400 nm, preferably 200 nm to 300 nm. In a display device with a high applied voltage of the thin film transistor (for example, about 15 V), typically a liquid crystal display device, when the buffer layer 54 is formed thick as shown in the above range, the withstand voltage increases, and a high voltage is applied to the thin film transistor. Even if it is applied, deterioration of the thin film transistor can be avoided.

Note that an impurity imparting one conductivity type, such as phosphorus or boron, is not added to the buffer layer 54. The buffer layer 54 functions as a barrier layer so that the impurity imparting one conductivity type does not diffuse into the microcrystalline semiconductor film 53 from the semiconductor film 55 to which the impurity imparting one conductivity type is added. In the case where the buffer layer is not provided, when the microcrystalline semiconductor film 53 is in contact with the semiconductor film 55 to which an impurity imparting one conductivity type is added, the impurity moves due to a later etching process or heat treatment, and the threshold value Control can be difficult.

Further, by forming the buffer layer 54 on the surface of the microcrystalline semiconductor film 53, natural oxidation of the surface of crystal grains included in the microcrystalline semiconductor film 53 can be prevented. In particular, in a region where an amorphous semiconductor is in contact with microcrystalline grains, cracks are likely to occur due to local stress. When the cracks come into contact with oxygen, the crystal grains are oxidized and silicon oxide is formed.

The energy gap of the buffer layer 54 which is an amorphous semiconductor film is larger than that of the microcrystalline semiconductor film 53 (the energy gap of the amorphous semiconductor film is 1.1 to 1.5 eV, and the energy gap of the microcrystalline semiconductor film 53 is 1.6 to 1.8 eV), high resistance, low mobility, and 1/5 to 1/10 that of the microcrystalline semiconductor film 53. Therefore, in a thin film transistor to be formed later, a buffer layer formed between the source and drain regions and the microcrystalline semiconductor film 53 functions as a high resistance region, and the microcrystalline semiconductor film 53 functions as a channel formation region. To do. Therefore, off current of the thin film transistor can be reduced. When the thin film transistor is used as a switching element of a display device, the contrast of the display device can be improved.

Note that the buffer layer 54 is preferably formed over the microcrystalline semiconductor film 53 at a temperature of 300 ° C. to 400 ° C. by a plasma CVD method. By this deposition treatment, hydrogen is supplied to the microcrystalline semiconductor film 53, and an effect equivalent to that obtained by hydrogenating the microcrystalline semiconductor film 53 is obtained. That is, by depositing the buffer layer 54 over the microcrystalline semiconductor film 53, hydrogen can be diffused into the microcrystalline semiconductor film 53 to terminate dangling bonds.

Next, after the buffer layer 54 is formed, the substrate is transported without being exposed to the atmosphere, and a semiconductor film 55 to which an impurity imparting one conductivity type is added in a vacuum chamber different from the vacuum chamber in which the buffer layer 54 is formed is added. It is preferable to form a film. A cross-sectional view at this stage corresponds to FIG. An impurity imparting one conductivity type is mixed during the formation of the buffer layer by depositing the semiconductor film 55 to which an impurity imparting one conductivity type is added in a vacuum chamber different from the vacuum chamber in which the buffer layer 54 is deposited. You can avoid it.

The semiconductor film 55 to which an impurity imparting one conductivity type is added may be formed by adding phosphorus as a typical impurity element when an n-channel thin film transistor is formed. Impurities such as PH ₃ are added to silicon hydride. Add gas. In the case of forming a p-channel thin film transistor, boron may be added as a typical impurity element, and an impurity gas such as B ₂ H ₆ may be added to silicon hydride. The semiconductor film 55 to which an impurity imparting one conductivity type is added can be formed using a microcrystalline semiconductor or an amorphous semiconductor. The semiconductor film 55 to which an impurity imparting one conductivity type is added is formed with a thickness of 2 nm to 50 nm. By reducing the thickness of the semiconductor film to which an impurity imparting one conductivity type is added, throughput can be improved.

Next, as illustrated in FIG. 5A, a resist mask 56 is formed over the semiconductor film 55 to which an impurity imparting one conductivity type is added. The resist mask 56 is formed by a photolithography technique or an inkjet method. Here, the resist applied to the semiconductor film 55 to which an impurity imparting one conductivity type is added is exposed and developed using the second photomask, so that the resist mask 56 is formed.

Next, the microcrystalline semiconductor film 53, the buffer layer 54, and the semiconductor film 55 to which an impurity imparting conductivity is added are etched and separated using a resist mask 56, and as illustrated in FIG. A crystalline semiconductor film 61, a buffer layer 62, and a semiconductor film 63 to which an impurity imparting one conductivity type is added are formed. Thereafter, the resist mask 56 is removed.

Since the side surfaces of the end portions of the microcrystalline semiconductor film 61 and the buffer layer 62 are inclined, leakage current is prevented from being generated between the source region and the drain region formed over the buffer layer 62 and the microcrystalline semiconductor film 61. Is possible. In addition, leakage current can be prevented from being generated between the source and drain electrodes and the microcrystalline semiconductor film 61. The inclination angles of the side surfaces of the end portions of the microcrystalline semiconductor film 61 and the buffer layer 62 are 90 ° to 30 °, preferably 80 ° to 45 °. With such an angle, disconnection of the source electrode or drain electrode due to the step shape can be prevented.

Next, as illustrated in FIG. 5C, conductive films 65a to 65c are formed so as to cover the semiconductor film 63 to which the impurity imparting one conductivity type is added and the gate insulating film 52c. The conductive films 65a to 65c are preferably formed using a single layer or a stacked layer of aluminum or an aluminum alloy to which a heat resistance improving element such as copper, silicon, titanium, neodymium, scandium, or molybdenum or a hillock preventing element is added. In addition, a film in contact with a semiconductor film to which an impurity imparting one conductivity type is added is formed using titanium, tantalum, molybdenum, tungsten, or a nitride of these elements, and aluminum or an aluminum alloy is formed thereover. It is good also as a laminated structure. Furthermore, a laminated structure in which the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched between titanium, tantalum, molybdenum, tungsten, or nitrides of these elements may be employed. Here, a conductive film having a structure in which conductive films 65a to 65c3 are stacked is shown as the conductive film. 65c shows a laminated conductive film using a titanium film and a conductive film 65b using an aluminum film. The conductive films 65a to 65c are formed by a sputtering method or a vacuum evaporation method.

Next, as illustrated in FIG. 5D, a resist mask 66 is formed over the conductive films 65a to 65c using a third photomask, and part of the conductive films 65a to 65c is etched to form a pair of sources. Electrodes and drain electrodes 71a to 71c are formed. When the conductive films 65a to 65c are wet-etched, the ends of the conductive films 65a to 65c are selectively etched. As a result, source and drain electrodes 71 a to 71 c having a smaller area than the resist mask 66 can be formed.

Next, as illustrated in FIG. 6A, the semiconductor film 63 to which an impurity imparting one conductivity type is added is etched using a resist mask 66, so that a pair of source and drain regions 72 is formed. Further, part of the buffer layer 62 is also etched in the etching step. A buffer layer that is partially etched and has a depression (groove) is referred to as a buffer layer 73. The step of forming the source region and the drain region and the depression (groove) of the buffer layer can be formed in the same step. Since the depth of the recess (groove) of the buffer layer is 1/2 to 1/3 of the thickest region of the buffer layer, the distance between the source region and the drain region can be increased. Leakage current between the source region and the drain region can be reduced. Thereafter, the resist mask 66 is removed.

In particular, when exposed to plasma used in dry etching or the like, the resist mask changes in quality, and is not completely removed in the resist removing process, and the buffer layer is etched by about 50 nm in order to prevent residues from remaining. The resist mask 66 is used twice for the etching process for a part of the conductive films 65a to 65c and the etching process for forming the source region and the drain region 72. Therefore, it is effective to increase the thickness of the buffer layer that may be etched when the residue is completely removed. In addition, the buffer layer 73 can prevent plasma damage from being given to the microcrystalline semiconductor film 61 during dry etching.

Next, as illustrated in FIG. 6B, an insulating film 76 covering the source and drain electrodes 71a to 71c, the source and drain regions 72, the buffer layer 73, the microcrystalline semiconductor film 61, and the gate insulating film 52c is formed. Form. The insulating film 76 can be formed using the same film formation method as the gate insulating films 52a, 52b, and 52c. Note that the insulating film 76 is for preventing entry of contaminant impurities such as organic substances, metal substances, and water vapor floating in the air, and is preferably a dense film. In addition, by using a silicon nitride film for the insulating film 76, the oxygen concentration in the buffer layer 87 can be set to 5 × 10 ¹⁹ atoms / cm ³ or lower, preferably 1 × 10 ¹⁹ atoms / cm ³ or lower.

As shown in FIG. 6B, the end portions of the source and drain electrodes 71a to 71c and the end portions of the source region and the drain region 72 are not coincident with each other. Since the end portions 71 to 71c are separated from each other, a leakage current and a short circuit between the source electrode and the drain electrode can be prevented. In addition, since the end portions of the source and drain electrodes 71a to 71c and the end portions of the source and drain regions 72 are not aligned and shifted, the source and drain electrodes 71a to 71c and the source and drain regions 72 are not aligned. As a result, the electric field is not concentrated at the end of the gate electrode, and leakage current between the gate electrode 51 and the source and drain electrodes 71a to 71c can be prevented. Therefore, a thin film transistor with high reliability and high withstand voltage can be manufactured.

  Through the above process, the thin film transistor 74 can be formed.

In the thin film transistor described in this embodiment, a gate insulating film, a microcrystalline semiconductor film, a buffer layer, a source region and a drain region, a source electrode and a drain electrode are stacked over a gate electrode, and the microcrystalline semiconductor film functions as a channel formation region A buffer layer covers the surface. Further, a depression (groove) is formed in a part of the buffer layer, and a region other than the depression is covered with the source region and the drain region. In other words, since the distance between the source region and the drain region is increased due to the depression formed in the buffer layer, leakage current between the source region and the drain region can be reduced. Further, since the depression is formed by etching a part of the buffer layer, the etching residue generated in the step of forming the source region and the drain region can be removed, so that the leakage to the source region and the drain region through the residue. Generation of a current (parasitic channel) can be avoided.

In addition, a buffer layer is formed between the microcrystalline semiconductor film functioning as a channel formation region and the source and drain regions. In addition, the surface of the microcrystalline semiconductor film is covered with a buffer layer. Since the high-resistance buffer layer extends between the microcrystalline semiconductor film and the source and drain regions, leakage current can be reduced in the thin film transistor and high voltage can be applied. It is possible to reduce deterioration due to. Further, the buffer layer, the microcrystalline semiconductor film, the source region, and the drain region are all formed over a region overlapping with the gate electrode. Therefore, it can be said that the structure is not affected by the end shape of the gate electrode. When the gate electrode has a laminated structure, if aluminum is used as the lower layer, aluminum may be exposed on the side surface of the gate electrode and hillocks may be generated, but the source region and the drain region do not overlap the gate electrode end. By doing so, it is possible to prevent a short circuit from occurring in a region overlapping with the side surface of the gate electrode. Further, since the amorphous semiconductor film whose surface is terminated with hydrogen is formed as a buffer layer on the surface of the microcrystalline semiconductor film, the microcrystalline semiconductor film can be prevented from being oxidized, and the source region and Etching residues generated in the drain region formation step can be prevented from entering the microcrystalline semiconductor film. Therefore, the thin film transistor has excellent electrical characteristics and excellent withstand voltage.

In addition, the channel length of the thin film transistor can be shortened, and the planar area of the thin film transistor can be reduced.

Next, a part of the insulating film 76 is etched using a resist mask formed using a fourth photomask for the insulating film 76 to form a contact hole. The contact hole is in contact with the source or drain electrode 71c. A pixel electrode 77 is formed. Note that FIG. 6C corresponds to a cross-sectional view taken along dashed line AB in FIG.

As shown in FIG. 7, it can be seen that the ends of the source and drain regions 72 are located outside the ends of the source and drain electrodes 71c. Further, the end portion of the buffer layer 73 is located outside the end portions of the source and drain electrodes 71 c and the source and drain regions 72. One of the source electrode and the drain electrode has a shape (specifically, a U shape or a C shape) surrounding the other of the source region and the drain region. Therefore, the area of the region where carriers move can be increased, so that the amount of current can be increased and the area of the thin film transistor can be reduced. In addition, since the microcrystalline semiconductor film, the source electrode, and the drain electrode are overlapped over the gate electrode, the influence of the unevenness of the gate electrode is small, so that coverage can be reduced and generation of leakage current can be suppressed. Note that one of the source electrode and the drain electrode also functions as a source wiring or a drain wiring.

The pixel electrode 77 includes indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, and indium zinc oxide. Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used.

The pixel electrode 77 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds thereof can be given.

Here, as the pixel electrode 77, an indium tin oxide film is formed by a sputtering method, and then a resist is applied on the indium tin oxide film. Next, the resist is exposed and developed using a fifth photomask to form a resist mask. Next, the pixel electrode 77 is formed by etching the indium tin oxide film using a resist mask.

Through the above steps, an element substrate that can be used for a display device can be formed.

(Embodiment 3)
In this embodiment, before carrying the substrate into the vacuum chamber, hydrogen or a rare gas is introduced to generate plasma to use for gas (atmospheric components such as oxygen and nitrogen, or cleaning of the vacuum chamber) attached to the inner wall of the vacuum chamber In this example, hydrogen, silane gas, and a small amount of phosphine (PH ₃ ) gas are introduced after the etching gas is removed. Since only some of the steps are different from the second embodiment, only the different steps will be described below in detail with reference to FIG. In FIG. 9, the same reference numerals are used for the same portions as those in the second embodiment.

First, a gate electrode is formed over a substrate 350 as in the second embodiment. Here, a non-alkali glass substrate having a size of 600 mm × 720 mm is used. In this example, a display device having a large display screen is manufactured using a large-area substrate, and thus the first conductive layer 351a made of aluminum having low electric resistance and heat resistance higher than those of the first conductive layer 351a are used. A gate electrode in which a second conductive layer 351b made of highly molybdenum is stacked is used.

  Next, a gate insulating film 352 is formed over the second conductive layer 351b which is an upper layer of the gate electrode. When used for a switching element of a liquid crystal display device, the gate insulating film 352 is preferably only a single layer of a silicon nitride film in order to drive with alternating current. Here, as the gate insulating film 352, a single-layer silicon nitride film (dielectric constant: 7.0, thickness: 300 nm) is formed by a plasma CVD method. A cross-sectional view after the steps up to here corresponds to FIG.

Next, after the gate insulating film is formed, the substrate is transferred without being exposed to the air, and a microcrystalline semiconductor film is formed in a vacuum chamber different from the vacuum chamber in which the gate insulating film is formed. In this embodiment, a microcrystalline semiconductor film is formed using the plasma CVD apparatus 103 installed in the first area in the clean room illustrated in FIG.

Before the substrate is carried into the vacuum chamber of the plasma CVD apparatus 103 shown in FIG. 1, hydrogen or a rare gas is introduced to generate plasma (atmospheric components such as oxygen and nitrogen, or oxygen components attached to the inner wall of the vacuum chamber, or After removing the etching gas used for cleaning the vacuum chamber, hydrogen, silane gas, and a small amount of phosphine (PH ₃ ) gas are introduced. Silane gas can be reacted with oxygen, moisture, etc. in a vacuum chamber. A small amount of phosphine gas can contain phosphorus in a microcrystalline semiconductor film to be formed later.

Next, after the substrate is carried into a vacuum chamber and exposed to silane gas and a small amount of phosphine gas as shown in FIG. 9B, a microcrystalline semiconductor film is formed. The microcrystalline semiconductor film can be typically formed by diluting silicon hydride such as SiH ₄ or Si ₂ H ₆ with hydrogen to generate plasma. The microcrystalline semiconductor film 353 containing phosphorus and hydrogen can be formed using hydrogen with a flow rate greater than 100 times and less than 2000 times the flow rate of silane gas. By exposure to a small amount of phosphine gas, generation of crystal nuclei is promoted, and a microcrystalline semiconductor film 353 is formed. This microcrystalline semiconductor film 353 exhibits a concentration profile in which the concentration of phosphorus decreases as the distance away from the gate insulating film interface increases.

Next, the film formation conditions are changed in the same chamber, and hydrogen is used at a flow rate of 1 to 10 times, more preferably 1 to 5 times the flow rate of silicon hydride. A buffer layer 54 is stacked. A cross-sectional view after the steps up to here corresponds to FIG.

Next, after forming the buffer layer 54, the substrate is transferred without being exposed to the air, and an impurity imparting one conductivity type is formed in a vacuum chamber different from the vacuum chamber in which the microcrystalline semiconductor film 353 and the buffer layer 54 are formed. The added semiconductor film 55 is formed. Since the steps after the formation of the semiconductor film 55 are the same as those in the second embodiment, a detailed description thereof is omitted here.

This embodiment can be freely combined with Embodiment 1 or Embodiment 2.

(Embodiment 4)
In Embodiments 2 and 3, an example in which a microcrystalline semiconductor film and a buffer layer are stacked is described. However, a film formation apparatus installed in the first area is not limited to a microcrystalline semiconductor film but an amorphous film. The semiconductor film can also obtain excellent film quality. In this embodiment mode, an example in which a single layer of an amorphous silicon film is used as an active layer is shown in FIG.

As in Embodiment Mode 3, a gate electrode is formed over the substrate 450. A gate electrode is formed by stacking a first conductive layer 451a made of aluminum with low electric resistance and a second conductive layer 451b made of molybdenum nitride having higher heat resistance than the first conductive layer 451a.

  Next, as in Embodiment 3, a gate insulating film 452 made of a silicon nitride film is formed over the second conductive layer 451b which is an upper layer of the gate electrode.

Next, after the gate insulating film is formed, the substrate is transferred without being exposed to the air, and an amorphous semiconductor film is formed in a vacuum chamber different from the vacuum chamber in which the gate insulating film is formed. In this embodiment mode, an amorphous semiconductor film is formed using the plasma CVD apparatus 103 with the clean room structure illustrated in FIG.

Here, cleaning is performed using NF ₃ , SF _3, or ClF ₃ before film formation, and the amorphous semiconductor film is intentionally included with a halogen such as chlorine or fluorine. The amorphous silicon film can be typically formed by generating plasma by diluting silicon hydride such as SiH ₄ or Si ₂ H ₆ with hydrogen. An amorphous silicon film containing halogen and hydrogen can be formed using hydrogen at a flow rate of 1 to 10 times, more preferably 1 to 5 times the flow rate of silicon hydride. The pressure in the vacuum chamber during film formation is at least in the range of 2 × 10 ⁻² Torr (2.666 Pa) to 1 Torr (133.3 Pa). The plasma CVD apparatus 103 shown in FIG. 1 can sufficiently reduce the concentration of atmospheric components such as oxygen and nitrogen mixed in the amorphous silicon film. The amorphous silicon film 473 exhibits a concentration profile in which the halogen concentration decreases as the distance away from the gate insulating film interface increases. Including halogen at the interface of the gate insulating film of the amorphous silicon film is effective because dangling bonds (dangling bonds) in the amorphous silicon film can be terminated.

Next, after the amorphous silicon film 473 is formed, the substrate is transferred without being exposed to the atmosphere, and an impurity imparting one conductivity type is added in a vacuum chamber different from the vacuum chamber in which the amorphous silicon film is formed. The formed semiconductor film 472 is formed.

Next, a resist mask is formed over the semiconductor film to which an impurity imparting one conductivity type is added. Using the resist mask, the amorphous silicon film 473 and the semiconductor film 472 to which an impurity imparting conductivity is added are etched and separated. Thereafter, the resist mask is removed.

Next, a conductive film is formed so as to cover the semiconductor film 472 to which an impurity imparting one conductivity type is added and the gate insulating film 452. Here, the conductive film is a conductive film having a structure in which three conductive films are stacked. Specifically, a molybdenum film is used as the first conductive film, a molybdenum film is used as the third conductive film, and an aluminum film is used as the second conductive film. A three-layer conductive film to be used is shown. The three-layer conductive film is formed by a sputtering method or a vacuum evaporation method.

Next, a resist mask is formed over the three-layer conductive film, and part of the three-layer conductive film is etched to form the pair of source and drain electrodes 471a to 471c. Next, the semiconductor film 472 to which an impurity imparting one conductivity type is added is etched using a resist mask, so that a pair of source and drain regions is formed. Further, in the etching step, part of the amorphous silicon film 473 is also etched by about 50 nm. FIG. 10 shows an amorphous silicon film 473 that is partially etched and has depressions (grooves) formed therein.

Next, an insulating film 476 that covers the source and drain electrodes 471a to 471c and the gate insulating film 52 is formed. The insulating film 476 can be formed using the same film formation method as the gate insulating film 452. Note that the insulating film 476 is for preventing entry of contaminant impurities such as organic substances, metal substances, and water vapor floating in the air, and is preferably a dense film. In addition, by using a silicon nitride film for the insulating film 476, the oxygen concentration in the amorphous silicon film 473 is set to 5 × 10 ¹⁹ atoms / cm ³ or less, preferably 1 × 10 ¹⁹ atoms / cm ³ or less. it can.

  Through the above process, the thin film transistor 74 illustrated in FIG. 10 can be formed.

In the thin film transistor described in this embodiment, a gate insulating film, an amorphous silicon film, a source region and a drain region, a source electrode and a drain electrode are stacked over a gate electrode. A depression (groove) is formed in a part of the amorphous silicon film, and regions other than the depression are covered with the source region and the drain region. That is, since the distance between the source region and the drain region is increased due to the depression formed in the amorphous silicon film, the leakage current between the source region and the drain region can be reduced. Further, since the depression is formed by etching a part of the amorphous silicon film, the etching residue generated in the step of forming the source region and the drain region can be removed. Generation of a leakage current (parasitic channel) in the region can be avoided.

Next, a planarization film 82 is formed over the insulating film 476. The planarization film 482 is formed using an organic resin film. Next, part of the insulating film 476 and the planarization film 482 are etched using a resist mask to form a contact hole, and a pixel electrode 477 in contact with the source or drain electrode 471c is formed in the contact hole.

Through the above steps, an element substrate that can be used for a display device can be formed. Note that although an example in which the planarization film 482 is provided is described in this embodiment mode, the present invention is not particularly limited.

This embodiment mode can be freely combined with Embodiment Modes 1 to 3.

(Embodiment 5)
A method for manufacturing a thin film transistor, which is different from that in Embodiment 2, will be described with reference to FIGS. Here, a process for manufacturing a thin film transistor using a process capable of reducing the number of photomasks as compared to Embodiment Mode 2 is described.

4A shown in Embodiment Mode 2, a conductive film is formed over the substrate 50, a resist is applied over the conductive film, and the resist is formed by a photolithography process using a first photomask. A part of the conductive film is etched using the mask to form the gate electrode 51. Next, gate insulating films 52 a, 52 b, and 52 c are sequentially formed on the gate electrode 51.

Next, as in FIG. 4B described in Embodiment Mode 2, the microcrystalline semiconductor film 53 is formed using the plasma CVD apparatus illustrated in FIG. Subsequently, film formation is performed in the same chamber under the second film formation condition, so that a microcrystalline semiconductor film 53 is formed as in FIG. 4C described in Embodiment Mode 2. Next, as in FIG. 4D described in Embodiment Mode 2, a buffer layer 54 and a semiconductor film 55 to which an impurity imparting one conductivity type is added are formed over the microcrystalline semiconductor film 53 in order.

Next, conductive films 65 a to 65 c are formed over the semiconductor film 55 to which an impurity imparting one conductivity type is added. Next, as shown in FIG. 12A, a resist 80 is applied over the conductive film 65a.

As the resist 80, a positive resist or a negative resist can be used. Here, a positive resist is used.

Next, the resist 80 is exposed to light by irradiating the resist 80 with light using the multi-tone mask 59 as a second photomask.

Here, exposure using the multi-tone mask 59 will be described with reference to FIG.

  A multi-tone mask is a mask capable of performing three exposure levels on an exposed portion, an intermediate exposed portion, and an unexposed portion, and a plurality of (typically two types) can be obtained by one exposure and development process. It is possible to form a resist mask having a region with a thickness of. Therefore, the number of photomasks can be reduced by using a multi-tone mask.

Typical examples of the multi-tone mask include a gray-tone mask 59a as shown in FIG. 11A and a half-tone mask 59b as shown in FIG.

As shown in FIG. 11A, the gray tone mask 59a includes a light-transmitting substrate 163, a light shielding portion 164 and a diffraction grating 165 formed thereon. In the light shielding portion 164, the amount of light transmitted is 100%. On the other hand, the diffraction grating 165 can control the amount of transmitted light by setting the interval between the light transmitting portions such as slits, dots, and meshes to be equal to or less than the resolution limit of the light used for exposure. Note that the diffraction grating 165 can use either a periodic slit, a dot, or a mesh, or an aperiodic slit, dot, or mesh.

As the substrate 163 having a light-transmitting property, a substrate having a light-transmitting property such as quartz can be used. The light shielding portion 164 and the diffraction grating 165 can be formed using a light shielding material that absorbs light such as chromium or chromium oxide.

When the gray-tone mask 59a is irradiated with exposure light, as shown in FIG. 11B, the light transmission amount 166 is 0% in the light shielding portion 164, and the light shielding portion 164 and the diffraction grating 165 are not provided. In the region, the light transmission amount 166 is 100%. The diffraction grating 165 can be adjusted in the range of 10 to 70%. The light transmission amount in the diffraction grating 165 can be adjusted by adjusting the interval and pitch of slits, dots, or meshes of the diffraction grating.

As shown in FIG. 11C, the halftone mask 59b includes a light-transmitting substrate 163, a semi-transmissive portion 167 and a light-shielding portion 168 formed thereon. For the semi-transmissive portion 167, MoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like can be used. The light shielding portion 168 can be formed using a light shielding material that absorbs light, such as chromium or chromium oxide.

When the halftone mask 59b is irradiated with exposure light, as shown in FIG. 11D, in the light shielding portion 168, the light transmission amount 169 is 0%, and the light shielding portion 168 and the semi-transmissive portion 167 are provided. In the absence region, the light transmission amount 169 is 100%. Moreover, in the semi-transmissive part 167, it can adjust in 10 to 70% of range. The amount of light transmitted through the semi-transmissive portion 167 can be adjusted by adjusting the material of the semi-transmissive portion 167.

By developing after exposure using a multi-tone mask, a resist mask 81 having regions with different thicknesses can be formed as shown in FIG.

Next, using the resist mask 81 as a mask, the microcrystalline semiconductor film 53, the buffer layer 54, the semiconductor film 55 to which an impurity imparting one conductivity type is added, and the conductive films 65a to 65c are etched and separated. As a result, as shown in FIG. 13A, a microcrystalline semiconductor film 61, a buffer layer 62, a semiconductor film 63 to which an impurity imparting one conductivity type is added, and conductive films 85a to 85c can be formed. . Note that FIG. 13A corresponds to a cross-sectional view taken along line AB of FIG. 15A (except for the resist mask 86).

  Next, the resist mask 81 is ashed. As a result, the resist area is reduced and the thickness is reduced. At this time, the resist in a thin region (a region overlapping with part of the gate electrode 51) is removed, and a separated resist mask 86 can be formed as shown in FIG.

Next, the conductive films 85 a to 85 c are etched and separated using the resist mask 86. As a result, a pair of source and drain electrodes 92a to 92c as shown in FIG. 13B can be formed. When the conductive films 89a to 89c are wet-etched using the resist mask 86, the ends of the conductive films 89a to 89c are selectively etched. As a result, source and drain electrodes 92a to 92c having a smaller area than the resist mask 86 can be formed.

  Next, the semiconductor film 63 to which an impurity imparting one conductivity type is added is etched using the resist mask 86, so that a pair of source and drain regions 88 is formed. Note that part of the buffer layer 62 is also etched in the etching step. The partially etched buffer layer is referred to as a buffer layer 87. A concave portion is formed in the buffer layer 87. The step of forming the source region and the drain region and the depression (groove) of the buffer layer can be formed in the same step. Here, a part of the buffer layer 87 is partially etched by the resist mask 86 whose area is reduced as compared with the resist mask 81, so that the buffer layer 87 protrudes outside the source and drain regions 88. . Thereafter, the resist mask 86 is removed. In addition, the end portions of the source and drain electrodes 92a to 92c and the end portions of the source and drain regions 88 are not aligned with each other. An end of the drain region 88 is formed.

Note that FIG. 13C corresponds to a cross-sectional view taken along a line AB in FIG. As shown in FIG. 15B, it can be seen that the ends of the source and drain regions 88 are located outside the ends of the source and drain electrodes 92c. The end portion of the buffer layer 87 is located outside the end portions of the source and drain electrodes 92 c and the source and drain regions 88. One of the source electrode and the drain electrode has a shape (specifically, a U shape or a C shape) surrounding the other of the source region and the drain region. Therefore, the area of the region where carriers move can be increased, so that the amount of current can be increased and the area of the thin film transistor can be reduced. In addition, since the microcrystalline semiconductor film, the source electrode, and the drain electrode are overlapped with each other over the gate electrode, the influence of the unevenness of the gate electrode is small, so that covering defects can be reduced and the occurrence of leakage current can be suppressed. Note that one of the source electrode and the drain electrode also functions as a source wiring or a drain wiring.

As shown in FIG. 13C, the end portions of the source and drain electrodes 92a to 92c and the end portions of the source and drain regions 88 are not aligned with each other, so that the source and drain electrodes 92a are displaced. Since the distance between the ends of .about.92c is increased, leakage current and short circuit between the source electrode and the drain electrode can be prevented. Further, since the end portions of the source and drain electrodes 92a to 92c and the end portions of the source and drain regions 88 do not coincide with each other and are shifted, the source and drain electrodes 92a to 92c, the source region and the drain region 88 are formed. As a result, the electric field is not concentrated on the end of the gate electrode, and leakage current between the gate electrode 51 and the source and drain electrodes 92a to 92c can be prevented. Therefore, a thin film transistor with high reliability and high withstand voltage can be manufactured.

  Through the above process, the thin film transistor 83 can be formed. In addition, a thin film transistor can be formed using two photomasks.

Next, as illustrated in FIG. 14A, an insulating film 76 is formed over the source and drain electrodes 92a to 92c, the source and drain regions 88, the buffer layer 87, the microcrystalline semiconductor film 90, and the gate insulating film 52c. Form.

Next, a part of the insulating film 76 is etched using a resist mask formed using a third photomask to form a contact hole. Next, a pixel electrode 77 in contact with the source or drain electrode 71c in the contact hole is formed. Here, as the pixel electrode 77, an indium tin oxide film is formed by a sputtering method, and then a resist is applied on the indium tin oxide film. Next, the resist is exposed and developed using a fourth photomask to form a resist mask. Next, the pixel electrode 77 is formed by etching the indium tin oxide film using a resist mask. Note that FIG. 14B corresponds to a cross-sectional view taken along a line AB in FIG.

As described above, an element substrate that can be used for a display device can be formed by reducing the number of masks using a multi-tone mask.

Further, this embodiment can be freely combined with any one of Embodiments 1 to 4.

(Embodiment 6)
In this embodiment, a liquid crystal display device including the thin film transistor described in Embodiment 2 is described below as one embodiment of the display device.

First, a VA (vertical alignment) liquid crystal display device is described. The VA liquid crystal display device is a type of a method for controlling the alignment of liquid crystal molecules in a liquid crystal panel. The VA liquid crystal display device is a method in which liquid crystal molecules face a vertical direction with respect to a panel surface when no voltage is applied. In the present embodiment, the pixel (pixel) is divided into several regions (sub-pixels), and each molecule is devised to tilt the molecules in different directions. This is called multi-domain or multi-domain design. In the following description, a liquid crystal display device considering multi-domain design will be described.

  17 and 18 show a pixel electrode and a counter electrode, respectively. FIG. 17 is a plan view of the substrate side on which the pixel electrode is formed, and FIG. 16 shows a cross-sectional structure corresponding to the cutting line AB shown in the drawing. FIG. 18 is a plan view of the substrate side on which the counter electrode is formed. The following description will be given with reference to these drawings.

  FIG. 16 illustrates a state in which a liquid crystal is injected by superimposing a substrate 600 on which a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor portion 630 are formed, and a counter substrate 601 on which the counter electrode 640 and the like are formed. Show.

A light shielding film 632, a first colored film 634, a second colored film 636, a third colored film 638, and a counter electrode 640 are formed at positions where the spacers 642 are formed on the counter substrate 601. With this structure, the heights of the protrusions 644 and the spacers 642 for controlling the alignment of the liquid crystal are made different. An alignment film 648 is formed over the pixel electrode 624, and similarly, an alignment film 646 is formed over the counter electrode 640. In the meantime, a liquid crystal layer 650 is formed.

The spacers 642 are shown here using columnar spacers, but bead spacers may be dispersed. Further, the spacer 642 may be formed over the pixel electrode 624 formed over the substrate 600.

A TFT 628, a pixel electrode 624 connected to the TFT 628, and a storage capacitor portion 630 are formed over the substrate 600. The pixel electrode 624 is connected to the wiring 618 through a contact hole 623 that passes through the insulating film 620 that covers the TFT 628, the wiring, and the storage capacitor portion 630, and the third insulating film 622 that covers the insulating film. As the TFT 628, the thin film transistor described in Embodiment 2 can be used as appropriate. The storage capacitor portion 630 includes a first capacitor wiring 604 formed in the same manner as the gate wiring 602 of the TFT 628, a gate insulating film 606, and a second capacitor wiring 617 formed in the same manner as the wirings 616 and 618. The

The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 overlap with each other to form a liquid crystal element.

FIG. 17 shows the structure on the substrate 600. The pixel electrode 624 is formed using the material described in Embodiment Mode 2. The pixel electrode 624 is provided with a slit 625. The slit 625 is for controlling the alignment of the liquid crystal.

  The TFT 629 and the pixel electrode 626 and the storage capacitor portion 631 connected to the TFT 629 shown in FIG. 17 can be formed in the same manner as the pixel electrode 624 and the storage capacitor portion 630, respectively. Both the TFT 628 and the TFT 629 are connected to the wiring 616. A pixel (pixel) of the liquid crystal panel includes a pixel electrode 624 and a pixel electrode 626. The pixel electrode 624 and the pixel electrode 626 are subpixels.

  FIG. 18 shows a structure on the counter substrate side. A counter electrode 640 is formed on the light shielding film 632. The counter electrode 640 is preferably formed using a material similar to that of the pixel electrode 624. On the counter electrode 640, a protrusion 644 for controlling the alignment of the liquid crystal is formed. A spacer 642 is formed in accordance with the position of the light shielding film 632.

  An equivalent circuit of this pixel structure is shown in FIG. The TFTs 628 and 629 are both connected to the gate wiring 602 and the wiring 616. In this case, operation of the liquid layer element 651 and the liquid crystal element 652 can be made different by making the potentials of the capacitor wiring 604 and the capacitor wiring 605 different. That is, by controlling the potentials of the capacitor wiring 604 and the capacitor wiring 605 individually, the orientation of the liquid crystal is precisely controlled to widen the viewing angle.

  When a voltage is applied to the pixel electrode 624 provided with the slit 625, an electric field distortion (an oblique electric field) is generated in the vicinity of the slit 625. By arranging the slits 625 and the protrusions 644 on the counter substrate 601 to alternately engage with each other, an oblique electric field is effectively generated to control the alignment of the liquid crystal, so that the direction in which the liquid crystal is aligned is determined. It is different depending on. That is, the viewing angle of the liquid crystal panel is widened by multi-domain.

Although an example of a VA liquid crystal display device is described above, the pixel electrode structure illustrated in FIG. 17 is not particularly limited.

Next, a form of a TN liquid crystal display device is described.

  20 and 21 show a pixel structure of a TN liquid crystal display device. FIG. 21 is a plan view, and FIG. 20 shows a cross-sectional structure corresponding to a cutting line AB shown in the drawing. The following description will be given with reference to both the drawings.

  The pixel electrode 624 is connected to the TFT 628 by a wiring 618 through a contact hole 623. A wiring 616 functioning as a data line is connected to the TFT 628. Any of the TFTs described in Embodiment 2 can be applied to the TFT 628.

  The pixel electrode 624 is formed using the pixel electrode 77 described in Embodiment 2.

  A counter substrate 601 is provided with a light shielding film 632, a second coloring film 636, and a counter electrode 640. In addition, a planarization film 637 is formed between the second coloring film 636 and the counter electrode 640 to prevent alignment disorder of the liquid crystal. The liquid crystal layer 650 is formed between the pixel electrode 624 and the counter electrode 640.

The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 overlap with each other to form a liquid crystal element.

  Further, a color filter, a shielding film (black matrix) for preventing disclination, or the like may be formed on the substrate 600 or the counter substrate 601. In addition, a polarizing plate is attached to a surface of the substrate 600 opposite to the surface on which the thin film transistor is formed, and a polarizing plate is attached to a surface of the counter substrate 601 opposite to the surface on which the counter electrode 640 is formed. Keep it.

Through the above process, a liquid crystal display device can be manufactured. The liquid crystal display device of this embodiment is a liquid crystal display device with high contrast and high visibility because it uses a thin film transistor with low off-state current, excellent electrical characteristics, and high reliability.

Further, it can be applied to a horizontal electric field liquid crystal display device. The horizontal electric field method is a method in which gradation is expressed by driving a liquid crystal by applying an electric field in a horizontal direction to liquid crystal molecules in a cell. According to this method, the viewing angle can be expanded to about 180 degrees.

(Embodiment 7)
In this embodiment, a light-emitting device which is one embodiment of a display device will be described with reference to FIGS. 12 to 14, 22, and 23. Here, the light-emitting device is described using a light-emitting element utilizing electroluminescence. A light-emitting element using electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

  In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are respectively injected from the pair of electrodes into the layer containing the light emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element. The thin film transistor of Embodiment 2 is used as a thin film transistor for controlling driving of the light-emitting element. The light-emitting device using the thin film transistor obtained in Embodiment Mode 2 can suppress a change in threshold value of the thin film transistor, which leads to improvement in reliability. In particular, since a thin film transistor used in a light emitting device is driven by a direct current, the gate insulating film has a three-layer structure, the first layer is a silicon nitride film, the second layer is a silicon oxynitride film, and the third layer is a silicon nitride film. The thin film transistor of mode 2 can suppress threshold drift mainly by the second layer silicon oxynitride film.

Through the steps of FIGS. 12 to 14, a thin film transistor 83 is formed on the substrate 50 as shown in FIG. 22, and an insulating film 76 functioning as a protective film is formed on the thin film transistor 83. A thin film transistor 84 is also formed in the drive circuit 12. The thin film transistor 84 can be manufactured in the same process as the thin film transistor 83 of the pixel portion 11. Next, a planarization film 93 is formed over the insulating film 76, and a pixel electrode 94 connected to the source electrode or the drain electrode of the thin film transistor 83 is formed over the planarization film 93.

  The planarization film 82 is preferably formed using an organic resin such as acrylic, polyimide, or polyamide, or siloxane.

  In FIG. 22A, since the thin film transistor of the pixel portion 11 is n-type, it is desirable to use a cathode as the pixel electrode 94. On the contrary, in the case of p-type, it is desirable to use an anode. Specifically, a known material having a small work function, such as calcium, aluminum, calcium fluoride, magnesium silver alloy, lithium aluminum alloy, or the like can be used as the cathode.

  Next, as shown in FIG. 22B, a partition wall 91 is formed over the end portions of the planarization film 82 and the pixel electrode 94. The partition wall 91 has an opening, and the pixel electrode 94 is exposed in the opening. The partition wall 91 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, it is preferable to use a photosensitive material and form an opening on the pixel electrode so that the side wall of the opening is an inclined surface formed with a continuous curvature.

Next, the light emitting layer 95 is formed so as to be in contact with the pixel electrode 94 in the opening of the partition wall 91. The light emitting layer 95 may be composed of a single layer or may be composed of a plurality of layers stacked.

  Then, a common electrode 96 using an anode is formed so as to cover the light emitting layer 95. The common electrode 96 can be formed using a light-transmitting conductive film using a light-transmitting conductive material listed as the pixel electrode 77 in Embodiment 2. As the common electrode 96, a titanium nitride film or a titanium film may be used in addition to the light-transmitting conductive film. In FIG. 22B, indium tin oxide is used for the common electrode 96. In the opening of the partition wall 91, the pixel electrode 94, the light emitting layer 95, and the common electrode 96 are overlapped to form a light emitting element 98. Thereafter, a protective film 97 is preferably formed over the common electrode 96 and the partition wall 91 so that oxygen, moisture, carbon dioxide, or the like does not enter the light-emitting element 98. As the protective film 97, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

  Furthermore, in actuality, when completed up to FIG. 22B, packaging with a protective film (laminated film, ultraviolet curable resin film, etc.) or cover material that is highly airtight and less degassed so as not to be exposed to the outside air ( (Encapsulation) is preferable.

  Next, the structure of the light-emitting element is described with reference to FIG. Here, the cross-sectional structure of the pixel will be described with an example in which the driving TFT is an n-type.

  In order to extract light emitted from the light-emitting element, at least one of the anode and the cathode may be transparent. Then, a thin film transistor and a light emitting element are formed on the substrate, and a top emission that extracts light from a surface opposite to the substrate, a bottom emission that extracts light from a surface on the substrate, and a surface opposite to the substrate and the substrate are provided. The pixel structure of the present invention can be applied to a light emitting element having any emission structure.

  A light-emitting element having a top emission structure will be described with reference to FIG.

  FIG. 23A is a cross-sectional view of a pixel in the case where the driving TFT 7001 is n-type and light emitted from the light-emitting element 7002 escapes to the anode 7005 side. In FIG. 23A, a cathode 7003 of a light emitting element 7002 and a driving TFT 7001 are electrically connected, and a light emitting layer 7004 and an anode 7005 are stacked over the cathode 7003 in this order. A known material can be used for the cathode 7003 as long as it has a small work function and reflects light. For example, calcium, aluminum, calcium fluoride, magnesium silver alloy, lithium aluminum alloy and the like are desirable. The light emitting layer 7004 may be formed of a single layer or may be formed of a plurality of stacked layers. In the case of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are stacked in this order on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, or titanium oxide. A light-transmitting conductive conductive film such as indium tin oxide, indium tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added may be used.

  A region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in FIG. 23A, light emitted from the light-emitting element 7002 is emitted to the anode 7005 side as indicated by a hollow arrow.

  Next, a light-emitting element having a bottom emission structure will be described with reference to FIG. A cross-sectional view of a pixel in the case where the driving TFT 7011 is n-type and light emitted from the light-emitting element 7012 is emitted to the cathode 7013 side is shown. In FIG. 23B, a cathode 7013 of a light-emitting element 7012 is formed over a light-transmitting conductive material 7017 electrically connected to a driving TFT 7011. A light-emitting layer 7014 is formed over the cathode 7013. An anode 7015 is sequentially stacked. Note that in the case where the anode 7015 has a light-transmitting property, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode. As in the case of FIG. 23A, a known material can be used for the cathode 7013 as long as it is a conductive film with a low work function. However, the film thickness is set so as to transmit light (preferably, about 5 nm to 30 nm). For example, Al having a thickness of 20 nm can be used as the cathode 7013. Similarly to FIG. 23A, the light-emitting layer 7014 may be formed of a single layer or a stack of a plurality of layers. The anode 7015 is not required to transmit light, but can be formed using a light-transmitting conductive material as in FIG. The shielding film 7016 can be formed using, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin to which a black pigment is added can be used.

  A region where the light emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 corresponds to the light emitting element 7012. In the case of the pixel shown in FIG. 23B, light emitted from the light-emitting element 7012 is emitted to the cathode 7013 side as indicated by a hollow arrow.

  Next, a light-emitting element having a dual emission structure will be described with reference to FIG. In FIG. 23C, a cathode 7023 of a light-emitting element 7022 is formed over a light-transmitting conductive material 7027 which is electrically connected to the driving TFT 7021. A light-emitting layer 7024 and a light-emitting layer 7024 are formed over the cathode 7023. An anode 7025 is sequentially stacked. As in the case of FIG. 23A, a known material can be used for the cathode 7023 as long as it is a conductive film having a low work function. However, the film thickness is set so as to transmit light. For example, Al having a thickness of 20 nm can be used as the cathode 7023. Similarly to FIG. 23A, the light-emitting layer 7024 may be formed of a single layer or a stack of a plurality of layers. The anode 7025 can be formed using a light-transmitting conductive material as in FIG. 23A.

  A portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 7022. In the case of the pixel shown in FIG. 23C, light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by white arrows.

Note that although an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.

  Note that in this embodiment mode, an example in which a thin film transistor (driving TFT) that controls driving of a light emitting element is electrically connected to the light emitting element is shown, but current control is performed between the driving TFT and the light emitting element. A configuration in which TFTs are connected may be used.

  Note that the light-emitting device described in this embodiment mode is not limited to the structure illustrated in FIG. 23, and various modifications can be made based on the technical idea of the present invention.

Through the above steps, a light-emitting device can be manufactured. The light-emitting device of this embodiment is a light-emitting device with high contrast and high visibility because it uses a thin film transistor with low off-state current, excellent electrical characteristics, and high reliability.

(Embodiment 8)
A structure of a display panel which is one embodiment of the display device of the present invention is described below.

  FIG. 24 shows a mode of a display panel in which only the signal line driver circuit 6013 is separately formed and connected to the pixel portion 6012 formed over the substrate 6011. The pixel portion 6012 and the scan line driver circuit 6014 are formed using a thin film transistor including a microcrystalline semiconductor film. By forming the signal line driver circuit with a transistor that can obtain higher mobility than a thin film transistor using a microcrystalline semiconductor film, the operation of the signal line driver circuit that requires a higher driving frequency than the scanning line driver circuit is stabilized. be able to. Note that the signal line driver circuit 6013 may be a transistor using a single crystal semiconductor, a thin film transistor using a polycrystalline semiconductor, or a transistor using SOI. The pixel portion 6012, the signal line driver circuit 6013, and the scan line driver circuit 6014 are supplied with a potential of a power source, various signals, and the like through the FPC 6015.

  Note that both the signal line driver circuit and the scan line driver circuit may be formed over the same substrate as the pixel portion.

  In the case where a driver circuit is separately formed, the substrate on which the driver circuit is formed is not necessarily bonded to the substrate on which the pixel portion is formed, and may be bonded to, for example, an FPC. FIG. 24B illustrates a mode of a liquid crystal display device panel in which only the signal line driver circuit 6023 is separately formed and connected to the pixel portion 6022 and the scan line driver circuit 6024 which are formed over the substrate 6021. The pixel portion 6022 and the scan line driver circuit 6024 are formed using a thin film transistor including a microcrystalline semiconductor film. The signal line driver circuit 6023 is connected to the pixel portion 6022 through the FPC 6025. The pixel portion 6022, the signal line driver circuit 6023, and the scan line driver circuit 6024 are supplied with power supply potential, various signals, and the like through the FPC 6025.

  In addition, only part of the signal line driver circuit or part of the scan line driver circuit is formed over the same substrate as the pixel portion by using a thin film transistor using a microcrystalline semiconductor film, and the rest is formed separately. You may make it connect electrically. In FIG. 24C, an analog switch 6033a included in the signal line driver circuit is formed over the same substrate 6031 as the pixel portion 6032 and the scan line driver circuit 6034, and a shift register 6033b included in the signal line driver circuit is provided over a different substrate. The form of the liquid crystal display device panel formed and bonded together is shown. The pixel portion 6032 and the scan line driver circuit 6034 are formed using a thin film transistor including a microcrystalline semiconductor film. A shift register 6033 b included in the signal line driver circuit is connected to the pixel portion 6032 through the FPC 6035. A potential of a power source, various signals, and the like are supplied to the pixel portion 6032, the signal line driver circuit, and the scan line driver circuit 6034 through the FPC 6035, respectively.

  As shown in FIG. 24, in the liquid crystal display device of the present invention, part or all of the driver circuit can be formed over the same substrate as the pixel portion using a thin film transistor including a microcrystalline semiconductor film.

  Note that a method for connecting a separately formed substrate is not particularly limited, and a known COG method, wire bonding method, TAB method, or the like can be used. Further, the connection position is not limited to the position illustrated in FIG. 24 as long as electrical connection is possible. In addition, a controller, a CPU, a memory, and the like may be separately formed and connected.

  Note that the signal line driver circuit used in the present invention is not limited to a mode having only a shift register and an analog switch. In addition to the shift register and the analog switch, other circuits such as a buffer, a level shifter, and a source follower may be included. The shift register and the analog switch are not necessarily provided. For example, another circuit that can select a signal line such as a decoder circuit may be used instead of the shift register, or a latch or the like may be used instead of the analog switch. May be.

(Embodiment 9)
The appearance and a cross section of a liquid crystal display panel, which is one embodiment of the display device of the present invention, will be described with reference to FIGS. FIG. 25 is a top view of a panel in which a thin film transistor 4010 and a liquid crystal element 4013 each including a microcrystalline semiconductor film formed over a first substrate 4001 are sealed with a sealant 4005 between the second substrate 4006 and FIG. FIG. 25B corresponds to a cross-sectional view taken along a line AA ′ in FIG.

  A sealant 4005 is provided so as to surround the pixel portion 4002 provided over the first substrate 4001 and the scan line driver circuit 4004. A second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with the liquid crystal 4008 by the first substrate 4001, the sealant 4005, and the second substrate 4006. In addition, a signal line driver circuit 4003 formed using a polycrystalline semiconductor film is mounted over a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the first substrate 4001. Note that in this embodiment, an example in which a signal line driver circuit including a thin film transistor using a polycrystalline semiconductor film is attached to the first substrate 4001 is described; however, the signal line driver circuit is a transistor using a single crystal semiconductor. It may be formed and bonded. FIG. 25 illustrates a thin film transistor 4009 formed of a polycrystalline semiconductor film, which is included in the signal line driver circuit 4003.

  In addition, the pixel portion 4002 provided over the first substrate 4001 and the scan line driver circuit 4004 each include a plurality of thin film transistors. FIG. 25B illustrates a thin film transistor 4010 included in the pixel portion 4002. ing. The thin film transistor 4010 corresponds to a thin film transistor using a microcrystalline semiconductor film.

  Reference numeral 4011 corresponds to a liquid crystal element, and the pixel electrode 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010 through a wiring 4040 and a wiring 4041. A counter electrode 4031 of the liquid crystal element 4013 is formed over the second substrate 4006. A portion where the pixel electrode 4030, the counter electrode 4031, and the liquid crystal 4008 overlap corresponds to the liquid crystal element 4013.

  Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or polyester films can also be used.

  Reference numeral 4035 denotes a spherical spacer, which is provided to control the distance (cell gap) between the pixel electrode 4030 and the counter electrode 4031. Note that a spacer obtained by selectively etching the insulating film may be used.

  In addition, a variety of signals and potentials are supplied to the signal line driver circuit 4003 which is formed separately, the scan line driver circuit 4004, or the pixel portion 4002 from an FPC 4018 through lead wirings 4014 and 4015.

  In this embodiment, the connection terminal 4016 is formed using the same conductive film as the pixel electrode 4030 included in the liquid crystal element 4013. The lead wirings 4014 and 4015 are formed using the same conductive film as the wiring 4041.

  The connection terminal 4016 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

  Although not illustrated, the liquid crystal display device described in this embodiment includes an alignment film and a polarizing plate, and may further include a color filter and a shielding film.

  FIG. 25 illustrates an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001; however, this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

  This embodiment can be implemented in combination with any of the structures described in the other embodiments.

(Embodiment 10)
Next, the appearance and cross section of a light-emitting display panel, which is one embodiment of the display device of the present invention, will be described with reference to FIGS. 26 is a top view of a panel in which a thin film transistor and a light-emitting element each using a microcrystalline semiconductor film formed over a first substrate are sealed with a sealant between the second substrate and FIG. FIG. 26B corresponds to a cross-sectional view taken along line AA ′ in FIG.

  A sealant 4005 is provided so as to surround the pixel portion 4002 provided over the first substrate 4001 and the scan line driver circuit 4004. A second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with the filler 4007 by the first substrate 4001, the sealant 4005, and the second substrate 4006. In addition, a signal line driver circuit 4003 formed using a polycrystalline semiconductor film is mounted over a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the first substrate 4001. Note that in this embodiment, an example in which a signal line driver circuit including a thin film transistor using a polycrystalline semiconductor film is attached to the first substrate 4001 is described; however, the signal line driver circuit is a transistor using a single crystal semiconductor. It may be formed and bonded. FIG. 26 illustrates a thin film transistor 4009 formed of a polycrystalline semiconductor film, which is included in the signal line driver circuit 4003.

  In addition, the pixel portion 4002 provided over the first substrate 4001 and the scan line driver circuit 4004 each include a plurality of thin film transistors. FIG. 26B illustrates a thin film transistor 4010 included in the pixel portion 4002. ing. Note that although the thin film transistor 4010 is assumed to be a driving TFT in this embodiment, the thin film transistor 4010 may be a current control TFT or an erasing TFT. The thin film transistor 4010 corresponds to a thin film transistor using a microcrystalline semiconductor film.

  4011 corresponds to a light-emitting element, and a pixel electrode included in the light-emitting element 4011 is electrically connected to a source electrode or a drain electrode of the thin film transistor 4010 through a wiring 4017. In this embodiment, the common electrode of the light-emitting element 4011 and the light-transmitting conductive material 4012 are electrically connected. Note that the structure of the light-emitting element 4011 is not limited to the structure described in this embodiment. The structure of the light-emitting element 4011 can be changed as appropriate depending on the direction of light extracted from the light-emitting element 4011, the polarity of the thin film transistor 4010, or the like.

  In addition, a variety of signals and potentials are supplied to the separately formed signal line driver circuit 4003 and the scan line driver circuit 4004 or the pixel portion 4002, although not shown in the cross-sectional view in FIG. And 4015 through the FPC 4018.

  In this embodiment, the connection terminal 4016 is formed using the same conductive film as the pixel electrode included in the light-emitting element 4011. The lead wirings 4014 and 4015 are formed of the same conductive film as the wiring 4017.

  The connection terminal 4016 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

  The second substrate must be transparent to the substrate located in the direction in which light is extracted from the light emitting element 4011. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

  As the filler 4007, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicon resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filler.

  If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or the like is provided on the light emitting element exit surface. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.

  Note that although FIG. 26 illustrates an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001, this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

  This embodiment can be implemented in combination with any of the structures described in the other embodiments.

(Embodiment 11)
The display device or the like obtained by the present invention can be used for an active matrix display device module. That is, the present invention can be implemented in all electronic devices in which they are incorporated in the display portion.

  Such electronic devices include video cameras, digital cameras, head mounted displays (goggles type displays), car navigation systems, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. An example of them is shown in FIG.

  FIG. 27A illustrates a television device. As shown in FIG. 27A, the display module can be incorporated into a housing to complete the television device. A display panel attached to the FPC is also called a display module. A main screen 2003 is formed by the display module, and a speaker portion 2009, operation switches, and the like are provided as other accessory equipment. In this manner, a television device can be completed.

  As shown in FIG. 27A, a display panel 2002 using a display element is incorporated in a housing 2001, and a general television broadcast is received by a receiver 2005 and wired or wirelessly via a modem 2004. By connecting to a communication network, information communication in one direction (from the sender to the receiver) or in both directions (between the sender and the receiver or between the receivers) can be performed. The television device can be operated by a switch incorporated in the housing or a separate remote controller 2006, and this remote controller is also provided with a display unit 2007 for displaying information to be output. Also good.

  In addition, the television device may have a configuration in which a sub screen 2008 is formed using the second display panel in addition to the main screen 2003 to display channels, volume, and the like. In this structure, the main screen 2003 may be formed using a liquid crystal display panel with an excellent viewing angle, and the sub screen may be formed using a light-emitting display panel that can display with low power consumption. In order to give priority to lower power consumption, the main screen 2003 may be formed using a light-emitting display panel, the sub screen may be formed using a light-emitting display panel, and the sub screen may be blinkable.

  Of course, the present invention is not limited to a television device, but can be applied to various applications such as personal computer monitors, information display boards at railway stations and airports, and advertisement display boards on streets. can do.

FIG. 27B illustrates an example of a mobile phone 2301. The cellular phone 2301 includes a display portion 2302, an operation portion 2303, and the like. In the display portion 2302, by applying the display device described in the above embodiment mode, mass productivity can be improved.

  A portable computer illustrated in FIG. 27C includes a main body 2401, a display portion 2402, and the like. By applying the display device described in any of the above embodiments to the display portion 2402, mass productivity can be improved.

FIG. 27D illustrates a table lamp, which includes a lighting unit 2501, an umbrella 2502, a variable arm 2503, a column 2504, a base 2505, and a power source 2506. The light-emitting device described in Embodiment Mode 10 is used for the lighting portion 2501. The lighting fixture includes a ceiling-fixed lighting fixture or a wall-mounted lighting fixture. By applying the display device described in any of the above embodiments, mass productivity can be increased and an inexpensive desk lamp can be provided.

Sectional drawing which shows an example of a clean room. The top view which shows an example of a clean room, and the top view of a plasma CVD apparatus. The perspective view which shows an example of the film-forming apparatus. It is a cross-sectional view illustrating a manufacturing method of the present invention. It is a cross-sectional view illustrating a manufacturing method of the present invention. It is a cross-sectional view illustrating a manufacturing method of the present invention. FIG. 11 is a top view illustrating a manufacturing method of the present invention. It is a figure which shows an example of the time chart explaining the process of forming a microcrystal silicon film. It is a cross-sectional view illustrating a manufacturing method of the present invention. It is sectional drawing of a semiconductor device. It is a figure explaining the multi-tone mask applicable to this invention. 10A to 10C are cross-sectional views illustrating a manufacturing process of the present invention. 10A to 10C are cross-sectional views illustrating a manufacturing process of the present invention. 10A to 10C are cross-sectional views illustrating a manufacturing process of the present invention. FIG. 6 is a top view of a manufacturing process of the present invention. It is a figure explaining an example of a liquid crystal display device. It is a figure explaining an example of a liquid crystal display device. It is a figure explaining an example of a liquid crystal display device. It is an equivalent circuit diagram of a pixel of a liquid crystal display device. It is a figure explaining an example of a liquid crystal display device. It is a figure explaining an example of a liquid crystal display device. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a light-emitting device. It is a cross-sectional view illustrating a pixel applicable to a light-emitting device. It is a perspective view explaining a display panel. 4A and 4B are a top view and a cross-sectional view illustrating a display panel. 4A and 4B are a top view and a cross-sectional view illustrating a display panel. It is a perspective view explaining an electronic device.

Explanation of symbols

11: Pixel portion 12: Drive circuit 23: Microcrystalline semiconductor film 50: Substrate 51: Gate electrodes 52a, 52b, 52c: Gate insulating film 53: Microcrystalline semiconductor film 54: Buffer layer 55: Impurities imparting one conductivity type Added semiconductor film 56: resist mask 59: multi-tone mask 61: microcrystalline semiconductor film 62: buffer layer 63: semiconductor films 65a, 65b, 65c to which an impurity imparting one conductivity type is added: conductive film 66: Resist masks 71a, 71b, 71c: source and drain electrodes 72: source and drain regions 73: buffer layer 74: thin film transistor 76: insulating film 77: pixel electrode 80: resist mask 81: resist mask 82: planarizing film 83: Thin film transistor 84: thin film transistors 85a to 85c conductive film 87: buffer layer 86: resist mass 88: Source and drain regions 89a, 89b, 89c: Conductive film 90: Microcrystalline semiconductor film 91: Partition walls 92a, 92b, 92c: Source and drain electrodes 93: Planarization film 94: Pixel electrode 95: Light emitting layer 96: Common electrode 97: protective film 98: light emitting element 101: first partition 102: first area 103: plasma CVD apparatus 104: first fan filter unit 105: gas supply unit 106: load chambers 107a to 107d: grating floor 108 : Exhaust unit 109: second partition 110: second area 111: automatic transfer device 112: air conditioner 113: second fan filter unit

Claims (12)

A first area in which a manufacturing apparatus having a vacuum chamber is arranged and surrounded by a first partition;
A gas circulating means for supplying and circulating a rare gas or hydrogen gas to the first area;
A second area surrounding the first area and surrounded by a second partition;
A clean room having air conditioning means for supplying and circulating air to the second area. 2. The clean room according to claim 1, wherein the first area is divided by the first partition, and the first area is adjusted to be more positive than the second area by the gas circulation means. 3. The clean room according to claim 1, wherein the second area is divided by the second partition, and the first area is adjusted to a positive pressure from an atmospheric pressure by the air conditioning means. 4. The clean room according to claim 1, wherein the manufacturing apparatus having the vacuum chamber includes a plasma CVD apparatus. The clean room according to any one of claims 1 to 4, wherein an automatic transfer device on which a substrate is mounted moves in the second area. Circulating rare gas or hydrogen gas in the first area where the plasma CVD apparatus is arranged,
Circulating the air that has passed through the fan filter unit to the second area surrounding the first area;
The substrate is transferred to the plasma CVD apparatus by an automatic transfer apparatus that moves in the second area,
A substrate is placed in a vacuum chamber of the plasma CVD apparatus,
A film forming method for forming a semiconductor film on the substrate by introducing a material gas into the vacuum chamber to generate plasma. 7. The film forming method according to claim 6, wherein the first area in which the rare gas or the hydrogen gas is circulated is a positive pressure whose pressure is higher than the atmospheric pressure. 8. The film forming method according to claim 6, wherein the oxygen concentration and the nitrogen concentration contained in the rare gas or the hydrogen gas are 30 ppm or less. The film forming method according to claim 6, wherein the material gas includes a silane gas.   10. The deposition method according to claim 6, wherein the semiconductor film is a microcrystalline semiconductor film. Forming a gate electrode over a substrate having an insulating surface;
Forming an insulating film on the gate electrode;
A first area in which a rare gas or hydrogen gas is circulated between the outside air and the outer wall of the vacuum chamber is provided in contact with the outer wall of the vacuum chamber,
The first area is enclosed by a first partition to isolate the vacuum chamber from the second area, and the second area and the first area are enclosed by a second partition to isolate the outside air from the second area. Installing a substrate provided with the insulating film in the vacuum chamber, introducing a material gas into the vacuum chamber to generate plasma, and forming a microcrystalline semiconductor film on the insulating film;
Forming a buffer layer on the microcrystalline semiconductor film;
In forming the microcrystalline semiconductor film, the film forming conditions are stepwise or continuous so that the first region near the interface with the buffer layer has a higher film forming speed than the second region near the interface with the insulating film. Of manufacturing a semiconductor device. The semiconductor film containing an n-type impurity element is further formed on the buffer layer according to claim 11,
Forming a source electrode or a drain electrode on the semiconductor film containing the n-type impurity element;
Etching the semiconductor film containing the n-type impurity element to form a source region and a drain region;
A method for manufacturing a semiconductor device, in which a region overlapping with the source region and the drain region is left and a part of the buffer layer is removed by etching.

Images