JP2009118650A - Power converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a power converter surely reducing EMI noises generated in case of turn-off without unnecessarily delaying a switching speed and being capable of lowering both EMI noises and switching loss when a semiconductor switching element is turned off. <P>SOLUTION: When the switching element 1a is turned off, noise-mode decision circuits 4 are provided for turning-on and turn-off respectively, and the necessity of the reduction of each noise in a common mode and a differential mode is determined in response to load currents. A switching-time adjusting circuit 5 is provided to reduce a voltage change rate between a collector and an emitter of the switching element 1a for lowering common-mode noises. The charge-discharge speeds of a gate electrode are delayed so as to decrease the current change rate of the switching element 1a for lowering the differential-mode noises. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a power conversion device that has both reduced radiation EMI (Electromagnetic Interference) noise and reduced switching loss.

  Conventional power converters include an active EMI filter to reduce EMI noise, reducing common mode noise and differential mode noise with respect to the input and detecting the noise level. It also has a gate voltage control circuit that controls the voltage applied to the gate of the power switch. In order to reduce common mode noise, the voltage change rate is moderated during both turn-on and turn-off to reduce differential mode noise. During the turn-on, the voltage change rate was moderated (see, for example, Patent Document 1).

JP 2005-534271 A

  In such a power converter, the voltage change rate of the gate voltage is moderated during both turn-on and turn-off to reduce common mode noise, and the voltage change of the gate voltage during turn-on to reduce differential mode noise. Although the rate has been moderated, it is difficult to obtain the desired effect precisely because it is not controlled by focusing on noise-dominating factors, and the switching speed is unnecessarily slowed. there were.

  The present invention has been made to solve the above-described problems, and reliably reduces EMI noise generated when a semiconductor switching element is turned on and turned off without unnecessarily slowing the switching speed. Then, it aims at obtaining the power converter device which can reduce both EMI noise and switching loss.

  The power conversion device according to the present invention includes a semiconductor switching element that is driven and controlled by a gate electrode, and supplies power to an inductive load. Based on the output of the current sensor, the noise mode to be reduced among the radiation noise having the differential mode and the common mode for each of the current sensor for detecting the load current and the turn-on and turn-off of the semiconductor switching element. A noise mode determination circuit for determining; and a switching time adjusting circuit for adjusting a switching time of the semiconductor switching element by changing a charge / discharge speed of the gate electrode by switching a gate command. The switching time adjustment circuit selectively reduces the current change rate and the voltage change rate between both terminals of the semiconductor switching element in accordance with the noise mode determined by the noise mode determination circuit.

  According to the present invention, the noise mode to be reduced is determined for each of turn-on and turn-off, and the current change rate and the voltage change rate between both terminals of the semiconductor switching element are selectively reduced according to the noise mode. EMI noise can be reliably reduced without unnecessarily slowing down the speed, and both EMI noise and switching loss can be reduced.

Embodiment 1 FIG.
Hereinafter, a power converter according to Embodiment 1 of the present invention will be described. 1 is a schematic configuration diagram showing a part of a power conversion apparatus according to Embodiment 1 of the present invention.
As shown in FIG. 1, a semiconductor switching element (hereinafter referred to as a switch element) 1a made of an IGBT having a diode 2a connected in antiparallel and a switch element 1b made of an IGBT having an antiparallel connected diode 2b are connected in series. A current sensor 6 is connected between the connection point and the inductive load for detecting the load current.

When a gate command which is a switching command to the switch element 1a is input from the outside, the amplifier 3 amplifies the switch element 1a to such an extent that the switch element 1a can be driven. Is adjusted and input to the gate electrode. Further, a turn-on common mode determination circuit 30 that determines whether or not noise reduction in the common mode (common mode) at the turn-on time is required, and a turn-on differential mode determination that determines whether noise reduction in the differential mode (differential mode) at the turn-on time is required. The circuit 31 includes a noise mode determination circuit 5 having a turn-off common mode determination circuit 32 that determines whether or not common mode noise reduction is required at the time of turn-off, and a noise mode determination circuit according to the load current detected by the current sensor 6 5 determines a noise mode to be reduced for each of turn-on and turn-off. The output from the noise mode determination circuit 5 is input to the switching time adjustment circuit 4, and the switching time adjustment circuit 4 charges and discharges the gate electrode so as to reduce noise in the noise mode to be reduced for each of turn-on and turn-off. To adjust the switching time.
In this case, the switching control of the switch element 1a has been described. However, the switch element 1b has the same configuration and similarly adjusts the switching time.

  A half-bridge inverter configured by connecting two switch elements 1a and 1b in which diodes 2a and 2b are connected in reverse parallel as shown in FIG. 1 is, for example, a motor drive system 41 as shown in FIG. It is a part of power converter device which constitutes. As shown in FIG. 2, the power converter includes a converter unit 42 that converts three-phase AC power from an AC power supply 45 into DC power, a smoothing capacitor 43 that smoothes the output of the converter unit 42, and DC power from the smoothing capacitor 43. And an inverter unit 44 that converts the power into three-phase AC power. Each phase of the inverter unit 44 is configured by connecting in series two switch elements 1a and 1b having diodes 2a and 2b connected in antiparallel, and supplies power to the motor 40 that is an inductive load.

  The EMI noise radiated in the motor drive system 41 shown in FIG. 2 will be described. There are two types of EMI noise, common mode and differential mode, and noise is radiated from these loops. The differential mode loop is a loop that flows from the positive electrode of the smoothing capacitor 43 to the negative electrode of the smoothing capacitor 43 through the inverter unit 44. The common mode loop is a loop that passes from the output terminal of the inverter unit 44 through the motor 40, passes through the parasitic capacitance between the motor 40 and the ground, passes through the ground, and returns to the inverter unit 40.

  The causes of noise radiated from these loops are steep current changes and voltage changes that occur when the switching elements 1a and 1b constituting the inverter unit 44 perform a switching operation. In both the differential mode and the common mode, the radiated noise is proportional to the current change rate of the current flowing in the loop. The current change rate of the differential mode loop is the current change rate itself of the current flowing between both terminals of the switch elements 1a and 1b, that is, between the collector and the emitter. The current change rate of the common mode loop is a current change rate of a current flowing through the common mode loop when a voltage between both terminals of the switch elements 1a and 1b, that is, a collector-emitter voltage is applied to the common mode loop. • Proportional to voltage change rate between emitters.

  In a power converter that supplies power to an inductive load such as the motor 40, the period during which the current between the two terminals changes during switching of the switch elements 1a, 1b is different from the period during which the voltage changes. In this embodiment, as described above, the switching time is adjusted by the switching time adjustment circuit 4, but when the differential mode noise is reduced, the current during the period in which the current between both terminals of the switch elements 1a and 1b changes. When adjustment is performed to reduce the change rate and common mode noise is reduced, adjustment is performed to reduce the voltage change rate during the period in which the voltage between both terminals of the switch elements 1a and 1b changes. Details of the adjustment of the switching time will be described later.

Next, FIG. 3A shows the relationship between the magnitude of each noise in the common mode and the differential mode and the load current. As shown in FIG. 3A, the characteristics are different depending on the noise mode and the turn-on and turn-off differences.
First, the differential mode noise will be described. Usually, an antiparallel diode of an IGBT switch element is composed of a PiN diode, and a large recovery current flows through the diode when the switch element is turned on, that is, when the diode is OFF. Since such a phenomenon does not occur when the switch element is turned off, the noise in the differential mode is larger when the switch element is turned on than when the switch element is turned on, and it is not usually necessary to consider the noise at the turn-off time. In addition, the differential mode noise increases as the load current increases.

  Next, common mode noise will be described. As described above, common mode noise is proportional to the voltage change rate between both terminals of the switch element, that is, noise is generated during a period in which the voltage changes. The voltage between the two terminals of the switch element changes depending on the load current depending on the load current when turning on and when turning off. The voltage change rate at turn-on increases as the load current decreases, and the voltage change rate at turn-off increases as the load current increases, contrary to the turn-on. Therefore, the common mode noise at turn-on increases as the load current decreases, and the common mode noise at turn-off increases as the load current increases.

In this embodiment, the magnitude of each noise in the common mode at turn-on, the common mode at turn-off, and the differential mode at turn-on is obtained in advance by using a measurement device in the time domain such as a real-time spectrum analyzer. To do. The load current value when the common mode noise when the switch element is turned on matches the differential mode radiation noise when the switch element is turned on is the first judgment value I _A , and the load current when the common mode noise matches the common mode noise when the switch element is turned off value as a second judgment value I _B, as shown in FIG. 3 (b), control to reduce the noise of the noise mode of the area indicated by the solid line. That is, when the load current is less than I _A, reduces the common mode noise at the time of turn-on, when the load current is smaller than the larger I _B than I _A, the common mode at the turn-on time, reduce the noise of the differential mode, load current when greater than I _B, the differential mode at the turn-on time is controlled so as to reduce the common mode noise at the time of turn-off.

FIG. 4 shows details of the circuit configuration of the power conversion device shown in FIG.
The turn-on common mode determination circuit 30, the turn-on differential mode determination circuit 31, and the turn-off common mode determination circuit 32 in the noise mode determination circuit 5 are configured by comparators 24, 26, and 28 and reference voltage sources 25, 27, and 29, respectively. . In turn-on common-mode decision circuit 30, a reference voltage source 25 of the comparator 24, a voltage corresponding to a second determination value I _B is set, when the magnitude of the load current inputted from the current sensor 6 is less than I _B A signal for determining that the common mode is a noise mode to be reduced at turn-on is output. In turn-on differential mode decision circuit 31, a reference voltage source 27 of the comparator 26, the voltage corresponding to the first determination value I _A is set, when the magnitude of the load current inputted from the current sensor 6 is greater than I _A A signal for determining that the differential mode is a noise mode to be reduced at turn-on is output. In turn-off common mode determination circuit 32, a reference voltage source 29 of the comparator 28, a voltage corresponding to a second determination value I _B is set, when the magnitude of the load current inputted from the current sensor 6 is greater than I _B A signal for determining that the common mode is a noise mode to be reduced at turn-off is output.

The amplifier 3 to which a gate command is input includes a preamplifier 7 and two MOSFETs 8 and 9. The gate command is amplified by the preamplifier 7, and when an on command is given to the switch element 1a, the MOSFET 8 is turned on and the switch element 1a is turned on. When an OFF command is given to, MOSFET 9 is turned on.
The switching time adjustment circuit 4 includes a variable gate resistance circuit 4a and a control signal generation circuit 4b that controls the gate resistance of the variable gate resistance circuit 4a. In the variable gate resistance circuit 4a, a series body of a resistor 12 and a P-type MOSFET 10 is connected in parallel with the gate resistor 13 when the switch element 1a is turned on, and the gate resistor 15 when the switch element 1a is turned off. A series body of the resistor 14 and the N-type MOSFET 11 is connected in parallel. The control signal generation circuit 4b outputs an on-time control signal 21a that is a control signal at turn-on and an off-time control signal 23a that is a control signal at turn-off. The on-time control signal 21a is the gate of the P-type MOSFET 10. The P-type MOSFET 10 is driven by being input to the electrode, and the OFF-time control signal 23 a is input to the gate electrode of the N-type MOSFET 11 to drive the N-type MOSFET 11.

When the P-type MOSFET 10 is turned off at the time of turn-on, the gate resistance becomes high only by the gate resistance 13, and the charge rate to the gate electrode is slowed down. On the other hand, when the P-type MOSFET 10 is on, the gate resistance is low due to the parallel resistance of the gate resistance 13 and the resistance 12, and the gate electrode is charged at high speed by the gate current flowing through the gate resistance 13 and the resistance 12. The time required is short.
Similarly, when the N-type MOSFET 11 is turned off at the time of turn-off, the gate resistance becomes high only by the gate resistance 15 and the discharge rate from the gate electrode becomes slow. On the other hand, when the N-type MOSFET 11 is in the on state, the gate resistance is low due to the parallel resistance of the gate resistance 15 and the resistance 14, and the gate electrode is discharged at high speed by the current flowing through the gate resistance 13 and the resistance 12, and switching is performed. The time required is short.

  The control signal generation circuit 4b includes delay circuits 16 and 22 that delay the gate command for a predetermined time, a delay circuit 19 that delays the gate command via the NOT circuit 18 for a predetermined time, AND circuits 17 and 20, an OR circuit 21, and a NAND circuit 23. The on-state control signal 21 a for driving the P-type MOSFET 10 is output from the OR circuit 21, and the off-time control signal 23 a for driving the N-type MOSFET 11 is output from the NAND circuit 23. Each delay circuit 16, 19, 22 receives a gate command and an output from the current sensor 6, and uses a delay time set according to the load current.

Next, the operation at turn-on and turn-off will be described.
First, when the load current is less than the first determination value I _A, the operation at the time of turn-on will be described with reference to the timing chart of FIG. Note that the first determination value I _A <the second determination value I _B.
When a gate command (turn-on command) as shown in FIG. 5A is given, the gate command is amplified by the preamplifier 7, turns on the MOSFET 8, and the gate electrode of the switch element 1a is charged. When the gate voltage (not shown) exceeds the threshold voltage, the collector current flowing between the collector and the emitter of the switch element 1a starts to rise, resulting in a waveform as shown in FIG. When the collector current reaches a peak, the collector-emitter voltage decreases as shown in FIG.

The delay circuit 16 delays the gate command for a predetermined time, and the delay circuit 19 delays the inversion command for the gate command for a predetermined time. The delay time (predetermined time) of the delay circuits 16 and 19 is set to a time from when the gate command is switched on / off until the collector current reaches a peak. Since the time until the collector current reaches the peak increases in proportion to the load current, the delay circuits 16 and 19 set a delay time according to the magnitude of the load current input from the current sensor 6. The set value of the delay time is as shown in FIG.
Reference voltage of the comparator 26 of the turn-on differential mode decision circuit 31 is a voltage corresponding to _{I A,} since the load current is less than _{I A,} the output of the comparator 26 remains LOW, the output of the AND circuit 20 is also LOW of It remains.

Since the reference voltage of the comparator 24 of the turn-on common mode determination circuit 30 is a voltage corresponding to I _B and the load current is smaller than I _A (<I _B ), the output of the comparator 24 is HIGH. Since the output of the delay circuit 16 changes from LOW to HIGH when the collector current reaches the peak, the output of the AND circuit 17 also changes from LOW to HIGH when the collector current reaches the peak. . The output of the AND circuit 17 is a signal for controlling the voltage change rate of the collector-emitter voltage at turn-on. The on-time control signal 21a, which is the output of the OR circuit 21 having the outputs of the two AND circuits 17 and 20 as inputs, is LOW until the collector current reaches a peak, similarly to the output of the AND circuit 17, and reaches the peak. From LOW to HIGH.

The collector current increases due to the gate command (turn-on command), and when the collector current reaches the peak, the collector-emitter voltage decreases. Therefore, by setting the on-time control signal 21a for driving the P-type MOSFET 10 to LOW until the collector current reaches a peak, the P-type MOSFET 10 continues to be on during the period when the collector current changes, The charging speed is not slowed and the switching of the switch element 1a is not slowed unnecessarily. Since the on-time control signal 21a changes from LOW to HIGH when the collector current reaches a peak, the P-type MOSFET 10 is turned off during the subsequent period when the collector-emitter voltage changes. As a result, the gate current flows only through the gate resistor 13, while the charge rate to the gate electrode is slowed down, and the collector-emitter voltage of the switch element 1a gradually decreases.
As described above, the load current is in the turn-on operation of the switching element 1a when less than the first determination value I _A, the switching time so as to reduce the voltage change rate of the collector-emitter voltage is adjusted, the common mode noise Is reduced.

Then, when the load current is greater than the second determination value I _B, the operation at the time of turn-on will be described with reference to the timing chart of FIG.
When a gate command (turn-on command) as shown in FIG. 7A is given, the gate command is amplified by the preamplifier 7 to turn on the MOSFET 8, and the gate electrode of the switch element 1a is charged. When the gate voltage (not shown) exceeds the threshold voltage, the collector current flowing between the collector and the emitter of the switch element 1a begins to rise, resulting in a waveform as shown in FIG. When the collector current reaches a peak, the collector-emitter voltage decreases as shown in FIG.

In the delay circuits 16 and 19, the time from when the gate command is switched on / off until the collector current reaches a peak is set as a delay time according to the magnitude of the load current input from the current sensor 6. The delay circuit 16 delays the gate command, and the delay circuit 19 delays the inversion command of the gate command.
Reference voltage of the comparator 24 turns on the common mode judging circuit 30 is a voltage corresponding to _{I B,} the load current for greater than _{I B,} the output of the comparator 24 remains LOW, the output of the AND circuit 17 is also LOW of It remains.

Since the reference voltage of the comparator 26 of the turn-on differential mode determination circuit 31 is a voltage corresponding to I _A and the load current is larger than I _B (> I _A ), the output of the comparator 26 is HIGH. Since the output of the delay circuit 19 changes from HIGH to LOW when the collector current reaches a peak, the output of the AND circuit 20 is also HIGH until the collector current reaches a peak, and from HIGH to LOW when the peak reaches the peak. . The output of the AND circuit 20 is a signal for controlling the current change rate between the collector and the emitter at the time of turn-on. The on-time control signal 21a, which is the output of the OR circuit 21 having the outputs of the two AND circuits 17 and 20 as inputs, reaches HIGH and the peak until the collector current reaches the peak, similarly to the output of the AND circuit 20. Sometimes it goes from HIGH to LOW.

The collector current increases due to the gate command (turn-on command), and when the collector current reaches the peak, the collector-emitter voltage decreases. For this reason, the on-time control signal 21a for driving the P-type MOSFET 10 is set to HIGH until the collector current reaches a peak, so that the P-type MOSFET 10 is turned off during the period in which the collector current changes. As a result, the gate current flows only through the gate resistor 13, while the charge rate to the gate electrode is slowed, and the collector current of the switch element 1a rises gently. Since the on-time control signal 21a changes from HIGH to LOW when the collector current reaches a peak, the P-type MOSFET 10 is turned on in the subsequent period when the collector-emitter voltage changes, and the charge rate to the gate electrode The switching of the switch element 1a is not unnecessarily delayed.
As described above, in the turn-on operation of the switching element 1a when the load current is greater than the second determination value I _B, the switching time is adjusted so as to reduce the current rate of change of the collector current, the differential mode noise can be reduced The

Then, when the magnitude of the load current is between the first judgment value I _A and the second determination value I _B, the operation at the time of turn-on it will be described with reference to the timing chart of FIG.
When a gate command (turn-on command) as shown in FIG. 8A is given, the gate command is amplified by the preamplifier 7, turns on the MOSFET 8, and the gate electrode of the switch element 1a is charged. When the gate voltage (not shown) exceeds the threshold voltage, the collector current flowing between the collector and the emitter of the switch element 1a starts to rise, resulting in a waveform as shown in FIG. When the collector current reaches a peak, the collector-emitter voltage decreases as shown in FIG.

In the delay circuits 16 and 19, the time from when the gate command is switched on / off until the collector current reaches a peak is set as a delay time according to the magnitude of the load current input from the current sensor 6. The delay circuit 16 delays the gate command, and the delay circuit 19 delays the inversion command of the gate command.
Reference voltage of the comparator 24 turns on the common mode judging circuit 30 is a voltage corresponding to _{I B,} the load current is smaller than _{I B,} the output of the comparator 24 is HIGH, the output of the AND circuit 17, the delay circuit 16 Similar to the output, it is LOW until the collector current reaches a peak, and when it reaches the peak, it goes from LOW to HIGH. The reference voltage of the comparator 26 of the turn-on differential mode decision circuit 31 is a voltage corresponding to _{I A,} since the load current is greater than _{I A,} the output of the comparator 26 is HIGH, the output of the AND circuit 20, the delay circuit Similarly to the output of 19, it is HIGH until the collector current reaches the peak, and when it reaches the peak, it goes from HIGH to LOW.

The on-time control signal 21a, which is the output of the OR circuit 21 that receives the outputs of the two AND circuits 17 and 20, continues to be in a HIGH state. Therefore, the P-type MOSFET 10 is turned off both in the current change period in which the collector current increases and in the subsequent voltage change period in which the collector-emitter voltage decreases. As a result, the gate current flows only through the gate resistor 13 and the charge rate to the gate electrode is slowed, the collector current rises gently, and then the collector-emitter voltage gently falls.
As described above, the magnitude of the load current at the turn-on operation of the first determination value I _A and the second determination value switching element 1a when it is between I _B, to reduce the current change rate of the collector current At the same time, the switching time is adjusted so as to reduce the voltage change rate of the collector-emitter voltage, and both common mode noise and differential mode noise are reduced.

Then, when the load current is less than the second determination value I _B, the operation at the time of turn-off will be described with reference to the timing chart of FIG.
When a gate command (turn-off command) as shown in FIG. 9A is given, the gate command is amplified by the preamplifier 7, turns on the MOSFET 9, and the gate electrode of the switch element 1a is discharged. When the gate voltage (not shown) becomes equal to or lower than the threshold voltage, the collector-emitter voltage of the switch element 1a starts to increase, and then the collector current decreases (FIGS. 9B and 9C).
Reference voltage of the turn-off common mode determination circuit 32 of the comparator 28 is a voltage corresponding to I _B. Since the load current is less than _{I B,} the output of the comparator 28 remains LOW, OFF-time control signal 23a which is the output of NAND circuit 23 continues the HIGH state. For this reason, the N-type MOSFET 11 is in an on state and does not slow down the charge rate to the gate electrode.

Then, when the load current is greater than the second determination value I _B, the operation at the time of turn-off will be described with reference to the timing chart of FIG.
When a gate command (turn-off command) as shown in FIG. 10A is given, the gate command is amplified by the preamplifier 7, turns on the MOSFET 9, and the gate electrode of the switch element 1a is discharged. When the gate voltage (not shown) becomes equal to or lower than the threshold voltage, the collector-emitter voltage of the switch element 1a starts to rise, and then the collector current falls (FIG. 10 (b), FIG. 10 (c)).
The delay circuit 22 delays the gate command for a predetermined time, and the delay time of the delay circuit 22 is set to a time from when the gate command is switched on / off to when the collector current starts to decrease. Since the time until the collector current starts to decrease is inversely proportional to the magnitude of the load current, the delay circuit 22 sets a delay time according to the magnitude of the load current input from the current sensor 6. The set values are as shown in FIG.

Reference voltage of the turn-off common mode determination circuit 32 of the comparator 28 is a voltage corresponding to I _B. Since the load current is greater than _{I B,} the output of the comparator 28 is HIGH, OFF-time control signal 23a which is the output of the NAND circuit 23 becomes a signal obtained by inverting the output of the delay circuit 22. That is, it is LOW until the timing when the collector current starts to decrease, and from LOW to HIGH at that timing.

By the gate command (turn-off command), the collector-emitter voltage starts to increase first, and then the collector current decreases. Therefore, when the off-time control signal 23a for driving the N-type MOSFET 11 is set to LOW until the collector current starts to decrease, the N-type MOSFET 11 is turned off during the period in which the collector-emitter voltage changes. During this time, the current discharged from the gate electrode flows only through the gate resistor 15, the discharge speed of the gate electrode is slowed, and the collector-emitter voltage of the switch element 1a rises gently. Since the off-time control signal 23a changes from LOW to HIGH at the timing when the collector current starts to decrease, the N-type MOSFET 11 is turned on during the period when the collector current changes, and the discharge rate from the gate electrode is not slowed down. The switching of the switch element 1a is not slowed unnecessarily.
As described above, the load current is in the turn-off operation of the switching element 1a when the second determination value larger than I _B, is switching control as to reduce the voltage change rate of the collector-emitter voltage, reducing the common mode noise Is done.

As described above, in this embodiment, the noise to be reduced for each of the turn-on and the turn-off using the characteristic that each noise of the common mode and the differential mode changes according to the load current when the switching element is switched. The mode is determined by the noise mode determination circuit 5. For this reason, it is possible to accurately determine a problematic noise mode among EMI noises generated at the time of switching. Since the switching time adjustment circuit 4 reduces the noise of the mode determined by the noise mode determination circuit 5, it surely reduces the noise to be reduced and does not unnecessarily slow the switching speed.
In order to reduce the common mode noise, the voltage change rate between the collector and the emitter of the switching element is reduced, and in order to reduce the differential mode noise, the current change rate of the collector current is reduced. For this reason, it is possible to accurately control only factors that have a large influence on noise generation, and it is possible to reliably reduce EMI noise without unnecessarily slowing the switching speed, and to reduce both EMI noise and switching loss. it can.

In addition, in order to selectively control the voltage change rate and current change rate between the collector and the emitter of the switch element, the period during which the voltage or current changes is selected to slow down the charge / discharge rate of the gate electrode during that period. Therefore, the above effect can be achieved easily and reliably without requiring a complicated circuit configuration.
In addition, by using a delay circuit in which a delay time is set according to the load current, the voltage or current changes during the period from when the gate command is switched to when the predetermined delay time elapses and thereafter. Since the period is selected, it is easy to select each period.

  In the above embodiment, the period from when the gate command is switched to when the predetermined delay time elapses and the period after that is selected as the period during which the voltage or current changes. It is also possible to detect a point at which the tendency changes and select a period before and after that point. That is, the peak point of the collector current is detected at turn-on, and the point at which the collector current starts to decrease is detected at turn-off. Thereby, the voltage change period and the current change period can be specified more accurately, and the effect of reliably reducing EMI noise without unnecessarily slowing the switching speed is further enhanced.

  In the above embodiment, the control of the switching element 1a in the three-phase inverter is shown. However, the present invention can be widely applied to a power conversion device having a semiconductor switching element that is turned on and off at high speed to supply power to an inductive load. Has the same effect.

The said embodiment is a case where the rated output of the inverter which is a power converter device is constant. When the voltage class of the inverter is constant and the rated output changes, the noise characteristic curve shown in FIG. 3 changes. For example, when the rated output increases, the noise characteristic curve changes as shown in FIG. 12, so the first and second determination values I _A and I _B used for determination in the noise mode determination circuit 4 are also changed.

3 and 12, the differential mode noise at turn-on is larger than the common mode noise at turn-off. However, the present invention is not limited to this, and the common mode noise at turn-off is turned on as shown in FIG. Sometimes it is larger than the differential mode noise of the hour. In this case, the second determination value _{I B} <first judgment value _{I A.}

Furthermore, in the above embodiment, the second determination value I _B as the determination value to reduce the common mode noise, common mode noise at the time of turn-on even when the load current is less than the second determination value I _B was controlled so as to reduce the first determination value I _a as a determination value for reducing noise during turn, the common mode noise at the time of turn-on, when the load current is less than the first determination value I _a You may control so that it may reduce.

Further, control may be performed so that each noise in the common mode at turn-on, the differential mode at turn-on, and the common mode at turn-off is reduced when a predetermined noise regulation level is exceeded. As shown in FIG. 14, a predetermined noise regulation level is set, and the load current value when each noise in the common mode at turn-on, the differential mode at turn-on, and the common mode at turn-off matches the noise regulation level, The first, second, and third determination values I _C , I _D , and _IE are used. The turn-on common mode determination circuit 30, the turn-on differential mode determination circuit 31, and the turn-off common mode determination circuit 32 in the noise mode determination circuit 5 are noises to be reduced using I _C , I _D , and _IE as the determination values, respectively. Determine the mode. As a result, the common mode noise at turn-on is reduced when the load current is smaller than I _C , the differential mode noise at turn-on is reduced when the load current is greater than _ID , and the common mode noise at turn-off is Noise is reduced when the magnitude of the load current is greater than _IE . Thereby, noise exceeding a desired noise regulation level can be reliably reduced.

Moreover, in the said embodiment, IGBT1a, 1b by which diode 2a, 2b was connected in reverse parallel was used as a semiconductor switching element, and the PiN diode was used for diode 2a, 2b. The semiconductor switching element may be a MOSFET, and in the MOSFET, it is easy to independently control a current change and a voltage change between the source and drain between both terminals, and the switching control according to the first embodiment can be effectively applied. The current change at the turn-off time of the IGBT can hardly be controlled by the gate electrode, and is almost constant once the voltage, current and main circuit conditions are determined. On the other hand, in the case of a MOSFET, for example, if the gate resistance is changed, the current change at turn-off can be changed. Since the differential mode noise at turn-off is lower than the noise of other modes, it has not been controlled in the above embodiment, but in the case of MOSFET, the differential mode noise is controlled at turn-off. As an object, it is also possible to reduce the noise to a lower level.
If the diode connected in reverse parallel to the MOSFET is a Schottky barrier diode, a large recovery current does not flow when the diode is turned off, and there is no influence of surge current. For this reason, even if the current change rate is changed, the voltage change rate is not affected, and the current change and the voltage change can be independently controlled with higher accuracy.

It is a schematic block diagram which shows a part of power converter device by Embodiment 1 of this invention. It is a block diagram of the motor drive system by Embodiment 1 of this invention. It is a figure which shows the characteristic curve of the radiation noise by Embodiment 1 of this invention. It is a figure which shows the detailed circuit structure of FIG. It is a timing chart which shows the operation | movement at the time of turn-on of the power converter device by Embodiment 1 of this invention. It is a figure which shows the relationship between the load current by Embodiment 1 of this invention, and the delay time set. It is a timing chart which shows the operation | movement at the time of turn-on of the power converter device by Embodiment 1 of this invention. It is a timing chart which shows the operation | movement at the time of turn-on of the power converter device by Embodiment 1 of this invention. It is a timing chart which shows the operation | movement at the time of turn-off of the power converter device by Embodiment 1 of this invention. It is a timing chart which shows the operation | movement at the time of turn-off of the power converter device by Embodiment 1 of this invention. It is a figure which shows the relationship between the load current by Embodiment 1 of this invention, and the delay time set. It is a figure which shows the characteristic curve of the radiation noise by another example of Embodiment 1 of this invention. It is a figure which shows the characteristic curve of the radiation noise by another example of Embodiment 1 of this invention. It is a figure explaining the judgment value of radiation noise reduction by another example of Embodiment 1 of this invention.

Explanation of symbols

1a, 1b semiconductor switching element, 2a, 2b diode,
4 switching time adjustment circuit, 4a variable gate resistance circuit, 4b control signal generation circuit,
5 Noise mode determination circuit, 6 Current sensor, 21a Control signal when ON,
23a OFF control signal, 30 turn-on common mode determination circuit,
31 Turn-on differential mode determination circuit,
32 turn-off common mode determination circuit, 40 load (motor),
I _A , I _B first and second determination values, I _C , I _D , _IE first, second and third determination values.

Claims (10)

In a power conversion device that includes a semiconductor switching element that is driven and controlled by a gate electrode and supplies power to an inductive load,
A current sensor for detecting the load current;
A noise mode determination circuit that determines a noise mode to be reduced among radiation noises having a differential mode and a common mode for each of turn-on and turn-off of the semiconductor switching element based on the output of the current sensor;
A switching time adjustment circuit for adjusting a switching time of the semiconductor switching element by changing a charge / discharge speed of the gate electrode by switching a gate command;
The switching time adjusting circuit selectively reduces a current change rate and a voltage change rate between both terminals of the semiconductor switching element according to a noise mode determined by the noise mode determination circuit. Conversion device. When the noise mode determined by the noise mode determination circuit has a differential mode, the switching time adjustment circuit reduces a current change rate between both terminals of the semiconductor switching element,
2. The switching time adjusting circuit reduces a voltage change rate between both terminals of the semiconductor switching element when a noise mode determined by the noise mode determination circuit has a common mode. The power converter described. The switching time adjustment circuit is
A period during which the current changes at turn-on and turn-off of the semiconductor switching element is selected, and the rate of current change between both terminals of the semiconductor switching element is reduced by changing the charge / discharge speed of the gate electrode slowly during the period. ,
A period during which the voltage changes at turn-on and turn-off of the semiconductor switching element is selected, and the rate of voltage change between the two terminals of the semiconductor switching element is reduced by slowly changing the charge / discharge speed of the gate electrode during the period. The power conversion device according to claim 1, wherein the power conversion device is a power conversion device. The selection of the period during which the current or voltage changes is to select one of the period from when the gate command is switched to when a predetermined time elapses and the period after that, and the predetermined time is applied to the current sensor. The power conversion device according to claim 3, wherein the power conversion device is set according to the load current detected. Means for detecting a point at which the current change tendency changes from when the gate command is switched, and the selection of the period during which the current or voltage is changed is from the period from the switching of the gate command to the point detection and thereafter The power conversion device according to claim 3, wherein one of the periods is selected. The power conversion device according to claim 1, wherein the charge / discharge speed of the gate electrode is changed by changing a gate resistance of the gate electrode. The noise mode determination circuit is
The load current value when the common mode radiation noise at the turn-on time of the semiconductor switching element matches the differential mode radiation noise at the turn-on time is the first judgment value, the load when the common mode radiation noise at the turn-off time coincides Let the current value be the second judgment value,
When the magnitude of the load current detected by the current sensor is smaller than the first or second determination value, the common mode is determined as a noise node to be reduced at turn-on,
When the magnitude of the load current detected by the current sensor is larger than the first determination value, the differential mode is determined as a noise node to be reduced at turn-on,
7. The method according to claim 1, wherein when the magnitude of the load current detected by the current sensor is larger than the second determination value, the common mode is determined as a noise node to be reduced at turn-off. The power converter device of Claim 1. The noise mode determination circuit is
The load current values when the common mode radiation noise at the turn-on time of the semiconductor switching element, the differential mode radiation noise at the turn-on time, and the common mode radiation noise at the turn-off time coincide with a predetermined noise level are first to third. The judgment value of
When the magnitude of the load current detected by the current sensor is smaller than the first determination value, the common mode is determined as a noise node to be reduced at turn-on,
When the magnitude of the load current detected by the current sensor is greater than the second determination value, the differential mode is determined as a noise node to be reduced at turn-on,
7. The method according to claim 1, wherein when the magnitude of the load current detected by the current sensor is larger than the third determination value, the common mode is determined as a noise node to be reduced at turn-off. The power converter device of Claim 1. Two combinations of diodes connected in reverse parallel to the semiconductor switching element are connected in series, the connection point is connected to the load, and the current sensor is arranged between the connection point and the load. The power conversion device according to claim 1, wherein the power conversion device is characterized in that The power converter according to claim 9, wherein a MOSFET is used as the semiconductor switching element, and a Schottky barrier diode is used as the diode.

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