JP2009117869A - Method of manufacturing functional element package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive functional element package having an improved manufacturing yield by providing bonding construction superior in solder wettability and bonding property, in a structure for air-sealing a functional element at a wafer level with solder bonding. <P>SOLUTION: The method of manufacturing functional element package includes: a step of preparing a first Si substrate 5 having a recessed portion 25 formed on the substrate, a metallized portion 22B formed on the surface of the substrate including the recessed portion, and a soldered portion 23 formed on the metallized portion; a step of preparing a second Si substrate 1 having a metallized portion 22A formed on the substrate; a step of making the first Si substrate and the second Si substrate opposing each other; and a step of making the opposed first and second Si substrates close to each other and bonding them to each other. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention is based on MEMS (Micro Electro Mechanical Systems) technology or the like, and a Si substrate (here, Si substrate is a Si wafer, SiO ₂ , or a Si / SiO ₂ / Si sandwich structure having an SiO ₂ insulating layer inside). In addition, the present invention relates to a functional element package such as various sensors and actuators that are manufactured by etching (including the same wafers) (hereinafter the same).

  Various sensors using MEMS technology, high frequency filters, functional elements such as mirror functional elements are manufactured. For example, in an acceleration sensor, generally, a structure including a weight is formed by making full use of an etching technique, and a capacitance detection at an electrode connected to the weight or a strain detection element formed on a thin beam connected to the weight. By reading the resistance change, the acceleration applied to the weight can be read. In the high-frequency filter, for example, in a structure called FBAR (Film Bulk Acoustic Resonator), a cavity is formed on the Si substrate, and an AlN piezoelectric film sandwiched between electrodes is formed so as to straddle the cavity. In the mirror device, an Si mirror is driven, and an image is generated by adjusting the optical path. Any MEMS functional element includes a movable part such as a weight, a piezoelectric film, or a mirror. Such operating characteristics of the movable part are naturally influenced by the atmosphere surrounding the movable part. Therefore, the air pressure in the space where the movable part exists needs to be kept constant, and hermetic sealing is required.

  Until now, ceramic packages and lids have been used to take out electrical signals from the functional elements while performing hermetic sealing. In this ceramic package, an electrode pad for connecting wire bonding is formed inside, and wiring is taken out from the inside of the ceramic package so as to be connected to this electrode and not to leak. Outside the ceramic package, an electrode pad connected to the wiring coming out from the inside is formed.

  However, in recent years, there is a strong demand for downsizing and cost reduction, and packaging at the wafer level is required as a means for realizing it. Packaging at the wafer level is a method of completing packaging by bonding another wafer for sealing to a wafer on which various functional elements are formed. Thousands or tens of thousands of functional elements can be collectively sealed by bonding the wafers, which is advantageous for cost reduction. In addition, since a precise sealing portion can be designed by photolithography technology, it is advantageous for downsizing of the package.

  Several new methods, such as direct bonding of Si-Si and anodic bonding of glass wafer and Si, have been announced as means for bonding wafers, but they have been used for packaging semiconductor components and have a proven track record. Examples of the joining method include solder joining.

  Here, as a technique disclosed so far, two methods, that is, not a wafer level package but a method of packaging a functional element by solder bonding and a method of packaging by solder at a wafer level will be described.

  The following Patent Document 1 is particularly suitable for a package that hermetically seals a high-frequency IC that forms an oscillation circuit, and even if the thickness of the cap is increased to increase the bonding area with the header side as a countermeasure against vibration, sufficient A package structure is described that achieves the desired hermetic seal while maintaining the desired bond strength. As a method, double annular concave grooves are provided on the inner peripheral side and outer peripheral side of the joint surface of the header joined to the cap, and the inner joint header and cap surrounded by the inner and outer annular concave grooves are brazed. And a header and a cap that are externally joined to the outer side of the annular groove on the outer peripheral side are welded by laser welding. It is shown that the inner and outer circumferential annular grooves formed in the joint are grooves for preventing the brazing material from flowing into the high frequency IC portion.

  Further, in Patent Document 2 below, an object wafer in which a plurality of active portions of a microsensor or a microactuator are formed on a wafer, a lid, and a lid are provided in order to provide a micropackage in which large-diameter wafers are well bonded. A method is described in which the member is hermetically sealed around each active portion of the device wafer by a joint. It is disclosed that solder is used for this joining.

JP-A-10-303323 JP2004-235440

  Patent Document 1 is characterized in that the protrusion of the brazing material is suppressed by forming annular concave grooves on the inner and outer periphery of the joint between the header and the cap. However, it is not considered to realize hermetic sealing of the functional elements by bonding that secures the wettability of the bonding material at the wafer level.

  Japanese Patent Laid-Open No. 2003-228561 discloses solder packaging at the wafer level, but in order to achieve hermetic sealing with a high yield, sufficient consideration is not given to ensuring solder wettability. In the packaging of microsensors and microactuators, it is generally difficult to use a flux at the time of soldering in order to prevent dust and foreign matters from entering. Therefore, it is essential to achieve sufficient solder wettability and solder bonding without flux.

  The present invention has been made to solve the above-described problems.

In order to solve the above problems, the present invention provides:
A functional element;
A first Si substrate having a concave portion with metallization on the inner surface;
A second Si substrate that has been metallized at a position facing the recess,
Solder is melted and connected between the metallization applied to the inner surface of the recess formed in the first Si substrate and the metallization applied to the position of the second Si substrate facing the recess. The functional element is hermetically sealed by bonding the first Si substrate and the second Si substrate.

  Further, the functional element is formed on the first Si substrate surrounded by the recess.

  The functional element is formed on the second Si substrate surrounded by metallization provided at a position facing the concave portion.

  Further, the concave portions are formed in a plurality of rows.

  Further, the concave portion is a V-shaped groove, and a mountain-shaped convex portion is formed by a side surface of the adjacent concave portion.

  Moreover, the depth of the said recessed part is several micrometers-20 micrometers, It is characterized by the above-mentioned.

  The solder is a solder material mainly composed of an alloy such as Au—Sn, Sn—Ag, Sn—Cu, Sn—Ag—Cu, Sn—Zn, Sn—Pb, Sn—Bi. And

  Further, metallization is formed outside the concave portion on the surface of the first Si substrate, and metallization formed on the inner surface of the concave portion is connected to the metallization outside the concave portion on the surface of the first Si substrate. It is characterized by that.

  In addition, the metallization of the inner surface of the recess of the first Si substrate, the metallization of the outer surface of the recess of the first Si substrate, and the position of the second Si substrate facing the recess are performed. The functionalized element is hermetically sealed by melting and connecting solder between the metallized layers and joining the first Si substrate and the second Si substrate. In addition, the metallization is formed on the surface of a thin film containing at least one of metals such as Ti, Cr, W, and V formed as an adhesive layer with the Si substrate, in order to suppress reaction with the solder, Ni, Cu , Pt, and Pd, and a Au film for preventing oxidation is formed on the surface of the thin film.

Further, the first Si substrate and the second Si substrate are Si wafers or wafers having a Si / SiO ₂ / Si sandwich structure having a SiO ₂ insulating layer inside.

Also, a functional element having a package structure in which two Si substrates each having a plurality of functional elements formed on either one are overlapped and joined together by soldering and hermetically sealed at a wafer level, and then individually cut and separated A package,
A Si substrate on the functional element side provided with a recess formed in a row or a plurality of rows continuously so as to surround one separated functional element and having a metallized surface;
A lid-side Si substrate that is metallized on the surface facing the region in which the concave portion is formed when superimposed on the functional element-side Si substrate;
The surface where the metallization of the concave portion provided on the Si substrate on the functional element side and the surface facing the region where the concave portion of the Si substrate on the lid side is formed are joined by solder, It has a package structure in which the one functional element is hermetically sealed.

In addition, the Si substrate on the functional element side having a functional element, provided with a concave portion formed so as to surround the functional element and subjected to metallization on the surface,
A lid-side Si substrate that is metallized on the surface of the functional element-side Si substrate facing the concave portion;
A first electrode metallization in a concave shape electrically connected to the functional element and provided in the Si substrate on the functional element side inside the concave portion;
A second electrode metallization provided at a position of the lid-side Si substrate facing the first electrode metallization;
A through hole provided penetrating in the position of the Si substrate on the lid side facing the first electrode metallization,
The surface of the functional element side Si substrate provided with the metallization of the concave portion and the surface of the lid side Si substrate facing the region where the concave portion is formed, and the functional element side Si The first electrode metallization provided on the substrate and the second electrode metallization provided on the Si substrate on the lid side are joined by solder so that the functional element is hermetically sealed. It is characterized by.

Also, a functional element having a package structure in which two Si substrates each having a plurality of functional elements formed on either one are overlapped and joined together by soldering and hermetically sealed at a wafer level, and then individually cut and separated A package,
A Si substrate on the functional element side, the surface of which is metallized continuously so as to surround one separated functional element;
A lid side provided with a recess formed in one or a plurality of rows on the surface facing the region where the metallization is formed and superimposed on the surface of the functional element side Si substrate. Si substrate,
The metallization provided on the functional element side Si substrate and the surface of the lid side Si substrate facing the region where the metallization is formed are formed in one or a plurality of rows, and the surface is metallized. It is characterized in that it has a package structure in which the one functional element is hermetically sealed by being joined to the concave portion by solder.

Furthermore, the Si substrate on the functional element side having a functional element and continuously metallizing the surface so as to surround the functional element;
On the surface of the functional element-side Si substrate facing the metallization, the lid-side Si substrate provided with a metallized recess,
A first electrode metallization electrically connected to the functional element and provided on the functional element side Si substrate on the inner side of the metallization;
At the position of the lid-side Si substrate facing the first electrode metallization, a through hole provided through and a continuous recess surrounding the through hole, and a second electrode metallization covering at least the surface of the recess are provided. Prepared,
The metallization provided on the Si substrate on the functional element side;
The first electrode metallization and the lid-side Si provided on the surface of the lid-side Si substrate facing the metallization, between the metallized recesses, and on the functional element-side Si substrate. It has a package structure in which the functional element is hermetically sealed by joining with a second electrode metallization provided on the substrate by solder.

  According to the present invention, functional elements such as MEMS can be collectively hermetically sealed in a wafer state, and a highly reliable and low-priced functional element package can be provided.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  First, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic view of bonding in a wafer state showing a state of hermetic sealing at a wafer level. FIG. 2 is a detailed cross-sectional structure diagram showing the connection process of the hermetic sealing portion.

  In FIG. 1, 2 represents a pattern for one functional element. A hermetic seal (functional element side) 3 is formed on the outer periphery of the functional element 4 provided on the Si substrate (functional element side) 1. On the other hand, on the Si substrate (lid side) 5 on the lid side, a hermetic seal portion (lid side) 6 is formed at an opposing position so as to be connected to the hermetic seal portion (functional element side) 3 on the functional element side. Has been. Positioning is performed so that the hermetic sealing portions of the Si substrate (functional element side) 1 and the Si substrate (lid side) 5 overlap, and this is temporarily fixed to a jig by clamping or screwing. This jig is set in the chamber of the bonding apparatus, a load of about several thousand N to 10,000 N (several hundred kgf to 1020 kgf) is applied to the entire substrate, and heated to the melting point or higher of the solder formed in the hermetic sealing portion. The solder can be melted for connection and hermetic sealing can be performed at the wafer level. After hermetically sealing at the wafer level, the device is cut and separated individually, and a functional device package having a structure in which the functional device 2 is packaged is manufactured as each product.

Here, if the Si substrate or the wafer having the Si / SiO ₂ / Si sandwich structure having the SiO ₂ insulating layer is used depending on the required characteristics of the Si substrate as the Si substrate, the cost becomes lower. Can do.

  Next, the detailed structure of the hermetic seal will be described in detail based on FIGS. 2A to 2D together with the connection process. First, the state before joining will be described with reference to FIG. On the Si substrate (functional element side) 1, a concave portion 25 is formed by pattern formation by photolithography technique and dry etching or wet etching techniques. In the case of a single crystal Si wafer, the lower surface of the concave portion may be curved, but the fine shape of the lower surface of the concave portion does not significantly affect the effect of the present embodiment. include. Moreover, although the concave portion has a vertical side surface, it may be slightly inclined due to the influence of side etching in the etching process, but these are also included in this embodiment. A recess having a relatively vertical side surface and a flat bottom surface as in this embodiment is formed when high-speed dry etching is performed using an SOI (Silicon On Insulator) substrate frequently used in MEMS. it can.

  In this embodiment, two rows of recesses 25 are formed on the outer periphery of the functional element, and FIG. 2A shows a partial cross section thereof. Although it is necessary to design the depth of the recess 25 depending on the thickness and volume of the solder film 23, a depth of about several μm to 20 μm is preferable.

  After the recess 25 is formed, the Si substrate (functional element side) 1 is subjected to a treatment such as thermal oxidation to form a Si oxide film 21A. The Si oxide film 21A is generally formed to insulate the surface of the Si substrate (functional element side) 1 in order to prevent an electrical short circuit between wirings on the wafer when a functional element is formed. Therefore, although illustrated, there is no particular effect on the bonding, and the Si oxide film 21A may not be formed if only the hermetic sealing is intended.

  Next, metallization 22 </ b> A is applied to the region of the hermetic sealing portion (functional element side) 3. There are mainly two methods for forming the pattern of the metallization 22A. First, there is a lift-off method in which a resist pattern is formed by a photolithography technique and metallized from the resist pattern to remove excess metallization on the resist. Next, there is a method in which metallization is first formed on the Si oxide film 21A, a resist is applied thereon, a resist pattern is formed by a photolithography technique, and metallization at the opening of the resist pattern is removed by milling. . Alternatively, the metallization of the resist opening can be removed by wet etching instead of milling.

  For example, when a metallized pattern is formed by lift-off, the resist pattern is formed outside the recess 25. The reason is that, within the recess 25, the resist thickness to be exposed is different from other places, and a clear pattern cannot be obtained. Further, as will be described later, in this embodiment, the metallization on the side surface of the concave portion 25 or the convex portion 26 is an important point for producing an effect. For this reason, in order to reliably form the metallization on the side surface portion, it is necessary to accurately form a resist pattern outside the concave portion 25. Therefore, like 22C in the figure, the metallization 22A is always formed outside the recess 25 and on the surface of the Si substrate (functional element side) 1.

Also when the metallized pattern is formed by milling or wet etching, the metallized 22A is formed outside the recess 25 on the surface of the Si substrate (functional element side) 1 as in 22C. In these steps, the metallization 22A is first formed on the entire surface of the Si substrate (functional element side) 1, and then resist coating and resist pattern formation are performed. However, it is difficult to form a clear pattern inside the recess 25. It is. If the resist pattern is not left outside the recess 25, milling ions and wet etching liquid may enter the recess 25, and the metallization on the side surfaces of the recess 25 and the protrusion 26 may be removed. Extremely high. Accordingly, even in these steps, the metallization 22A is always formed continuously on the outside of the recess 25 and on the surface of the Si substrate (functional element side) 1 as in 22C.

  Next, the configuration of the metallization 22A will be described. In the metallized 22A, a thin film containing at least one of metals such as Ti, Cr, W, and V is formed by sputtering or vapor deposition as an adhesive layer with the Si oxide film 21A. Their thickness is preferably about 0.1 μm to 0.3 μm. On top of that, a thin film of a metal such as Ni, Cu, Pt, or Pd is formed as a protective film for these adhesive layers. These thicknesses are preferably 0.2 to 5 μm or the like. Sputtering or vapor deposition can also be used in this process, but in the case of Ni or Cu metallization, a plating method can also be applied. In the case of sputtering or vapor deposition, the thickness of the protective film is reduced, and in the case of plating, it tends to be relatively thick. Finally, Au is deposited on the surface. Au metallization can also be formed by sputtering or vapor deposition, but otherwise, electroless plating can be performed. The thickness of Au is preferably 0.2 to 0.5 μm in the case of sputtering or vapor deposition, and 0.1 to 3 μm in the case of plating.

  When these processes are all performed by sputtering or vapor deposition, it is general that the films are continuously formed without being taken out into the atmosphere after being put into the film forming apparatus. In the case of using a plating method, first, a metal such as Ti, Cr, W, or V of the adhesive layer is first formed by sputtering or vapor deposition, and the subsequent protective film and the Au film on the surface are generally formed by the plating method. Is.

  Similarly to the Si substrate (functional element side) 1 on the functional element side, the metallization 22B is also formed on the Si oxide film 21B on the Si substrate (lid side) 5 on the lid side. Further, a solder film 23 is formed.

  As a solder film forming method, a resist pattern is formed by a photolithography technique, a solder film is deposited by a method such as vapor deposition or sputtering, and then a solder pattern is formed by a lift-off method. In addition, the solder film 23 can also be formed by printing a solder paste using a screen mask or a metal mask and reflowing the entire Si substrate (cover side) 5. Alternatively, the metallization 22 can be formed by solder plating. In addition, a method of forming a solder film by spraying molten solder particles directly onto the metallized by a method called a melt discharge method can be applied.

  Examples of metals that can be used as solder include Au-20 to 37.6Sn (wt%), Au-90Sn, Sn-9Zn, Sn-3.5Ag, Sn-3Ag-0.5Cu, Pb-5Sn, and Pb. -10Sn, Sn-37Pb, Sn-57Bi, and other solder materials widely used for electronic component mounting can be applied. The composition of the solder is not limited to these, and includes those containing a small amount of alloy elements and those slightly deviated in composition.

  The solder composition will be described. In the case of Au—Sn binary solder, Au-20Sn eutectic is generally used. However, in joining using a very small amount of solder as in this embodiment, it is necessary to design a solder composition in consideration of the reaction between the solder and metallization. That is, since Au is present on the surface of the metallized 22A or the metallized 22B, the wettability of the solder may change when the Au is dissolved in the solder. In general, the wettability decreases when the composition of the solder is Au richer than that of Au-20Sn. Accordingly, it is effective to shift the composition to the Sn side accordingly, which is possible up to Au-37.6Sn in the range including the eutectic reaction with Au-20Sn. The connection temperature of these solders is generally selected from a range of 280 ° C. (eutectic temperature) to about 350 ° C.

  Compositions other than this, that is, Au-90Sn, Sn-9Zn, Sn-3.5Ag, Sn-3Ag-0.5Cu, and the like generally have a connection temperature in the range of about 220 ° C to 260 ° C. Since these solders originally have a lot of Sn in the solder, it is generally unnecessary to design a detailed composition for dissolution of Au, such as a solder having a composition in the vicinity of Au-20Sn.

  Pb-5Sn and Pb-10Sn are high melting point solders that are connected at about 300 ° C. with high Pb. Although it is possible to apply such a solder material, it is not desirable to use Pb-containing solder when considering Pb-free considering the influence on the environment.

  Sn-37Pb could be connected at about 220 ° C. and was once the most common solder. Therefore, although it is possible to apply this solder, it is not desirable from the viewpoint of making Pb free.

  Sn-57Bi is a low melting point solder having a melting point near 138 ° C. The connection temperature can be lowered to about 160 to 180 ° C. Although it is an advantage that the thermal influence on the functional element can be reduced, when the packaged functional element is mounted on an electronic device, the mounting design must consider the heat resistance of the solder joint.

  As mentioned above, although the solder material was demonstrated, these solder materials have a common subject. When the solder film 23 of FIG. 2 is formed, generally an oxide film of Sn or an alloy element is often formed on the surface. This is the oxide film 24. This oxide film 24 becomes a cause of poor wetting when bonded without flux.

  As described at the beginning, the soldering in the hermetic sealing of the MEMS functional element is premised on complete fluxless. Therefore, it is necessary to avoid wet defects caused by the oxide film 24.

  In the present embodiment, as means for this purpose, first, the Si substrate (functional element side) 1 and the Si substrate (lid side) 5 are accurately aligned, temporarily fixed, then set on the heater in the chamber, and the atmosphere is changed. Fill with vacuum or inert gas. The atmosphere type and atmospheric pressure are determined from the characteristics of the MEMS functional element, but at least at the time of connection, the atmosphere does not cause oxidation of the solder. This state is shown in FIG.

  Next, the edge formed by the concave portion 25, which is the upper surface including the corner portion of the convex portion 26 in this embodiment, is pressed against the solder film 23. First, before the solder is melted, a load of several thousand N to 10,000 N (several hundred to ten 20 kgf) is applied in the direction of the arrow, and the convex portion 26 is sunk into the solder film 23. In this process, the oxide film 24 is broken. Since the atmosphere is inactive, the portion where the oxide film is broken does not oxidize. This is FIG. 2 (b).

  Furthermore, it heats with a load applied, and heats up to the melting point or higher of the solder. The solder is melted and the melted solder 27 spreads wet to the metallizations 22A and B. This state is shown in FIG.

In some cases, the oxide film 24 originally present on the convex portion 26 may be partially left inside the solder connection portion. However, the oxide film 24 originally present on the majority of the solder surface is formed on the side surface of the convex portion 26. In the process of spreading the solder, it is discharged outside the solder without being taken into the solder. Since the specific gravity of the oxide film is smaller than that of the solder, it does not settle into the solder. Since the concave portion and the convex portion in between are formed so as to surround the outer periphery of the MEMS functional element, when the solder spreads on the side surface of the concave portion (the convex portion), the hermetic sealing by the solder continuous to the outer periphery of the MEMS functional element is performed. A stop structure is formed. As a result, it is possible to realize a reliable hermetic sealing of the functional elements by bonding that ensures the wettability of the bonding material at the wafer level. This is FIG. 2 (d).

  As described above, in the structure of this embodiment, the wettability of the solder is improved in addition to the above, in addition to the edge of the recess 25 (in this embodiment, the edge of the protrusion 26). One reason is that the solder forms a fillet in the region surrounded by the metallization 22A and spreads wet. In the region surrounded by such metallization, the solder tends to spread out by the so-called capillary phenomenon due to the surface tension of the solder. Therefore, since such a fillet is formed along the edge of the recess surrounding the functional element, hermetic sealing can be performed with a high yield. In order to actively cause the fillet formation, it is an indispensable condition to be metallized on the side surfaces of the concave portion 25 and the convex portion 26. For this purpose, it is necessary to form the metallization to the outside of the recess 25 when the metallization is originally formed as in 22C. As a result, the solder spreads during connection and spreads to the position of the metallization 22A outside the recess 25, that is, 22C, as shown in FIG. 2D, so that the functional element can be reliably hermetically sealed at the wafer level. It can be realized.

  In Patent Document 1, the annular concave groove is used for preventing the brazing material from protruding, but in this embodiment, the concave portion 25 is not formed to prevent the brazing material, that is, the solder, from protruding. The purpose of forming the concave portion and the convex portion is to realize hermetic sealing at a high yield by forming a metallization on the side surface of the concave portion and utilizing the fillet formation of the solder. It is also different from Patent Document 1 that the solder protrudes to the outside.

  Japanese Patent Laid-Open No. 2004-228561 performs solder bonding at the wafer level, but does not consider a wetting defect due to surface oxidation of the solder. In a functional element premised on fluxless bonding, the surface oxidation of solder is a decisive factor for reducing wettability and yield.

  Therefore, this embodiment realizes solder bonding at a wafer level and with high yield, and the principle and structure are different from those of Patent Document 1 and Patent Document 2.

  In the present embodiment, the case where the recesses 25 are in two rows is shown, but the recesses 25 may have one or more rows. In the case of one row, the edge portion of the recess 25 is sunk into the solder film 23, and hermetic sealing is performed in the process where the solder spreads on the side surface of the recess 25. When the recesses 25 are formed in more rows, the overall sealing width is widened, but the yield of hermetic sealing is further improved.

  In this embodiment, the concave portion is formed in the Si substrate (functional element side) 1 on the functional element side. However, the concave portion is formed in the Si substrate (lid side) 5 on the lid side, and the Si substrate (functional element side) 1 is formed. Even if a solder film is formed, the effect of this embodiment can be obtained without any problem.

  As described above, according to the present embodiment, since the solder fillet is formed along the edge of the concave portion surrounding the functional element, hermetic sealing can be performed at a high yield, and at the wafer level. A reliable hermetic sealing of functional elements can be realized.

  Next, a second embodiment of the present invention will be described with reference to FIGS. In this embodiment, a solder film is formed inside the recess and connected. As shown in FIG. 3A, the concave portion 25 and the convex portion 26 are formed on the Si substrate (lid side) 5 on the lid side, and the metallized 22B and the solder film 23 are formed on the surfaces thereof. The solder film 23 basically has no oxide film 24 so that the solder wets better. However, in this embodiment, the case where the oxide film 24 exists on the surface will be described, depending on the solder formation method. To do.

  Here, the configuration of metallization, the forming process, the composition of the solder, and the forming method are the same as those in the first embodiment, and thus the description thereof is omitted.

  Note that, when the solder film 23 is supplied by a method such as lift-off or plating, it is difficult to precisely form the resist pattern inside the recess 25, and therefore, the solder film 23 may be partially formed outside the recess 25. . In this case, the solder protrusion is expected to increase. Therefore, the resist pattern for the solder pattern is formed so as to coincide with the side surface of the concave portion 25 as much as possible, and the solder film 23 is formed on the bottom surface of the concave portion 25 and the upper surface and side surface of the convex portion 26 as shown in FIG. It is desirable to be formed.

  In bonding, the substrates are aligned, temporarily fixed using clamps, screws, etc., and set in the chamber. The atmosphere is inert. Such a process is the same as that of Example 1.

  When a load is applied between the substrates before the solder is melted, the solder film 23 is plastically deformed as shown in FIG. As the solder spreads laterally, the surface area increases, and the oxide film 24 is broken there. Since the atmosphere is inactive, new oxidation does not occur where the oxide film 24 is broken.

  When heating is started in this state and a load is applied in the direction of the arrow, the solder is melted as shown in FIG. 3C, and the solder is metallized 22A, B from the portion where the oxide film 24 is broken. Spread out wet. The oxide film 24 is left in part, but finally, the inside of the recess can be soldered in a state where the void 51 is left in the center of the recess 25, and hermetic sealing is performed as shown in FIG. It can be carried out. After hermetically sealing at the wafer level, the device is cut and separated individually to manufacture a functional device package having a package structure as a product.

  In the present embodiment, the case where the recesses 25 are two rows has been shown. However, as in the first embodiment, the recesses 25 may have one row or more rows. In the case of one row, the edge portion of the recess 25 is sunk into the solder film 23, and hermetic sealing is performed in the process where the solder spreads on the side surface of the recess 25. When the recesses 25 are formed in more rows, the overall sealing width is widened, but the yield of hermetic sealing is further improved.

  In this embodiment, the concave portion is formed on the Si substrate (lid side) 5 on the lid side, but the concave portion is formed on the Si substrate (functional element side) 1 on the functional element side, and the Si substrate (functional element side) 1 is formed. Even if a solder film is formed, the effect of this embodiment can be obtained without any problem.

  As an effect obtained in the present embodiment, in addition to the effect of the first embodiment, the concave portion for solder bonding and the formation of the solder film are performed on the Si substrate 5 on the lid side. This is because the number of steps of the Si substrate 1 for forming elements can be reduced. When forming a solder film or the like after forming the functional element, if a functional element that cannot withstand processes such as resist coating, solder film formation, and cleaning is formed, the solder film is formed on the Si substrate 1 side. Difficult to form. In such a case, since it is necessary to form a solder film on the Si substrate 5 on the lid side, the structure of this embodiment is suitable.

  A third embodiment of the present invention will be described with reference to FIG. Here, the structure of metallization, the formation process, the composition of the solder, and the formation method are the same as those in the first embodiment, and thus the description thereof is omitted. However, the formation method of the recess 25 is different from the previous embodiments.

  As described in the first embodiment, the recess 25 can be formed on the Si substrate (functional element side) 1 by dry etching or wet etching. In particular, when a wafer having a (100) surface exposed on the surface of the Si substrate is used, the closest (111) surface is exposed and a V-shaped groove is formed by wet etching as in this embodiment. Can do. As a result, a mountain-shaped convex portion 26 is formed by the side surfaces of the adjacent concave portions. Even in this case, as in the first and second embodiments so far, the convex portion 26 is sunk into the solder film 23 before the solder is melted, so that a part of the oxide film 24 is destroyed and then melted. Due to the spreading of the solder, a joining portion in which the oxide film 24 is little involved is formed, and hermetic sealing can be performed. After hermetically sealing at the wafer level, the device is cut and separated individually to manufacture a functional device package having a package structure as a product.

  In the present embodiment, the case where the recesses 25 are in two rows is shown. However, as in the first and second embodiments, the recesses 25 may have one row or more rows. In the case of one row, the edge portion of the recess 25 is sunk into the solder film 23, and hermetic sealing is performed in the process where the solder spreads on the side surface of the recess 25. When the recesses 25 are formed in more rows, the overall sealing width is widened, but the yield of hermetic sealing is further improved.

  In this embodiment, the concave portion is formed in the Si substrate (functional element side) 1 on the functional element side. However, the concave portion is formed in the Si substrate (lid side) 5 on the lid side, and the Si substrate (functional element side) 1 is formed. Even if a solder film is formed, the effect of this embodiment can be obtained without any problem.

  As an effect obtained in the present embodiment, in addition to the effect of the first embodiment, since the convex portion 26 has a mountain shape and has a sharp point, it is easy to sink into the solder film 23 and easily break through the oxide film 24. It can be done. Therefore, it becomes possible to join with a relatively low load.

  A fourth embodiment of the present invention will be described with reference to FIGS. This example describes a MEMS functional element package to which the conventional sealing structure is applied. FIG. 5 is a schematic view of one piezoresistive triaxial acceleration sensor using an SOI wafer, and FIG. 6 is a diagram showing a cross-sectional structure thereof. The operation principle of the piezoresistive acceleration sensor and the conventional mounting structure have been described in many documents, and will not be described here.

  In the SOI substrate 71, the recesses 72 are formed in two rows, and the metallized 74A is formed thereon. A piezo element 75 and a wiring 76 are formed inside the recess 72. A glass substrate 77 is bonded to the lower surface of the SOI substrate 71.

  On one Si cap substrate 78, a solder film 79 is formed on the metallization 74B, and a cavity 80 is also formed.

  FIG. 6 shows these cross-sectional structures, in which an electrode metallization 73 is provided on the Si substrate 71 on the functional element side, inside the recess 72 (on the piezoelectric element 75 side). A through electrode 81 is formed under the electrode metallized 73 and is connected to the electrode 82. As in the previous embodiments, the solder film 79 is pressed against the recess 72, and in this state, the solder film 79 is heated to a temperature equal to or higher than the melting point of the solder to be bonded and hermetically sealed.

  As the structure of the hermetic sealing portion, any structure described in the first to third embodiments can be applied.

  As described above, according to the present embodiment, since reliable hermetic sealing can be performed collectively in a wafer state, it is possible to realize a functional element package that is highly reliable, small, and inexpensive. .

  A fifth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a diagram showing a cross-sectional structure of one MEMS functional element (acceleration sensor) in the present embodiment. The present embodiment relates to a structure that does not require the through electrode 81 formed in the fourth embodiment. 6 denote the same components, and are partially omitted for the sake of explanation.

  A through hole 91 is formed in the Si cap substrate 78 using a technique such as etching, sandblasting, or laser processing. On the lower surface of the Si cap substrate 78, that is, on the bonding surface side, the periphery of the through hole 91 is surrounded by a metallization 74B, and a solder film 79 is also formed. This is connected to an electrode metallized 73 connected to the piezo element 75 via a wiring 76.

  An electrode metallization 73 is provided on the Si substrate 71 on the functional element side on the inner side (the piezo element 75 side) than the recess 72. Since the electrode metallized 73 is formed in a concave shape in advance, a high yield can be achieved between the metallized 74B and the electrode metallized 73 due to the solder wetting and fillet formation as described in the previous examples. Can be hermetically sealed solder joint. As in the fourth embodiment, all the structures of the first to third embodiments can be applied.

  As an effect obtained in the present embodiment, in addition to the effect of the fourth embodiment, first, it is not necessary to process a through hole in the Si substrate 71 on which the functional element is formed. For this reason, since the Si cap substrate 78 can be made thinner than the Si substrate 71 that forms the functional element, the processing of the through hole is easier than in the fourth embodiment. In general, when a deep hole is to be made, the hole becomes smaller as the depth becomes deeper, so a larger opening is required. In the present embodiment where the through hole becomes shallow, the diameter of the opening of the through hole can be reduced, which is advantageous for further miniaturization.

It is a schematic diagram of the joining in the wafer state in the Example of this invention. It is a detailed cross-section figure which shows the connection process of the airtight sealing part in the Example of this invention. It is a figure which shows the detailed cross-section of the airtight sealing part in the Example of this invention. It is a figure which shows the detailed cross-section of the airtight sealing part in the Example of this invention. It is a schematic diagram for one MEMS functional element (acceleration sensor) in the Example of this invention. It is a figure which shows the cross-section of one MEMS functional element (acceleration sensor) in the Example of this invention. It is a figure which shows the cross-section of one MEMS functional element (acceleration sensor) in the Example of this invention.

DESCRIPTION OF SYMBOLS 1 ... Si substrate (functional element side), 2 ... Pattern for one functional element, 3 ... Airtight sealing part (functional element side), 4 ... Functional element, 5 ... Si substrate (lid side), 6 ... Airtight Stop (lid side),
21A ... Si oxide film (functional element side), 21B ... Si oxide film, 22A ... metallized, 22B ... metallized, 22C ... metallized outside the recess 25 and on the surface of the Si substrate, 23 ... solder film, 24 ... oxide film, 25 ... Concave part, 26 ... convex part, 27 ... molten solder, 28 ... solidified solder,
31 ... Au bump, 32 ... Au-Si eutectic melt, 33 ... Au-Si eutectic solder (solidification),
41 ... Ge film, 42 ... Au-Ge eutectic melt, 43 ... Au-Ge eutectic solder (solidification), 51 ... void,
71 ... SOI substrate, 72 ... recess, 73 ... electrode metallization, 74A ... metallization, 74B ... metallization, 75 ... piezo element, 76 ... wiring, 77 ... glass substrate, 78 ... Si cap substrate, 79 ... solder film, 80 ... cavity , 81 ... through electrode, 82 ... electrode, 91 ... through hole.

Claims (16)

Preparing a first Si substrate having a recess formed on the substrate and a metallization formed on the substrate surface including the inside of the recess and the outside of the recess;
Preparing a second Si substrate having a metallization formed on the substrate and a solder formed on the metallization and having a thickness smaller than the depth of the recess of the first Si substrate;
The first Si substrate and the second Si substrate so that the solder of the second Si substrate faces the region corresponding to the metallization formed inside and outside the recess of the first Si substrate. A step of facing each other,
And a step of bringing the first Si substrate and the second Si substrate opposed to each other close to each other and joining the same. Preparing a first Si substrate having a recess formed on the substrate, a metallization formed on the substrate surface including the recess, and a solder formed on the metallization;
Preparing a second Si substrate having a metallization formed on the substrate;
A step of facing the first Si substrate and the second Si substrate so that the solder of the first Si substrate faces the region corresponding to the metallized region of the second Si substrate;
And a step of bringing the first Si substrate and the second Si substrate opposed to each other close to each other and joining the same. In claim 2,
The method of manufacturing a functional device package, wherein the solder is formed in a region outside the recess. In any one of Claims 1 thru | or 3,
In the bonding step, the solder spreads on the metallization on the side surface of the recess. In any one of Claims 1 thru | or 4,
In the bonding step, the solder wets the bottom surface of the concave portion. In any one of Claims 1 thru | or 5,
A method of manufacturing a functional device package, wherein a solder fillet is formed along a surface of the recess. In any one of Claims 1 thru | or 6,
The method of manufacturing a functional device package, wherein the step of facing the first Si substrate and the second Si substrate and the step of bonding are performed in an inert atmosphere. In claim 1 or 2,
A method of manufacturing a functional device package, wherein the functional device is surrounded by metallization and formed on the first Si substrate or the second Si substrate. In claim 1 or 2,
A method of manufacturing a functional device package, wherein the recesses are formed in a plurality of rows. In claim 1 or 2,
The method of manufacturing a functional element package, wherein the concave portion is a V-shaped groove, and a mountain-shaped convex portion is formed by a side surface of the adjacent concave portion. In claim 1 or 2,
A method for manufacturing a functional device package, wherein the depth of the recess is 20 μm or less. In claim 1 or 2,
The solder is a solder material mainly composed of an alloy such as Au—Sn, Sn—Ag, Sn—Cu, Sn—Ag—Cu, Sn—Zn, Sn—Pb, Sn—Bi. A method for manufacturing a functional device package. In claim 1 or 2,
The metallization is formed on the surface of a thin film containing at least one of metals such as Ti, Cr, W, and V formed as an adhesive layer with the Si substrate, in order to suppress the reaction with the solder, Ni, Cu, Pt A method for producing a functional device package, characterized in that a thin film containing at least one of Pd is formed, and an Au film for preventing oxidation is formed on the surface thereof. In claim 1 or 2,
Metallization is formed outside the recess on the surface of the first Si substrate, and the metallization formed on the inner surface of the recess is coupled to the metallization outside the recess on the surface of the first Si substrate. A method for manufacturing a functional device package, comprising: In claim 1 or 2,
Metallization of the inner surface of the recess of the first Si substrate, metallization outside the recess of the surface of the first Si substrate, and the position of the second Si substrate facing the recess A method of manufacturing a functional device package, comprising melting and connecting solder between the metallization, joining the first Si substrate and the second Si substrate, and hermetically sealing the functional device. In claim 1 or 2,
Manufacturing of a functional device package, wherein the first Si substrate and the second Si substrate are Si wafers or wafers having a Si / SiO ₂ / Si sandwich structure having an SiO ₂ insulating layer therein. Method.

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