JP2009116993A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress, when a power source pad is arranged at one end of a memory cell array and sense amplifiers are arranged at the one end and the other end of the memory cell array, voltage drop of a power source caused at the sense amplifier of the other end and increase in chip area caused by the increase of wiring width of power source wiring from a power source pad to the sense amplifier of the other end. <P>SOLUTION: The power source pad 20 and a sense amplifier 12A are arranged at one end of a memory cell array 11. A first bit line is arranged correspondingly to the sense amplifier 12A, and the first bit line is sensed by the sense amplifier 12A. A sense amplifier 12B is arranged at the other end of the memory cell array 11. A second bit line is arranged adjacently to the first bit line correspondingly to the sense amplifier 12B, and the second bit line is sensed by the sense amplifier 12B. A connecting circuit 21 connects the first bit line and the second bit line to the sense amplifier 12A during pre-charge operation for pre-charging the first bit line and the second bit line. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device in which data can be electrically rewritten, and is used, for example, for a read operation of a sense amplifier in a NAND flash memory.

  A NAND flash memory is known as one of nonvolatile semiconductor memory devices. In the NAND flash memory, when all bit line selection methods that precharge and simultaneously read all bit lines are used, there is no amplitude of the bit line potential during the read operation, so that adjacent bit lines are read simultaneously. It can be performed.

  When the all bit line selection method is used, one sense amplifier is required for one bit line as compared with the conventional sense method for shielding adjacent bit lines. For this reason, disposing all the sense amplifiers on one side of the memory cell array is not physically practical because the distance between the bit lines becomes too narrow. Therefore, when the all bit line selection method is adopted, the sense amplifiers are arranged at the upper end and the lower end of the memory cell array. For example, Patent Document 1 describes a semiconductor memory device in which sense amplifiers are arranged at the upper end and the lower end of a memory cell array, respectively.

  Currently, by reducing the chip size of a NAND flash memory or using the NAND flash memory in a package such as a micro SD, the arrangement of power supply pads to which a power supply voltage is supplied is often limited to one side of the memory cell array.

When sense amplifiers are arranged at both ends of the memory cell array and a power supply pad is arranged at one end of the memory cell array, the power supply voltage is applied when power is supplied to a remote sense amplifier arranged at one end far from the power supply pad. Descent is a problem. For this reason, it is necessary to lay out a thick power supply wiring from the power supply pad to a remote sense amplifier in a region on the side of the memory cell array. However, when such measures are taken, the chip area increases, and the characteristics of the NAND flash memory that the occupation ratio of the memory cells is high are lost.
JP 2006-338996 A

  In the present invention, when a power supply pad is arranged at one end of a memory cell array and sense amplifiers are arranged at one end and the other end of the memory cell array, a power supply voltage drop generated in the sense amplifier at the other end, An object of the present invention is to provide a non-volatile semiconductor memory device that can suppress an increase in chip area due to an increase in the wiring width of a power supply line to a sense amplifier.

  A nonvolatile semiconductor memory device according to an embodiment of the present invention includes a memory cell array in which a plurality of memory cells are arranged, a power supply pad disposed at one end of the memory cell array and supplied with a power supply voltage, and the one end of the memory cell array. And a first bit line arranged corresponding to the first sense amplifier and sensed by the first sense amplifier, and opposed to the one end of the memory cell array. A second sense amplifier disposed at the other end and a second bit line corresponding to the second sense amplifier and disposed adjacent to the first bit line and sensed by the second sense amplifier And during the precharge operation for precharging the first bit line and the second bit line, the first bit line and the second bit line are connected to the first sensor. Characterized by comprising a connection circuit connected to the amplifier.

  According to the present invention, when the power supply pad is disposed at one end of the memory cell array and the sense amplifier is disposed at one end and the other end of the memory cell array, the voltage drop of the power generated in the sense amplifier at the other end, It is possible to provide a nonvolatile semiconductor memory device capable of suppressing an increase in chip area due to an increase in the wiring width of the power supply wiring to the end sense amplifier.

  Embodiments of the present invention will be described below with reference to the drawings. Here, a NAND flash memory is taken as an example of the nonvolatile semiconductor memory device. In the description, common parts are denoted by common reference symbols throughout the drawings.

  A NAND flash memory according to an embodiment of the present invention will be described. FIG. 1 is a block diagram showing a configuration of a NAND flash memory according to an embodiment of the present invention.

  A plurality of memory cells are arranged in a matrix in the memory cell array 11, and word lines and bit lines are connected to these memory cells. The word lines are wired in the row direction, and the bit lines are wired so as to cross each other in the column direction. A sense amplifier 12A is disposed at one end of the memory cell array 11 in the bit line direction, and a sense amplifier 12B is disposed at the other end of the memory cell array 11 opposite to one end in the bit line direction. A connection circuit 21 that connects the bit line and the sense amplifier 12A is disposed between the memory cell array 11 and the sense amplifier 12A. Further, row decoders 13 are disposed at both ends of the memory cell array 11 in the word line direction.

  Data exchange between the sense amplifiers 12A and 12B and the external input / output terminal I / O is performed via the data bus 14 and the I / O buffer 15.

  Various external control signals such as a chip enable signal / CE, an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal / WE, and a read enable signal / RE are input to the controller 16. Based on these control signals, the controller 16 identifies an address “Add” and a command “Com” supplied from the input / output terminal I / O. Then, the controller 16 transfers the address “Add” to the row decoder 13 and the column decoder 18 via the address register 17. Further, the controller 16 decodes the command “Com”.

  The controller 16 performs data read control, data write and erase sequence control according to the external control signal and command. An internal voltage generation circuit 19 is provided to generate an internal voltage (for example, a voltage boosted from the power supply voltage) necessary for each operation mode. The internal voltage generation circuit 19 is also controlled by the controller 16 to perform a boosting operation and generate a necessary voltage.

  FIG. 2 is a layout diagram when the NAND flash memory of the embodiment is formed on the chip 10. As shown in FIG. 2, a power supply pad 20 to which a power supply voltage is supplied is disposed at one end of the memory cell array 11 in the bit line direction (one end of the chip 10). Further, a sense amplifier 12A is disposed at one end of the memory cell array 11 in the bit line direction, and a sense amplifier 12B is disposed at the other end of the memory cell array 11 in the bit line direction. A connection circuit 21 that connects the bit line and the sense amplifier 12A is disposed between the memory cell array 11 and the sense amplifier 12A. Furthermore, row decoders 13 are arranged at both ends of the memory cell array 11 in the word line direction.

  A peripheral circuit 22 for operating the memory cell array 11 is disposed between the power supply pad 20 and the sense amplifier 12A. As the peripheral circuit 22, for example, the I / O buffer 15, the controller 16, the address register 17, the column decoder 18, and the internal voltage generation circuit 19 described above are arranged. Further, a power supply wiring 23 for supplying a power supply voltage from the power supply pad 20 to the sense amplifier 12B is disposed outside the row decoder 13.

  Next, the precharge operation of the bit line connected to the memory cell will be described.

  FIGS. 3A and 3B are schematic diagrams showing the connection state of the sense amplifier, the bit line, and the connection circuit during the precharge operation of the bit line. The bit line BLe is an even-numbered bit line in the memory cell array 11, and the bit line BLo is an odd-numbered bit line in the memory cell array 11. The bit line BLe is connected to the sense amplifier 12B via the bit line selection transistor BLSe ′. The bit line BLe is further connected to the sense amplifier 12A via the connection transistor BLSe. The bit line BLo is connected to the sense amplifier 12A via the connection transistor BLSo.

(1) A first example of the bit line precharge operation will be described. First, the bit line BLe is precharged, and then the bit line BLo is precharged. Details of the precharge operation are as follows. First, as shown in FIG. 3A, the connection transistor BLSe is turned on, and the sense amplifier 12A is connected to the bit line BLe. The bit line selection transistor BLSe ′ and the connection transistor BLSo are turned off and are cut off. In this state, the bit line BLe is precharged.

  Subsequently, as shown in FIG. 3B, the connection transistor BLSe is turned off, and the bit line BLe and the sense amplifier 12A are cut off. The connection transistor BLSo is turned on, and the sense amplifier 12A is connected to the bit line BLo. Further, the bit line selection transistor BLSe ′ is turned on, and the sense amplifier 12B is connected to the bit line BLe. In this state, the bit line BLo is precharged. At this time, the bit line BLe is precharged again by the sense amplifier 12B. The bit line BLe is precharged because the bit line BLe has already reached the precharge potential, so that current consumption is smaller than when the bit line BLe is precharged first, and the voltage drop of the power supply in the sense amplifier 12B. Can be reduced.

  Thereafter, the sensing operation of the memory cell is performed. FIG. 4 is a schematic diagram illustrating a connection state of the sense amplifier, the bit line, and the connection circuit at the time of sensing. At the time of sensing, as shown in FIG. 4, the bit line BLe is connected to the sense amplifier 12B, and the bit line BLo is connected to the sense amplifier 12A. At this time, the bit line BLe is disconnected from the sense amplifier 12A by the connection transistor BLSe. In this state, the current flowing through the bit line BLe is sensed by the sense amplifier 12B, and the read operation of the memory cell connected to the bit line BLe is performed. Similarly, the current flowing through the bit line BLo is sensed by the sense amplifier 12A, and the read operation of the memory cell connected to the bit line BLo is performed.

(2) A second example of the bit line precharge operation will be described. In this example, the bit line BLe and the bit line BLo are precharged simultaneously. Details of the precharge operation are as follows. As shown in FIG. 5, the connection transistor BLSe is turned on, and the sense amplifier 12A is connected to the bit line BLe. At the same time, the connection transistor BLSo is turned on, and the sense amplifier 12A is connected to the bit line BLo. Further, the bit line selection transistor BLSe ′ is turned off, and the bit line BLe and the sense amplifier 12B are cut off. In this state, the bit line BLe and the bit line BLo are precharged simultaneously.

  Thereafter, the sensing operation of the memory cell is performed. FIG. 6 is a schematic diagram illustrating a connection state of the sense amplifier, the bit line, and the connection circuit at the time of sensing. At the time of sensing, as shown in FIG. 6, the bit line BLe is connected to the sense amplifier 12B, and the bit line BLo is connected to the sense amplifier 12A. At this time, the bit line BLe is disconnected from the sense amplifier 12A by the connection transistor BLSe. In this state, the current flowing through the bit line BLe is sensed by the sense amplifier 12B, and the read operation of the memory cell connected to the bit line BLe is performed. Similarly, the current flowing through the bit line BLo is sensed by the sense amplifier 12A, and the read operation of the memory cell connected to the bit line BLo is performed.

  Next, an example of the connection circuit 21 for precharging all the bit lines using the sense amplifier 12A arranged on the side where the power supply pad 20 is formed and its operation will be described.

  FIG. 7 shows a connection circuit 21 that connects the sense amplifier 12A and the bit lines BLe and BLo. A circuit as shown in FIG. 7 is inserted between the sense amplifier 12A and the bit lines BLe and BLo arranged close to the power supply pad 20 so that the bit lines BLe and BLo can be precharged from the sense amplifier 12A. To do.

  An operation of precharging even-numbered bit lines BLe as the first example and then precharging odd-numbered bit lines BLo will be described.

  The connection transistor BLSe is turned on, and the bias transistor BIASe is turned off. Further, the bit line selection transistor BLSe ′ is turned off. As a result, the bit line BLe is connected to the sense amplifier 12A, and the bit line BLe is precharged. At this time, the connection transistor BLSo is turned off and the bias transistor BIASo is turned on. Thus, the predetermined potential BLCRL (for example, the ground potential Vss) is supplied to the bit line BLo, and the bit line BLo is set as a shield line.

  After precharging the bit line BLe, the connection transistor BLSe is turned off. The bit line selection transistor BLSe ′ is turned on while the bias transistor BIASe remains off. As a result, the bit line BLe is disconnected from the sense amplifier 12A and connected to the sense amplifier 12B. Further, the bias transistor BIASo is turned off and the connection transistor BLSo is turned on. As a result, the bit line BLo is connected to the sense amplifier 12A, and the bit line BLo is precharged. Until the bit line BLo is completely precharged, the bit line BLe is precharged once again by the sense amplifier 12B. As described above, the bit line BLe is precharged because the voltage drop of the power supply can be made smaller than usual because the bit line BLe has already reached the precharge potential. After the precharge of the bit line BLo is completed, the read operation is started.

  Next, the operation of precharging the even-numbered bit lines BLe and the odd-numbered bit lines BLo simultaneously as the second example will be described.

  The connection transistor BLSe is turned on, and the bit line selection transistor BLSe ′ and the bias transistor BIASe are turned off. Further, the connection transistor BLSo is turned on and the transistor BIASo is turned off. As a result, the bit line BLe and the bit line BLo are connected to the sense amplifier 12A, and the bit line BLe and the bit line BLo are simultaneously precharged. At this time, the voltage drop of the power supply on the sense amplifier 12B side can be suppressed by turning off the bit line selection transistor BLSe ′ and disconnecting the bit line BLe from the sense amplifier 12B. After the precharge of the bit lines BLs and BLo is completed, the connection transistor BLSe is turned off, the bit line selection transistor BLSe ′ is turned on, and the read operation is started.

  As described above, when the sense amplifiers are arranged on both sides of the cell array by precharging all the bit lines using the sense amplifiers arranged on the side where the power pads are formed, the side far from the power pads To suppress the voltage drop of the power supply that occurs when precharging by the sense amplifier arranged in the circuit, and the increase in chip area that occurs when the wiring width of the power supply wiring is increased to suppress this voltage drop of the power supply Is possible.

  The operation at the time of bit line precharging and the operation at the time of sensing in the all bit line selection method of the NAND flash memory will be described below. 8 and 9 are circuit diagrams of the sense amplifier in the all bit line selection method. FIG. 8 shows the bit line precharge time, and FIG. 9 shows the sense time.

  In the read operation, first, the bit line BL and the sense node SEN are precharged. For example, as shown in FIG. 8, the bit line BL is 0.5 V, the sense node SEN is 2.5 V, and the current Icell is 1 μA. At this time, the bit line is charged while discharging to the ground potential (common source line) via the NAND cell (while a current flows). Thereafter, the sensing is started while being charged.

  At the time of sensing shown in FIG. 9, when the selected cell is “1” data, the current Icell is 1 μA (current supply capability) or more, the bit line potential is changed from 0.5 V to 0 V, and the potential of the sense node SEN is 2.5 V. To 0V. Then, the voltage Vdd is held in the latch circuit LA. On the other hand, when the selected cell is “0” data, the current Icell becomes less than the current supply capability, and the potential of the bit line BL and the sense node SEN do not change, so that the ground potential Vss is held in the latch circuit LA. As described above, since the bit line potential is fixed to either 0V or 0.5V during the read operation, it is not necessary to shield the adjacent bit line BL.

  In the embodiment of the present invention, the difference from the read operation of the conventional all bit line selection method is that all the bit lines are first connected to the sense amplifier arranged close to the power supply pad, and this sense amplifier is used. The bit line is precharged. Thereafter, the bit line sensed by the sense amplifier arranged on the side far from the power supply pad is disconnected from the adjacent sense amplifier, and connected to the far sense amplifier to start sensing. By adopting this method, since the peak current at the time of bit line precharging is supplied only from the adjacent sense amplifier, the influence of the voltage drop of the power supply in the remote sense amplifier can be suppressed. Thus, since the voltage drop of the power supply can be suppressed, the power supply wiring having a large wiring width for supplying power to the sense amplifier far from the power supply pad can be thinned. Thereby, the chip area can be reduced.

  According to the embodiment of the present invention, in the read operation of the sense amplifier, the voltage drop of the power supply in the sense amplifier far from the power supply pad is obtained by precharging all the bit lines with the sense amplifier closer to the power supply pad. In addition, the width of the power supply wiring from the power supply pad to the remote sense amplifier can be reduced, so that it is possible to provide a nonvolatile semiconductor memory device capable of improving reliability and reducing the chip area.

  Here, the NAND flash memory has been described as an example of the nonvolatile semiconductor memory device, but the embodiment of the present invention is an AND flash memory, a NOR flash memory, a DINOR flash memory, a three-transistor NAND type. The present invention can be applied to both a flash memory (3Tr.-NAND flash memory) and a nano flash memory.

  In addition, the above-described embodiment is not the only embodiment, and various embodiments can be formed by changing the configuration or adding various configurations.

1 is a block diagram showing a configuration of a NAND flash memory according to an embodiment of the present invention. FIG. 3 is a layout diagram when the NAND flash memory of the embodiment is formed on a chip. 6 is a schematic diagram illustrating a connection state (first example) of a sense amplifier, a bit line, and a connection circuit during the bit line precharge operation of the embodiment. FIG. FIG. 3 is a schematic diagram illustrating a connection state (first example) of a sense amplifier, a bit line, and a connection circuit during sensing according to the embodiment. 5 is a schematic diagram illustrating a connection state (second example) of the sense amplifier, the bit line, and the connection circuit during the bit line precharge operation of the embodiment. FIG. 6 is a schematic diagram illustrating a connection state (second example) of the sense amplifier, the bit line, and the connection circuit at the time of sensing according to the embodiment. FIG. 4 is a circuit diagram illustrating a connection circuit that connects the sense amplifier and the bit lines BLe and BLo of the embodiment. FIG. FIG. 4 is a circuit diagram of a sense amplifier in a NAND flash memory all bit line selection method (at the time of bit line precharging). FIG. 3 is a circuit diagram (at the time of sensing) of a sense amplifier in an all bit line selection method of a NAND flash memory.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Chip, 11 ... Memory cell array, 12A, 12B ... Sense amplifier, 21 ... Connection circuit, 13 ... Row decoder, 14 ... Data bus, 15 ... I / O buffer, 16 ... Controller, / CE ... Chip enable signal, ALE ... Address latch enable signal, CLE ... Command latch enable signal, / WE ... Write enable signal, / RE ... Read enable signal, 17 ... Address register, 18 ... Column decoder, 19 ... Internal voltage generation circuit, 20 ... Power supply pad, 21 Connection circuit 22 Peripheral circuit 23 Power supply wiring

Claims (5)

A memory cell array in which a plurality of memory cells are arranged;
A power supply pad disposed at one end of the memory cell array and supplied with a power supply voltage;
A first sense amplifier disposed at the one end of the memory cell array;
A first bit line arranged corresponding to the first sense amplifier and sensed by the first sense amplifier;
A second sense amplifier disposed at the other end opposite to the one end of the memory cell array;
A second bit line corresponding to the second sense amplifier and disposed adjacent to the first bit line and sensed by the second sense amplifier;
A connection circuit for connecting the first bit line and the second bit line to the first sense amplifier during a precharge operation for precharging the first bit line and the second bit line;
A non-volatile semiconductor memory device comprising:   The connection circuit includes a first connection transistor that switches between the first sense amplifier and the first bit line to a connected state or a cut-off state, the first sense amplifier, and the second bit line. A second connection transistor that switches between a connection state and a cut-off state; a first bias transistor that connects the first bit line to a predetermined potential; and a second connection transistor that connects the second bit line to the predetermined potential. The nonvolatile semiconductor memory device according to claim 1, further comprising two bias transistors. A selection transistor for switching between the second sense amplifier and the second bit line to a connected state or a cut-off state;
The second connection transistor connects the second bit line to the first sense amplifier, the selection transistor disconnects the second bit line from the second sense amplifier, and The bias transistor connects the first bit line to the predetermined potential, the first sense amplifier precharges the second bit line,
The second connection transistor disconnects the second bit line from the first sense amplifier, the first connection transistor connects the first bit line to the first sense amplifier, and 3. The nonvolatile memory according to claim 2, wherein a second bias transistor connects the second bit line to the predetermined potential, and the first sense amplifier precharges the first bit line. Semiconductor memory device. A selection transistor for switching between the second sense amplifier and the second bit line to a connected state or a cut-off state;
The second connection transistor connects the second bit line to the first sense amplifier, the selection transistor disconnects the second bit line from the second sense amplifier, and A connection transistor connects the first bit line to the first sense amplifier, and the first sense amplifier simultaneously precharges the first bit line and the second bit line. The nonvolatile semiconductor memory device according to claim 2. After precharging the first bit line and the second bit line by the first sense amplifier, the second connection transistor cuts off the second bit line from the first sense amplifier. The first sense amplifier senses the first bit line;
5. The selection transistor according to claim 3, wherein the selection transistor connects the second bit line to the second sense amplifier, and the second sense amplifier senses the second bit line. Nonvolatile semiconductor memory device.

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